2 * cortex arm arch v7 cache flushing and invalidation
3 * included by l.s and rebootcode.s
6 TEXT cacheiinv(SB), $-4 /* I invalidate */
8 MTCP CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cortex */
13 * set/way operators, passed a suitable set/way value in R0.
15 TEXT cachedwb_sw(SB), $-4
16 MTCP CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEsi
19 TEXT cachedwbinv_sw(SB), $-4
20 MTCP CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEsi
23 TEXT cachedinv_sw(SB), $-4
24 MTCP CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvd), CpCACHEsi
27 /* set cache size select */
28 TEXT setcachelvl(SB), $-4
29 MTCP CpSC, CpIDcssel, R0, C(CpID), C(CpIDidct), 0
33 /* return cache sizes */
34 TEXT getwayssets(SB), $-4
35 MFCP CpSC, CpIDcsize, R0, C(CpID), C(CpIDidct), 0
39 * l1 cache operations.
40 * l1 and l2 ops are intended to be called from C, thus need save no
41 * caller's regs, only those we need to preserve across calls.
44 TEXT cachedwb(SB), $-4
46 MOVW $cachedwb_sw(SB), R0
51 TEXT cachedwbinv(SB), $-4
53 MOVW $cachedwbinv_sw(SB), R0
58 TEXT cachedinv(SB), $-4
60 MOVW $cachedinv_sw(SB), R0
65 TEXT cacheuwbinv(SB), $-4
66 MOVM.DB.W [R14], (R13) /* save lr on stack */
70 MOVM.DB.W [R1], (R13) /* save R1 on stack */
75 MOVM.IA.W (R13), [R1] /* restore R1 (saved CPSR) */
77 MOVM.IA.W (R13), [R14] /* restore lr */
81 * architectural l2 cache operations
84 TEXT _l2cacheuwb(SB), $-4
86 MOVW $cachedwb_sw(SB), R0
89 MOVW.P 8(R13), R15 /* return */
91 TEXT _l2cacheuwbinv(SB), $-4
96 MOVM.DB.W [R1], (R13) /* save R1 on stack */
98 MOVW $cachedwbinv_sw(SB), R0
104 MOVM.IA.W (R13), [R1] /* restore R1 (saved CPSR) */
106 MOVW.P 8(R13), R15 /* return */
108 TEXT _l2cacheuinv(SB), $-4
110 MOVW $cachedinv_sw(SB), R0
113 MOVW.P 8(R13), R15 /* return */
116 * callers are assumed to be the above l1 and l2 ops.
117 * R0 is the function to call in the innermost loop.
118 * R8 is the cache level (1-origin: 1 or 2).
120 * R0 func to call at entry
121 * R1 func to call after entry
123 * R3 way shift (computed from R8)
124 * R4 set shift (computed from R8)
128 * R8 cache level, 0-origin
132 * initial translation by 5c, then massaged by hand.
134 TEXT wholecache+0(SB), $-4
136 MOVM.DB.W [R2,R14], (SP) /* save regs on stack */
138 MOVW R0, R1 /* save argument for inner loop in R1 */
139 SUB $1, R8 /* convert cache level to zero origin */
141 /* we might not have the MMU on yet, so map R1 (func) to R14's space */
142 MOVW R14, R0 /* get R14's segment ... */
144 BIC $KSEGM, R1 /* strip segment from func address */
145 ORR R0, R1 /* combine them */
147 /* get cache sizes */
148 SLL $1, R8, R0 /* R0 = (cache - 1) << 1 */
149 MTCP CpSC, CpIDcssel, R0, C(CpID), C(CpIDidct), 0 /* set cache select */
151 MFCP CpSC, CpIDcsize, R0, C(CpID), C(CpIDidct), 0 /* get cache sizes */
153 /* compute # of ways and sets for this cache level */
154 SRA $3, R0, R5 /* R5 (ways) = R0 >> 3 */
155 AND $((1<<10)-1), R5 /* R5 = (R0 >> 3) & MASK(10) */
156 ADD $1, R5 /* R5 (ways) = ((R0 >> 3) & MASK(10)) + 1 */
158 SRA $13, R0, R2 /* R2 = R0 >> 13 */
159 AND $((1<<15)-1), R2 /* R2 = (R0 >> 13) & MASK(15) */
160 ADD $1, R2 /* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
162 /* precompute set/way shifts for inner loop */
163 MOVW $(CACHECONF+0), R3 /* +0 = l1waysh */
164 MOVW $(CACHECONF+4), R4 /* +4 = l1setsh */
165 CMP $0, R8 /* cache == 1? */
166 ADD.NE $(4*2), R3 /* no, assume l2: +8 = l2waysh */
167 ADD.NE $(4*2), R4 /* +12 = l2setsh */
169 MOVW R14, R0 /* get R14's segment ... */
172 BIC $KSEGM, R3 /* strip segment from address */
173 ORR R0, R3 /* combine them */
174 BIC $KSEGM, R4 /* strip segment from address */
175 ORR R0, R4 /* combine them */
179 CMP $0, R3 /* sanity checks */
184 CPSID /* splhi to make entire op atomic */
187 /* iterate over ways */
188 MOVW $0, R7 /* R7: way */
190 /* iterate over sets */
191 MOVW $0, R6 /* R6: set */
193 /* compute set/way register contents */
194 SLL R3, R7, R0 /* R0 = way << R3 (L?WAYSH) */
195 ORR R8<<1, R0 /* R0 = way << L?WAYSH | (cache - 1) << 1 */
196 ORR R6<<R4, R0 /* R0 = way<<L?WAYSH | (cache-1)<<1 |set<<R4 */
198 BL (R1) /* call set/way operation with R0 arg. */
200 ADD $1, R6 /* set++ */
201 CMP R2, R6 /* set >= sets? */
202 BLT inner /* no, do next set */
204 ADD $1, R7 /* way++ */
205 CMP R5, R7 /* way >= ways? */
206 BLT outer /* no, do next way */
208 MOVM.IA.W (SP), [R2,R14] /* restore regs */
210 MOVW R2, CPSR /* splx */
224 MOVW $.string<>+0(SB), R0
225 BIC $KSEGM, R0 /* strip segment from address */
226 MOVW R14, R1 /* get R14's segment ... */
228 ORR R1, R0 /* combine them */
229 SUB $12, R13 /* not that it matters, since we're panicing */
231 BL panic(SB) /* panic("msg %#p", LR) */
236 DATA .string<>+0(SB)/8,$"bad cach"
237 DATA .string<>+8(SB)/8,$"e params"
238 DATA .string<>+16(SB)/8,$"\073 pc %\043p"
239 DATA .string<>+24(SB)/1,$"\z"
240 GLOBL .string<>+0(SB),$25