2 * nvidia tegra 2 architecture-specific stuff
6 #include "../port/lib.h"
10 #include "../port/error.h"
14 #include "../port/netif.h"
16 #include "../port/flashif.h"
17 #include "../port/usb.h"
18 #include "../port/portusbehci.h"
22 /* hardware limits imposed by register contents or layouts */
29 typedef struct Clkrst Clkrst;
30 typedef struct Diag Diag;
31 typedef struct Flow Flow;
32 typedef struct Scu Scu;
33 typedef struct Power Power;
45 uchar _pad0[0x24-0x1c];
46 ulong supcclkdiv; /* super cclk divider */
48 ulong supsclkdiv; /* super sclk divider */
50 uchar _pad4[0x4c-0x30];
53 uchar _pad1[0xe0-0x50];
54 ulong pllxbase; /* pllx controls CPU clock speed */
56 ulong pllebase; /* plle is dedicated to pcie */
59 uchar _pad2[0x340-0xf0];
69 Wdsel = 1<<4, /* tmr1 or tmr2? */
91 ulong ctl; /* mainly for rtc clock signals */
100 ulong dpdpadsovr; /* deep power down pads override */
108 ulong gatests; /* ro */
126 ulong autowaklvlmask;
131 ulong usbdebdel; /* usb de-bounce delay */
135 ulong scratch24[42-24+1];
136 ulong boundoutmirr[3];
138 ulong boundoutmirracc;
156 uchar _pad0[0x40-0x10];
160 uchar _pad1[0x50-0x48];
161 ulong accctl; /* initially 0 */
170 Specfill = 1<<3, /* only for PL310 */
191 Event = 1<<14, /* w1c */
192 Waitwfebitsshift = 4,
193 Waitwfebitsmask = MASK(2),
206 extern ulong testmem;
209 * number of cpus available. contrast with conf.nmach, which is number
216 .clkrst = 0x60006000, /* clock & reset signals */
218 .exceptvec = PHYSEVP, /* undocumented magic */
220 .l2cache= PHYSL2BAG, /* pl310 bag on the side */
223 /* 4 non-gic controllers */
224 // .intr = { 0x60004000, 0x60004100, 0x60004200, 0x60004300, },
226 /* private memory region */
228 /* we got this address from the `cortex-a series programmer's guide'. */
229 .intr = 0x50040100, /* per-cpu interface */
230 .glbtmr = 0x50040200,
231 .loctmr = 0x50040600,
232 .intrdist=0x50041000,
234 .uart = { 0x70006000, 0x70006040,
235 0x70006200, 0x70006300, 0x70006400, },
238 .tmr = { 0x60005000, 0x60005008, 0x60005050, 0x60005058, },
245 .nor = 0x70009000, /* also VIRTNOR */
247 .ehci = P2VAHB(0xc5000000), /* 1st of 3 */
248 .ide = P2VAHB(0xc3000000),
250 .gpio = { 0x6000d000, 0x6000d080, 0x6000d100, 0x6000d180,
251 0x6000d200, 0x6000d280, 0x6000d300, },
252 .spi = { 0x7000d400, 0x7000d600, 0x7000d800, 0x7000da00, },
254 .mmc = { P2VAHB(0xc8000000), P2VAHB(0xc8000200),
255 P2VAHB(0xc8000400), P2VAHB(0xc8000600), },
258 static volatile Diag diag;
262 dumpcpuclks(void) /* run CPU at full speed */
264 Clkrst *clk = (Clkrst *)soc.clkrst;
266 iprint("pllx base %#lux misc %#lux\n", clk->pllxbase, clk->pllxmisc);
267 iprint("plle base %#lux misc %#lux\n", clk->pllebase, clk->pllemisc);
268 iprint("super cclk divider %#lux\n", clk->supcclkdiv);
269 iprint("super sclk divider %#lux\n", clk->supsclkdiv);
275 return "ARM Cortex-A9";
283 /* convert AddrDevid register to a string in buf and return buf */
285 cputype2name(char *buf, int size)
289 r = cpidget(); /* main id register */
290 assert((r >> 24) == 'A');
291 seprint(buf, buf + size, "Cortex-A9 r%ldp%ld",
292 (r >> 20) & MASK(4), r & MASK(4));
301 /* apply cortex-a9 errata workarounds */
302 r = cpidget(); /* main id register */
303 assert((r >> 24) == 'A');
304 p = r & MASK(4); /* minor revision */
306 r &= MASK(4); /* major revision */
308 /* this is an undocumented `diagnostic register' that linux knows */
309 reg = cprdsc(0, CpDTLB, 0, 1);
310 if (r < 2 || r == 2 && p <= 2)
311 reg |= 1<<4; /* 742230 */
312 if (r == 2 && p <= 2)
313 reg |= 1<<6 | 1<<12 | 1<<22; /* 743622, 2×742231 */
315 reg |= 1<<11; /* 751472 */
316 cpwrsc(0, CpDTLB, 0, 1, reg);
326 m->cpuhz = 1000 * Mhz; /* trimslice speed */
327 p = getconf("*cpumhz");
330 if (hz >= 100*Mhz && hz <= 3600UL*Mhz)
333 m->delayloop = m->cpuhz/2000; /* initial estimate */
338 archether(unsigned ctlrno, Ether *ether)
342 ether->type = "rtl8169"; /* pci-e ether */
343 ether->ctlrno = ctlrno;
344 ether->irq = Pcieirq; /* non-msi pci-e intr */
355 Scu *scu = (Scu *)soc.scu;
357 print("cpu%d scu: accctl %#lux\n", m->machno, scu->accctl);
358 print("cpu%d scu: smp cpu bit map %#lo for %ld cpus; ", m->machno,
359 (scu->cfg >> 4) & MASK(4), (scu->cfg & MASK(2)) + 1);
360 print("cpus' power %#lux\n", scu->cpupwrsts);
366 Scu *scu = (Scu *)soc.scu;
368 if (scu->ctl & Scuenable)
370 scu->inval = MASK(16);
372 scu->ctl = Scuparity | Scuenable | Specfill;
383 if (navailcpus == 0) {
384 scu = (Scu *)soc.scu;
385 navailcpus = (scu->cfg & MASK(2)) + 1;
386 if (navailcpus > MAXMACH)
387 navailcpus = MAXMACH;
389 p = getconf("*ncpu");
392 if (n > 0 && n < navailcpus)
404 cputype2name(name, sizeof name);
405 delay(50); /* let uart catch up */
406 iprint("cpu%d: %lldMHz ARM %s %s-endian\n",
407 m->machno, m->cpuhz / Mhz, name,
408 getpsr() & PsrBigend? "big": "little");
414 Clkrst *clk = (Clkrst *)soc.clkrst;
416 /* enable all by clearing resets */
417 clk->rstdevl = clk->rstdevh = clk->rstdevu = 0;
419 clk->clkoutl = clk->clkouth = clk->clkoutu = ~0; /* enable all clocks */
422 clk->rstsrc = Wdcpurst | Wdcoprst | Wdsysrst | Wdena;
426 /* we could be shutting down ourself (if cpu == m->machno), so take care. */
430 Flow *flow = (Flow *)soc.flow;
431 Clkrst *clk = (Clkrst *)soc.clkrst;
434 iprint("stopcpu: may not stop cpu0\n");
440 active.stopped |= 1 << cpu;
444 /* shut down arm7 avp coproc so it can't cause mischief. */
445 /* could try watchdog without stopping avp. */
446 flow->haltcop = Stop;
448 flow->cop = 0; /* no Cpuenable */
452 assert(cpu < Maxflowcpus);
453 *(cpu == 0? &flow->haltcpu0: &flow->haltcpu1) = Stop;
455 *(cpu == 0? &flow->cpu0: &flow->cpu1) = 0; /* no Cpuenable */
460 assert(cpu < Maxcpus);
461 clk->cpuset = (Cpu0reset | Cpu0dbgreset | Cpu0dereset) << cpu;
469 synccpus(Ref *cntp, int n)
472 while (cntp->ref < n)
474 /* all cpus should now be here */
478 pass1(int pass, volatile Diag *dp)
484 for (i = 1000*1000; --i > 0; ) {
489 synccpus(&dp->sync, navailcpus);
490 /* all cpus are now here */
494 panic("cpu%d: diag: failed w count %ld", m->machno, dp->cnt.ref);
497 synccpus(&dp->sync, 2 * navailcpus);
498 /* all cpus are now here */
504 * try to confirm coherence of l1 caches.
505 * assume that all available cpus will be started.
519 * synchronise and print
524 iprint("l1: waiting for %d cpus... ", navailcpus);
527 synccpus(&dp->sync, navailcpus);
531 iprint("cache coherency pass");
534 synccpus(&dp->sync, 2 * navailcpus);
541 for (pass = 0; pass < 3; pass++)
545 * synchronise and check sanity
547 synccpus(&dp->sync, navailcpus);
549 if(dp->sync.ref < navailcpus || dp->sync.ref >= 2 * navailcpus)
550 panic("cpu%d: diag: failed w dp->sync %ld", m->machno,
553 panic("cpu%d: diag: failed w dp->cnt %ld", m->machno,
557 iprint(" cpu%d ok", m->machno);
560 synccpus(&dp->sync, 2 * navailcpus);
577 Clkrst *clk = (Clkrst *)soc.clkrst;
578 Flow *flow = (Flow *)soc.flow;
580 assert(cpu < Maxcpus);
582 clk->clkcpu &= ~(Cpu0stop << cpu);
585 clk->cpuclr = (Cpu0reset | Cpu0wdreset | Cpu0dbgreset | Cpu0dereset) <<
589 assert(cpu < Maxflowcpus);
590 *(cpu == 0? &flow->cpu0: &flow->cpu1) = 0;
592 *(cpu == 0? &flow->haltcpu0: &flow->haltcpu1) = 0; /* normal operat'n */
597 * this is all a bit magic. the soc.exceptvec register is effectively
598 * undocumented. we had to look at linux and experiment, alas. this is the
599 * sort of thing that should be standardised as part of the cortex mpcore spec.
600 * even intel document their equivalent procedure.
606 ulong oldvec, rstaddr;
607 ulong *evp = (ulong *)soc.exceptvec; /* magic */
610 if (getncpus() < 2 || cpu == m->machno ||
611 cpu >= MAXMACH || cpu >= navailcpus)
615 l1cache->wb(); /* start next cpu w same view of ram */
616 *evp = rstaddr = PADDR(_vrst); /* will start cpu executing at _vrst */
621 for (i = 2000; i > 0 && *evp == rstaddr; i--)
623 if (i <= 0 || *evp != cpu) {
624 iprint("cpu%d: didn't start!\n", cpu);
625 stopcpu(cpu); /* make sure it's stopped */
636 extern ulong getdebug(void);
639 panic("cpu%d: running non-secure", m->machno);
642 iprint("cpu%d: debug enable reg %#lux\n", m->machno, db);
650 /* cortex-a9 model-specific configuration */
652 putauxctl(aux | CpACsmp | CpACmaintbcast);
657 cortexa9cachecfg(void)
659 /* cortex-a9 model-specific configuration */
660 putauxctl(getauxctl() | CpACparity | CpAClwr0line | CpACl2pref);
664 * called on a cpu other than 0 from cpureset in l.s,
665 * from _vrst in lexception.s.
666 * mmu and l1 (and system-wide l2) caches and coherency (smpon) are on,
667 * but interrupts are disabled.
668 * our mmu is using an exact copy of cpu0's l1 page table
669 * as it was after userinit ran.
679 if (active.machs[m->machno]) {
682 panic("cpu%d: resetting after start", m->machno);
684 assert(m->machno != 0);
690 machinit(); /* bumps nmach, adds bit to machs */
691 machoff(m->machno); /* not ready to go yet */
693 /* clock signals and scu are system-wide and already on */
694 clockshutdown(); /* kill any watch-dog timer */
697 clockinit(); /* sets loop delay */
702 * notify cpu0 that we're up so it can proceed to l1diag.
704 evp = (ulong *)soc.exceptvec; /* magic */
708 l1diag(); /* contend with other cpus to verify sanity */
712 * pwr->detect == 0x1ff (default, all disabled)
714 pwr = (Power *)soc.power;
715 assert(pwr->gatests == MASK(7)); /* everything has power */
718 * 8169 has to initialise before we get past this, thus cpu0
719 * has to schedule processes first.
722 iprint("cpu%d: waiting for 8169\n", m->machno);
723 for (ms = 0; !l1ptstable.word && ms < 5000; ms += 10) {
725 cachedinvse(&l1ptstable.word, sizeof l1ptstable.word);
727 if (!l1ptstable.word)
728 iprint("cpu%d: 8169 unreasonably slow; proceeding\n", m->machno);
729 /* now safe to copy cpu0's l1 pt in mmuinit */
731 mmuinit(); /* update our l1 pt from cpu0's */
733 machon(m->machno); /* now ready to go and be scheduled */
736 iprint("cpu%d: scheding\n", m->machno);
738 panic("cpu%d: schedinit returned", m->machno);
741 /* mainly used to break out of wfi */
743 sgintr(Ureg *ureg, void *)
745 iprint("cpu%d: got sgi\n", m->machno);
746 /* try to prod cpu1 into life when it gets stuck */
760 /* conservative temporary values until archconfinit runs */
761 m->cpuhz = 1000 * Mhz; /* trimslice speed */
762 m->delayloop = m->cpuhz/2000; /* initial estimate */
767 /* all partitions were powered up by u-boot, so needn't do anything */
773 panic("archreset: too early for irqenable");
774 irqenable(Cpu0irq, sgintr, nil, "cpu0");
775 irqenable(Cpu1irq, sgintr, nil, "cpu1");
782 Clkrst *clk = (Clkrst *)soc.clkrst;
784 assert(m->machno == 0);
785 iprint("archreboot: reset!\n");
788 clk->rstdevl |= Sysreset;
792 /* shouldn't get here */
794 iprint("awaiting reset");
807 missing(ulong addr, char *name)
809 static int firstmiss = 1;
812 iprint("address zero for %s\n", name);
815 if (probeaddr(addr) >= 0)
823 iprint(" %s at %#lux", name, addr);
826 /* verify that all the necessary device registers are accessible */
831 missing(KZERO, "dram");
832 missing(soc.intr, "intr ctlr");
833 missing(soc.intrdist, "intr distrib");
834 missing(soc.tmr[0], "tegra timer1");
835 missing(soc.uart[0], "console uart");
836 missing(soc.pci, "pcie");
837 missing(soc.ether, "ether8169");
838 missing(soc.µs, "µs counter");
845 archflashwp(Flash*, int)
850 * for ../port/devflash.c:/^flashreset
851 * retrieve flash type, virtual base and length and return 0;
852 * return -1 on error (no flash)
855 archflashreset(int bank, Flash *f)
859 panic("archflashreset: rewrite for nor & nand flash on ts");
861 * this is set up for the igepv2 board.
864 f->addr = (void*)VIRTNOR; /* mapped here by archreset */
865 f->size = 0; /* done by probe */