2 * Memory and machine-specific definitions. Used in C and assembler.
5 #define MIN(a, b) ((a) < (b)? (a): (b))
6 #define MAX(a, b) ((a) > (b)? (a): (b))
12 #define BI2BY 8 /* bits per byte */
13 #define BI2WD 32 /* bits per word */
14 #define BY2WD 4 /* bytes per word */
15 #define BY2V 8 /* bytes per vlong */
17 #define ROUND(s, sz) (((s)+((sz)-1))&~((sz)-1))
18 #define PGROUND(s) ROUND(s, BY2PG)
20 #define MAXBY2PG (16*1024) /* rounding for UTZERO in executables; see mkfile */
21 #define UTROUND(t) ROUNDUP((t), MAXBY2PG)
24 #define BY2PG 4096 /* bytes per page */
25 #define PGSHIFT 12 /* log2(BY2PG) */
28 /* 16K pages work very poorly */
29 #define BY2PG (16*1024) /* bytes per page */
30 #define PGSHIFT 14 /* log2(BY2PG) */
34 #define KSTACK (8*1024) /* Size of kernel stack */
35 #define MACHSIZE (BY2PG+KSTACK)
36 #define WD2PG (BY2PG/BY2WD) /* words per page */
38 #define MAXMACH 1 /* max # cpus system can run; see active.machs */
39 #define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */
41 #define CACHELINESZ 32 /* mips24k */
42 #define ICACHESIZE (64*1024) /* rb450g */
43 #define DCACHESIZE (32*1024) /* rb450g */
45 #define MASK(w) FMASK(0, w)
50 #define HZ 100 /* clock frequency */
51 #define MS2HZ (1000/HZ) /* millisec per clock tick */
52 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
60 #define TLBPHYS0 2 /* aka ENTRYLO0 */
61 #define TLBPHYS1 3 /* aka ENTRYLO1 */
67 #define TLBVIRT 10 /* aka ENTRYHI */
90 #define KMODEMASK 0x0000001f
91 #define IE 0x00000001 /* master interrupt enable */
92 #define EXL 0x00000002 /* exception level */
93 #define ERL 0x00000004 /* error level */
94 #define KSUPER 0x00000008
95 #define KUSER 0x00000010
96 #define KSU 0x00000018
100 #define INTMASK 0x0000ff00
101 #define SW0 0x00000100
102 #define SW1 0x00000200
103 #define INTR0 0x00000100 /* interrupt enable bits */
104 #define INTR1 0x00000200
105 #define INTR2 0x00000400
106 #define INTR3 0x00000800
107 #define INTR4 0x00001000
108 #define INTR5 0x00002000
109 #define INTR6 0x00004000
110 #define INTR7 0x00008000
111 #define DE 0x00010000
112 #define TS 0x00200000 /* tlb shutdown; on 24k at least */
113 #define BEV 0x00400000 /* bootstrap exception vectors */
114 #define RE 0x02000000 /* reverse-endian in user mode */
115 #define FR 0x04000000 /* enable 32 FP regs */
116 #define CU0 0x10000000
117 #define CU1 0x20000000 /* FPU enable */
123 #define CFG_K0 7 /* kseg0 cachability */
124 #define CFG_MM (1<<18) /* write-through merging enabled */
130 #define BD (1<<31) /* last excep'n occurred in branch delay slot */
135 #define EXCMASK 0x1f /* mask of all causes */
136 #define CINT 0 /* external interrupt */
137 #define CTLBM 1 /* TLB modification: store to unwritable page */
138 #define CTLBL 2 /* TLB miss (load or fetch) */
139 #define CTLBS 3 /* TLB miss (store) */
140 #define CADREL 4 /* address error (load or fetch) */
141 #define CADRES 5 /* address error (store) */
142 #define CBUSI 6 /* bus error (fetch) */
143 #define CBUSD 7 /* bus error (data load or store) */
144 #define CSYS 8 /* system call */
145 #define CBRK 9 /* breakpoint */
146 #define CRES 10 /* reserved instruction */
147 #define CCPU 11 /* coprocessor unusable */
148 #define COVF 12 /* arithmetic overflow */
149 #define CTRAP 13 /* trap */
150 #define CVCEI 14 /* virtual coherence exception (instruction) */
151 #define CFPE 15 /* floating point exception */
152 #define CTLBRI 19 /* tlb read-inhibit */
153 #define CTLBXI 20 /* tlb execute-inhibit */
154 #define CWATCH 23 /* watch exception */
155 #define CMCHK 24 /* machine checkcore */
156 #define CCACHERR 30 /* cache error */
157 #define CVCED 31 /* virtual coherence exception (data) */
160 * M(CACHEECC) a.k.a. ErrCtl bits
170 #define UTLBMISS (KSEG0+0x000)
171 #define XEXCEPTION (KSEG0+0x080)
172 #define CACHETRAP (KSEG0+0x100)
173 #define EXCEPTION (KSEG0+0x180)
179 #define USER 24 /* R24 is up-> */
180 #define MACH 25 /* R25 is m-> */
182 #define UREGSIZE 0xA0 /* sizeof(Ureg)+8 */
187 #define PGSZ4K (0x00<<13)
188 #define PGSZ16K (0x03<<13) /* on 24k */
189 #define PGSZ64K (0x0F<<13)
190 #define PGSZ256K (0x3F<<13)
191 #define PGSZ1M (0xFF<<13)
192 #define PGSZ4M (0x3FF<<13)
193 #define PGSZ8M (0x7FF<<13) /* not on 24k */
194 #define PGSZ16M (0xFFF<<13)
195 #define PGSZ64M (0x3FFF<<13) /* on 24k */
196 #define PGSZ256M (0xFFFF<<13) /* on 24k */
198 /* mips address spaces, tlb-mapped unless marked otherwise */
199 #define KUSEG 0x00000000 /* user process */
200 #define KSEG0 0x80000000 /* kernel (direct mapped, cached) */
201 #define KSEG1 0xA0000000 /* kernel (direct mapped, uncached: i/o) */
202 #define KSEG2 0xC0000000 /* kernel, used for TSTKTOP */
203 #define KSEG3 0xE0000000 /* kernel, used by kmap */
204 #define KSEGM 0xE0000000 /* mask to check which seg */
207 * Fundamental addresses
210 #define REBOOTADDR KADDR(0x1000) /* just above vectors */
211 #define MACHADDR 0x88014000 /* Mach structures */
212 #define MACHP(n) ((Mach *)(MACHADDR+(n)*MACHSIZE))
213 #define KMAPADDR 0xE0000000 /* kmap'd addresses */
214 #define SPBADDR 0x80001000
219 #define PIDX ((NCOLOR-1)<<PIDXSHFT)
220 #define getpgcolor(a) (((ulong)(a)>>PIDXSHFT) % NCOLOR)
222 /* no cache aliases are possible with pages of 16K or larger */
225 #define getpgcolor(a) 0
229 #define PTEGLOBL (1<<0)
230 #define PTEVALID (1<<1)
231 #define PTEWRITE (1<<2)
233 #define PTEALGMASK (7<<3)
234 #define PTENONCOHERWT (0<<3) /* cached, write-through (slower) */
235 #define PTEUNCACHED (2<<3)
236 #define PTENONCOHERWB (3<<3) /* cached, write-back */
237 #define PTEUNCACHEDACC (7<<3)
238 /* rest are reserved on 24k */
239 #define PTECOHERXCL (4<<3)
240 #define PTECOHERXCLW (5<<3)
241 #define PTECOHERUPDW (6<<3)
243 /* how much faster is it? mflops goes from about .206 (WT) to .37 (WB) */
244 // #define PTECACHABILITY PTENONCOHERWT /* 24k erratum 48 disallows WB */
245 #define PTECACHABILITY PTENONCOHERWB
247 #define PTEPID(n) (n)
248 #define PTEMAPMEM (1024*1024)
249 #define PTEPERTAB (PTEMAPMEM/BY2PG)
250 #define SEGMAPSIZE 512
251 #define SSEGMAPSIZE 16
254 #define STLBSIZE (1<<STLBLOG) /* entries in the soft TLB */
255 /* page # bits that don't fit in STLBLOG bits */
256 #define HIPFNBITS (BI2WD - (PGSHIFT+1) - STLBLOG)
258 #define KPTESIZE (1<<KPTELOG) /* entries in the kfault soft TLB */
260 #define TLBPID(n) ((n)&0xFF)
261 #define NTLBPID 256 /* # of pids (affects size of Mach) */
262 #define NTLB 48 /* # of entries (r4k) */
263 #define TLBOFF 1 /* first tlb entry (0 used within mmuswitch) */
264 #define NKTLB 2 /* # of initial kfault tlb entries */
265 #define TLBROFF (TLBOFF+NKTLB) /* first large IO window tlb entry */
270 #define UZERO KUSEG /* base of user address space */
271 #define UTZERO (UZERO+MAXBY2PG) /* 1st user text address; see mkfile */
272 #define USTKTOP (KZERO-BY2PG) /* byte just beyond user stack */
273 #define USTKSIZE (8*1024*1024) /* size of user stack */
274 #define TSTKTOP (KSEG2+USTKSIZE-BY2PG) /* top of temporary stack */
275 #define TSTKSIZ (1024*1024/BY2PG) /* can be at most UTSKSIZE/BY2PG */
276 #define KZERO KSEG0 /* base of kernel address space */
277 #define KTZERO (KZERO+0x08020000) /* first address in kernel text */