sys/src/9/ppc/m8260.h

   1
   2 typedef struct BD BD;
   3 struct BD {
   4         ushort  status;
   5         ushort  length;
   6         ulong   addr;
   7 };
   8
   9 enum{
  10         BDEmpty=        SBIT(0),
  11         BDReady=        SBIT(0),
  12         BDWrap=         SBIT(2),
  13         BDInt=          SBIT(3),
  14         BDLast=         SBIT(4),
  15         BDFirst=        SBIT(5),
  16 };
  17
  18 typedef struct Ring Ring;
  19
  20 struct Ring {
  21         BD*     rdr;            /* receive descriptor ring */
  22         void*   rrb;            /* receive ring buffers */
  23         int     rdrx;           /* index into rdr */
  24         int     nrdre;          /* length of rdr */
  25
  26         BD*     tdr;            /* transmit descriptor ring */
  27         void**  txb;            /* corresponding transmit ring buffers */
  28         int     tdrh;           /* host index into tdr */
  29         int     tdri;           /* interface index into tdr */
  30         int     ntdre;          /* length of tdr */
  31         int     ntq;            /* pending transmit requests */
  32 };
  33
  34 int     ioringinit(Ring*, int, int, int);
  35
  36 /*
  37  * MCC parameters
  38  */
  39 typedef struct MCCparam MCCparam;
  40 struct MCCparam {
  41 /*0x00*/        ulong   mccbase;
  42 /*0x04*/        ushort  mccstate;
  43 /*0x06*/        ushort  mrblr;
  44 /*0x08*/        ushort  grfthr;
  45 /*0x0a*/        ushort  grfcnt;
  46 /*0x0c*/        ulong   rinttmp;
  47 /*0x10*/        ulong   data0;
  48 /*0x14*/        ulong   data1;
  49 /*0x18*/        ulong   tintbase;
  50 /*0x1c*/        ulong   tintptr;
  51 /*0x20*/        ulong   tinttmp;
  52 /*0x24*/        ushort  sctpbase;
  53 /*0x26*/        ushort  Rsvd26;
  54 /*0x28*/        ulong   cmask32;
  55 /*0x2c*/        ushort  xtrabase;
  56 /*0x2e*/        ushort  cmask16;
  57 /*0x30*/        ulong   rinttmp[4];
  58 /*0x40*/        struct {
  59                         ulong   base;
  60                         ulong   ptr;
  61                 }               rint[4];
  62 /*0x60*/        ulong   tstmp;
  63 /*0x64*/
  64 };
  65 /*
  66  * IO controller parameters
  67  */
  68 typedef struct IOCparam IOCparam;
  69 struct IOCparam {
  70 /*0x00*/        ushort  rbase;
  71 /*0x02*/        ushort  tbase;
  72 /*0x04*/        uchar   rfcr;
  73 /*0x05*/        uchar   tfcr;
  74 /*0x06*/        ushort  mrblr;
  75 /*0x08*/        ulong   rstate;
  76 /*0x0c*/        ulong   rxidp;
  77 /*0x10*/        ushort  rbptr;
  78 /*0x12*/        ushort  rxibc;
  79 /*0x14*/        ulong   rxtemp;
  80 /*0x18*/        ulong   tstate;
  81 /*0x1c*/        ulong   txidp;
  82 /*0x20*/        ushort  tbptr;
  83 /*0x22*/        ushort  txibc;
  84 /*0x24*/        ulong   txtemp;
  85 /*0x28*/
  86 };
  87
  88 typedef struct SCCparam SCCparam;
  89 struct SCCparam {
  90         IOCparam;
  91         ulong   rcrc;
  92         ulong   tcrc;
  93 };
  94
  95 typedef struct FCCparam FCCparam;
  96 struct FCCparam {
  97 /*0x00*/        ushort  riptr;
  98 /*0x02*/        ushort  tiptr;
  99 /*0x04*/        ushort  Rsvd04;
 100 /*0x06*/        ushort  mrblr;
 101 /*0x08*/        ulong   rstate;
 102 /*0x0c*/        ulong   rbase;
 103 /*0x10*/        ushort  rbdstat;
 104 /*0x12*/        ushort  rbdlen;
 105 /*0x14*/        char*   rdptr;
 106 /*0x18*/        ulong   tstate;
 107 /*0x1c*/        ulong   tbase;
 108 /*0x20*/        ushort  tbdstat;
 109 /*0x22*/        ushort  tbdlen;
 110 /*0x24*/        ulong   tdptr;
 111 /*0x28*/        ulong   rbptr;
 112 /*0x2c*/        ulong   tbptr;
 113 /*0x30*/        ulong   rcrc;
 114 /*0x34*/        ulong   Rsvd34;
 115 /*0x38*/        ulong   tcrc;
 116 /*0x3c*/
 117 };
 118
 119 typedef struct SCC SCC;
 120 struct SCC {
 121         ulong   gsmrl;
 122         ulong   gsmrh;
 123         ushort  psmr;
 124         uchar   rsvscc0[2];
 125         ushort  todr;
 126         ushort  dsr;
 127         ushort  scce;
 128         uchar   rsvscc1[2];
 129         ushort  sccm;
 130         uchar   rsvscc2;
 131         uchar   sccs;
 132         ushort  irmode;
 133         ushort  irsip;
 134         uchar   rsvscc3[4];     /* BUG */
 135 };
 136
 137 typedef struct FCC FCC;
 138 struct FCC {
 139 /*0x00*/        ulong   gfmr;           /*  general mode register 28.2/28-3 */
 140 /*0x04*/        ulong   fpsmr;          /*  protocol-specific mode reg. 29.13.2(ATM) 30.18.1(Ether) */
 141 /*0x08*/        ushort  ftodr;          /*  transmit on demand register 28.5/28-7 */
 142 /*0x0A*/        ushort  Rsvd0A;
 143 /*0x0C*/        ushort  fdsr;           /*  data synchronization register 28.4/28-7 */
 144 /*0x0E*/        ushort  Rsvd0E;
 145 /*0x10*/        ushort  fcce;           /* event register 29.13.3 (ATM), 30.18.2 (Ethernet) */
 146 /*0x12*/        ushort  Rsvd12;
 147 /*0x14*/        ushort  fccm;           /* mask register */
 148 /*0x16*/        ushort  Rsvd16;
 149 /*0x18*/        uchar   fccs;           /* status register 8 bits 31.10 (HDLC) */
 150 /*0x19*/        uchar   Rsvd19[3];
 151 /*0x1C*/        uchar   ftirrphy[4];    /* transmit internal rate registers for PHY0DH3 29.13.4/29-88 (ATM) */
 152 /*0x20*/
 153 };
 154
 155 typedef struct SMC SMC;
 156 struct SMC {
 157 /*0x0*/ ushort  pad1;
 158 /*0x2*/ ushort  smcmr;
 159 /*0x4*/ ushort  pad2;
 160 /*0x6*/ uchar   smce;
 161 /*0x7*/ uchar   pad3[3];
 162 /*0xa*/ uchar   smcm;
 163 /*0xb*/ uchar   pad4[5];
 164 /*0x10*/
 165 };
 166
 167 typedef struct SPI SPI;
 168 struct SPI {
 169         ushort  spmode;
 170         uchar   res1[4];
 171         uchar   spie;
 172         uchar   res2[3];
 173         uchar   spim;
 174         uchar   res3[2];
 175         uchar   spcom;
 176         uchar   res4[2];
 177 };
 178
 179 typedef struct Bankmap Bankmap;
 180 struct Bankmap {
 181 /*0*/   ulong   br;             /*  Base register bank 32 bits 10.3.1/10-14 */
 182 /*4*/   ulong   or;             /*  Option register bank 32 bits 10.3.2/10-16 */
 183 /*8*/
 184 };
 185
 186 typedef struct Port Port;
 187 struct Port {
 188 /*0x00*/        ulong   pdir;           /*  Port A data direction register 32 bits 35.2.3/35-3 */
 189 /*0x04*/        ulong   ppar;   /*  Port Apin assignment register 32 bits 35.2.4/35-4 */
 190 /*0x08*/        ulong   psor;           /*  Port A special options register 32 bits 35.2.5/35-4 */
 191 /*0x0C*/        ulong   podr;   /*  Port Aopen drain register 32 bits 35.2.1/35-2 */
 192 /*0x10*/        ulong   pdat;           /*  Port A data register 32 bits 35.2.2/35-2 */
 193 /*0x14*/        uchar   Rsvd14[12];
 194 /*0x20*/
 195 };
 196
 197 typedef struct IDMA IDMA;
 198 struct IDMA {
 199 /*0x0*/ uchar   idsr;           /*  IDMA event register 8 bits 18.8.4/18-22 */
 200 /*0x1*/ uchar   Rsvd1[3];
 201 /*0x4*/ uchar   idmr;   /*  IDMA mask register 8 bits 18.8.4/18-22 */
 202 /*0x5*/ uchar   Rsvd5[3];
 203 /*0x8*/
 204 };
 205
 206 typedef struct PrmSCC PrmSCC;
 207 struct PrmSCC {
 208         uchar   sccbytes[0x100];
 209 };
 210
 211 typedef struct PrmFCC PrmFCC;
 212 struct PrmFCC {
 213         uchar   fccbytes[0x100];
 214 };
 215
 216 typedef struct Bases Bases;
 217 struct Bases {
 218 /*0x00*/        uchar   mcc[0x80];
 219 /*0x80*/        uchar   Rsvd80[0x60];
 220 /*0xe0*/        uchar   risctimers[0x10];
 221 /*0xf0*/        ushort  revnum;
 222 /*0xf2*/        uchar   Rsvdf2[6];
 223 /*0xf8*/        ulong   rand;
 224 /*0xfc*/        ushort  smcbase;
 225 #define i2cbase smcbase
 226 /*0xfe*/        ushort  idmabase;
 227 /*0x100*/
 228 };
 229
 230 typedef struct Uartsmc Uartsmc;
 231 struct Uartsmc {
 232 /*0x00*/        IOCparam;
 233 /*0x28*/        ushort  maxidl;
 234 /*0x2a*/        ushort  idlc;
 235 /*0x2c*/        ushort  brkln;
 236 /*0x2e*/        ushort  brkec;
 237 /*0x30*/        ushort  brkcr;
 238 /*0x32*/        ushort  r_mask;
 239 /*0x34*/        ulong   sdminternal;
 240 /*0x38*/        uchar   Rsvd38[8];
 241 /*0x40*/
 242 };
 243
 244 typedef struct SI SI;
 245 struct SI {
 246 /*0x11B20*/     ushort  siamr;          /*  SI TDMA1 mode register 16 bits 14.5.2/14-17 */
 247 /*0x11B22*/     ushort  sibmr;          /*  SI TDMB1 mode register 16 bits */
 248 /*0x11B24*/     ushort  sicmr;          /*  SI TDMC1 mode register 16 bits */
 249 /*0x11B26*/     ushort  sidmr;          /*  SI TDMD1 mode register 16 bits */
 250 /*0x11B28*/     uchar   sigmr;          /*  SI global mode register 8 bits 14.5.1/14-17 */
 251 /*0x11B29*/     uchar   Rsvd11B29;
 252 /*0x11B2A*/     ushort  sicmdr;         /*  SI command register 8 bits 14.5.4/14-24 */
 253 /*0x11B2C*/     ushort  sistr;                  /*  SI status register 8 bits 14.5.5/14-25 */
 254 /*0x11B2E*/     ushort  sirsr;                  /*  SI RAM shadow address register 16 bits 14.5.3/14-23 */
 255 };
 256
 257 typedef struct IMM IMM;
 258 struct IMM {
 259 /* General SIU */
 260 /*0x10000*/     ulong   siumcr;         /*  SIU module configuration register 32 bits 4.3.2.6/4-31 */
 261 /*0x10004*/     ulong   sypcr;          /*  System protection control register 32 bits 4.3.2.8/4-35 */
 262 /*0x10008*/     uchar   Rsvd10008[0xe-0x8];
 263 /*0x1000E*/     ushort  swsr;           /*  Softwareservice register 16 bits 4.3.2.9/4-36 */
 264 /*0x10010*/     uchar   Rsvd10010[0x14];
 265 /*0x10024*/     ulong   bcr;                    /*  Bus configuration register 32 bits 4.3.2.1/4-25 */
 266 /*0x10028*/     ulong   PPC_ACR;                /*  60x bus arbiter configuration register 8 bits 4.3.2.2/4-28 */
 267 /*0x1002C*/     ulong   PPCALRH;                /*  60x bus arbitration-level register high (first 8 clients) 32 bits 4.3.2.3/4-28 */
 268 /*0x10030*/     ulong   PPC_ALRL;       /*  60x bus arbitration-level register low (next 8 clients) 32 bits 4.3.2.3/4-28 */
 269 /*0x10034*/     ulong   LCL_ACR;                /*  Local arbiter configuration register 8 bits 4.3.2.4/4-29 */
 270 /*0x10038*/     ulong   LCL_ALRH;       /*  Local arbitration-level register (first 8 clients) 32 bits 4.3.2.5/4-30 */
 271
 272 /*0x1003C*/     ulong   LCL_ALRL;       /*  Local arbitration-level register (next 8 clients) 32 bits 4.3.2.3/4-28 */
 273 /*0x10040*/     ulong   TESCR1;         /*  60x bus transfer error status control register1 32 bits 4.3.2.10/4-36 */
 274 /*0x10044*/     ulong   TESCR2;         /*  60x bus transfer error status control register2 32 bits 4.3.2.11/4-37 */
 275 /*0x10048*/     ulong   L_TESCR1;       /*  Local bus transfer error status control register1 32 bits 4.3.2.12/4-38 */
 276 /*0x1004C*/     ulong   L_TESCR2;       /*  Local bus transfer error status control register2 32 bits 4.3.2.13/4-39 */
 277 /*0x10050*/     ulong   pdtea;          /*  60x bus DMAtransfer error address 32 bits 18.2.3/18-4 */
 278 /*0x10054*/     uchar   pdtem;          /*  60x bus DMAtransfer error MSNUM 8 bits 18.2.4/18-4 */
 279 /*0x10055*/     uchar   Rsvd10055[3];
 280 /*0x10058*/     void*   ldtea;          /*  Local bus DMA transfer error address 32 bits 18.2.3/18-4 */
 281 /*0x1005C*/     uchar   ldtem;          /*  Local bus DMA transfer error MSNUM 8 bits 18.2.4/18-4 */
 282 /*0x1005D*/     uchar   Rsvd1005D[163];
 283
 284 /* Memory Controller */
 285 /*0x10100*/     Bankmap bank[12];
 286
 287 /*0x10160*/     uchar   Rsvd10160[8];
 288 /*0x10168*/     void*   MAR;            /*  Memory address register 32 bits 10.3.7/10-29 */
 289 /*0x1016C*/     ulong   Rsvd1016C;
 290 /*0x10170*/     ulong   MAMR;           /*  Machine A mode register 32 bits 10.3.5/10-26 */
 291 /*0x10174*/     ulong   MBMR;           /*  Machine B mode register 32 bits */
 292 /*0x10178*/     ulong   MCMR;           /*  Machine C mode register 32 bits */
 293 /*0x1017C*/     uchar   Rsvd1017C[6];
 294 /*0x10184*/     ulong   mptpr;          /*  Memory periodic timer prescaler 16 bits 10.3.12/10-32 */
 295 /*0x10188*/     ulong   mdr;                    /*  Memorydata register 32 bits 10.3.6/10-28 */
 296 /*0x1018C*/     ulong   Rsvd1018C;
 297 /*0x10190*/     ulong   psdmr;          /*  60x bus SDRAM mode register 32 bits 10.3.3/10-21 */
 298 /*0x10194*/     ulong   lsdmr;          /*  Local bus SDRAM mode register 32 bits 10.3.4/10-24 */
 299 /*0x10198*/     ulong   PURT;           /*  60x bus-assigned UPM refresh timer 8 bits 10.3.8/10-30 */
 300 /*0x1019C*/     ulong   PSRT;           /*  60x bus-assigned SDRAM refresh timer 8 bits 10.3.10/10-31 */
 301
 302 /*0x101A0*/     ulong   LURT;           /*  Local bus-assigned UPM refresh timer8 bits 10.3.9/10-30 */
 303 /*0x101A4*/     ulong   LSRT;           /*  Local bus-assigned SDRAM refresh timer 8 bits 10.3.11/10-32 */
 304
 305 /*0x101A8*/     ulong   immr;           /*  Internal memory map register 32 bits 4.3.2.7/4-34 */
 306 /*0x101AC*/     uchar   Rsvd101AC[84];
 307 /* System Integration Timers */
 308 /*0x10200*/     uchar   Rsvd10200[32];
 309 /*0x10220*/     ulong   TMCNTSC;        /*  Time counter statusand control register 16 bits 4.3.2.14/4-40 */
 310
 311 /*0x10224*/     ulong   TMCNT;          /*  Time counter register 32 bits 4.3.2.15/4-41 */
 312 /*0x10228*/     ulong   Rsvd10228;
 313 /*0x1022C*/     ulong   TMCNTAL;        /*  Time counter alarm register 32 bits 4.3.2.16/4-41 */
 314 /*0x10230*/     uchar   Rsvd10230[0x10];
 315 /*0x10240*/     ulong   PISCR;          /*  Periodic interrupt statusand control register 16 bits 4.3.3.1/4-42 */
 316
 317 /*0x10244*/     ulong   PITC;           /*  Periodic interrupt count register 32 bits 4.3.3.2/4-43 */
 318 /*0x10248*/     ulong   PITR;                   /*  Periodic interrupt timer register 32 bits 4.3.3.3/4-44 */
 319 /*0x1024C*/     uchar   Rsvd1024C[94];
 320 /*0x102AA*/     uchar   Rsvd102AA[2390];
 321
 322 /* Interrupt Controller */
 323 /*0x10C00*/     ushort  sicr;                   /*  SIU interrupt configuration register 16 bits 4.3.1.1/4-17 */
 324 /*0x10C02*/     ushort  Rsvd10C02;
 325 /*0x10C04*/     ulong   sivec;          /*  SIU interrupt vector register 32 bits 4.3.1.6/4-23 */
 326 /*0x10C08*/     ulong   sipnr_h;                /*  SIU interrupt pending register(high) 32 bits 4.3.1.4/4-21 */
 327 /*0x10C0C*/     ulong   sipnr_l;                /*  SIU interrupt pending register(low) 32 bits 4.3.1.4/4-21 */
 328 /*0x10C10*/     ulong   siprr;          /*  SIU interrupt priority register 32 bits 4.3.1.2/4-18 */
 329 /*0x10C14*/     ulong   scprr_h;                /*  CPM interrupt priority register(high) 32 bits 4.3.1.3/4-19 */
 330 /*0x10C18*/     ulong   scprr_l;                /*  CPM interrupt priority register(low) 32 bits 4.3.1.3/4-19 */
 331 /*0x10C1C*/     ulong   simr_h;         /*  SIU interrupt mask register(high) 32 bits 4.3.1.5/4-22 */
 332 /*0x10C20*/     ulong   simr_l;         /*  SIU interrupt mask register(low) 32 bits 4.3.1.5/4-22 */
 333 /*0x10C24*/     ulong   siexr;          /*  SIUexternal interrupt control register 32 bits 4.3.1.7/4-24 */
 334 /*0x10C28*/     uchar   Rsvd10C28[88];
 335
 336 /* Clocksand Reset */
 337 /*0x10C80*/     ulong   sccr;                   /*  Systemclock control register 32 bits 9.8/9-8 */
 338 /*0x10C84*/     uchar   Rsvd10C84[4];
 339 /*0x10C88*/     ulong   scmr;           /*  Systemclock mode register 32 bits 9.9/9-9 */
 340 /*0x10C8C*/     uchar   Rsvd10C8C[4];
 341 /*0x10C90*/     ulong   rsr;                    /*  Reset status register 32 bits 5.2/5-4 */
 342 /*0x10C94*/     ulong   rmr;                    /*  Reset mode register 32 bits 5.3/5-5 */
 343 /*0x10C98*/     uchar   Rsvd10C98[104];
 344
 345 /* Part I.Overview Input/Output Port */
 346 /*0x10D00*/     Port            port[4];
 347
 348 /* CPMTimers */
 349 /*0x10D80*/     uchar   tgcr1;          /*  Timer1 and timer2 global configuration register 8 bits 17.2.2/17-4 */
 350
 351 /*0x10D81*/     uchar   Rsvd10D81[3];
 352 /*0x10D84*/     uchar   tgcr2;          /*  Timer3 and timer4 global configuration register 8 bits 17.2.2/17-4 */
 353 /*0x10D85*/     uchar   Rsvd10D85[3];
 354
 355 /*0x10D88*/     uchar   Rsvd10D88[8];
 356 /*0x10D90*/     ushort  tmr1;           /*  Timer1 mode register 16 bits 17.2.3/17-6 */
 357 /*0x10D92*/     ushort  tmr2;           /*  Timer2 mode register 16 bits 17.2.3/17-6 */
 358                 union{
 359                         struct {
 360 /*0x10D94*/     ushort  trr1;                   /*  Timer1 reference register 16 bits 17.2.4/17-7 */
 361 /*0x10D96*/     ushort  trr2;                   /*  Timer2 reference register 16 bits 17.2.4/17-7 */
 362                         };
 363 /*0x10D94*/     ulong   trrl1;                  /*  Combined Timer 1/2 trr register */
 364                 };
 365                 union{
 366                         struct {
 367 /*0x10D98*/     ushort  tcr1;                   /*  Timer1 capture register 16 bits 17.2.5/17-8 */
 368 /*0x10D9A*/     ushort  tcr2;                   /*  Timer2 capture register 16 bits 17.2.5/17-8 */
 369                         };
 370 /*0x10D98*/     ulong   tcrl1;          /*  Combined timer1/2 capture register */
 371                 };
 372                 union{
 373                         struct {
 374 /*0x10D9C*/     ushort  tcn1;                   /*  Timer1 counter 16 bits 17.2.6/17-8 */
 375 /*0x10D9E*/     ushort  tcn2;                   /*  Timer2 counter 16 bits 17.2.6/17-8 */
 376                         };
 377 /*0x10D9C*/     ulong   tcnl1;          /*  Combined timer1/2 counter */
 378                 };
 379 /*0x10DA0*/     ushort  tmr3;           /*  Timer3 mode register 16 bits 17.2.3/17-6 */
 380 /*0x10DA2*/     ushort  tmr4;           /*  Timer4 mode register 16 bits 17.2.3/17-6 */
 381                 union{
 382                         struct {
 383 /*0x10DA4*/     ushort  trr3;                   /*  Timer3 reference register 16 bits 17.2.4/17-7 */
 384 /*0x10DA6*/     ushort  trr4;                   /*  Timer4 reference register 16 bits 17.2.4/17-7 */
 385                         };
 386 /*0x10DA4*/     ulong   trrl3;
 387                 };
 388                 union{
 389                         struct {
 390 /*0x10DA8*/     ushort  tcr3;                   /*  Timer3 capture register 16 bits 17.2.5/17-8 */
 391 /*0x10DAA*/     ushort  tcr4;                   /*  Timer4 capture register 16 bits 17.2.5/17-8 */
 392                         };
 393 /*0x10DA8*/     ulong   tcrl3;
 394                 };
 395                 union{
 396                         struct {
 397 /*0x10DAC*/     ushort  tcn3;                   /*  Timer3 counter 16 bits 17.2.6/17-8 */
 398 /*0x10DAE*/     ushort  tcn4;                   /*  Timer4 counter 16 bits 17.2.6/17-8 */
 399                         };
 400 /*0x10DAC*/     ulong   tcnl3;
 401                 };
 402 /*0x10DB0*/     ushort  ter1;                   /*  Timer1 event register 16 bits 17.2.7/17-8 */
 403 /*0x10DB2*/     ushort  ter2;                   /*  Timer2 event register 16 bits 17.2.7/17-8 */
 404 /*0x10DB4*/     ushort  ter3;                   /*  Timer3 event register 16 bits 17.2.7/17-8 */
 405 /*0x10DB6*/     ushort  ter4;                   /*  Timer4 event register 16 bits 17.2.7/17-8 */
 406 /*0x10DB8*/     uchar   Rsvd10DB8[608];
 407
 408 /* SDMADHGeneral */
 409 /*0x11018*/     uchar   sdsr;                   /*  SDMA status register 8 bits 18.2.1/18-3 */
 410 /*0x11019*/     uchar   Rsvd11019[3];
 411 /*0x1101C*/     uchar   sdmr;           /*  SDMA mask register 8 bits 18.2.2/18-4 */
 412 /*0x1101D*/     uchar   Rsvd1101D[3];
 413
 414 /* IDMA */
 415 /*0x11020*/     IDMA    idma[4];
 416
 417 /*0x11040*/     uchar   Rsvd11040[704];
 418
 419 /*0x11300*/     FCC             fcc[3];
 420
 421 /*0x11360*/     uchar   Rsvd11360[0x290];
 422
 423 /* BRGs5DH8 */
 424 /*0x115F0*/     ulong   BRGC5;          /*  BRG5 configuration register 32 bits 16.1/16-2 */
 425 /*0x115F4*/     ulong   BRGC6;          /*  BRG6configuration register 32 bits */
 426 /*0x115F8*/     ulong   BRGC7;          /*  BRG7configuration register 32 bits */
 427 /*0x115FC*/     ulong   BRGC8;          /*  BRG8configuration register 32 bits */
 428 /*0x11600*/     uchar   Rsvd11600[0x260];
 429 /*0x11860*/     uchar   I2MOD;          /*  I2C mode register 8 bits 34.4.1/34-6 */
 430 /*0x11861*/     uchar   Rsvd11861[3];
 431 /*0x11864*/     uchar   I2ADD;          /*  I2C address register 8 bits 34.4.2/34-7 */
 432 /*0x11865*/     uchar   Rsvd11865[3];
 433 /*0x11868*/     uchar   I2BRG;          /*  I2C BRG register 8 bits 34.4.3/34-7 */
 434 /*0x11869*/     uchar   Rsvd11869[3];
 435 /*0x1186C*/     uchar   I2COM;          /*  I2C command register 8 bits 34.4.5/34-8 */
 436 /*0x1186D*/     uchar   Rsvd1186D[3];
 437 /*0x11870*/     uchar   I2CER;          /*  I2C event register 8 bits 34.4.4/34-8 */
 438 /*0x11871*/     uchar   Rsvd11871[3];
 439 /*0x11874*/     uchar   I2CMR;          /*  I2C mask register 8 bits 34.4.4/34-8 */
 440 /*0x11875*/     uchar   Rsvd11875[331];
 441
 442 /* Communications Processor */
 443 /*0x119C0*/     ulong   cpcr;           /*  Communications processor command register 32 bits 13.4.1/13-11 */
 444
 445 /*0x119C4*/     ulong   rccr;           /*  CP configuration register 32 bits 13.3.6/13-7 */
 446 /*0x119C8*/     uchar   Rsvd119C8[14];
 447 /*0x119D6*/     ushort  rter;           /*  CP timers event register 16 bits 13.6.4/13-21 */
 448 /*0x119D8*/     ushort  Rsvd119D8;
 449 /*0x119DA*/     ushort  rtmr;           /*  CP timers mask register 16 bits */
 450 /*0x119DC*/     ushort  rtscr;          /*  CPtime-stamp timer control register 16 bits 13.3.7/13-9 */
 451 /*0x119DE*/     ushort  Rsvd119DE;
 452 /*0x119E0*/     ulong   rtsr;           /*  CPtime-stamp register 32 bits 13.3.8/13-10 */
 453 /*0x119E4*/     uchar   Rsvd119E4[12];
 454
 455 /*0x119F0*/     ulong   brgc[4];                /*  BRG configuration registers 32 bits 16.1/16-2 */
 456
 457 /*0x11A00*/     SCC             scc[4];
 458
 459 /*0x11A80*/     SMC             smc[2];
 460
 461                         SPI             spi;
 462
 463 /*0x11AB0*/     uchar   Rsvd11AB0[80];
 464
 465 /* CPMMux */
 466 /*0x11B00*/     uchar   cmxsi1cr;       /*  CPM mux SI1clock route register 8 bits 15.4.2/15-10 */
 467 /*0x11B01*/     uchar   Rsvd11B01;
 468 /*0x11B02*/     uchar   cmxsi2cr;       /*  CPM mux SI2clock route register 8 bits 15.4.3/15-11 */
 469 /*0x11B03*/     uchar   Rsvd11B03;
 470 /*0x11B04*/     ulong   cmxfcr; /*  CPM mux FCC clock route register 32 bits 15.4.4/15-12 */
 471 /*0x11B08*/     ulong   cmxscr; /*  CPM mux SCC clock route register 32 bits 15.4.5/15-14 */
 472 /*0x11B0C*/     uchar   cmxsmr; /*  CPM mux SMC clock route register 8 bits 15.4.6/15-17 */
 473 /*0x11B0D*/     uchar   Rsvd11B0D;
 474 /*0x11B0E*/     ushort  cmxuar; /*  CPM mux UTOPIA address register 16 bits 15.4.1/15-7 */
 475 /*0x11B10*/     uchar   Rsvd11B10[16];
 476
 477                         SI              si1;                    /* SI 1 Registers */
 478
 479 /* MCC1Registers */
 480 /*0x11B30*/     ushort  MCCE1;          /*  MCC1 event register 16 bits 27.10.1/27-18 */
 481 /*0x11B32*/     ushort  Rsvd11B32;
 482 /*0x11B34*/     ushort  MCCM1;          /*  MCC1 mask register 16 bits */
 483 /*0x11B36*/     ushort  Rsvd11B36;
 484 /*0x11B38*/     uchar   MCCF1;          /*  MCC1 configuration register 8 bits 27.8/27-15 */
 485 /*0x11B39*/     uchar   Rsvd11B39[7];
 486
 487                         SI              si2;                    /* SI 2 Registers */
 488
 489 /* MCC2Registers */
 490 /*0x11B50*/     ushort  MCCE2;          /*  MCC2 event register 16 bits 27.10.1/27-18 */
 491 /*0x11B52*/     ushort  Rsvd11B52;
 492 /*0x11B54*/     ushort  MCCM2;          /*  MCC2 mask register 16 bits */
 493 /*0x11B56*/     ushort  Rsvd11B56;
 494 /*0x11B58*/     uchar   MCCF2;          /*  MCC2 configuration register 8 bits 27.8/27-15 */
 495 /*0x11B59*/     uchar   Rsvd11B59[1191];
 496
 497 /* SI1RAM */
 498 /*0x12000*/     uchar   SI1TxRAM[0x200];/*  SI1 transmit routing RAM    512 14.4.3/14-10 */
 499 /*0x12200*/     uchar   Rsvd12200[0x200];
 500 /*0x12400*/     uchar   SI1RxRAM[0x200];/*  SI1 receive routing RAM     512 14.4.3/14-10 */
 501 /*0x12600*/     uchar   Rsvd12600[0x200];
 502
 503 /* SI2RAM */
 504 /*0x12800*/     uchar   SI2TxRAM[0x200];/*  SI2 transmit routing RAM    512 14.4.3/14-10 */
 505 /*0x12A00*/     uchar   Rsvd12A00[0x200];
 506 /*0x12C00*/     uchar   SI2RxRAM[0x200];/*  SI2 receive routing RAM     512 14.4.3/14-10 */
 507 /*0x12E00*/     uchar   Rsvd12E00[0x200];
 508 /*0x13000*/     uchar   Rsvd13000[0x800];
 509 /*0x13800*/     uchar   Rsvd13800[0x800];
 510 };
 511
 512 typedef struct FCCextra FCCextra;
 513 struct FCCextra {
 514 /*0x00*/        uchar   ri[0x20];
 515 /*0x20*/        uchar   ti[0x20];
 516 /*0x40*/        uchar   pad[0x20];
 517 };
 518
 519 typedef struct Imap Imap;
 520 struct Imap {
 521 /* CPMDual-Port RAM */
 522 /*0x00000*/     uchar   dpram1[0x3800]; /*  Dual-port RAM       16Kbytes 13.5/13-15 */
 523 /*0x03800*/     FCCextra        fccextra[4];
 524 /*0x03980*/     Uartsmc uartsmc[2];
 525 /*0x03a00*/     uchar   dsp1p[0x40];
 526 /*0x03a40*/     uchar   dsp2p[0x40];
 527 /*0x03a80*/     BD              bd[(0x04000-0x03a80)/sizeof(BD)];       /* Buffer descriptors */
 528 /*0x04000*/     uchar   Rsvd4000[0x04000];
 529
 530 /* Dual port RAM bank 2 -- Parameter Ram, Section 13.5 */
 531 /*0x08000*/     PrmSCC  prmscc[4];
 532 /*0x08400*/     PrmFCC  prmfcc[3];
 533 /*0x08700*/     Bases   param[4];
 534 /*0x08b00*/     uchar   dpram2[0x500];
 535
 536 /*0x09000*/     uchar   Rsvd9000[0x2000];
 537
 538 /* Dual port RAM bank 3 -- Section 13.5 */
 539 /*0x0B000*/     uchar   dpram3[0x1000]; /*  Dual-port RAM       4Kbytes 13.5/13-15 */
 540 /*0x0C000*/     uchar   Rsvdc000[0x4000];
 541
 542 /*0x10000*/     IMM;
 543 };
 544
 545 enum {
 546 /* CPM Command register. */
 547         cpm_rst         = 0x80000000,
 548         cpm_page        = 0x7c000000,
 549         cpm_sblock      = 0x03e00000,
 550         cpm_flg         = 0x00010000,
 551         cpm_mcn         = 0x00003fc0,
 552         cpm_opcode      = 0x0000000f,
 553
 554 /* Device sub-block and page codes. */
 555         cpm_fcc1_sblock = 0x10,
 556         cpm_fcc2_sblock = 0x11,
 557         cpm_fcc3_sblock = 0x12,
 558         cpm_scc1_sblock = 0x04,
 559         cpm_scc2_sblock = 0x05,
 560         cpm_scc3_sblock = 0x06,
 561         cpm_scc4_sblock = 0x07,
 562         cpm_smc1_sblock = 0x08,
 563         cpm_smc2_sblock = 0x09,
 564         cpm_rand_sblock = 0x0e,
 565         cpm_spi_sblock  = 0x0a,
 566         cpm_i2c_sblock  = 0x0b,
 567         cpm_timer_sblock        = 0x0f,
 568         cpm_mcc1_sblock = 0x1c,
 569         cpm_mcc2_sblock = 0x1d,
 570         cpm_idma1_sblock        = 0x14,
 571         cpm_idma2_sblock        = 0x15,
 572         cpm_idma3_sblock        = 0x16,
 573         cpm_idma4_sblock        = 0x17,
 574
 575         cpm_scc1_page   = 0x00,
 576         cpm_scc2_page   = 0x01,
 577         cpm_scc3_page   = 0x02,
 578         cpm_scc4_page   = 0x03,
 579         cpm_smc1_page   = 0x07,
 580         cpm_smc2_page   = 0x08,
 581         cpm_spi_page            = 0x09,
 582         cpm_i2c_page            = 0x0a,
 583         cpm_timer_page  = 0x0a,
 584         cpm_rand_page   = 0x0a,
 585         cpm_fcc1_page   = 0x04,
 586         cpm_fcc2_page   = 0x05,
 587         cpm_fcc3_page   = 0x06,
 588         cpm_idma1_page  = 0x07,
 589         cpm_idma2_page  = 0x08,
 590         cpm_idma3_page  = 0x09,
 591         cpm_idma4_page  = 0x0a,
 592         cpm_mcc1_page   = 0x07,
 593         cpm_mcc2_page   = 0x08,
 594
 595 };
 596
 597 /*
 598  * CPM
 599  */
 600 enum {
 601         /* commands */
 602         InitRxTx =      0,
 603         InitRx =                1,
 604         InitTx =                2,
 605         EnterHunt=      3,
 606         StopTx=         4,
 607         GracefulStopTx = 5,
 608         InitIDMA =      5,
 609         RestartTx =     6,
 610         CloseRxBD =     7,
 611         SetGroupAddr = 8,
 612         SetTimer =      8,
 613         GCITimeout =    9,
 614         GCIAbort =      10,
 615         StopIDMA =      11,
 616         StartDSP =      12,
 617         ArmIDMA =       13,
 618         InitDSP =               13,
 619         USBCmd =        15,
 620
 621         /* channel IDs */
 622         SCC1ID= cpm_scc1_page << 5 | cpm_scc1_sblock,
 623         SCC2ID= cpm_scc2_page << 5 | cpm_scc2_sblock,
 624         SCC3ID= cpm_scc3_page << 5 | cpm_scc3_sblock,
 625         SMC1ID= cpm_smc1_page << 5 | cpm_smc1_sblock,
 626         SMC2ID= cpm_smc2_page << 5 | cpm_smc2_sblock,
 627         FCC1ID= cpm_fcc1_page << 5 | cpm_fcc1_sblock,
 628         FCC2ID= cpm_fcc2_page << 5 | cpm_fcc2_sblock,
 629         FCC3ID= cpm_fcc3_page << 5 | cpm_fcc3_sblock,
 630 //      USBID=  0,              These are wrong
 631 //      I2CID=  1,
 632 //      IDMA1ID= 1,
 633 //      SPIID=  5,
 634 //      IDMA2ID= 5,
 635 //      TIMERID=        5,
 636 //      DSP1ID=9,
 637 //      SCC4ID= 10,
 638 //      DSP2ID= 13,
 639
 640         /* sicr */
 641         BRG1 = 0,
 642         BRG2 = 1,
 643         BRG3 = 2,
 644         BRG4 = 4,
 645         CLK1 = 4,
 646         CLK2 = 5,
 647         CLK3 = 6,
 648         CLK4 = 7,
 649
 650 };
 651
 652 extern IMM* iomem;
 653
 654 BD*     bdalloc(int);
 655 void    cpmop(int, int, int);
 656 void    ioplock(void);
 657 void    iopunlock(void);
 658 void    kreboot(ulong);