2 #include "../port/lib.h"
9 * Simple segment descriptors with no translation.
11 #define EXECSEGM(p) { 0, SEGL|SEGP|SEGPL(p)|SEGEXEC }
12 #define DATASEGM(p) { 0, SEGB|SEGG|SEGP|SEGPL(p)|SEGDATA|SEGW }
13 #define EXEC32SEGM(p) { 0xFFFF, SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(p)|SEGEXEC|SEGR }
14 #define DATA32SEGM(p) { 0xFFFF, SEGB|SEGG|(0xF<<16)|SEGP|SEGPL(p)|SEGDATA|SEGW }
18 [NULLSEG] { 0, 0}, /* null descriptor */
19 [KESEG] EXECSEGM(0), /* kernel code */
20 [KDSEG] DATASEGM(0), /* kernel data */
21 [UE32SEG] EXEC32SEGM(3), /* user code 32 bit*/
22 [UDSEG] DATA32SEGM(3), /* user data/stack */
23 [UESEG] EXECSEGM(3), /* user code */
26 static int didmmuinit = 0;
42 MAPBITS = 8*sizeof(m->mmumap[0]),
46 loadptr(u16int lim, uintptr off, void (*load)(void*))
61 taskswitch(uintptr stack)
66 tss->rsp0[0] = (u32int)stack;
67 tss->rsp0[1] = stack >> 32;
68 tss->rsp1[0] = (u32int)stack;
69 tss->rsp1[1] = stack >> 32;
70 tss->rsp2[0] = (u32int)stack;
71 tss->rsp2[1] = stack >> 32;
84 /* zap double map done by l.s */
88 m->tss = mallocz(sizeof(Tss), 1);
90 panic("mmuinit: no memory for Tss");
91 m->tss->iomap = 0xDFFF;
93 x = (uintptr)m + MACHSIZE;
95 m->tss->ist[i+1] = x>>32;
99 * We used to keep the GDT in the Mach structure, but it
100 * turns out that that slows down access to the rest of the
101 * page. Since the Mach structure is accessed quite often,
102 * it pays off anywhere from a factor of 1.25 to 2 on real
103 * hardware to separate them (the AMDs are more sensitive
104 * than Intels in this regard). Under VMware it pays off
105 * a factor of about 10 to 100.
107 memmove(m->gdt, gdt, sizeof gdt);
110 m->gdt[TSSSEG+0].d0 = (x<<16)|(sizeof(Tss)-1);
111 m->gdt[TSSSEG+0].d1 = (x&0xFF000000)|((x>>16)&0xFF)|SEGTSS|SEGPL(0)|SEGP;
112 m->gdt[TSSSEG+1].d0 = x>>32;
113 m->gdt[TSSSEG+1].d1 = 0;
115 loadptr(sizeof(gdt)-1, (uintptr)m->gdt, lgdt);
116 loadptr(sizeof(Segdesc)*512-1, (uintptr)IDTADDR, lidt);
117 taskswitch((uintptr)m + MACHSIZE);
120 wrmsr(0xc0000100, 0ull); /* 64 bit fsbase */
121 wrmsr(0xc0000101, (uvlong)&machp[m->machno]); /* 64 bit gsbase */
122 wrmsr(0xc0000102, 0ull); /* kernel gs base */
124 /* enable syscall extension */
125 rdmsr(0xc0000080, &v);
127 wrmsr(0xc0000080, v);
130 wrmsr(0xc0000081, ((uvlong)UE32SEL << 48) | ((uvlong)KESEL << 32));
133 wrmsr(0xc0000082, (uvlong)syscallentry);
135 /* SYSCALL flags mask */
136 wrmsr(0xc0000084, 0x200);
140 * These could go back to being macros once the kernel is debugged,
141 * but the extra checking is nice to have.
146 if(pa > (uintptr)-KZERO)
147 panic("kaddr: pa=%#p pc=%#p", pa, getcallerpc(&pa));
148 return (void*)(pa+KZERO);
161 panic("paddr: va=%#p pc=%#p", va, getcallerpc(&v));
173 m->mmufree = p->next;
179 mmupool.free = p->next;
185 p = malloc(n * sizeof(MMU));
187 panic("mmualloc: out of memory for MMU");
188 p->page = mallocalign(n * PTSZ, BY2PG, 0, 0);
190 panic("mmualloc: out of memory for MMU pages");
192 p[i].page = p[i-1].page + (1<<PTSHIFT);
197 p[n-1].next = mmupool.free;
198 mmupool.free = p->next;
200 mmupool.nfree += n-1;
209 mmucreate(uintptr *table, uintptr va, int level, int index)
211 uintptr *page, flags;
214 flags = PTEWRITE|PTEVALID;
217 assert((va < TSTKTOP) || (va >= KMAP && va < KMAP+KMAPSIZE));
225 if((p->next = up->mmuhead) == nil)
228 m->mmumap[index/MAPBITS] |= 1ull<<(index%MAPBITS);
230 up->mmutail->next = p;
239 up->kmaptail->next = p;
245 } else if(didmmuinit) {
246 page = mallocalign(PTSZ, BY2PG, 0, 0);
250 memset(page, 0, PTSZ);
251 table[index] = PADDR(page) | flags;
256 mmuwalk(uintptr* table, uintptr va, int level, int create)
262 for(i = 2; i >= level; i--){
267 table = KADDR(PPN(pte));
271 table = mmucreate(table, va, i, x);
279 ptecount(uintptr va, int level)
281 return (1<<PTSHIFT) - (va & PGLSZ(level+1)-1) / PGLSZ(level);
285 pmap(uintptr *pml4, uintptr pa, uintptr va, int size)
287 uintptr *pte, *ptee, flags;
290 if((size <= 0) || va < VMAP)
291 panic("pmap: pa=%#p va=%#p size=%d", pa, va, size);
298 if(size >= PGLSZ(1) && (va % PGLSZ(1)) == 0)
300 l = (flags & PTESIZE) != 0;
302 pte = mmuwalk(pml4, va, l, 1);
304 pte = mmuwalk(pml4, va, ++l, 0);
305 if(pte && (*pte & PTESIZE)){
307 z = va & (PGLSZ(l)-1);
313 panic("pmap: pa=%#p va=%#p size=%d", pa, va, size);
315 ptee = pte + ptecount(va, l);
316 while(size > 0 && pte < ptee){
333 pte[PTLX(KMAP, 3)] = 0;
336 pte[PTLX(UTZERO, 3)] = 0;
337 pte[PTLX(TSTKTOP, 3)] = 0;
338 m->mmumap[PTLX(UTZERO, 3)/MAPBITS] &= ~(1ull<<(PTLX(UTZERO, 3)%MAPBITS));
339 m->mmumap[PTLX(TSTKTOP, 3)/MAPBITS] &= ~(1ull<<(PTLX(TSTKTOP, 3)%MAPBITS));
341 for(i = 0; i < nelem(m->mmumap); pte += MAPBITS, i++){
364 if(m->mmucount+proc->mmucount < 256){
365 p->next = m->mmufree;
366 m->mmufree = proc->mmuhead;
367 m->mmucount += proc->mmucount;
370 p->next = mmupool.free;
371 mmupool.free = proc->mmuhead;
372 mmupool.nfree += proc->mmucount;
375 proc->mmuhead = proc->mmutail = nil;
391 mmuswitch(Proc *proc)
400 if((p = proc->kmaphead) != nil)
401 m->pml4[PTLX(KMAP, 3)] = PADDR(p->page) | PTEWRITE|PTEVALID;
402 for(p = proc->mmuhead; p != nil && p->level == PML4E; p = p->next){
403 m->mmumap[p->index/MAPBITS] |= 1ull<<(p->index%MAPBITS);
404 m->pml4[p->index] = PADDR(p->page) | PTEUSER|PTEWRITE|PTEVALID;
406 taskswitch((uintptr)proc->kstack+KSTACK);
410 mmurelease(Proc *proc)
415 if((p = proc->kmaptail) != nil){
416 if((p->next = proc->mmuhead) == nil)
418 proc->mmuhead = proc->kmaphead;
419 proc->mmucount += proc->kmapcount;
421 proc->kmaphead = proc->kmaptail = nil;
422 proc->kmapcount = proc->kmapindex = 0;
425 taskswitch((uintptr)m+MACHSIZE);
429 putmmu(uintptr va, uintptr pa, Page *)
435 pte = mmuwalk(m->pml4, va, 0, 1);
437 panic("putmmu: bug: va=%#p pa=%#p", va, pa);
439 *pte = pa | PTEVALID|PTEUSER;
446 checkmmu(uintptr va, uintptr pa)
460 countpagerefs(ulong *ref, int print)
468 uintptr *pte, pa, va;
472 if(cankaddr(pa) != 0)
473 return (KMap*)KADDR(pa);
476 va = KMAP + ((uintptr)up->kmapindex << PGSHIFT);
477 pte = mmuwalk(m->pml4, va, 0, 1);
478 if(pte == 0 || *pte & PTEVALID)
479 panic("kmap: pa=%#p va=%#p", pa, va);
480 *pte = pa | PTEWRITE|PTEVALID;
481 up->kmapindex = (up->kmapindex + 1) % (1<<PTSHIFT);
482 if(up->kmapindex == 0)
499 pte = mmuwalk(m->pml4, va, 0, 0);
500 if(pte == 0 || (*pte & PTEVALID) == 0)
501 panic("kunmap: va=%#p", va);
507 * Add a device mapping to the vmap range.
510 vmap(uintptr pa, int size)
517 * might be asking for less than a page.
523 pmap(m->pml4, pa | PTEUNCACHED|PTEWRITE|PTEVALID, va, size);
524 return (void*)(va+o);
530 paddr(v); /* will panic on error */
534 * vmapsync() is currently unused as the VMAP and KZERO PDPs
535 * are shared between processors. (see mpstartap)
540 uintptr *pte1, *pte2;
543 if(va < VMAP || m->machno == 0)
546 for(level=0; level<2; level++){
547 pte1 = mmuwalk(MACHP(0)->pml4, va, level, 0);
548 if(pte1 && *pte1 & PTEVALID){
549 pte2 = mmuwalk(m->pml4, va, level, 1);