2 * ATI Radeon [789]XXX vga driver
3 * see /sys/src/cmd/aux/vga/radeon.c
6 #include "../port/lib.h"
11 #include "../port/error.h"
19 #include "/sys/src/cmd/aux/vga/radeon.h" /* ugh */
21 /* #define HW_ACCEL */
31 OUTREG8(ulong *mmio, ulong offset, uchar val)
33 ((uchar*)KADDR((((uintptr)mmio) + offset)))[0] = val;
37 OUTREG(ulong *mmio, ulong offset, ulong val)
39 ((ulong*)KADDR((((uintptr)mmio) + offset)))[0] = val;
43 INREG(ulong *mmio, ulong offset)
45 return ((ulong*)KADDR((((uintptr)mmio) + offset)))[0];
49 OUTREGP(ulong *mmio, ulong offset, ulong val, ulong mask)
51 OUTREG(mmio, offset, (INREG(mmio, offset) & mask) | val);
55 OUTPLL(ulong *mmio, ulong offset, ulong val)
57 OUTREG8(mmio, CLOCK_CNTL_INDEX, (offset & 0x3f) | PLL_WR_EN);
58 OUTREG(mmio, CLOCK_CNTL_DATA, val);
62 INPLL(ulong *mmio, ulong offset)
64 OUTREG8(mmio, CLOCK_CNTL_INDEX, offset & 0x3f);
65 return INREG(mmio, CLOCK_CNTL_DATA);
69 OUTPLLP(ulong *mmio, ulong offset, ulong val, ulong mask)
71 OUTPLL(mmio, offset, (INPLL(mmio, offset) & mask) | val);
75 radeonlinear(VGAscr *, int, int)
80 radeonenable(VGAscr *scr)
91 scr->mmio = vmap(p->mem[2].bar & ~0x0f, p->mem[2].size);
94 addvgaseg("radeonmmio", p->mem[2].bar & ~0x0f, p->mem[2].size);
98 addvgaseg("radeonscreen", scr->paddr, scr->apsize);
102 radeoncurload(VGAscr *scr, Cursor *curs)
110 p = (ulong*)KADDR(scr->storage);
112 for(y = 0; y < 64; y++){
116 cv = curs->clr[2*y] << 8 | curs->clr[2*y+1];
117 sv = curs->set[2*y] << 8 | curs->set[2*y+1];
121 for(x = 0; x < 64; x++){
126 c = (cv >> (15 - x)) & 1;
127 s = (sv >> (15 - x)) & 1;
136 col = ~0ul; /* white */
140 col = 0xff000000; /* black */
148 scr->offset.x = curs->offset.x;
149 scr->offset.y = curs->offset.y;
153 radeoncurmove(VGAscr *scr, Point p)
156 static ulong storage = 0;
162 storage = scr->apsize - 1*Meg;
164 x = p.x + scr->offset.x;
165 y = p.y + scr->offset.y;
177 OUTREG(scr->mmio, CUR_OFFSET, storage + oy * 256);
178 OUTREG(scr->mmio, CUR_HORZ_VERT_OFF,
179 (ox & 0x7fff) << 16 | (oy & 0x7fff));
180 OUTREG(scr->mmio, CUR_HORZ_VERT_POSN,
181 (x & 0x7fff) << 16 | (y & 0x7fff));
186 radeoncurdisable(VGAscr *scr)
190 OUTREGP(scr->mmio, CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
194 radeoncurenable(VGAscr *scr)
201 radeoncurdisable(scr);
202 storage = scr->apsize - 1*Meg;
203 scr->storage = (uintptr)KADDR(scr->paddr + storage);
204 radeoncurload(scr, &cursor);
205 radeoncurmove(scr, ZP);
207 OUTREGP(scr->mmio, CRTC_GEN_CNTL, CRTC_CUR_EN | 2<<20,
208 ~(CRTC_CUR_EN | 3<<20));
214 radeonblank(VGAscr* scr, int blank)
222 // iprint("radeon: hwblank(%d)\n", blank);
224 mask = CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS;
226 OUTREGP(scr->mmio, CRTC_EXT_CNTL, 0, ~mask);
230 cp = getconf("*dpms");
232 if (strcmp(cp, "standby") == 0)
233 OUTREGP(scr->mmio, CRTC_EXT_CNTL,
234 CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS, ~mask);
235 else if (strcmp(cp, "suspend") == 0)
236 OUTREGP(scr->mmio, CRTC_EXT_CNTL,
237 CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS, ~mask);
238 else if (strcmp(cp, "off") == 0)
239 OUTREGP(scr->mmio, CRTC_EXT_CNTL, mask, ~mask);
243 OUTREGP(scr->mmio, CRTC_EXT_CNTL, mask, ~mask);
246 /* hw acceleration */
249 radeonwaitfifo(VGAscr *scr, int entries)
253 for (i = 0; i < 2000000; i++)
254 if (INREG(scr->mmio, RBBM_STATUS) & RBBM_FIFOCNT_MASK >=
257 iprint("radeon: fifo timeout\n");
261 radeonwaitidle(VGAscr *scr)
263 radeonwaitfifo(scr, 64);
268 for (i = 0; i < 2000000; i++)
269 if (!(INREG(scr->mmio, RBBM_STATUS) & RBBM_ACTIVE))
272 iprint("radeon: idle timed out: %uld entries, stat=0x%.8ulx\n",
273 INREG(scr->mmio, RBBM_STATUS) & RBBM_FIFOCNT_MASK,
274 INREG(scr->mmio, RBBM_STATUS));
278 static ulong dp_gui_master_cntl = 0;
281 radeonfill(VGAscr *scr, Rectangle r, ulong color)
283 if (scr->mmio == nil)
286 radeonwaitfifo(scr, 6);
287 OUTREG(scr->mmio, DP_GUI_MASTER_CNTL,
288 dp_gui_master_cntl | GMC_BRUSH_SOLID_COLOR |
289 GMC_SRC_DATATYPE_COLOR | ROP3_P);
290 OUTREG(scr->mmio, DP_BRUSH_FRGD_CLR, color);
291 OUTREG(scr->mmio, DP_WRITE_MASK, ~0ul);
292 OUTREG(scr->mmio, DP_CNTL,
293 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
294 OUTREG(scr->mmio, DST_Y_X, r.min.y << 16 | r.min.x);
295 OUTREG(scr->mmio, DST_WIDTH_HEIGHT, Dx(r) << 16 | Dy(r));
302 radeonscroll(VGAscr*scr, Rectangle dst, Rectangle src)
304 int xs, ys, xd, yd, w, h;
305 ulong dp_cntl = 0x20;
307 if (scr->mmio == nil)
310 // iprint("radeon: hwscroll(dst:%R, src:%R)\n", dst, src);
323 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
329 dp_cntl |= DST_X_LEFT_TO_RIGHT;
331 radeonwaitfifo(scr, 6);
332 OUTREG(scr->mmio, DP_GUI_MASTER_CNTL, dp_gui_master_cntl |
333 GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | DP_SRC_SOURCE_MEMORY |
335 OUTREG(scr->mmio, DP_WRITE_MASK, ~0ul);
336 OUTREG(scr->mmio, DP_CNTL, dp_cntl);
337 OUTREG(scr->mmio, SRC_Y_X, ys << 16 | xs);
338 OUTREG(scr->mmio, DST_Y_X, yd << 16 | xd);
339 OUTREG(scr->mmio, DST_WIDTH_HEIGHT, w << 16 | h);
343 // iprint("radeon: hwscroll(xs=%d ys=%d xd=%d yd=%d w=%d h=%d)\n",
344 // xs, ys, xd, yd, w, h);
349 radeondrawinit(VGAscr*scr)
351 ulong bpp, dtype, i, pitch, clock_cntl_index, mclk_cntl, rbbm_soft_reset;
356 switch (scr->gscreen->depth) {
379 OUTREG(scr->mmio, RB3D_CNTL, 0);
382 OUTREGP(scr->mmio, RB2D_DSTCACHE_CTLSTAT,
383 RB2D_DC_FLUSH_ALL, ~RB2D_DC_FLUSH_ALL);
384 for (i = 0; i < 2000000; i++)
385 if (!(INREG(scr->mmio, RB2D_DSTCACHE_CTLSTAT) &
389 /* reset 2D engine */
390 clock_cntl_index = INREG(scr->mmio, CLOCK_CNTL_INDEX);
392 mclk_cntl = INPLL(scr->mmio, MCLK_CNTL);
393 OUTPLL(scr->mmio, MCLK_CNTL, mclk_cntl | FORCEON_MCLKA |
394 FORCEON_MCLKB | FORCEON_YCLKA | FORCEON_YCLKB | FORCEON_MC |
396 rbbm_soft_reset = INREG(scr->mmio, RBBM_SOFT_RESET);
398 OUTREG(scr->mmio, RBBM_SOFT_RESET, rbbm_soft_reset |
399 SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_SE | SOFT_RESET_RE |
400 SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB);
401 INREG(scr->mmio, RBBM_SOFT_RESET);
402 OUTREG(scr->mmio, RBBM_SOFT_RESET, rbbm_soft_reset &
403 ~(SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_SE | SOFT_RESET_RE |
404 SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB));
405 INREG(scr->mmio, RBBM_SOFT_RESET);
407 OUTPLL(scr->mmio, MCLK_CNTL, mclk_cntl);
408 OUTREG(scr->mmio, CLOCK_CNTL_INDEX, clock_cntl_index);
411 radeonwaitfifo(scr, 1);
412 OUTREG(scr->mmio, RB2D_DSTCACHE_MODE, 0);
414 pitch = Dx(scr->gscreen->r) * bpp;
415 radeonwaitfifo(scr, 4);
416 OUTREG(scr->mmio, DEFAULT_PITCH, pitch);
417 OUTREG(scr->mmio, DST_PITCH, pitch);
418 OUTREG(scr->mmio, SRC_PITCH, pitch);
419 OUTREG(scr->mmio, DST_PITCH_OFFSET_C, 0);
421 radeonwaitfifo(scr, 3);
422 OUTREG(scr->mmio, DEFAULT_OFFSET, 0);
423 OUTREG(scr->mmio, DST_OFFSET, 0);
424 OUTREG(scr->mmio, SRC_OFFSET, 0);
426 radeonwaitfifo(scr, 1);
427 OUTREGP(scr->mmio, DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
429 radeonwaitfifo(scr, 1);
430 OUTREG(scr->mmio, DEFAULT_SC_BOTTOM_RIGHT,
431 DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX);
433 dp_gui_master_cntl = dtype << GMC_DST_DATATYPE_SHIFT |
434 GMC_SRC_PITCH_OFFSET_CNTL | GMC_DST_PITCH_OFFSET_CNTL |
435 GMC_CLR_CMP_CNTL_DIS;
436 radeonwaitfifo(scr, 1);
437 OUTREG(scr->mmio, DP_GUI_MASTER_CNTL,
438 dp_gui_master_cntl | GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR);
440 radeonwaitfifo(scr, 7);
441 OUTREG(scr->mmio, DST_LINE_START, 0);
442 OUTREG(scr->mmio, DST_LINE_END, 0);
443 OUTREG(scr->mmio, DP_BRUSH_FRGD_CLR, ~0ul);
444 OUTREG(scr->mmio, DP_BRUSH_BKGD_CLR, 0);
445 OUTREG(scr->mmio, DP_SRC_FRGD_CLR, ~0ul);
446 OUTREG(scr->mmio, DP_SRC_BKGD_CLR, 0);
447 OUTREG(scr->mmio, DP_WRITE_MASK, ~0ul);
451 scr->fill = radeonfill;
452 scr->scroll = radeonscroll;
453 scr->blank = radeonblank;
459 radeonovlctl(VGAscr *scr, Chan *c, void *data, int len)
461 USED(scr, c, data, len);
465 radeonovlwrite(VGAscr *scr, void *data, int len, vlong opt)
467 USED(scr, data, len, opt);
472 radeonflush(VGAscr *scr, Rectangle r)
479 VGAdev vgaradeondev = {
496 VGAcur vgaradeoncur = {