2 * USB Open Host Controller Interface (Ohci) driver
5 * - Missing isochronous input streams.
6 * - Too many delays and ilocks.
7 * - bandwidth admission control must be done per-frame.
8 * - Buffering could be handled like in uhci, to avoid
9 * needed block allocation and avoid allocs for small Tds.
10 * - must warn of power overruns.
14 #include "../port/lib.h"
19 #include "../port/error.h"
21 #include "../port/usb.h"
23 typedef struct Ctlio Ctlio;
24 typedef struct Ctlr Ctlr;
26 typedef struct Edpool Edpool;
27 typedef struct Epx Epx;
28 typedef struct Hcca Hcca;
29 typedef struct Isoio Isoio;
30 typedef struct Ohci Ohci;
31 typedef struct Qio Qio;
32 typedef struct Qtree Qtree;
34 typedef struct Tdpool Tdpool;
38 Incr = 64, /* for Td and Ed pools */
40 Align = 0x20, /* OHCI only requires 0x10 */
41 /* use always a power of 2 */
43 Abortdelay = 1, /* delay after cancelling Tds (ms) */
44 Tdatomic = 8, /* max nb. of Tds per bulk I/O op. */
45 Enabledelay = 100, /* waiting for a port to enable */
48 /* Queue states (software) */
57 Edmpsmask = 0x7ff, /* max packet size */
59 Edlow = 1 << 13, /* low speed */
60 Edskip = 1 << 14, /* skip this ed */
61 Ediso = 1 << 15, /* iso Tds used */
62 Edtddir = 0, /* get dir from td */
63 Edin = 2 << 11, /* direction in */
64 Edout = 1 << 11, /* direction out */
65 Eddirmask = 3 << 11, /* direction bits */
66 Edhalt = 1, /* halted (in head ptr) */
67 Edtoggle = 2, /* toggle (in head ptr) 1 == data1 */
70 Tdround = 1<<18, /* (rounding) short packets ok */
71 Tdtoksetup = 0<<19, /* setup packet */
72 Tdtokin = 2<<19, /* in packet */
73 Tdtokout = 1<<19, /* out packet */
74 Tdtokmask = 3<<19, /* in/out/setup bits */
75 Tdnoioc = 7<<21, /* intr. cnt. value for no interrupt */
76 Tdusetog = 1<<25, /* use toggle from Td (1) or Ed (0) */
77 Tddata1 = 1<<24, /* data toggle (1 == data1) */
79 Tdfcmask = 7, /* frame count (iso) */
81 Tdsfmask = 0xFFFF, /* starting frame (iso) */
82 Tderrmask = 3, /* error counter */
84 Tdccmask = 0xf, /* condition code (status) */
86 Tdiccmask = 0xf, /* condition code (iso, offsets) */
89 Ntdframes = 0x10000, /* # of different iso frame numbers */
91 /* Td errors (condition code) */
106 /* control register */
107 Cple = 0x04, /* periodic list enable */
108 Cie = 0x08, /* iso. list enable */
109 Ccle = 0x10, /* ctl list enable */
110 Cble = 0x20, /* bulk list enable */
111 Cir = 0x100, /* interrupt routing (smm active) */
112 Cfsmask = 3 << 6, /* functional state... */
119 Socr = 1 << 3, /* ownership change request */
120 Sblf = 1 << 2, /* bulk list (load) flag */
121 Sclf = 1 << 1, /* control list (load) flag */
122 Shcr = 1 << 0, /* host controller reset */
135 Fmaxpktmask = 0x7fff,
137 HcRhDescA_POTPGT_MASK = 0xff << 24,
138 HcRhDescA_POTPGT_SHIFT = 24,
153 Ccs = 0x00001, /* current connect status */
154 Pes = 0x00002, /* port enable status */
155 Pss = 0x00004, /* port suspend status */
156 Poci = 0x00008, /* over current indicator */
157 Prs = 0x00010, /* port reset status */
158 Pps = 0x00100, /* port power status */
159 Lsda = 0x00200, /* low speed device attached */
160 Csc = 0x10000, /* connect status change */
161 Pesc = 0x20000, /* enable status change */
162 Pssc = 0x40000, /* suspend status change */
163 Ocic = 0x80000, /* over current ind. change */
164 Prsc = 0x100000, /* reset status change */
166 /* port status write bits */
167 Cpe = 0x001, /* clear port enable */
168 Spe = 0x002, /* set port enable */
169 Spr = 0x010, /* set port reset */
170 Spp = 0x100, /* set port power */
171 Cpp = 0x200, /* clear port power */
176 * Endpoint descriptor. (first 4 words used by hardware)
180 ulong tail; /* transfer descriptor */
184 Ed* next; /* sw; in free list or next in list */
185 Td* tds; /* in use by current xfer; all for iso */
186 Ep* ep; /* debug/align */
187 Ed* inext; /* debug/align (dump interrupt eds). */
191 * Endpoint I/O state (software), per direction.
195 QLock; /* for the entire I/O process */
196 Rendez; /* wait for completion */
197 Ed* ed; /* to place Tds on it */
198 int sched; /* queue number (intr/iso) */
199 int toggle; /* Tddata0/Tddata1 */
200 ulong usbid; /* device/endpoint address */
201 int tok; /* Tdsetup, Tdtokin, Tdtokout */
202 long iotime; /* last I/O time; to hold interrupt polls */
203 int debug; /* for the endpoint */
204 char* err; /* error status */
205 int state; /* Qidle -> Qinstall -> Qrun -> Qdone | Qclose */
206 long bw; /* load (intr/iso) */
211 Qio; /* single Ed for all transfers */
212 uchar* data; /* read from last ctl req. */
213 int ndata; /* number of bytes read */
219 int nframes; /* number of frames for a full second */
220 Td* atds; /* Tds avail for further I/O */
221 int navail; /* number of avail Tds */
222 ulong frno; /* next frame number avail for I/O */
223 ulong left; /* remainder after rounding Hz to samples/ms */
224 int nerrs; /* consecutive errors on iso I/O */
225 int delay; /* maximum number of frames to buffer */
229 * Transfer descriptor. Size must be multiple of 32
230 * First block is used by hardware (aligned to 32).
235 ulong cbp; /* current buffer pointer */
238 ushort offsets[8]; /* used by Iso Tds only */
240 Td* next; /* in free or Ed tds list */
241 Td* anext; /* in avail td list (iso) */
242 Ep* ep; /* using this Td for I/O */
243 Qio* io; /* using this Td for I/O */
244 Block* bp; /* data for this Td */
245 ulong nbytes; /* bytes in this Td */
246 ulong cbp0; /* initial value for cbp */
247 ulong last; /* true for last Td in Qio */
251 * Host controller communication area (hardware)
267 /* control and status group */
268 ulong revision; /*00*/
269 ulong control; /*04*/
271 ulong intrsts; /*0c*/
272 ulong intrenable; /*10*/
273 ulong intrdisable; /*14*/
275 /* memory pointer group */
277 ulong periodcurred; /*1c*/
278 ulong ctlheaded; /*20*/
279 ulong ctlcurred; /*24*/
280 ulong bulkheaded; /*28*/
281 ulong bulkcurred; /*2c*/
282 ulong donehead; /*30*/
284 /* frame counter group */
285 ulong fminterval; /*34*/
286 ulong fmremaining; /*38*/
287 ulong fmnumber; /*3c*/
288 ulong periodicstart; /*40*/
289 ulong lsthreshold; /*44*/
292 ulong rhdesca; /*48*/
293 ulong rhdescb; /*4c*/
295 ulong rhportsts[15]; /*54*/
296 ulong pad25[20]; /*90*/
299 ulong hostueaddr; /*e0*/
300 ulong hostuests; /*e4*/
301 ulong hosttimeoutctrl; /*e8*/
304 ulong hostrevision; /*f4*/
310 * Endpoint tree (software)
340 Lock; /* for ilock; lists and basic ctlr I/O */
341 QLock resetl; /* lock controller during USB reset */
346 Ohci* ohci; /* base I/O address */
347 Hcca* hcca; /* intr/done Td lists (used by hardware) */
348 int overrun; /* sched. overrun */
349 Ed* intrhd; /* list of intr. eds in tree */
350 Qtree* tree; /* tree for t Ep i/o */
351 int ntree; /* number of dummy Eds in tree */
355 #define dqprint if(debug || io && io->debug)print
356 #define ddqprint if(debug>1 || (io && io->debug>1))print
357 #define diprint if(debug || iso && iso->debug)print
358 #define ddiprint if(debug>1 || (iso && iso->debug>1))print
359 #define TRUNC(x, sz) ((x) & ((sz)-1))
361 static int ohciinterrupts[Nttypes];
362 static char* iosname[] = { "idle", "install", "run", "done", "close", "FREE" };
365 static Edpool edpool;
366 static Tdpool tdpool;
367 static Ctlr* ctlrs[Nhcis];
369 static char EnotWritten[] = "usb write unfinished";
370 static char EnotRead[] = "usb read unfinished";
371 static char Eunderrun[] = "usb endpoint underrun";
373 static QLock usbhstate; /* protects name space state */
375 static int schedendpt(Ctlr *ub, Ep *ep);
376 static void unschedendpt(Ctlr *ub, Ep *ep);
377 static long qtd(Ctlr*, Ep*, int, Block*, uchar*, uchar*, int, ulong);
379 static char* errmsgs[] =
382 [Tdbitstuff] "bit stuffing error",
383 [Tdbadtog] "bad toggle",
384 [Tdstalled] Estalled,
385 [Tdtmout] "timeout error",
386 [Tdpidchk] "pid check error",
387 [Tdbadpid] "bad pid",
388 [Tddataovr] "data overrun",
389 [Tddataund] "data underrun",
390 [Tdbufovr] "buffer overrun",
391 [Tdbufund] "buffer underrun",
392 [Tdnotacc] "not accessed"
416 int frame = ub->hcca->framenumber & 0x3f;
420 } while(frame == (ub->hcca->framenumber & 0x3f));
427 if(err < nelem(errmsgs))
435 return pa2ptr(ctlr->ohci->ctlheaded);
441 return pa2ptr(ctlr->ohci->bulkheaded);
445 edlinked(Ed *ed, Ed *next)
448 print("edlinked: nil ed: pc %#p\n", getcallerpc(&ed));
449 ed->nexted = ptr2pa(next);
454 setctlhd(Ctlr *ctlr, Ed *ed)
456 ctlr->ohci->ctlheaded = ptr2pa(ed);
458 ctlr->ohci->cmdsts |= Sclf; /* reload it on next pass */
462 setbulkhd(Ctlr *ctlr, Ed *ed)
464 ctlr->ohci->bulkheaded = ptr2pa(ed);
466 ctlr->ohci->cmdsts |= Sblf; /* reload it on next pass */
470 unlinkctl(Ctlr *ctlr, Ed *ed)
472 Ed *this, *prev, *next;
474 ctlr->ohci->control &= ~Ccle;
477 ctlr->ohci->ctlcurred = 0;
479 while(this != nil && this != ed){
484 print("unlinkctl: not found\n");
489 setctlhd(ctlr, next);
491 edlinked(prev, next);
492 ctlr->ohci->control |= Ccle;
493 edlinked(ed, nil); /* wipe out next field */
497 unlinkbulk(Ctlr *ctlr, Ed *ed)
499 Ed *this, *prev, *next;
501 ctlr->ohci->control &= ~Cble;
504 ctlr->ohci->bulkcurred = 0;
506 while(this != nil && this != ed){
511 print("unlinkbulk: not found\n");
516 setbulkhd(ctlr, next);
518 edlinked(prev, next);
519 ctlr->ohci->control |= Cble;
520 edlinked(ed, nil); /* wipe out next field */
524 edsetaddr(Ed *ed, ulong addr)
528 ctrl = ed->ctrl & ~((Epmax<<7)|Devmax);
529 ctrl |= (addr & ((Epmax<<7)|Devmax));
534 edsettog(Ed *ed, int c)
537 ed->head |= Edtoggle;
539 ed->head &= ~Edtoggle;
545 return ed->head & Edtoggle;
551 return ed->head & Edhalt;
557 return (ed->ctrl >> Edmpsshift) & Edmpsmask;
561 edsetmaxpkt(Ed *ed, int m)
565 c = ed->ctrl & ~(Edmpsmask << Edmpsshift);
566 ed->ctrl = c | ((m&Edmpsmask) << Edmpsshift);
572 return (td->ctrl >> Tdccshift) & Tdccmask;
578 return (td->ctrl & Tdtokmask);
589 if(tdpool.free == nil){
590 ddprint("ohci: tdalloc %d Tds\n", Incr);
591 pool = xspanalloc(Incr*sizeof(Td), Align, 0);
593 panic("ohci: tdalloc");
594 for(i=Incr; --i>=0;){
595 pool[i].next = tdpool.free;
596 tdpool.free = &pool[i];
598 tdpool.nalloc += Incr;
599 tdpool.nfree += Incr;
604 tdpool.free = td->next;
605 memset(td, 0, sizeof(Td));
608 assert(((uintptr)td & 0xF) == 0);
620 if(td->nexttd == 0x77777777)
621 panic("ohci: tdfree: double free");
622 memset(td, 7, sizeof(Td)); /* poison */
623 td->next = tdpool.free;
637 if(edpool.free == nil){
638 ddprint("ohci: edalloc %d Eds\n", Incr);
639 pool = xspanalloc(Incr*sizeof(Ed), Align, 0);
641 panic("ohci: edalloc");
642 for(i=Incr; --i>=0;){
643 pool[i].next = edpool.free;
644 edpool.free = &pool[i];
646 edpool.nalloc += Incr;
647 edpool.nfree += Incr;
652 edpool.free = ed->next;
653 memset(ed, 0, sizeof(Ed));
668 for(td = ed->tds; td != nil; td = next){
672 print("ohci: bug: ed with more than 2000 tds\n");
677 if(ed->nexted == 0x99999999)
678 panic("ohci: edfree: double free");
679 memset(ed, 9, sizeof(Ed)); /* poison */
680 ed->next = edpool.free;
685 ddprint("edfree: ed %#p\n", ed);
689 * return smallest power of 2 >= n
696 for(i = 0; (1 << i) < n; i++)
702 * return smallest power of 2 <= n
709 for(i = 0; (1 << (i + 1)) <= n; i++)
715 pickschedq(Qtree *qt, int pollival, ulong bw, ulong limit)
717 int i, j, d, upperb, q;
718 ulong best, worst, total;
720 d = flog2lower(pollival);
726 upperb = (1 << (d+1)) - 1;
727 for(i = (1 << d) - 1; i < upperb; i++){
729 for(j = i; j > 0; j = (j - 1) / 2)
738 if(worst + bw >= limit)
744 schedq(Ctlr *ctlr, Qio *io, int pollival)
749 q = pickschedq(ctlr->tree, pollival, io->bw, ~0);
750 ddqprint("ohci: sched %#p q %d, ival %d, bw %ld\n", io, q, pollival, io->bw);
752 print("ohci: no room for ed\n");
755 ctlr->tree->bw[q] += io->bw;
756 ted = ctlr->tree->root[q];
758 edlinked(io->ed, ted->next);
759 edlinked(ted, io->ed);
760 io->ed->inext = ctlr->intrhd;
761 ctlr->intrhd = io->ed;
766 unschedq(Ctlr *ctlr, Qio *qio)
769 Ed *prev, *this, *next;
775 ctlr->tree->bw[q] -= qio->bw;
777 prev = ctlr->tree->root[q];
779 while(this != nil && this != qio->ed){
784 print("ohci: unschedq %d: not found\n", q);
787 edlinked(prev, next);
790 for(l = &ctlr->intrhd; *l != nil; l = &(*l)->inext)
795 print("ohci: unschedq: ed %#p not found\n", qio->ed);
799 seprinttdtok(char *s, char *e, int tok)
803 s = seprint(s, e, " setup");
806 s = seprint(s, e, " in");
809 s = seprint(s, e, " out");
817 seprinttd(char *s, char *e, Td *td, int iso)
823 return seprint(s, e, "<nil td>\n");
824 s = seprint(s, e, "%#p ep %#p ctrl %#p", td, td->ep, td->ctrl);
825 s = seprint(s, e, " cc=%#ulx", (td->ctrl >> Tdccshift) & Tdccmask);
827 if((td->ctrl & Tdround) != 0)
828 s = seprint(s, e, " rnd");
829 s = seprinttdtok(s, e, td->ctrl & Tdtokmask);
830 if((td->ctrl & Tdusetog) != 0)
831 s = seprint(s, e, " d%d", (td->ctrl & Tddata1) ? 1 : 0);
833 s = seprint(s, e, " d-");
834 s = seprint(s, e, " ec=%uld", (td->ctrl >> Tderrshift) & Tderrmask);
836 s = seprint(s, e, " fc=%uld", (td->ctrl >> Tdfcshift) & Tdfcmask);
837 s = seprint(s, e, " sf=%uld", td->ctrl & Tdsfmask);
839 s = seprint(s, e, " cbp0 %#p cbp %#p next %#p be %#p %s",
840 td->cbp0, td->cbp, td->nexttd, td->be, td->last ? "last" : "");
841 s = seprint(s, e, "\n\t\t%ld bytes", td->nbytes);
842 if((bp = td->bp) != nil){
843 s = seprint(s, e, " rp %#p wp %#p ", bp->rp, bp->wp);
845 s = seprintdata(s, e, bp->rp, bp->wp - bp->rp);
848 return seprint(s, e, "\n");
849 s = seprint(s, e, "\n\t\t");
850 /* we use only offsets[0] */
852 s = seprint(s, e, "[%d] %#ux cc=%#ux sz=%ud\n", i, td->offsets[i],
853 (td->offsets[i] >> Tdiccshift) & Tdiccmask,
854 td->offsets[i] & 0x7FF);
859 dumptd(Td *td, char *p, int iso)
861 static char buf[512]; /* Too much */
864 s = seprint(buf, buf+sizeof(buf), "%s: ", p);
865 s = seprinttd(s, buf+sizeof(buf), td, iso);
866 if(s > buf && s[-1] != '\n')
872 dumptds(Td *td, char *p, int iso)
876 for(i = 0; td != nil; td = td->next){
880 if(tdtok(td) == Tdtokin && ++i > 2){
893 print("<null ed>\n");
897 /* no waserror; may want to use from interrupt context */
901 s = seprint(buf, e, "\ted %#p: ctrl %#p", ed, ed->ctrl);
902 if((ed->ctrl & Edskip) != 0)
903 s = seprint(s, e, " skip");
904 if((ed->ctrl & Ediso) != 0)
905 s = seprint(s, e, " iso");
906 if((ed->ctrl & Edlow) != 0)
907 s = seprint(s, e, " low");
908 s = seprint(s, e, " d%d", (ed->head & Edtoggle) ? 1 : 0);
909 if((ed->ctrl & Eddirmask) == Edin)
910 s = seprint(s, e, " in");
911 if((ed->ctrl & Eddirmask) == Edout)
912 s = seprint(s, e, " out");
914 s = seprint(s, e, " hlt");
915 s = seprint(s, e, " ep%uld.%uld", (ed->ctrl>>7)&Epmax, ed->ctrl&0x7f);
916 s = seprint(s, e, " maxpkt %uld", (ed->ctrl>>Edmpsshift)&Edmpsmask);
917 seprint(s, e, " tail %#p head %#p next %#p\n",ed->tail,ed->head,ed->nexted);
920 if(ed->tds != nil && (ed->ctrl & Ediso) == 0)
921 dumptds(ed->tds, "td", 0);
925 seprintio(char *s, char *e, Qio *io, char *pref)
927 s = seprint(s, e, "%s qio %#p ed %#p", pref, io, io->ed);
928 s = seprint(s, e, " tog %d iot %ld err %s id %#ulx",
929 io->toggle, io->iotime, io->err, io->usbid);
930 s = seprinttdtok(s, e, io->tok);
931 s = seprint(s, e, " %s\n", iosname[io->state]);
936 seprintep(char* s, char* e, Ep *ep)
943 return seprint(s, e, "<nil ep>\n");
945 return seprint(s, e, "no mdep\n");
949 s = seprintio(s, e, cio, "c");
950 s = seprint(s, e, "\trepl %d ndata %d\n", ep->rhrepl, cio->ndata);
955 if(ep->mode != OWRITE)
956 s = seprintio(s, e, &io[OREAD], "r");
957 if(ep->mode != OREAD)
958 s = seprintio(s, e, &io[OWRITE], "w");
962 s = seprintio(s, e, iso, "w");
963 s = seprint(s, e, "\tntds %d avail %d frno %uld left %uld next avail %#p\n",
964 iso->nframes, iso->navail, iso->frno, iso->left, iso->atds);
971 seprintctl(char *s, char *se, ulong ctl)
973 s = seprint(s, se, "en=");
975 s = seprint(s, se, "p");
977 s = seprint(s, se, "i");
979 s = seprint(s, se, "c");
981 s = seprint(s, se, "b");
982 switch(ctl & Cfsmask){
984 return seprint(s, se, " reset");
986 return seprint(s, se, " resume");
988 return seprint(s, se, " run");
990 return seprint(s, se, " suspend");
992 return seprint(s, se, " ???");
1005 seprintctl(cs, cs+sizeof(cs), ctlr->ohci->control);
1006 print("ohci ctlr %#p: frno %#ux ctl %#lux %s sts %#lux intr %#lux\n",
1007 ctlr, ctlr->hcca->framenumber, ctlr->ohci->control, cs,
1008 ctlr->ohci->cmdsts, ctlr->ohci->intrsts);
1009 print("ctlhd %#ulx cur %#ulx bulkhd %#ulx cur %#ulx done %#ulx\n",
1010 ctlr->ohci->ctlheaded, ctlr->ohci->ctlcurred,
1011 ctlr->ohci->bulkheaded, ctlr->ohci->bulkcurred,
1012 ctlr->ohci->donehead);
1013 if(ctlhd(ctlr) != nil)
1015 for(ed = ctlhd(ctlr); ed != nil; ed = ed->next)
1017 if(bulkhd(ctlr) != nil)
1019 for(ed = bulkhd(ctlr); ed != nil; ed = ed->next)
1021 if(ctlr->intrhd != nil)
1023 for(ed = ctlr->intrhd; ed != nil; ed = ed->inext)
1025 if(ctlr->tree->root[0]->next != nil)
1027 for(ed = ctlr->tree->root[0]->next; ed != nil; ed = ed->next)
1029 print("%d eds in tree\n", ctlr->ntree);
1032 print("%d tds allocated = %d in use + %d free\n",
1033 tdpool.nalloc, tdpool.ninuse, tdpool.nfree);
1036 print("%d eds allocated = %d in use + %d free\n",
1037 edpool.nalloc, edpool.ninuse, edpool.nfree);
1042 * Compute size for the next iso Td and setup its
1043 * descriptor for I/O according to the buffer size.
1046 isodtdinit(Ep *ep, Isoio *iso, Td *td)
1053 assert(bp != nil && BLEN(bp) == 0);
1054 size = (ep->hz+iso->left) * ep->pollival / 1000;
1055 iso->left = (ep->hz+iso->left) * ep->pollival % 1000;
1056 size *= ep->samplesz;
1057 if(size > ep->maxpkt){
1058 print("ohci: ep%d.%d: size > maxpkt\n",
1059 ep->dev->nb, ep->nb);
1060 print("size = %uld max = %ld\n", size, ep->maxpkt);
1064 memset(bp->wp, 0, size); /* in case we don't fill it on time */
1065 td->cbp0 = td->cbp = ptr2pa(bp->rp) & ~0xFFF;
1066 td->ctrl = TRUNC(iso->frno, Ntdframes);
1067 td->offsets[0] = (ptr2pa(bp->rp) & 0xFFF);
1068 td->offsets[0] |= (Tdnotacc << Tdiccshift);
1069 /* in case the controller checks out the offests... */
1070 for(i = 1; i < nelem(td->offsets); i++)
1071 td->offsets[i] = td->offsets[0];
1072 td->be = ptr2pa(bp->rp + size - 1);
1073 td->ctrl |= (0 << Tdfcshift); /* frame count is 1 */
1075 iso->frno = TRUNC(iso->frno + ep->pollival, Ntdframes);
1079 * start I/O on the dummy td and setup a new dummy to fill up.
1082 isoadvance(Ep *ep, Isoio *iso, Td *td)
1087 iso->atds = dtd->anext;
1090 dtd->bp->wp = dtd->bp->rp;
1092 td->nexttd = ptr2pa(dtd);
1093 isodtdinit(ep, iso, dtd);
1094 iso->ed->tail = ptr2pa(dtd);
1098 isocanwrite(void *a)
1103 return iso->state == Qclose || iso->err != nil ||
1104 iso->navail > iso->nframes / 2;
1113 if(iso->state == Qclose || iso->err != nil || iso->delay == 0)
1115 return (iso->nframes - iso->navail) <= iso->delay;
1119 * Service a completed/failed Td from the done queue.
1120 * It may be of any transfer type.
1121 * The queue is not in completion order.
1122 * (It's actually in reverse completion order).
1124 * When an error, a short packet, or a last Td is found
1125 * we awake the process waiting for the transfer.
1126 * Although later we will process other Tds completed
1127 * before, epio won't be able to touch the current Td
1128 * until interrupt returns and releases the lock on the
1132 qhinterrupt(Ctlr *, Ep *ep, Qio *io, Td *td, int)
1139 if(io->state != Qrun)
1141 if(tdtok(td) == Tdtokin)
1149 case Tddataovr: /* Overrun is not an error */
1151 /* virtualbox doesn't always report underflow on short packets */
1156 /* short input packets are ok */
1159 panic("ohci: short packet but cbp == 0");
1161 * td->cbp and td->cbp0 are the real addresses
1162 * corresponding to virtual addresses bp->wp and
1163 * bp->rp respectively.
1165 bp->wp = bp->rp + (td->cbp - td->cbp0);
1167 panic("ohci: wp < rp");
1169 * It's ok. clear error and flag as last in xfer.
1170 * epio must ignore following Tds.
1173 td->ctrl &= ~(Tdccmask << Tdccshift);
1176 /* else fall; it's an error */
1184 bp->wp = bp->rp; /* no bytes in xfer. */
1185 io->err = errmsg(err);
1186 if(debug || ep->debug){
1187 print("tdinterrupt: failed err %d (%s)\n", err, io->err);
1188 dumptd(td, "failed", ed->ctrl & Ediso);
1193 panic("ohci: td cc %ud unknown", err);
1198 * clear td list and halt flag.
1200 ed->head = (ed->head & Edtoggle) | ed->tail;
1201 ed->tds = pa2ptr(ed->tail);
1208 * BUG: Iso input streams are not implemented.
1211 isointerrupt(Ctlr *ctlr, Ep *ep, Qio *io, Td *td, int)
1220 if(io->state == Qclose)
1224 * When we get more than half the frames consecutive errors
1225 * we signal an actual error. Errors in the entire Td are
1226 * more serious and are always singaled.
1227 * Errors like overrun are not really errors. In fact, for
1228 * output, errors cannot be really detected. The driver will
1229 * hopefully notice I/O errors on input endpoints and detach the device.
1232 isoerr = (td->offsets[0] >> Tdiccshift) & Tdiccmask;
1233 if(isoerr == Tdok || isoerr == Tdnotacc)
1235 else if(iso->nerrs++ > iso->nframes/2)
1237 if(err != Tdok && err != Tddataovr){
1239 io->err = errmsg(err);
1240 if(debug || ep->debug){
1241 print("ohci: isointerrupt: ep%d.%d: err %d (%s) frnum 0x%lux\n",
1242 ep->dev->nb, ep->nb,
1243 err, errmsg(err), ctlr->ohci->fmnumber);
1244 dumptd(td, "failed", ed->ctrl & Ediso);
1247 td->bp->wp = td->bp->rp;
1249 td->anext = iso->atds;
1253 * If almost all Tds are avail the user is not doing I/O at the
1254 * required rate. We put another Td in place to keep the polling rate.
1256 if(iso->err == nil && iso->navail > iso->nframes - 10)
1257 isoadvance(ep, iso, pa2ptr(iso->ed->tail));
1259 * If there's enough buffering futher I/O can be done.
1261 if(isocanwrite(iso))
1266 interrupt(Ureg *, void *arg)
1271 ulong status, curred, done;
1277 done = ctlr->hcca->donehead;
1278 status = ctlr->ohci->intrsts;
1284 ctlr->hcca->donehead = 0;
1287 else if(status & Wdh){
1288 done = ctlr->hcca->donehead;
1289 ctlr->hcca->donehead = 0;
1296 ctlr->ohci->intrsts = status;
1297 status &= ctlr->ohci->intrenable;
1298 status &= Oc|Rhsc|Fno|Ue|Rd|Sf|Wdh|So;
1300 frno = TRUNC(ctlr->ohci->fmnumber, Ntdframes);
1301 td = pa2ptr(done & ~0xF);
1302 for(i = 0; td != nil && i < 1024; i++){
1303 if(0)ddprint("ohci tdinterrupt: td %#p\n", td);
1304 ntd = pa2ptr(td->nexttd & ~0xF);
1306 if(td->ep == nil || td->io == nil)
1307 panic("ohci: interrupt: ep %#p io %#p", td->ep, td->io);
1308 ohciinterrupts[td->ep->ttype]++;
1309 if(td->ep->ttype == Tiso)
1310 isointerrupt(ctlr, td->ep, td->io, td, frno);
1312 qhinterrupt(ctlr, td->ep, td->io, td, frno);
1316 iprint("ohci: bug: more than 1024 done Tds?\n");
1321 iprint("ohci: sched overrun: too much load\n");
1326 curred = ctlr->ohci->periodcurred;
1327 iprint("ohci: unrecoverable error frame 0x%.8lux ed 0x%.8lux, "
1328 "ints %d %d %d %d\n",
1329 ctlr->ohci->fmnumber, curred,
1330 ohciinterrupts[Tctl], ohciinterrupts[Tintr],
1331 ohciinterrupts[Tbulk], ohciinterrupts[Tiso]);
1333 dumped(pa2ptr(curred));
1337 iprint("ohci interrupt: unhandled sts 0x%.8lux\n", status);
1338 ctlr->ohci->intrdisable = status;
1344 * The old dummy Td is used to implement the new Td.
1345 * A new dummy is linked at the end of the old one and
1346 * returned, to link further Tds if needed.
1349 epgettd(Ep *ep, Qio *io, Td **dtdp, int flags, void *a, int count)
1358 panic("ohci: transfer > two pages");
1359 /* maximum of one physical page crossing allowed */
1360 bp = allocb(count+BY2PG);
1361 bp->rp = (uchar*)PGROUND((uintptr)bp->rp);
1368 td->cbp0 = td->cbp = ptr2pa(bp->wp);
1369 td->be = ptr2pa(bp->wp + count - 1);
1371 /* validaddr((uintptr)a, count, 0); DEBUG */
1373 assert(bp->wp != nil);
1374 memmove(bp->wp, a, count);
1379 td->ctrl = io->tok|Tdusetog|io->toggle|flags;
1380 if(io->toggle == Tddata0)
1381 io->toggle = Tddata1;
1383 io->toggle = Tddata0;
1384 assert(td->ep == ep);
1386 dtd = tdalloc(); /* new dummy */
1388 td->nexttd = ptr2pa(dtd);
1395 * Try to get them idle
1407 for(td = ed->tds; td != nil; td = td->next)
1409 td->bp->wp = td->bp->rp;
1410 ed->head = (ed->head&0xF) | ed->tail;
1411 if((ed->ctrl & Ediso) == 0)
1412 ed->tds = pa2ptr(ed->tail);
1421 return io->state != Qrun;
1425 epiowait(Ctlr *ctlr, Qio *io, int tmout, ulong)
1431 if(0)ddqprint("ohci io %#p sleep on ed %#p state %s\n",
1432 io, ed, iosname[io->state]);
1435 dqprint("ohci io %#p ed %#p timed out\n", io, ed);
1439 sleep(io, epiodone, io);
1441 tsleep(io, epiodone, io, tmout);
1445 if(io->state == Qrun)
1447 else if(io->state != Qdone && io->state != Qclose)
1448 panic("epio: ed not done and not closed");
1451 io->err = "request timed out";
1454 tsleep(&up->sleep, return0, 0, Abortdelay);
1459 if(io->state != Qclose)
1466 * To make it work for control transfers, the caller may
1467 * lock the Qio for the entire control transfer.
1470 epio(Ep *ep, Qio *io, void *a, long count, int mustlock)
1477 Td *td, *ltd, *ntd, *td0;
1478 int last, ntds, tmout;
1484 io->debug = ep->debug;
1486 ddeprint("ohci: %s ep%d.%d io %#p count %ld\n",
1487 io->tok == Tdtokin ? "in" : "out",
1488 ep->dev->nb, ep->nb, io, count);
1489 if((debug > 1 || ep->debug > 1) && io->tok != Tdtokin){
1490 seprintdata(buf, buf+sizeof(buf), a, count);
1491 print("\t%s\n", buf);
1502 if(io->state == Qclose){ /* Tds released by cancelio */
1504 error(io->err ? io->err : Eio);
1506 if(io->state != Qidle)
1507 panic("epio: qio not idle");
1508 io->state = Qinstall;
1511 ltd = td0 = ed->tds;
1517 if(c != nil && io->tok != Tdtokin)
1518 td = epgettd(ep, io, <d, 0, c+tot, n);
1520 td = epgettd(ep, io, <d, 0, nil, n);
1523 }while(tot < count);
1524 if(td0 == nil || ltd == nil || td0 == ltd)
1525 panic("epio: no td");
1527 if(debug > 2 || ep->debug > 2)
1528 dumptds(td0, "put td", ep->ttype == Tiso);
1532 if(io->state != Qclose){
1533 io->iotime = TK2MS(MACHP(0)->ticks);
1535 ed->tail = ptr2pa(ltd);
1536 if(ep->ttype == Tctl)
1537 ctlr->ohci->cmdsts |= Sclf;
1538 else if(ep->ttype == Tbulk)
1539 ctlr->ohci->cmdsts |= Sblf;
1543 epiowait(ctlr, io, tmout, load);
1545 if(debug > 1 || ep->debug > 1)
1546 dumptds(td0, "got td", 0);
1552 for(td = td0; td != ltd; td = ntd){
1555 * If the Td is flagged as last we must
1556 * ignore any following Td. The block may
1557 * seem to have bytes but interrupt has not seen
1558 * those Tds through the done queue, and they are void.
1560 if(last == 0 && tderrs(td) == Tdok){
1563 if(c != nil && tdtok(td) == Tdtokin && n > 0){
1564 memmove(c, td->bp->rp, n);
1572 if(edtoggle(ed) == 0)
1573 io->toggle = Tddata0;
1575 io->toggle = Tddata1;
1582 ddeprint("ohci: io %#p: %d tds: return %ld err '%s'\n\n",
1583 io, ntds, tot, err);
1592 * halt condition was cleared on the endpoint. update our toggles.
1604 if(ep->mode != OREAD){
1606 io[OWRITE].toggle = Tddata0;
1607 deprint("ep clrhalt for io %#p\n", io+OWRITE);
1608 qunlock(&io[OWRITE]);
1610 if(ep->mode != OWRITE){
1612 io[OREAD].toggle = Tddata0;
1613 deprint("ep clrhalt for io %#p\n", io+OREAD);
1614 qunlock(&io[OREAD]);
1621 epread(Ep *ep, void *a, long count)
1629 panic("epread: not open");
1639 ddeprint("epread ctl ndata %d\n", cio->ndata);
1641 error("request expected");
1642 else if(cio->ndata == 0){
1646 if(count > cio->ndata)
1649 memmove(a, cio->data, count);
1650 /* BUG for big transfers */
1653 cio->ndata = 0; /* signal EOF next time */
1657 if(debug>1 || ep->debug){
1658 seprintdata(buf, buf+sizeof(buf), a, count);
1659 print("epread: %s\n", buf);
1666 return epio(ep, &io[OREAD], a, count, 1);
1669 delta = TK2MS(MACHP(0)->ticks) - io[OREAD].iotime + 1;
1670 if(delta < ep->pollival / 2)
1671 tsleep(&up->sleep, return0, 0, ep->pollival/2 - delta);
1674 return epio(ep, &io[OREAD], a, count, 1);
1676 error("iso read not implemented");
1679 panic("epread: bad ep ttype %d", ep->ttype);
1685 * Control transfers are one setup write (data0)
1686 * plus zero or more reads/writes (data1, data0, ...)
1687 * plus a final write/read with data1 to ack.
1688 * For both host to device and device to host we perform
1689 * the entire transfer when the user writes the request,
1690 * and keep any data read from the device for a later read.
1691 * We call epio three times instead of placing all Tds at
1692 * the same time because doing so leads to crc/tmout errors
1694 * Upon errors on the data phase we must still run the status
1695 * phase or the device may cease responding in the future.
1698 epctlio(Ep *ep, Ctlio *cio, void *a, long count)
1703 ddeprint("epctlio: cio %#p ep%d.%d count %ld\n",
1704 cio, ep->dev->nb, ep->nb, count);
1705 if(count < Rsetuplen)
1706 error("short usb command");
1719 /* set the address if unset and out of configuration state */
1720 if(ep->dev->state != Dconfig && ep->dev->state != Dreset)
1721 if(cio->usbid == 0){
1722 cio->usbid = (ep->nb&Epmax)<<7 | (ep->dev->nb&Devmax);
1723 edsetaddr(cio->ed, cio->usbid);
1725 /* adjust maxpkt if the user has learned a different one */
1726 if(edmaxpkt(cio->ed) != ep->maxpkt)
1727 edsetmaxpkt(cio->ed, ep->maxpkt);
1729 cio->tok = Tdtoksetup;
1730 cio->toggle = Tddata0;
1731 if(epio(ep, cio, a, Rsetuplen, 0) < Rsetuplen)
1737 cio->toggle = Tddata1;
1738 if(c[Rtype] & Rd2h){
1740 len = GET2(c+Rcount);
1742 error("bad length in d2h request");
1744 error("d2h data too large to fit in ohci");
1745 a = cio->data = smalloc(len+1);
1747 cio->tok = Tdtokout;
1754 len = epio(ep, cio, a, len, 0);
1757 if(c[Rtype] & Rd2h){
1760 cio->tok = Tdtokout;
1765 count = Rsetuplen + len;
1768 cio->toggle = Tddata1;
1769 epio(ep, cio, nil, 0, 0);
1772 ddeprint("epctlio cio %#p return %ld\n", cio, count);
1777 * Put new samples in the dummy Td.
1780 putsamples(Ctlr *ctlr, Ep *ep, Isoio *iso, uchar *b, long n)
1784 td = pa2ptr(iso->ed->tail);
1785 if(n > td->nbytes - BLEN(td->bp))
1786 n = td->nbytes - BLEN(td->bp);
1787 assert(td->bp->wp + n <= td->bp->lim);
1788 iunlock(ctlr); /* We could page fault here */
1789 memmove(td->bp->wp, b, n);
1791 if(td == pa2ptr(iso->ed->tail)){
1793 if(BLEN(td->bp) == td->nbytes) /* full Td: activate it */
1794 isoadvance(ep, iso, td);
1800 episowrite(Ep *ep, void *a, long count)
1810 iso->delay = (ep->sampledelay*ep->samplesz + ep->maxpkt-1) / ep->maxpkt;
1811 iso->debug = ep->debug;
1818 diprint("ohci: episowrite: %#p ep%d.%d\n", iso, ep->dev->nb, ep->nb);
1820 if(iso->state == Qclose){
1822 error(iso->err ? iso->err : Eio);
1826 for(tot = 0; tot < count; tot += nw){
1827 while(isocanwrite(iso) == 0){
1829 diprint("ohci: episowrite: %#p sleep\n", iso);
1832 iso->err = "I/O timed out";
1836 tsleep(iso, isocanwrite, iso, ep->tmout);
1842 if(iso->state == Qclose || err != nil){
1844 error(err ? err : Eio);
1846 if(iso->state != Qrun)
1847 panic("episowrite: iso not running");
1848 nw = putsamples(ctlr, ep, iso, b+tot, count-tot);
1850 while(isodelay(iso) == 0){
1852 sleep(iso, isodelay, iso);
1855 if(iso->state != Qclose)
1858 err = iso->err; /* in case it failed early */
1864 diprint("ohci: episowrite: %#p %ld bytes\n", iso, tot);
1869 epwrite(Ep *ep, void *a, long count)
1878 panic("ohci: epwrite: not open");
1882 return epctlio(ep, cio, a, count);
1888 * Put at most Tdatomic Tds (512 bytes) at a time.
1889 * Otherwise some devices produce babble errors.
1893 for(tot = 0; tot < count ; tot += nw){
1895 if(nw > Tdatomic * ep->maxpkt)
1896 nw = Tdatomic * ep->maxpkt;
1897 nw = epio(ep, &io[OWRITE], b+tot, nw, 1);
1902 delta = TK2MS(MACHP(0)->ticks) - io[OWRITE].iotime + 1;
1903 if(delta < ep->pollival)
1904 tsleep(&up->sleep, return0, 0, ep->pollival - delta);
1907 return epio(ep, &io[OWRITE], a, count, 1);
1909 return episowrite(ep, a, count);
1911 panic("ohci: epwrite: bad ep ttype %d", ep->ttype);
1917 newed(Ctlr *ctlr, Ep *ep, Qio *io, char *)
1922 ed = io->ed = edalloc(); /* no errors raised here, really */
1926 ed->tail = ptr2pa(td);
1927 ed->head = ptr2pa(td);
1930 ed->ctrl = (ep->maxpkt & Edmpsmask) << Edmpsshift;
1931 if(ep->ttype == Tiso)
1938 /* For setup endpoints we start with the config address */
1939 if(ep->ttype != Tctl)
1940 edsetaddr(io->ed, io->usbid);
1941 if(ep->dev->speed == Lowspeed)
1951 ed->ctrl |= Edtddir; /* Td will say */
1958 edlinked(ed, ctlhd(ctlr));
1964 edlinked(ed, bulkhd(ctlr));
1965 setbulkhd(ctlr, ed);
1971 schedq(ctlr, io, ep->pollival);
1975 panic("ohci: newed: bad ttype");
1982 isoopen(Ctlr *ctlr, Ep *ep)
1989 iso->usbid = (ep->nb&Epmax)<<7 | (ep->dev->nb&Devmax);
1990 iso->bw = ep->hz * ep->samplesz; /* bytes/sec */
1991 if(ep->mode != OWRITE){
1992 print("ohci: bug: iso input streams not implemented\n");
1993 error("ohci iso input streams not implemented");
1995 iso->tok = Tdtokout;
1999 iso->frno = TRUNC(ctlr->ohci->fmnumber + 10, Ntdframes);
2000 iso->nframes = 1000 / ep->pollival;
2001 if(iso->nframes < 10){
2002 print("ohci: isoopen: less than 10 frames; using 10.\n");
2005 iso->navail = iso->nframes;
2006 iso->atds = edtds = nil;
2007 for(i = 0; i < iso->nframes-1; i++){ /* -1 for dummy */
2011 td->bp = allocb(ep->maxpkt);
2012 td->anext = iso->atds; /* link as avail */
2017 newed(ctlr, ep, iso, "iso"); /* allocates a dummy td */
2018 iso->ed->tds->bp = allocb(ep->maxpkt); /* but not its block */
2019 iso->ed->tds->next = edtds;
2020 isodtdinit(ep, iso, iso->ed->tds);
2024 * Allocate the endpoint and set it up for I/O
2025 * in the controller. This must follow what's said
2026 * in Ep regarding configuration, including perhaps
2027 * the saved toggles (saved on a previous close of
2028 * the endpoint data file by epclose).
2039 deprint("ohci: epopen ep%d.%d\n", ep->dev->nb, ep->nb);
2041 panic("ohci: epopen called with open ep");
2049 error("endpoint not configured");
2051 ep->aux = smalloc(sizeof(Isoio));
2055 cio = ep->aux = smalloc(sizeof(Ctlio));
2056 cio->debug = ep->debug;
2059 cio->tok = -1; /* invalid; Tds will say */
2060 if(ep->dev->isroot != 0 && ep->nb == 0) /* root hub */
2062 newed(ctlr, ep, cio, "epc");
2065 ep->pollival = 1; /* assume this; doesn't really matter */
2068 io = ep->aux = smalloc(sizeof(Qio)*2);
2069 io[OREAD].debug = io[OWRITE].debug = ep->debug;
2070 usbid = (ep->nb&Epmax)<<7 | (ep->dev->nb&Devmax);
2071 if(ep->mode != OREAD){
2072 if(ep->toggle[OWRITE] != 0)
2073 io[OWRITE].toggle = Tddata1;
2075 io[OWRITE].toggle = Tddata0;
2076 io[OWRITE].tok = Tdtokout;
2077 io[OWRITE].usbid = usbid;
2078 io[OWRITE].bw = ep->maxpkt*1000/ep->pollival; /* bytes/s */
2079 newed(ctlr, ep, io+OWRITE, "epw");
2081 if(ep->mode != OWRITE){
2082 if(ep->toggle[OREAD] != 0)
2083 io[OREAD].toggle = Tddata1;
2085 io[OREAD].toggle = Tddata0;
2086 io[OREAD].tok = Tdtokin;
2087 io[OREAD].usbid = usbid;
2088 io[OREAD].bw = ep->maxpkt*1000/ep->pollival; /* bytes/s */
2089 newed(ctlr, ep, io+OREAD, "epr");
2093 deprint("ohci: epopen done:\n");
2094 if(debug || ep->debug)
2100 cancelio(Ep *ep, Qio *io)
2108 if(io == nil || io->state == Qclose){
2109 assert(io == nil || io->ed == nil);
2119 tsleep(&up->sleep, return0, 0, Abortdelay);
2125 /* wait for epio if running */
2131 unlinkctl(ctlr, ed);
2134 unlinkbulk(ctlr, ed);
2141 panic("ohci cancelio: bad ttype");
2155 deprint("ohci: epclose ep%d.%d\n", ep->dev->nb, ep->nb);
2157 panic("ohci: epclose called with closed ep");
2168 if(ep->mode != OWRITE){
2169 cancelio(ep, &io[OREAD]);
2170 if(io[OREAD].toggle == Tddata1)
2171 ep->toggle[OREAD] = 1;
2173 if(ep->mode != OREAD){
2174 cancelio(ep, &io[OWRITE]);
2175 if(io[OWRITE].toggle == Tddata1)
2176 ep->toggle[OWRITE] = 1;
2184 panic("epclose: bad ttype %d", ep->ttype);
2187 deprint("ohci: epclose ep%d.%d: done\n", ep->dev->nb, ep->nb);
2193 portreset(Hci *hp, int port, int on)
2202 eqlock(&ctlr->resetl);
2204 qunlock(&ctlr->resetl);
2209 ohci->rhportsts[port - 1] = Spp;
2210 if((ohci->rhportsts[port - 1] & Ccs) == 0){
2212 error("port not connected");
2214 ohci->rhportsts[port - 1] = Spr;
2215 while((ohci->rhportsts[port - 1] & Prsc) == 0){
2217 dprint("ohci: portreset, wait for reset complete\n");
2220 ohci->rhportsts[port - 1] = Prsc;
2223 qunlock(&ctlr->resetl);
2228 portenable(Hci *hp, int port, int on)
2233 dprint("ohci: %#p port %d enable=%d\n", ctlr->ohci, port, on);
2234 eqlock(&ctlr->resetl);
2236 qunlock(&ctlr->resetl);
2241 ctlr->ohci->rhportsts[port - 1] = Spe | Spp;
2243 ctlr->ohci->rhportsts[port - 1] = Cpe;
2245 tsleep(&up->sleep, return0, 0, Enabledelay);
2247 qunlock(&ctlr->resetl);
2252 portstatus(Hci *hp, int port)
2259 * We must return status bits as a
2260 * get port status hub request would do.
2263 ohcistatus = ub->ohci->rhportsts[port - 1];
2265 if(ohcistatus & Ccs)
2267 if(ohcistatus & Pes)
2269 if(ohcistatus & Pss)
2271 if(ohcistatus & Prs)
2274 /* port is not in reset; these potential writes are ok */
2275 if(ohcistatus & Csc){
2277 ub->ohci->rhportsts[port - 1] = Csc;
2279 if(ohcistatus & Pesc){
2281 ub->ohci->rhportsts[port - 1] = Pesc;
2284 if(ohcistatus & Lsda)
2286 if(v & (HPstatuschg|HPchange))
2287 ddprint("ohci port %d sts %#ulx hub sts %#x\n", port, ohcistatus, v);
2292 dumpohci(Ctlr *ctlr)
2297 ohci = &ctlr->ohci->revision;
2298 print("ohci registers: \n");
2299 for(i = 0; i < sizeof(Ohci)/sizeof(ulong); i++)
2300 if(i < 3 || ohci[i] != 0)
2301 print("\t[%#2.2x]\t%#8.8ulx\n", i * 4, ohci[i]);
2311 ulong ival, ctrl, fmi;
2314 dprint("ohci %#p init\n", ctlr->ohci);
2317 fmi = ohci->fminterval;
2318 ohci->cmdsts = Shcr; /* reset the block */
2319 for(i = 0; i<100; i++){
2320 if((ohci->cmdsts & Shcr) == 0)
2322 delay(1); /* wait till reset complete, Ohci says 10us max. */
2325 print("ohci: reset timed out\n");
2326 ohci->fminterval = fmi;
2329 * now that soft reset is done we are in suspend state.
2330 * Setup registers which take in suspend state
2331 * (will only be here for 2ms).
2334 ctlr->ohci->hcca = ptr2pa(ctlr->hcca);
2335 setctlhd(ctlr, nil);
2336 ctlr->ohci->ctlcurred = 0;
2337 setbulkhd(ctlr, nil);
2338 ctlr->ohci->bulkcurred = 0;
2340 ohci->intrenable = Mie | Wdh | Ue;
2341 ohci->control |= Ccle | Cble | Cple | Cie | Cfsoper;
2343 /* set frame after operational */
2344 ohci->rhdesca = Nps; /* no power switching */
2345 if(ohci->rhdesca & Nps){
2346 dprint("ohci: ports are not power switched\n");
2348 dprint("ohci: ports are power switched\n");
2349 ohci->rhdesca &= ~Psm;
2350 ohci->rhsts &= ~Lpsc;
2352 for(i = 0; i < ctlr->nports; i++) /* paranoia */
2353 ohci->rhportsts[i] = 0; /* this has no effect */
2356 for(i = 0; i < ctlr->nports; i++){
2357 ohci->rhportsts[i] = Spp;
2358 if((ohci->rhportsts[i] & Ccs) != 0)
2359 ohci->rhportsts[i] |= Spr;
2363 ctrl = ohci->control;
2364 if((ctrl & Cfsmask) != Cfsoper){
2365 ctrl = (ctrl & ~Cfsmask) | Cfsoper;
2366 ohci->control = ctrl;
2369 ival = ohci->fminterval & ~(Fmaxpktmask << Fmaxpktshift);
2370 ohci->fminterval = ival | (5120 << Fmaxpktshift);
2383 static int already = 0;
2389 while(p = pcimatch(p, 0, 0)) {
2391 * Find Ohci controllers (Programming Interface = 0x10).
2393 if(p->ccrb != Pcibcserial || p->ccru != Pciscusb ||
2396 mem = p->mem[0].bar & ~0x0F;
2397 dprint("ohci: %x/%x port 0x%lux size 0x%x irq %d\n",
2398 p->vid, p->did, mem, p->mem[0].size, p->intl);
2400 print("ohci: failed to map registers\n");
2404 ctlr = malloc(sizeof(Ctlr));
2406 print("ohci: no memory\n");
2410 ctlr->ohci = vmap(mem, p->mem[0].size);
2411 dprint("scanpci: ctlr %#p, ohci %#p\n", ctlr, ctlr->ohci);
2414 for(i = 0; i < Nhcis; i++)
2415 if(ctlrs[i] == nil){
2420 print("ohci: bug: no more controllers\n");
2425 usbdebug(Hci*, int d)
2431 * build the periodic scheduling tree:
2432 * framesize must be a multiple of the tree size
2435 mkqhtree(Ctlr *ctlr)
2437 int i, n, d, o, leaf0, depth;
2442 n = (1 << (depth+1)) - 1;
2443 qt = mallocz(sizeof(*qt), 1);
2445 panic("ohci: can't allocate scheduling tree");
2448 qt->bw = mallocz(n * sizeof(qt->bw), 1);
2449 qt->root = tree = mallocz(n * sizeof(Ed *), 1);
2450 if(qt->bw == nil || qt->root == nil)
2451 panic("ohci: can't allocate scheduling tree");
2452 for(i = 0; i < n; i++){
2453 if((tree[i] = edalloc()) == nil)
2454 panic("ohci: mkqhtree");
2455 tree[i]->ctrl = (8 << Edmpsshift); /* not needed */
2456 tree[i]->ctrl |= Edskip;
2459 edlinked(tree[i], tree[(i-1)/2]);
2461 edlinked(tree[i], nil);
2464 dprint("ohci: tree: %d endpoints allocated\n", i);
2466 /* distribute leaves evenly round the frame list */
2468 for(i = 0; i < 32; i++){
2470 for(d = 0; d < depth; d++){
2476 print("leaf0=%d o=%d i=%d n=%d\n", leaf0, o, i, n);
2479 ctlr->hcca->intrtable[i] = ptr2pa(tree[leaf0 + o]);
2485 ohcimeminit(Ctlr *ctlr)
2489 edfree(edalloc()); /* allocate pools now */
2492 hcca = xspanalloc(sizeof(Hcca), 256, 0);
2494 panic("ohci: no memory for Hcca");
2495 memset(hcca, 0, sizeof(*hcca));
2502 ohcireset(Ctlr *ctlr)
2507 dprint("ohci %#p reset\n", ctlr->ohci);
2509 if(ctlr->ohci->control & Cir){
2510 dprint("ohci: smm active, taking over\n");
2511 ctlr->ohci->cmdsts |= Socr; /* take ownership */
2512 for(i = 0; i<100; i++){
2513 if((ctlr->ohci->control & Cir) == 0)
2518 print("ohci: smm takeover timed out\n");
2522 * usually enter here in reset, wait till its through,
2523 * then do our own so we are on known timing conditions.
2527 ctlr->ohci->control = 0;
2530 /* legacy support register: turn off lunacy mode */
2531 pcicfgw16(ctlr->pcidev, 0xc0, 0x2000);
2544 ctlr->ohci->intrdisable = Mie;
2545 ctlr->ohci->intrenable = 0;
2546 ctlr->ohci->control = 0;
2557 static Lock resetlck;
2559 if(getconf("*nousbohci"))
2565 * Any adapter matches if no hp->port is supplied,
2566 * otherwise the ports must match.
2569 for(i = 0; i < Nhcis && ctlrs[i] != nil; i++){
2571 if(ctlr->active == 0)
2572 if(hp->port == 0 || hp->port == (uintptr)ctlr->ohci){
2578 if(ctlrs[i] == nil || i == Nhcis)
2580 if(ctlr->ohci->control == ~0)
2586 hp->port = (uintptr)ctlr->ohci;
2589 ctlr->nports = hp->nports = ctlr->ohci->rhdesca & 0xff;
2595 * Linkage to the generic HCI driver.
2599 hp->interrupt = interrupt;
2600 hp->epopen = epopen;
2601 hp->epclose = epclose;
2602 hp->epread = epread;
2603 hp->epwrite = epwrite;
2604 hp->seprintep = seprintep;
2605 hp->portenable = portenable;
2606 hp->portreset = portreset;
2607 hp->portstatus = portstatus;
2608 hp->shutdown = shutdown;
2609 hp->debug = usbdebug;
2613 * IRQ2 doesn't really exist, it's used to gang the interrupt
2614 * controllers together. A device set to IRQ2 will appear on
2615 * the second interrupt controller as IRQ9.
2619 intrenable(hp->irq, hp->interrupt, hp, hp->tbdf, hp->type);
2627 addhcitype("ohci", reset);