1 /* override default macros from ../port/usb.h */
6 #define dprint if(ehcidebug)print
7 #define ddprint if(ehcidebug>1)print
8 #define deprint if(ehcidebug || ep->debug)print
9 #define ddeprint if(ehcidebug>1 || ep->debug>1)print
11 typedef struct Ctlr Ctlr;
12 typedef struct Ecapio Ecapio;
13 typedef struct Edbgio Edbgio;
14 typedef struct Eopio Eopio;
15 typedef struct Isoio Isoio;
16 typedef struct Poll Poll;
18 typedef struct Qtree Qtree;
20 #pragma incomplete Ctlr;
21 #pragma incomplete Ecapio;
22 #pragma incomplete Edbgio;
23 #pragma incomplete Eopio;
24 #pragma incomplete Isoio;
25 #pragma incomplete Poll;
26 #pragma incomplete Qh;
27 #pragma incomplete Qtree;
30 * EHCI interface registers and bits
34 Cnports = 0xF, /* nport bits in Ecapio parms. */
35 Cdbgportshift = 20, /* debug port in Ecapio parms. */
37 C64 = 1, /* 64-bits, in Ecapio capparms. */
38 Ceecpshift = 8, /* extended capabilities ptr. in */
39 Ceecpmask = 8, /* the Ecapio capparms reg. */
40 Clegacy = 1, /* legacy support cap. id */
41 CLbiossem = 2, /* legacy cap. bios sem. */
42 CLossem = 3, /* legacy cap. os sem */
43 CLcontrol = 4, /* legacy support control & status */
50 Lfstn = 3<<1, /* we don't use these */
53 Cstop = 0x00000, /* stop running */
54 Crun = 0x00001, /* start operation */
55 Chcreset = 0x00002, /* host controller reset */
56 Cflsmask = 0x0000C, /* frame list size bits */
57 Cfls1024 = 0x00000, /* frame list size 1024 */
58 Cfls512 = 0x00004, /* frame list size 512 frames */
59 Cfls256 = 0x00008, /* frame list size 256 frames */
60 Cpse = 0x00010, /* periodic sched. enable */
61 Case = 0x00020, /* async sched. enable */
62 Ciasync = 0x00040, /* interrupt on async advance doorbell */
63 Citc1 = 0x10000, /* interrupt threshold ctl. 1 µframe */
64 Citc4 = 0x40000, /* same. 2 µframes */
66 Citc8 = 0x80000, /* same. 8 µframes (can go up to 64) */
69 Sasyncss = 0x08000, /* aync schedule status */
70 Speriodss = 0x04000, /* periodic schedule status */
71 Srecl = 0x02000, /* reclamnation (empty async sched.) */
72 Shalted = 0x01000, /* h.c. is halted */
73 Sasync = 0x00020, /* interrupt on async advance */
74 Sherr = 0x00010, /* host system error */
75 Sfrroll = 0x00008, /* frame list roll over */
76 Sportchg = 0x00004, /* port change detect */
77 Serrintr = 0x00002, /* error interrupt */
78 Sintr = 0x00001, /* interrupt */
79 Sintrs = 0x0003F, /* interrupts status */
82 Iusb = 0x01, /* intr. on usb */
83 Ierr = 0x02, /* intr. on usb error */
84 Iportchg = 0x04, /* intr. on port change */
85 Ifrroll = 0x08, /* intr. on frlist roll over */
86 Ihcerr = 0x10, /* intr. on host error */
87 Iasync = 0x20, /* intr. on async advance enable */
88 Iall = 0x3F, /* all interrupts */
91 Callmine = 1, /* route all ports to us */
94 Pspresent = 0x00000001, /* device present */
95 Psstatuschg = 0x00000002, /* Pspresent changed */
96 Psenable = 0x00000004, /* device enabled */
97 Pschange = 0x00000008, /* Psenable changed */
98 Psresume = 0x00000040, /* resume detected */
99 Pssuspend = 0x00000080, /* port suspended */
100 Psreset = 0x00000100, /* port reset */
101 Pspower = 0x00001000, /* port power on */
102 Psowner = 0x00002000, /* port owned by companion */
103 Pslinemask = 0x00000C00, /* line status bits */
104 Pslow = 0x00000400, /* low speed device */
106 /* Debug port csw reg. */
107 Cowner = 0x40000000, /* port owned by ehci */
108 Cenable = 0x10000000, /* debug port enabled */
109 Cdone = 0x00010000, /* request is done */
110 Cbusy = 0x00000400, /* port in use by a driver */
111 Cerrmask= 0x00000380, /* error code bits */
112 Chwerr = 0x00000100, /* hardware error */
113 Cterr = 0x00000080, /* transaction error */
114 Cfailed = 0x00000040, /* transaction did fail */
115 Cgo = 0x00000020, /* execute the transaction */
116 Cwrite = 0x00000010, /* request is a write */
117 Clen = 0x0000000F, /* data len */
119 /* Debug port pid reg. */
120 Prpidshift = 16, /* received pid */
122 Pspidshift = 8, /* sent pid */
124 Ptokshift = 0, /* token pid */
127 Ptoggle = 0x00008800, /* to update toggles */
128 Ptogglemask = 0x0000FF00,
130 /* Debug port addr reg. */
131 Adevshift = 8, /* device address */
133 Aepshift = 0, /* endpoint number */
138 * Capability registers (hw)
142 ulong cap; /* 00 controller capability register */
143 ulong parms; /* 04 structural parameters register */
144 ulong capparms; /* 08 capability parameters */
145 ulong portroute; /* 0c not on the CS5536 */
149 * Debug port registers (hw)
153 ulong csw; /* control and status */
154 ulong pid; /* USB pid */
155 uchar data[8]; /* data buffer */
156 ulong addr; /* device and endpoint addresses */
169 Rendez; /* for waiting to async advance doorbell */
170 Lock; /* for ilock. qh lists and basic ctlr I/O */
171 QLock portlck; /* for port resets/enable... (and doorbell) */
172 int active; /* in use or not */
174 Ecapio* capio; /* Capability i/o regs */
175 Eopio* opio; /* Operational i/o regs */
177 int nframes; /* 1024, 512, or 256 frames in the list */
178 ulong* frames; /* periodic frame list (hw) */
179 Qh* qhs; /* async Qh circular list for bulk/ctl */
180 Qtree* tree; /* tree of Qhs for the periodic list */
181 int ntree; /* number of dummy qhs in tree */
182 Qh* intrqhs; /* list of (not dummy) qhs in tree */
183 Isoio* iso; /* list of active Iso I/O */
186 int nintr; /* number of interrupts attended */
187 int ntdintr; /* number of intrs. with something to do */
188 int nqhintr; /* number of async td intrs. */
189 int nisointr; /* number of periodic td intrs. */
199 * Operational registers (hw)
203 ulong cmd; /* 00 command */
204 ulong sts; /* 04 status */
205 ulong intr; /* 08 interrupt enable */
206 ulong frno; /* 0c frame index */
207 ulong seg; /* 10 bits 63:32 of EHCI datastructs (unused) */
208 ulong frbase; /* 14 frame list base addr, 4096-byte boundary */
209 ulong link; /* 18 link for async list */
210 uchar d2c[0x40-0x1c]; /* 1c dummy */
211 ulong config; /* 40 1: all ports default-routed to this HC */
212 ulong portsc[1]; /* 44 Port status and control, one per port */
215 extern int ehcidebug;
216 extern Ecapio *ehcidebugcapio;
217 extern int ehcidebugport;
219 void ehcilinkage(Hci *hp);
220 void ehcimeminit(Ctlr *ctlr);
221 void ehcirun(Ctlr *ctlr, int on);