2 #include "../port/lib.h"
7 #include "../port/error.h"
9 extern PhysUart i8250physuart;
10 extern PhysUart pciphysuart;
11 extern void* i8250alloc(int, int, int);
13 static Uart *perlehead, *perletail;
16 uartpci(int ctlrno, Pcidev* p, int barno, int n, int freq, char* name,
24 head = malloc(sizeof(Uart)*n);
26 print("uartpci: no memory for Uarts\n");
30 io = p->mem[barno].bar & ~0x01;
31 snprint(buf, sizeof(buf), "%s%d", pciphysuart.name, ctlrno);
32 if(ioalloc(io, p->mem[barno].size, 0, buf) < 0){
33 print("uartpci: I/O 0x%uX in use\n", io);
40 for(i = 0; i < n; i++){
41 ctlr = i8250alloc(io + i*iosize, p->intl, p->tbdf);
46 snprint(buf, sizeof(buf), "%s.%8.8uX", name, p->tbdf);
47 kstrdup(&uart->name, buf);
49 uart->phys = &i8250physuart;
51 (uart-1)->next = uart;
61 perletail->next = head;
64 for(perletail = head; perletail->next != nil;
65 perletail = perletail->next)
72 ultraport16si(int ctlrno, Pcidev *p, ulong freq)
78 name = "Ultraport16si"; /* 16L788 UARTs */
79 io = p->mem[4].bar & ~1;
80 if (ioalloc(io, p->mem[4].size, 0, name) < 0) {
81 print("uartpci: can't get IO space to set %s to rs-232\n", name);
84 for (i = 0; i < 16; i++) {
86 outb(io, (i << 4) + 1); /* set to RS232 mode (Don't ask!) */
89 uart = uartpci(ctlrno, p, 2, 8, freq, name, 16);
91 uart = uartpci(ctlrno, p, 3, 8, freq, name, 16);
105 * Loop through all PCI devices looking for simple serial
106 * controllers (ccrb == Pcibccomm (7)) and configure the ones which
107 * are familiar. All suitable devices are configured to
108 * simply point to the generic i8250 driver.
110 perlehead = perletail = nil;
112 for(p = pcimatch(nil, 0, 0); p != nil; p = pcimatch(p, 0, 0)){
113 /* StarTech PCI8S9503V has ccru == 0x80 (other) */
114 if(p->ccrb != Pcibccomm || p->ccru > 2 && p->ccru != 0x80)
117 switch(p->did<<16 | p->vid){
120 case (0x9835<<16)|0x9710: /* StarTech PCI2S550 */
121 uart = uartpci(ctlrno, p, 0, 1, 1843200, "PCI2S550-0", 8);
124 uart->next = uartpci(ctlrno, p, 1, 1, 1843200,
126 if(uart->next == nil)
129 case (0x950A<<16)|0x1415: /* Oxford Semi OX16PCI954 */
130 case (0x9501<<16)|0x1415:
131 case (0x9521<<16)|0x1415:
133 * These are common devices used by 3rd-party
135 * Must check the subsystem VID and DID for correct
138 subid = pcicfgr16(p, PciSVID);
139 subid |= pcicfgr16(p, PciSID)<<16;
142 print("oxsemi uart %.8#ux of vid %#ux did %#ux unknown\n",
143 subid, p->vid, p->did);
146 uart = uartpci(ctlrno, p, 0, 4, 1843200,
147 "starport-pex4s", 8);
150 uart = uartpci(ctlrno, p, 0, 2, 14745600,
151 "starport-pex2s", 8);
153 case (0x2000<<16)|0x131F:/* SIIG CyberSerial PCIe */
154 uart = uartpci(ctlrno, p, 0, 1, 18432000,
155 "CyberSerial-1S", 8);
159 case (0x9505<<16)|0x1415: /* Oxford Semi OXuPCI952 */
160 name = "SATAGear-IOI-102"; /* PciSVID=1415, PciSID=0 */
161 if (uartpci(ctlrno, p, 0, 1, 14745600, name, 8) != nil)
163 if (uartpci(ctlrno, p, 1, 1, 14745600, name, 8) != nil)
165 uart = nil; /* don't ctlrno++ below */
167 case (0x9050<<16)|0x10B5: /* Perle PCI-Fast4 series */
168 case (0x9030<<16)|0x10B5: /* Perle Ultraport series */
170 * These devices consists of a PLX bridge (the above
171 * PCI VID+DID) behind which are some 16C654 UARTs.
172 * Must check the subsystem VID and DID for correct
175 subid = pcicfgr16(p, PciSVID);
176 subid |= pcicfgr16(p, PciSID)<<16;
180 print("uartpci: unknown perle subid %#ux\n", subid);
182 case (0x1588<<16)|0x10B5: /* StarTech PCI8S9503V (P588UG) */
184 /* max. baud rate is 921,600 */
186 uart = uartpci(ctlrno, p, 2, 8, freq, name, 8);
188 case (0x0011<<16)|0x12E0: /* Perle PCI-Fast16 */
190 uart = uartpci(ctlrno, p, 2, 16, freq, name, 8);
192 case (0x0021<<16)|0x12E0: /* Perle PCI-Fast8 */
194 uart = uartpci(ctlrno, p, 2, 8, freq, name, 8);
196 case (0x0031<<16)|0x12E0: /* Perle PCI-Fast4 */
198 uart = uartpci(ctlrno, p, 2, 4, freq, name, 8);
200 case (0x0021<<16)|0x155F: /* Perle Ultraport8 */
201 name = "Ultraport8"; /* 16C754 UARTs */
202 uart = uartpci(ctlrno, p, 2, 8, freq, name, 8);
204 case (0x0041<<16)|0x155F: /* Perle Ultraport16 */
205 name = "Ultraport16";
206 uart = uartpci(ctlrno, p, 2, 16, 2 * freq,
209 case (0x0241<<16)|0x155F: /* Perle Ultraport16 */
210 uart = ultraport16si(ctlrno, p, 4 * freq);
222 PhysUart pciphysuart = {