sys/src/9/pc/uartpci.c

   1 #include "u.h"
   2 #include "../port/lib.h"
   3 #include "mem.h"
   4 #include "dat.h"
   5 #include "fns.h"
   6 #include "io.h"
   7 #include "../port/error.h"
   8
   9 extern PhysUart i8250physuart;
  10 extern PhysUart pciphysuart;
  11 extern void* i8250alloc(int, int, int);
  12
  13 static Uart *perlehead, *perletail;
  14
  15 static Uart*
  16 uartpci(int ctlrno, Pcidev* p, int barno, int n, int freq, char* name,
  17         int iosize)
  18 {
  19         int i, io;
  20         void *ctlr;
  21         char buf[64];
  22         Uart *head, *uart;
  23
  24         head = malloc(sizeof(Uart)*n);
  25         if(head == nil){
  26                 print("uartpci: no memory for Uarts\n");
  27                 return nil;
  28         }
  29
  30         io = p->mem[barno].bar & ~0x01;
  31         snprint(buf, sizeof(buf), "%s%d", pciphysuart.name, ctlrno);
  32         if(ioalloc(io, p->mem[barno].size, 0, buf) < 0){
  33                 print("uartpci: I/O 0x%uX in use\n", io);
  34                 free(head);
  35                 return nil;
  36         }
  37
  38         uart = head;
  39         for(i = 0; i < n; i++){
  40                 ctlr = i8250alloc(io + i*iosize, p->intl, p->tbdf);
  41                 if(ctlr == nil)
  42                         continue;
  43
  44                 uart->regs = ctlr;
  45                 snprint(buf, sizeof(buf), "%s.%8.8uX", name, p->tbdf);
  46                 kstrdup(&uart->name, buf);
  47                 uart->freq = freq;
  48                 uart->phys = &i8250physuart;
  49                 if(uart != head)
  50                         (uart-1)->next = uart;
  51                 uart++;
  52         }
  53         if(head == uart){
  54                 iofree(io);
  55                 free(head);
  56                 return nil;
  57         }
  58
  59         if(perlehead != nil)
  60                 perletail->next = head;
  61         else
  62                 perlehead = head;
  63         for(perletail = head; perletail->next != nil;
  64             perletail = perletail->next)
  65                 ;
  66
  67         return head;
  68 }
  69
  70 static Uart *
  71 ultraport16si(int ctlrno, Pcidev *p, ulong freq)
  72 {
  73         int io, i;
  74         char *name;
  75         Uart *uart;
  76
  77         name = "Ultraport16si";         /* 16L788 UARTs */
  78         io = p->mem[4].bar & ~1;
  79         if (ioalloc(io, p->mem[4].size, 0, name) < 0) {
  80                 print("uartpci: can't get IO space to set %s to rs-232\n", name);
  81                 return nil;
  82         }
  83         for (i = 0; i < 16; i++) {
  84                 outb(io, i << 4);
  85                 outb(io, (i << 4) + 1); /* set to RS232 mode  (Don't ask!) */
  86         }
  87
  88         uart = uartpci(ctlrno, p, 2, 8, freq, name, 16);
  89         if(uart)
  90                 uart = uartpci(ctlrno, p, 3, 8, freq, name, 16);
  91         return uart;
  92 }
  93
  94 static Uart*
  95 uartpcipnp(void)
  96 {
  97         Pcidev *p;
  98         char *name;
  99         int ctlrno, subid;
 100         ulong freq;
 101         Uart *uart;
 102
 103         /*
 104          * Loop through all PCI devices looking for simple serial
 105          * controllers (ccrb == Pcibccomm (7)) and configure the ones which
 106          * are familiar. All suitable devices are configured to
 107          * simply point to the generic i8250 driver.
 108          */
 109         perlehead = perletail = nil;
 110         ctlrno = 0;
 111         for(p = pcimatch(nil, 0, 0); p != nil; p = pcimatch(p, 0, 0)){
 112                 /* StarTech PCI8S9503V has ccru == 0x80 (other) */
 113                 if(p->ccrb != Pcibccomm || p->ccru > 2 && p->ccru != 0x80)
 114                         continue;
 115
 116                 switch(p->did<<16 | p->vid){
 117                 default:
 118                         continue;
 119                 case (0x9835<<16)|0x9710:       /* StarTech PCI2S550 */
 120                         uart = uartpci(ctlrno, p, 0, 1, 1843200, "PCI2S550-0", 8);
 121                         if(uart == nil)
 122                                 continue;
 123                         uart->next = uartpci(ctlrno, p, 1, 1, 1843200,
 124                                 "PCI2S550-1", 8);
 125                         if(uart->next == nil)
 126                                 continue;
 127                         break;
 128                 case (0x950A<<16)|0x1415:       /* Oxford Semi OX16PCI954 */
 129                 case (0x9501<<16)|0x1415:
 130                 case (0x9521<<16)|0x1415:
 131                         /*
 132                          * These are common devices used by 3rd-party
 133                          * manufacturers.
 134                          * Must check the subsystem VID and DID for correct
 135                          * match.
 136                          */
 137                         subid = pcicfgr16(p, PciSVID);
 138                         subid |= pcicfgr16(p, PciSID)<<16;
 139                         switch(subid){
 140                         default:
 141                                 print("oxsemi uart %.8#ux of vid %#ux did %#ux unknown\n",
 142                                         subid, p->vid, p->did);
 143                                 continue;
 144                         case (0<<16)|0x1415:
 145                                 uart = uartpci(ctlrno, p, 0, 4, 1843200,
 146                                         "starport-pex4s", 8);
 147                                 break;
 148                         case (1<<16)|0x1415:
 149                                 uart = uartpci(ctlrno, p, 0, 2, 14745600,
 150                                         "starport-pex2s", 8);
 151                                 break;
 152                         case (0x2000<<16)|0x131F:/* SIIG CyberSerial PCIe */
 153                                 uart = uartpci(ctlrno, p, 0, 1, 18432000,
 154                                         "CyberSerial-1S", 8);
 155                                 break;
 156                         }
 157                         break;
 158                 case (0x9505<<16)|0x1415:       /* Oxford Semi OXuPCI952 */
 159                         name = "SATAGear-IOI-102";  /* PciSVID=1415, PciSID=0 */
 160                         if (uartpci(ctlrno, p, 0, 1, 14745600, name, 8) != nil)
 161                                 ctlrno++;
 162                         if (uartpci(ctlrno, p, 1, 1, 14745600, name, 8) != nil)
 163                                 ctlrno++;
 164                         uart = nil;             /* don't ctlrno++ below */
 165                         break;
 166                 case (0x9050<<16)|0x10B5:       /* Perle PCI-Fast4 series */
 167                 case (0x9030<<16)|0x10B5:       /* Perle Ultraport series */
 168                         /*
 169                          * These devices consists of a PLX bridge (the above
 170                          * PCI VID+DID) behind which are some 16C654 UARTs.
 171                          * Must check the subsystem VID and DID for correct
 172                          * match.
 173                          */
 174                         subid = pcicfgr16(p, PciSVID);
 175                         subid |= pcicfgr16(p, PciSID)<<16;
 176                         freq = 7372800;
 177                         switch(subid){
 178                         default:
 179                                 print("uartpci: unknown perle subid %#ux\n", subid);
 180                                 continue;
 181                         case (0x1588<<16)|0x10B5:       /* StarTech PCI8S9503V (P588UG) */
 182                                 name = "P588UG";
 183                                 /* max. baud rate is 921,600 */
 184                                 freq = 1843200;
 185                                 uart = uartpci(ctlrno, p, 2, 8, freq, name, 8);
 186                                 break;
 187                         case (0x0011<<16)|0x12E0:       /* Perle PCI-Fast16 */
 188                                 name = "PCI-Fast16";
 189                                 uart = uartpci(ctlrno, p, 2, 16, freq, name, 8);
 190                                 break;
 191                         case (0x0021<<16)|0x12E0:       /* Perle PCI-Fast8 */
 192                                 name = "PCI-Fast8";
 193                                 uart = uartpci(ctlrno, p, 2, 8, freq, name, 8);
 194                                 break;
 195                         case (0x0031<<16)|0x12E0:       /* Perle PCI-Fast4 */
 196                                 name = "PCI-Fast4";
 197                                 uart = uartpci(ctlrno, p, 2, 4, freq, name, 8);
 198                                 break;
 199                         case (0x0021<<16)|0x155F:       /* Perle Ultraport8 */
 200                                 name = "Ultraport8";    /* 16C754 UARTs */
 201                                 uart = uartpci(ctlrno, p, 2, 8, freq, name, 8);
 202                                 break;
 203                         case (0x0041<<16)|0x155F:       /* Perle Ultraport16 */
 204                                 name = "Ultraport16";
 205                                 uart = uartpci(ctlrno, p, 2, 16, 2 * freq,
 206                                         name, 8);
 207                                 break;
 208                         case (0x0241<<16)|0x155F:       /* Perle Ultraport16 */
 209                                 uart = ultraport16si(ctlrno, p, 4 * freq);
 210                                 break;
 211                         }
 212                         break;
 213                 }
 214                 if(uart)
 215                         ctlrno++;
 216         }
 217
 218         return perlehead;
 219 }
 220
 221 PhysUart pciphysuart = {
 222         .name           = "UartPCI",
 223         .pnp            = uartpcipnp,
 224         .enable         = nil,
 225         .disable        = nil,
 226         .kick           = nil,
 227         .dobreak        = nil,
 228         .baud           = nil,
 229         .bits           = nil,
 230         .stop           = nil,
 231         .parity         = nil,
 232         .modemctl       = nil,
 233         .rts            = nil,
 234         .dtr            = nil,
 235         .status         = nil,
 236         .fifo           = nil,
 237 };