2 #include "../port/lib.h"
7 #include "../port/error.h"
10 * 8250 UART and compatibles.
13 Uart0 = 0x3F8, /* COM1 */
15 Uart1 = 0x2F8, /* COM2 */
21 enum { /* I/O ports */
22 Rbr = 0, /* Receiver Buffer (RO) */
23 Thr = 0, /* Transmitter Holding (WO) */
24 Ier = 1, /* Interrupt Enable */
25 Iir = 2, /* Interrupt Identification (RO) */
26 Fcr = 2, /* FIFO Control (WO) */
27 Lcr = 3, /* Line Control */
28 Mcr = 4, /* Modem Control */
29 Lsr = 5, /* Line Status */
30 Msr = 6, /* Modem Status */
31 Scr = 7, /* Scratch Pad */
32 Dll = 0, /* Divisor Latch LSB */
33 Dlm = 1, /* Divisor Latch MSB */
37 Erda = 0x01, /* Enable Received Data Available */
38 Ethre = 0x02, /* Enable Thr Empty */
39 Erls = 0x04, /* Enable Receiver Line Status */
40 Ems = 0x08, /* Enable Modem Status */
44 Ims = 0x00, /* Ms interrupt */
45 Ip = 0x01, /* Interrupt Pending (not) */
46 Ithre = 0x02, /* Thr Empty */
47 Irda = 0x04, /* Received Data Available */
48 Irls = 0x06, /* Receiver Line Status */
49 Ictoi = 0x0C, /* Character Time-out Indication */
51 Ifena = 0xC0, /* FIFOs enabled */
55 FIFOena = 0x01, /* FIFO enable */
56 FIFOrclr = 0x02, /* clear Rx FIFO */
57 FIFOtclr = 0x04, /* clear Tx FIFO */
58 FIFO1 = 0x00, /* Rx FIFO trigger level 1 byte */
59 FIFO4 = 0x40, /* 4 bytes */
60 FIFO8 = 0x80, /* 8 bytes */
61 FIFO14 = 0xC0, /* 14 bytes */
65 Wls5 = 0x00, /* Word Length Select 5 bits/byte */
66 Wls6 = 0x01, /* 6 bits/byte */
67 Wls7 = 0x02, /* 7 bits/byte */
68 Wls8 = 0x03, /* 8 bits/byte */
70 Stb = 0x04, /* 2 stop bits */
71 Pen = 0x08, /* Parity Enable */
72 Eps = 0x10, /* Even Parity Select */
73 Stp = 0x20, /* Stick Parity */
74 Brk = 0x40, /* Break */
75 Dlab = 0x80, /* Divisor Latch Access Bit */
79 Dtr = 0x01, /* Data Terminal Ready */
80 Rts = 0x02, /* Ready To Send */
81 Out1 = 0x04, /* no longer in use */
82 Ie = 0x08, /* IRQ Enable */
83 Dm = 0x10, /* Diagnostic Mode loopback */
87 Dr = 0x01, /* Data Ready */
88 Oe = 0x02, /* Overrun Error */
89 Pe = 0x04, /* Parity Error */
90 Fe = 0x08, /* Framing Error */
91 Bi = 0x10, /* Break Interrupt */
92 Thre = 0x20, /* Thr Empty */
93 Temt = 0x40, /* Tramsmitter Empty */
94 FIFOerr = 0x80, /* error in receiver FIFO */
98 Dcts = 0x01, /* Delta Cts */
99 Ddsr = 0x02, /* Delta Dsr */
100 Teri = 0x04, /* Trailing Edge of Ri */
101 Ddcd = 0x08, /* Delta Dcd */
102 Cts = 0x10, /* Clear To Send */
103 Dsr = 0x20, /* Data Set Ready */
104 Ri = 0x40, /* Ring Indicator */
105 Dcd = 0x80, /* Data Set Ready */
108 typedef struct Ctlr {
122 extern PhysUart i8250physuart;
124 static Ctlr i8250ctlr[2] = {
127 .tbdf = BUSUNKNOWN, },
131 .tbdf = BUSUNKNOWN, },
134 static Uart i8250uart[2] = {
135 { .regs = &i8250ctlr[0],
138 .phys = &i8250physuart,
140 .next = &i8250uart[1], },
142 { .regs = &i8250ctlr[1],
145 .phys = &i8250physuart,
150 #define csr8r(c, r) inb((c)->io+(r))
151 #define csr8w(c, r, v) outb((c)->io+(r), (c)->sticky[(r)]|(v))
154 i8250status(Uart* uart, void* buf, long n, long offset)
158 uchar ier, lcr, mcr, msr;
161 p = smalloc(READSTR);
162 mcr = ctlr->sticky[Mcr];
163 msr = csr8r(ctlr, Msr);
164 ier = ctlr->sticky[Ier];
165 lcr = ctlr->sticky[Lcr];
167 "b%d c%d d%d e%d l%d m%d p%c r%d s%d i%d\n"
168 "dev(%d) type(%d) framing(%d) overruns(%d) "
169 "berr(%d) serr(%d)%s%s%s%s\n",
177 (lcr & Pen) ? ((lcr & Eps) ? 'e': 'o'): 'n',
188 (msr & Cts) ? " cts": "",
189 (msr & Dsr) ? " dsr": "",
190 (msr & Dcd) ? " dcd": "",
191 (msr & Ri) ? " ring": ""
193 n = readstr(offset, buf, n, p);
200 i8250fifo(Uart* uart, int level)
205 if(ctlr->hasfifo == 0)
209 * Changing the FIFOena bit in Fcr flushes data
210 * from both receive and transmit FIFOs; there's
211 * no easy way to guarantee not losing data on
212 * the receive side, but it's possible to wait until
213 * the transmitter is really empty.
216 while(!(csr8r(ctlr, Lsr) & Temt))
220 * Set the trigger level, default is the max.
222 * Some UARTs require FIFOena to be set before
223 * other bits can take effect, so set it twice.
230 level = FIFO1|FIFOena;
233 level = FIFO4|FIFOena;
236 level = FIFO8|FIFOena;
239 level = FIFO14|FIFOena;
242 csr8w(ctlr, Fcr, level);
243 csr8w(ctlr, Fcr, level);
248 i8250dtr(Uart* uart, int on)
257 ctlr->sticky[Mcr] |= Dtr;
259 ctlr->sticky[Mcr] &= ~Dtr;
264 i8250rts(Uart* uart, int on)
273 ctlr->sticky[Mcr] |= Rts;
275 ctlr->sticky[Mcr] &= ~Rts;
280 i8250modemctl(Uart* uart, int on)
287 ctlr->sticky[Ier] |= Ems;
288 csr8w(ctlr, Ier, ctlr->sticky[Ier]);
290 uart->cts = csr8r(ctlr, Msr) & Cts;
293 ctlr->sticky[Ier] &= ~Ems;
294 csr8w(ctlr, Ier, ctlr->sticky[Ier]);
298 iunlock(&uart->tlock);
300 /* modem needs fifo */
301 (*uart->phys->fifo)(uart, on);
305 i8250parity(Uart* uart, int parity)
311 lcr = ctlr->sticky[Lcr] & ~(Eps|Pen);
325 ctlr->sticky[Lcr] = lcr;
328 uart->parity = parity;
334 i8250stop(Uart* uart, int stop)
340 lcr = ctlr->sticky[Lcr] & ~Stb;
351 ctlr->sticky[Lcr] = lcr;
360 i8250bits(Uart* uart, int bits)
366 lcr = ctlr->sticky[Lcr] & ~WlsMASK;
384 ctlr->sticky[Lcr] = lcr;
393 i8250baud(Uart* uart, int baud)
399 * Set the Baud rate by calculating and setting the Baud rate
400 * Generator Constant. This will work with fairly non-standard
403 if(uart->freq == 0 || baud <= 0)
405 bgc = (uart->freq+8*baud-1)/(16*baud);
408 csr8w(ctlr, Lcr, Dlab);
409 outb(ctlr->io+Dlm, bgc>>8);
410 outb(ctlr->io+Dll, bgc);
419 i8250break(Uart* uart, int ms)
430 csr8w(ctlr, Lcr, Brk);
431 tsleep(&up->sleep, return0, 0, ms);
436 i8250kick(Uart* uart)
441 if(uart->cts == 0 || uart->blocked)
445 * 128 here is an arbitrary limit to make sure
446 * we don't stay in this loop too long. If the
447 * chip's output queue is longer than 128, too
451 for(i = 0; i < 128; i++){
452 if(!(csr8r(ctlr, Lsr) & Thre))
454 if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
456 outb(ctlr->io+Thr, *(uart->op++));
461 i8250interrupt(Ureg*, void* arg)
465 int iir, lsr, old, r;
470 for(iir = csr8r(ctlr, Iir); !(iir & Ip); iir = csr8r(ctlr, Iir)){
471 switch(iir & IirMASK){
472 case Ims: /* Ms interrupt */
473 r = csr8r(ctlr, Msr);
478 if(old == 0 && uart->cts)
479 uart->ctsbackoff = 2;
480 iunlock(&uart->tlock);
484 if(uart->hup_dsr && uart->dsr && !old)
490 if(uart->hup_dcd && uart->dcd && !old)
495 case Ithre: /* Thr Empty */
498 case Irda: /* Received Data Available */
499 case Irls: /* Receiver Line Status */
500 case Ictoi: /* Character Time-out Indication */
502 * Consume any received data.
503 * If the received byte came in with a break,
504 * parity or framing error, throw it away;
505 * overrun is an indication that something has
506 * already been tossed.
508 while((lsr = csr8r(ctlr, Lsr)) & Dr){
509 if(lsr & (FIFOerr|Oe))
515 r = csr8r(ctlr, Rbr);
516 if(!(lsr & (Bi|Fe|Pe)))
522 iprint("weird uart interrupt 0x%2.2uX\n", iir);
529 i8250disable(Uart* uart)
534 * Turn off DTR and RTS, disable interrupts and fifos.
536 (*uart->phys->dtr)(uart, 0);
537 (*uart->phys->rts)(uart, 0);
538 (*uart->phys->fifo)(uart, 0);
541 ctlr->sticky[Ier] = 0;
542 csr8w(ctlr, Ier, ctlr->sticky[Ier]);
546 intrdisable(ctlr->irq, i8250interrupt, uart, ctlr->tbdf, uart->name);
551 i8250enable(Uart* uart, int ie)
558 * Check if there is a FIFO.
559 * Changing the FIFOena bit in Fcr flushes data
560 * from both receive and transmit FIFOs; there's
561 * no easy way to guarantee not losing data on
562 * the receive side, but it's possible to wait until
563 * the transmitter is really empty.
564 * Also, reading the Iir outwith i8250interrupt()
565 * can be dangerous, but this should only happen
566 * once before interrupts are enabled.
569 if(!ctlr->checkfifo){
571 * Wait until the transmitter is really empty.
573 while(!(csr8r(ctlr, Lsr) & Temt))
575 csr8w(ctlr, Fcr, FIFOena);
576 if(csr8r(ctlr, Iir) & Ifena)
584 * Enable interrupts and turn on DTR and RTS.
585 * Be careful if this is called to set up a polled serial line
586 * early on not to try to enable interrupts as interrupt-
587 * -enabling mechanisms might not be set up yet.
591 intrenable(ctlr->irq, i8250interrupt, uart, ctlr->tbdf, uart->name);
594 ctlr->sticky[Ier] = Ethre|Erda;
595 ctlr->sticky[Mcr] |= Ie;
598 ctlr->sticky[Ier] = 0;
599 ctlr->sticky[Mcr] = 0;
601 csr8w(ctlr, Ier, ctlr->sticky[Ier]);
602 csr8w(ctlr, Mcr, ctlr->sticky[Mcr]);
604 (*uart->phys->dtr)(uart, 1);
605 (*uart->phys->rts)(uart, 1);
608 * During startup, the i8259 interrupt controller is reset.
609 * This may result in a lost interrupt from the i8250 uart.
610 * The i8250 thinks the interrupt is still outstanding and does not
611 * generate any further interrupts. The workaround is to call the
612 * interrupt handler to clear any pending interrupt events.
613 * Note: this must be done after setting Ier.
616 i8250interrupt(nil, uart);
620 i8250alloc(int io, int irq, int tbdf)
624 ctlr = malloc(sizeof(Ctlr));
626 print("i8250alloc: no memory for Ctlr\n");
642 i8250getc(Uart *uart)
647 while(!(csr8r(ctlr, Lsr)&Dr))
649 return csr8r(ctlr, Rbr);
653 i8250putc(Uart *uart, int c)
659 for(i = 0; !(csr8r(ctlr, Lsr)&Thre) && i < 128; i++)
661 outb(ctlr->io+Thr, c);
662 for(i = 0; !(csr8r(ctlr, Lsr)&Thre) && i < 128; i++)
666 PhysUart i8250physuart = {
669 .enable = i8250enable,
670 .disable = i8250disable,
672 .dobreak = i8250break,
676 .parity = i8250parity,
677 .modemctl = i8250modemctl,
680 .status = i8250status,
693 if((p = getconf("console")) == nil)
695 n = strtoul(p, &cmd, 0);
696 if(p == cmd || n < 0 || n >= nelem(i8250uart))
698 uart = &i8250uart[n];
700 (*uart->phys->enable)(uart, 0);
701 uartctl(uart, "b9600 l8 pn s1");