2 * Mylex MultiMaster (Buslogic BT-*) SCSI Host Adapter
3 * in both 24-bit and 32-bit mode.
4 * 24-bit mode works for Adaptec AHA-154xx series too.
7 * allocate more Ccb's as needed, up to NMbox-1;
8 * add nmbox and nccb to Ctlr struct for the above;
9 * 64-bit LUN/explicit wide support necessary?
13 #include "../port/lib.h"
19 #include "../port/error.h"
21 #include "../port/sd.h"
23 #define K2BPA(va, tbdf) PADDR(va)
24 #define BPA2K(pa, tbdf) KADDR(pa)
26 extern SDifc sdmylexifc;
28 enum { /* registers */
29 Rcontrol = 0x00, /* WO: control register */
30 Rstatus = 0x00, /* RO: status register */
31 Rcpr = 0x01, /* WO: command/parameter register */
32 Rdatain = 0x01, /* RO: data-in register */
33 Rinterrupt = 0x02, /* RO: interrupt register */
37 Rsbus = 0x10, /* SCSI Bus Reset */
38 Rint = 0x20, /* Interrupt Reset */
39 Rsoft = 0x40, /* Soft Reset */
40 Rhard = 0x80, /* Hard Reset */
44 Cmdinv = 0x01, /* Command Invalid */
45 Dirrdy = 0x04, /* Data In Register Ready */
46 Cprbsy = 0x08, /* Command/Parameter Register Busy */
47 Hardy = 0x10, /* Host Adapter Ready */
48 Inreq = 0x20, /* Initialisation Required */
49 Dfail = 0x40, /* Diagnostic Failure */
50 Dact = 0x80, /* Diagnostic Active */
54 Cinitialise = 0x01, /* Initialise Mailbox */
55 Cstart = 0x02, /* Start Mailbox Command */
56 Cinquiry = 0x04, /* Adapter Inquiry */
57 Ceombri = 0x05, /* Enable OMBR Interrupt */
58 Cinquire = 0x0B, /* Inquire Configuration */
59 Cextbios = 0x28, /* AHA-1542: extended BIOS info. */
60 Cmbienable = 0x29, /* AHA-1542: Mailbox interface enable */
61 Ciem = 0x81, /* Initialise Extended Mailbox */
62 Ciesi = 0x8D, /* Inquire Extended Setup Information */
63 Cerrm = 0x8F, /* Enable strict round-robin mode */
64 Cwide = 0x96, /* Wide CCB */
67 enum { /* Rinterrupt */
68 Imbl = 0x01, /* Incoming Mailbox Loaded */
69 Mbor = 0x02, /* Mailbox Out Ready */
70 Cmdc = 0x04, /* Command Complete */
71 Rsts = 0x08, /* SCSI Reset State */
72 Intv = 0x80, /* Interrupt Valid */
75 typedef struct Mbox24 Mbox24;
77 uchar code; /* action/completion code */
78 uchar ccb[3]; /* CCB pointer (MSB, ..., LSB) */
81 typedef struct Mbox32 Mbox32;
83 uchar ccb[4]; /* CCB pointer (LSB, ..., MSB) */
84 uchar btstat; /* BT-7[45]7[SD] status */
85 uchar sdstat; /* SCSI device status */
87 uchar code; /* action/completion code */
90 enum { /* mailbox commands */
91 Mbfree = 0x00, /* Mailbox not in use */
93 Mbostart = 0x01, /* Start a mailbox command */
94 Mboabort = 0x02, /* Abort a mailbox command */
96 Mbiok = 0x01, /* CCB completed without error */
97 Mbiabort = 0x02, /* CCB aborted at request of host */
98 Mbinx = 0x03, /* Aborted CCB not found */
99 Mbierror = 0x04, /* CCB completed with error */
102 typedef struct Ccb24 Ccb24;
103 typedef struct Ccb32 Ccb32;
104 typedef union Ccb Ccb;
106 typedef struct Ccb24 {
107 uchar opcode; /* Operation code */
108 uchar datadir; /* Data direction control */
109 uchar cdblen; /* Length of CDB */
110 uchar senselen; /* Length of sense area */
111 uchar datalen[3]; /* Data length (MSB, ..., LSB) */
112 uchar dataptr[3]; /* Data pointer (MSB, ..., LSB) */
113 uchar linkptr[3]; /* Link pointer (MSB, ..., LSB) */
114 uchar linkid; /* command linking identifier */
115 uchar btstat; /* BT-* adapter status */
116 uchar sdstat; /* SCSI device status */
117 uchar reserved[2]; /* */
118 uchar cs[12+0xFF]; /* Command descriptor block + Sense */
120 void* data; /* buffer if address > 24-bits */
123 int done; /* command completed */
125 Ccb* ccb; /* link on free list */
129 typedef struct Ccb32 {
130 uchar opcode; /* Operation code */
131 uchar datadir; /* Data direction control */
132 uchar cdblen; /* Length of CDB */
133 uchar senselen; /* Length of sense area */
134 uchar datalen[4]; /* Data length (LSB, ..., MSB) */
135 uchar dataptr[4]; /* Data pointer (LSB, ..., MSB) */
137 uchar btstat; /* BT-* adapter status */
138 uchar sdstat; /* SCSI device status */
139 uchar targetid; /* Target ID */
140 uchar luntag; /* LUN & tag */
141 uchar cdb[12]; /* Command descriptor block */
142 uchar ccbctl; /* CCB control */
143 uchar linkid; /* command linking identifier */
144 uchar linkptr[4]; /* Link pointer (LSB, ..., MSB) */
145 uchar senseptr[4]; /* Sense pointer (LSB, ..., MSB) */
146 uchar sense[0xFF]; /* Sense bytes */
149 int done; /* command completed */
151 Ccb* ccb; /* link on free list */
160 OInitiator = 0x00, /* initiator CCB */
161 Ordl = 0x03, /* initiator CCB with
162 * residual data length returned
167 CCBdatain = 0x08, /* inbound, length is checked */
168 CCBdataout = 0x10, /* outbound, length is checked */
172 Eok = 0x00, /* normal completion with no errors */
176 TagEnable = 0x20, /* Tag enable */
177 SQTag = 0x00, /* Simple Queue Tag */
178 HQTag = 0x40, /* Head of Queue Tag */
179 OQTag = 0x80, /* Ordered Queue Tag */
182 enum { /* CCB control */
183 NoDisc = 0x08, /* No disconnect */
184 NoUnd = 0x10, /* No underrrun error report */
185 NoData = 0x20, /* No data transfer */
186 NoStat = 0x40, /* No CCB status if zero */
187 NoIntr = 0x80, /* No Interrupts */
190 typedef struct Ctlr Ctlr;
192 int port; /* I/O port */
193 int id; /* adapter SCSI id */
194 int bus; /* 24 or 32 -bit */
208 void* mb; /* mailbox out + mailbox in */
209 int mbox; /* current mailbox out index into mb */
210 int mbix; /* current mailbox in index into mb */
213 Ccb* ccb; /* list of free Ccb's */
214 Ccb** cache; /* last completed Ccb */
218 * The number of mailboxes should be a multiple of 8 (4 for Mbox32)
219 * to ensure the boundary between the out and in mailboxes doesn't
220 * straddle a cache-line boundary.
221 * The number of Ccb's should be less than the number of mailboxes to
222 * ensure no queueing is necessary on mailbox allocation.
225 NMbox = 8*8, /* number of Mbox's */
226 NCcb = NMbox-1, /* number of Ccb's */
229 #define PADDR24(a, n) ((PADDR(a)+(n)) <= (1<<24))
232 ccbfree(Ctlr* ctlr, Ccb* ccb)
234 lock(&ctlr->ccblock);
236 ((Ccb24*)ccb)->ccb = ctlr->ccb;
238 ((Ccb32*)ccb)->ccb = ctlr->ccb;
242 unlock(&ctlr->ccblock);
246 ccbavailable(void* a)
248 return ((Ctlr*)a)->ccb != nil;
257 lock(&ctlr->ccblock);
258 if((ccb = ctlr->ccb) != nil){
260 ctlr->ccb = ((Ccb24*)ccb)->ccb;
262 ctlr->ccb = ((Ccb32*)ccb)->ccb;
263 unlock(&ctlr->ccblock);
267 unlock(&ctlr->ccblock);
270 qunlock(&ctlr->ccbq);
273 sleep(&ctlr->ccbr, ccbavailable, ctlr);
274 qunlock(&ctlr->ccbq);
284 return ((Ccb24*)arg)->done;
294 uchar *data, lun, *sense;
295 int d, n, btstat, sdstat, target;
297 ctlr = r->unit->dev->ctlr;
298 target = r->unit->subno;
299 lun = (r->cmd[1]>>5) & 0x07;
302 * Ctlr->cache holds the last completed Ccb for this target if it
303 * returned 'check condition'.
304 * If this command is a request-sense and there is valid sense data
305 * from the last completed Ccb, return it immediately.
307 lock(&ctlr->cachelock);
308 if((ccb = ctlr->cache[target]) != nil){
309 ctlr->cache[target] = nil;
311 && ccb->sdstat == SDcheck && lun == ((ccb->cs[1]>>5) & 0x07)){
312 unlock(&ctlr->cachelock);
314 sense = &ccb->cs[ccb->cdblen];
318 memmove(r->data, sense, n);
321 ccbfree(ctlr, (Ccb*)ccb);
325 unlock(&ctlr->cachelock);
327 ccb = ccballoc(ctlr);
330 * Check if the transfer is to memory above the 24-bit limit the
331 * controller can address. If it is, try to allocate a temporary
332 * buffer as a staging area.
335 if(n && !PADDR24(r->data, n)){
336 data = mallocz(n, 0);
337 if(data == nil || !PADDR24(data, n)){
342 ccbfree(ctlr, (Ccb*)ccb);
346 memmove(data, r->data, n);
357 ccb->datadir = (target<<5)|lun;
359 ccb->datadir |= CCBdataout|CCBdatain;
361 ccb->datadir |= CCBdatain;
363 ccb->datadir |= CCBdataout;
365 ccb->cdblen = r->clen;
366 ccb->senselen = 0xFF;
368 ccb->datalen[0] = n>>16;
369 ccb->datalen[1] = n>>8;
375 ccb->dataptr[0] = p>>16;
376 ccb->dataptr[1] = p>>8;
379 ccb->linkptr[0] = ccb->linkptr[1] = ccb->linkptr[2] = 0;
381 ccb->btstat = ccb->sdstat = 0;
382 ccb->reserved[0] = ccb->reserved[1] = 0;
384 memmove(ccb->cs, r->cmd, r->clen);
387 * There's one more mbox than there there is
388 * ccb so there is always one free.
390 lock(&ctlr->mboxlock);
399 if(ctlr->mbox >= NMbox)
403 * This command does not require Hardy
404 * and doesn't generate a Cmdc interrupt.
407 outb(ctlr->port+Rcpr, Cstart);
408 unlock(&ctlr->mboxlock);
411 * Wait for the request to complete and return the status.
412 * Since the buffer is not reference counted cannot return
413 * until the DMA is done writing into the buffer so the caller
414 * cannot free the buffer prematurely.
418 sleep(ccb, done24, ccb);
422 * Save the status and patch up the number of
423 * bytes actually transferred.
424 * There's a firmware bug on some 956C controllers
425 * which causes the return count from a successful
426 * READ CAPACITY not be updated, so fix it here.
428 sdstat = ccb->sdstat;
429 btstat = ccb->btstat;
431 d = ccb->datalen[0]<<16;
432 d |= ccb->datalen[1]<<8;
433 d |= ccb->datalen[2];
434 if(ccb->cs[0] == 0x25 && sdstat == SDok)
440 * Tidy things up if a staging area was used for the data,
442 if(ccb->data != nil){
443 if(sdstat == SDok && btstat == 0 && !r->write)
444 memmove(ccb->data, data, n);
450 * If there was a check-condition, save the
451 * ccb for a possible request-sense command.
453 if(sdstat == SDcheck){
454 if(r->flags & SDnosense){
455 lock(&ctlr->cachelock);
456 if(ctlr->cache[target])
457 ccbfree(ctlr, ctlr->cache[target]);
458 ctlr->cache[target] = (Ccb*)ccb;
459 unlock(&ctlr->cachelock);
462 sense = &ccb->cs[ccb->cdblen];
464 if(n > sizeof(r->sense)-1)
465 n = sizeof(r->sense)-1;
466 memmove(r->sense, sense, n);
467 r->flags |= SDvalidsense;
469 ccbfree(ctlr, (Ccb*)ccb);
480 mylex24interrupt(Ureg*, void* arg)
486 int port, rinterrupt, rstatus;
492 * Save and clear the interrupt(s). The only
493 * interrupts expected are Cmdc, which is ignored,
494 * and Imbl which means something completed.
495 * There's one spurious interrupt left over from
496 * initialisation, ignore it.
498 rinterrupt = inb(port+Rinterrupt);
499 rstatus = inb(port+Rstatus);
500 outb(port+Rcontrol, Rint);
501 if((rinterrupt & ~(Cmdc|Imbl)) != Intv && ctlr->spurious++)
502 print("%s: interrupt 0x%2.2ux\n",
503 ctlr->sdev->name, rinterrupt);
504 if((rinterrupt & Cmdc) && (rstatus & Cmdinv))
505 print("%s: command invalid\n", ctlr->sdev->name);
508 * Look for something in the mail.
509 * If there is, save the status, free the mailbox
510 * and wakeup whoever.
513 for(mbox = &mb[ctlr->mbix]; mbox->code; mbox = &mb[ctlr->mbix]){
514 pa = (mbox->ccb[0]<<16)|(mbox->ccb[1]<<8)|mbox->ccb[2];
515 ccb = BPA2K(pa, BUSUNKNOWN);
521 if(ctlr->mbix >= NMbox+NMbox)
529 return ((Ccb32*)arg)->done;
540 int d, n, btstat, sdstat, target;
542 ctlr = r->unit->dev->ctlr;
543 target = r->unit->subno;
544 lun = (r->cmd[1]>>5) & 0x07;
547 * Ctlr->cache holds the last completed Ccb for this target if it
548 * returned 'check condition'.
549 * If this command is a request-sense and there is valid sense data
550 * from the last completed Ccb, return it immediately.
552 lock(&ctlr->cachelock);
553 if((ccb = ctlr->cache[target]) != nil){
554 ctlr->cache[target] = nil;
556 && ccb->sdstat == SDcheck && lun == (ccb->luntag & 0x07)){
557 unlock(&ctlr->cachelock);
562 memmove(r->data, ccb->sense, n);
565 ccbfree(ctlr, (Ccb*)ccb);
569 unlock(&ctlr->cachelock);
571 ccb = ccballoc(ctlr);
580 ccb->datadir = CCBdataout|CCBdatain;
582 ccb->datadir = CCBdatain;
584 ccb->datadir = CCBdataout;
586 ccb->cdblen = r->clen;
589 ccb->datalen[1] = n>>8;
590 ccb->datalen[2] = n>>16;
591 ccb->datalen[3] = n>>24;
597 ccb->dataptr[1] = p>>8;
598 ccb->dataptr[2] = p>>16;
599 ccb->dataptr[3] = p>>24;
601 ccb->targetid = target;
603 if(r->unit->inquiry[7] & 0x02)
605 ccb->datadir |= SQTag|TagEnable;
607 ccb->luntag |= SQTag|TagEnable;
608 memmove(ccb->cdb, r->cmd, r->clen);
609 ccb->btstat = ccb->sdstat = 0;
613 * There's one more mbox than there there is
614 * ccb so there is always one free.
616 lock(&ctlr->mboxlock);
626 if(ctlr->mbox >= NMbox)
630 * This command does not require Hardy
631 * and doesn't generate a Cmdc interrupt.
634 outb(ctlr->port+Rcpr, Cstart);
635 unlock(&ctlr->mboxlock);
638 * Wait for the request to complete and return the status.
639 * Since the buffer is not reference counted cannot return
640 * until the DMA is done writing into the buffer so the caller
641 * cannot free the buffer prematurely.
645 sleep(ccb, done32, ccb);
649 * Save the status and patch up the number of
650 * bytes actually transferred.
651 * There's a firmware bug on some 956C controllers
652 * which causes the return count from a successful
653 * READ CAPACITY not to be updated, so fix it here.
655 sdstat = ccb->sdstat;
656 btstat = ccb->btstat;
659 d |= (ccb->datalen[1]<<8);
660 d |= (ccb->datalen[2]<<16);
661 d |= (ccb->datalen[3]<<24);
662 if(ccb->cdb[0] == 0x25 && sdstat == SDok)
668 * If there was a check-condition, save the
669 * ccb for a possible request-sense command.
671 if(sdstat == SDcheck){
672 if(r->flags & SDnosense){
673 lock(&ctlr->cachelock);
674 if(ctlr->cache[target])
675 ccbfree(ctlr, ctlr->cache[target]);
676 ctlr->cache[target] = (Ccb*)ccb;
677 unlock(&ctlr->cachelock);
681 if(n > sizeof(r->sense)-1)
682 n = sizeof(r->sense)-1;
683 memmove(r->sense, ccb->sense, n);
684 r->flags |= SDvalidsense;
686 ccbfree(ctlr, (Ccb*)ccb);
697 mylex32interrupt(Ureg*, void* arg)
703 int port, rinterrupt, rstatus;
709 * Save and clear the interrupt(s). The only
710 * interrupts expected are Cmdc, which is ignored,
711 * and Imbl which means something completed.
712 * There's one spurious interrupt left over from
713 * initialisation, ignore it.
714 * In order to share PCI IRQs, just ignore spurious interrupts.
716 rinterrupt = inb(port+Rinterrupt);
717 rstatus = inb(port+Rstatus);
718 outb(port+Rcontrol, Rint);
719 if(0 && (rinterrupt & ~(Cmdc|Imbl)) != Intv && ctlr->spurious++)
720 print("%s: interrupt 0x%2.2ux\n",
721 ctlr->sdev->name, rinterrupt);
722 if((rinterrupt & Cmdc) && (rstatus & Cmdinv))
723 print("%s: command invalid\n", ctlr->sdev->name);
726 * Look for something in the mail.
727 * If there is, free the mailbox and wakeup whoever.
730 for(mbox = &mb[ctlr->mbix]; mbox->code; mbox = &mb[ctlr->mbix]){
731 pa = (mbox->ccb[3]<<24)
736 ccb = BPA2K(pa, ctlr->pcidev->tbdf);
738 ccb = BPA2K(pa, BUSUNKNOWN);
744 if(ctlr->mbix >= NMbox+NMbox)
755 subno = r->unit->subno;
756 ctlr = r->unit->dev->ctlr;
757 if(subno == ctlr->id || (!ctlr->wide && subno >= 8))
758 r->status = SDtimeout;
759 else if(ctlr->bus == 24)
760 r->status = mylex24rio(r);
762 r->status = mylex32rio(r);
767 * Issue a command to a controller. The command and its length is
768 * contained in cmd and cmdlen. If any data is to be
769 * returned, datalen should be non-zero, and the returned data
770 * will be placed in data.
771 * If Cmdc is set, bail out, the invalid command will be handled
772 * when the interrupt is processed.
775 issueio(int port, uchar* cmd, int cmdlen, uchar* data, int datalen)
779 if(cmd[0] != Cstart && cmd[0] != Ceombri){
780 while(!(inb(port+Rstatus) & Hardy))
783 outb(port+Rcpr, cmd[0]);
787 if(!(inb(port+Rstatus) & Cprbsy)){
788 outb(port+Rcpr, cmd[len]);
791 if(inb(port+Rinterrupt) & Cmdc)
797 while(len < datalen){
798 if(inb(port+Rstatus) & Dirrdy){
799 data[len] = inb(port+Rdatain);
802 if(inb(port+Rinterrupt) & Cmdc)
809 * Issue a command to a controller, wait for it to complete then
810 * try to reset the interrupt. Should only be called at initialisation.
813 issue(Ctlr* ctlr, uchar* cmd, int cmdlen, uchar* data, int datalen)
816 uchar rinterrupt, rstatus;
817 static Lock mylexissuelock;
821 ilock(&ctlr->issuelock);
822 issueio(port, cmd, cmdlen, data, datalen);
824 while(!((rinterrupt = inb(port+Rinterrupt)) & Cmdc))
827 rstatus = inb(port+Rstatus);
828 outb(port+Rcontrol, Rint);
829 iunlock(&ctlr->issuelock);
831 if((rinterrupt & Cmdc) && (rstatus & Cmdinv))
837 mylexprobe(int port, int irq)
841 uchar cmd[6], data[256];
842 int clen, dlen, timeo;
844 if(ioalloc(port, 0x3, 0, "mylex") < 0)
849 * Attempt to hard-reset the board and reset
850 * the SCSI bus. If the board state doesn't settle to
851 * idle with mailbox initialisation required, either
852 * it isn't a compatible board or it's broken.
853 * If the controller has SCAM set this can take a while.
855 if(getconf("*noscsireset") != nil)
856 outb(port+Rcontrol, Rhard);
858 outb(port+Rcontrol, Rhard|Rsbus);
859 for(timeo = 0; timeo < 100; timeo++){
860 if(inb(port+Rstatus) == (Inreq|Hardy))
864 if(inb(port+Rstatus) != (Inreq|Hardy)){
874 if((ctlr = malloc(sizeof(Ctlr))) == nil)
882 * Try to determine if this is a 32-bit MultiMaster controller
883 * by attempting to obtain the extended inquiry information;
884 * this command is not implemented on Adaptec 154xx
885 * controllers. If successful, the first byte of the returned
886 * data is the host adapter bus type, 'E' for 32-bit EISA,
893 if(issue(ctlr, cmd, clen, data, dlen)){
896 print("mylex ctlr @ port 0x%ux: 32-bit ", ctlr->port);
897 ctlr->wide = data[0x0D] & 0x01;
902 print("SCSI host adapter\n");
906 * Inconceivable though it may seem, a hard controller reset
907 * is necessary here to clear out the command queue. Every
908 * board seems to lock-up in a different way if you give an
909 * invalid command and then try to clear out the
910 * command/parameter and/or data-in register.
911 * Soft reset doesn't do the job either. Fortunately no
912 * serious initialisation has been done yet so there's nothing
915 outb(port+Rcontrol, Rhard);
916 for(timeo = 0; timeo < 100; timeo++){
917 if(inb(port+Rstatus) == (Inreq|Hardy))
921 if(inb(port+Rstatus) != (Inreq|Hardy))
926 * If the BIOS is enabled on the AHA-1542C/CF and BIOS options for
927 * support of drives > 1Gb, dynamic scanning of the SCSI bus or more
928 * than 2 drives under DOS 5.0 are enabled, the BIOS disables
929 * accepting Cmbinit to protect against running with drivers which
930 * don't support those options. In order to unlock the interface it
931 * is necessary to read a lock-code using Cextbios and write it back
932 * using Cmbienable; the lock-code is non-zero.
937 if(issue(ctlr, cmd, clen, data, dlen) == 0)
943 if(issue(ctlr, cmd, clen, data, dlen) == 0)
947 * Lock-code returned in data[1]. If it's non-zero write
948 * it back along with bit 0 of byte 0 cleared to enable
949 * mailbox initialisation.
956 if(issue(ctlr, cmd, clen, 0, 0) == 0)
962 * Get the id, DMA and IRQ info from the board. This will
963 * cause an interrupt which will hopefully not cause any
964 * trouble because the interrupt number isn't known yet.
965 * This is necessary as the DMA won't be set up if the
966 * board has the BIOS disabled.
968 * If the IRQ is already known, this must be a 32-bit PCI
969 * or EISA card, in which case the returned DMA and IRQ can
975 if(issue(ctlr, cmd, clen, data, dlen) == 0)
978 ctlr->id = data[2] & 0x07;
980 switch(data[0]){ /* DMA Arbitration Priority */
981 case 0x80: /* Channel 7 */
985 case 0x40: /* Channel 6 */
989 case 0x20: /* Channel 5 */
993 case 0x01: /* Channel 0 */
1003 switch(data[1]){ /* Interrupt Channel */
1027 if((sdev = malloc(sizeof(SDev))) == nil)
1029 sdev->ifc = &sdmylexifc;
1041 static int mylexport[8] = {
1042 0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0x000, 0x000,
1051 int cfg, ctlrno, i, x;
1052 SDev *sdev, *head, *tail;
1056 while(p = pcimatch(p, 0x104B, 0)){
1057 if((sdev = mylexprobe(p->mem[0].bar & ~0x01, p->intl)) == nil)
1070 if(strncmp(KADDR(0xFFFD9), "EISA", 4) == 0){
1071 for(cfg = 0x1000; cfg < MaxEISA*0x1000; cfg += 0x1000){
1073 for(i = 0; i < 4; i++)
1074 x |= inb(cfg+CfgEISA+i)<<(i*8);
1075 if(x != 0x0142B30A && x != 0x0242B30A)
1079 if((sdev = mylexprobe(mylexport[x & 0x07], -1)) == nil)
1090 for(ctlrno = 0; ctlrno < 4; ctlrno++){
1091 memset(&isa, 0, sizeof(isa));
1092 if(!isaconfig("scsi", ctlrno, &isa))
1094 if(strcmp(isa.type, "aha1542"))
1096 if((sdev = mylexprobe(isa.port, -1)) == nil)
1110 mylex24enable(Ctlr* ctlr)
1117 len = (sizeof(Mbox24)*NMbox*2)+(sizeof(Ccb24)*NCcb);
1118 v = xspanalloc(len, 32, 0);
1120 if(!PADDR24(ctlr, sizeof(Ctlr)) || !PADDR24(v, len))
1124 v += sizeof(Mbox24)*NMbox*2;
1127 for(ccbp = ccb; ccbp < &ccb[NCcb]; ccbp++){
1128 ccbp->ccb = ctlr->ccb;
1129 ctlr->ccb = (Ccb*)ccbp;
1133 * Initialise the software controller and
1134 * set the board scanning the mailboxes.
1138 cmd[0] = Cinitialise;
1140 p = K2BPA(ctlr->mb, BUSUNKNOWN);
1145 return issue(ctlr, cmd, 5, 0, 0);
1149 mylex32enable(Ctlr* ctlr)
1155 v = xspanalloc((sizeof(Mbox32)*NMbox*2)+(sizeof(Ccb32)*NCcb), 32, 0);
1158 v += sizeof(Mbox32)*NMbox*2;
1161 for(ccbp = ccb; ccbp < &ccb[NCcb]; ccbp++){
1163 * Fill in some stuff that doesn't change.
1165 ccbp->senselen = sizeof(ccbp->sense);
1166 p = PADDR(ccbp->sense);
1167 ccbp->senseptr[0] = p;
1168 ccbp->senseptr[1] = p>>8;
1169 ccbp->senseptr[2] = p>>16;
1170 ccbp->senseptr[3] = p>>24;
1172 ccbp->ccb = ctlr->ccb;
1173 ctlr->ccb = (Ccb*)ccbp;
1177 * Attempt wide mode setup.
1182 if(!issue(ctlr, cmd, 2, 0, 0)) {
1185 "mylex32enable: ctlr @ port 0x%ux: scsi wide-mode setup failed on wide host adapter",
1191 * Initialise the software controller and
1192 * set the board scanning the mailboxes.
1199 p = K2BPA(ctlr->mb, ctlr->tbdf);
1201 p = K2BPA(ctlr->mb, BUSUNKNOWN);
1207 return issue(ctlr, cmd, 6, 0, 0);
1211 mylexenable(SDev* sdev)
1215 void (*interrupt)(Ureg*, void*);
1219 if(ctlr->cache == nil){
1220 if((ctlr->cache = malloc(sdev->nunit*sizeof(Ccb*))) == nil)
1225 if(ctlr->bus == 32){
1227 tbdf = ctlr->pcidev->tbdf;
1228 pcisetbme(ctlr->pcidev);
1230 if(!mylex32enable(ctlr))
1232 interrupt = mylex32interrupt;
1234 else if(mylex24enable(ctlr))
1235 interrupt = mylex24interrupt;
1239 snprint(name, sizeof(name), "sd%c (%s)", sdev->idno, sdev->ifc->name);
1240 intrenable(ctlr->irq, interrupt, ctlr, tbdf, name);
1245 SDifc sdmylexifc = {
1250 mylexenable, /* enable */
1253 scsiverify, /* verify */
1254 scsionline, /* online */