sys/src/9/pc/sdide.c

   1 #include "u.h"
   2 #include "../port/lib.h"
   3 #include "mem.h"
   4 #include "dat.h"
   5 #include "fns.h"
   6 #include "io.h"
   7 #include "ureg.h"
   8 #include "../port/error.h"
   9
  10 #include "../port/sd.h"
  11 #include <fis.h>
  12
  13 #define HOWMANY(x, y)   (((x)+((y)-1))/(y))
  14 #define ROUNDUP(x, y)   (HOWMANY((x), (y))*(y))
  15 #define uprint(...)     snprint(up->genbuf, sizeof up->genbuf, __VA_ARGS__);
  16 #pragma varargck        argpos  atadebug                3
  17
  18 extern SDifc sdideifc;
  19
  20 enum {
  21         DbgCONFIG       = 0x0001,       /* detected drive config info */
  22         DbgIDENTIFY     = 0x0002,       /* detected drive identify info */
  23         DbgSTATE        = 0x0004,       /* dump state on panic */
  24         DbgPROBE        = 0x0008,       /* trace device probing */
  25         DbgDEBUG        = 0x0080,       /* the current problem... */
  26         DbgINL          = 0x0100,       /* That Inil20+ message we hate */
  27         Dbg48BIT        = 0x0200,       /* 48-bit LBA */
  28         DbgBsy          = 0x0400,       /* interrupt but Bsy (shared IRQ) */
  29         DbgAtazz        = 0x0800,       /* debug raw ata io */
  30 };
  31 #define DEBUG           (DbgDEBUG|DbgSTATE)
  32
  33 enum {                                  /* I/O ports */
  34         Data            = 0,
  35         Error           = 1,            /* (read) */
  36         Features        = 1,            /* (write) */
  37         Count           = 2,            /* sector count<7-0>, sector count<15-8> */
  38         Ir              = 2,            /* interrupt reason (PACKET) */
  39         Sector          = 3,            /* sector number */
  40         Lbalo           = 3,            /* LBA<7-0>, LBA<31-24> */
  41         Cyllo           = 4,            /* cylinder low */
  42         Bytelo          = 4,            /* byte count low (PACKET) */
  43         Lbamid          = 4,            /* LBA<15-8>, LBA<39-32> */
  44         Cylhi           = 5,            /* cylinder high */
  45         Bytehi          = 5,            /* byte count hi (PACKET) */
  46         Lbahi           = 5,            /* LBA<23-16>, LBA<47-40> */
  47         Dh              = 6,            /* Device/Head, LBA<27-24> */
  48         Status          = 7,            /* (read) */
  49         Command         = 7,            /* (write) */
  50
  51         As              = 2,            /* Alternate Status (read) */
  52         Dc              = 2,            /* Device Control (write) */
  53 };
  54
  55 enum {                                  /* Error */
  56         Med             = 0x01,         /* Media error */
  57         Ili             = 0x01,         /* command set specific (PACKET) */
  58         Nm              = 0x02,         /* No Media */
  59         Eom             = 0x02,         /* command set specific (PACKET) */
  60         Abrt            = 0x04,         /* Aborted command */
  61         Mcr             = 0x08,         /* Media Change Request */
  62         Idnf            = 0x10,         /* no user-accessible address */
  63         Mc              = 0x20,         /* Media Change */
  64         Unc             = 0x40,         /* Uncorrectable data error */
  65         Wp              = 0x40,         /* Write Protect */
  66         Icrc            = 0x80,         /* Interface CRC error */
  67 };
  68
  69 enum {                                  /* Features */
  70         Dma             = 0x01,         /* data transfer via DMA (PACKET) */
  71         Ovl             = 0x02,         /* command overlapped (PACKET) */
  72 };
  73
  74 enum {                                  /* Interrupt Reason */
  75         Cd              = 0x01,         /* Command/Data */
  76         Io              = 0x02,         /* I/O direction */
  77         Rel             = 0x04,         /* Bus Release */
  78 };
  79
  80 enum {                                  /* Device/Head */
  81         Dev0            = 0xA0,         /* Master */
  82         Dev1            = 0xB0,         /* Slave */
  83         Devs            = Dev0 | Dev1,
  84         Lba             = 0x40,         /* LBA mode */
  85 };
  86
  87 enum {                                  /* Status, Alternate Status */
  88         Err             = 0x01,         /* Error */
  89         Chk             = 0x01,         /* Check error (PACKET) */
  90         Drq             = 0x08,         /* Data Request */
  91         Dsc             = 0x10,         /* Device Seek Complete */
  92         Serv            = 0x10,         /* Service */
  93         Df              = 0x20,         /* Device Fault */
  94         Dmrd            = 0x20,         /* DMA ready (PACKET) */
  95         Drdy            = 0x40,         /* Device Ready */
  96         Bsy             = 0x80,         /* Busy */
  97 };
  98
  99 enum {                                  /* Command */
 100         Cnop            = 0x00,         /* NOP */
 101         Crs             = 0x20,         /* Read Sectors */
 102         Crs48           = 0x24,         /* Read Sectors Ext */
 103         Crd48           = 0x25,         /* Read w/ DMA Ext */
 104         Crsm48          = 0x29,         /* Read Multiple Ext */
 105         Cws             = 0x30,         /* Write Sectors */
 106         Cws48           = 0x34,         /* Write Sectors Ext */
 107         Cwd48           = 0x35,         /* Write w/ DMA Ext */
 108         Cwsm48          = 0x39,         /* Write Multiple Ext */
 109         Cedd            = 0x90,         /* Execute Device Diagnostics */
 110         Cpkt            = 0xA0,         /* Packet */
 111         Cidpkt          = 0xA1,         /* Identify Packet Device */
 112         Crsm            = 0xC4,         /* Read Multiple */
 113         Cwsm            = 0xC5,         /* Write Multiple */
 114         Csm             = 0xC6,         /* Set Multiple */
 115         Crd             = 0xC8,         /* Read DMA */
 116         Cwd             = 0xCA,         /* Write DMA */
 117         Cid             = 0xEC,         /* Identify Device */
 118 };
 119
 120 enum {                                  /* Device Control */
 121         Nien            = 0x02,         /* (not) Interrupt Enable */
 122         Srst            = 0x04,         /* Software Reset */
 123         Hob             = 0x80,         /* High Order Bit [sic] */
 124 };
 125
 126 enum {                                  /* PCI Configuration Registers */
 127         Bmiba           = 0x20,         /* Bus Master Interface Base Address */
 128         Idetim          = 0x40,         /* IE Timing */
 129         Sidetim         = 0x44,         /* Slave IE Timing */
 130         Udmactl         = 0x48,         /* Ultra DMA/33 Control */
 131         Udmatim         = 0x4A,         /* Ultra DMA/33 Timing */
 132 };
 133
 134 enum {                                  /* Bus Master IDE I/O Ports */
 135         Bmicx           = 0,            /* Command */
 136         Bmisx           = 2,            /* Status */
 137         Bmidtpx         = 4,            /* Descriptor Table Pointer */
 138 };
 139
 140 enum {                                  /* Bmicx */
 141         Ssbm            = 0x01,         /* Start/Stop Bus Master */
 142         Rwcon           = 0x08,         /* Read/Write Control */
 143 };
 144
 145 enum {                                  /* Bmisx */
 146         Bmidea          = 0x01,         /* Bus Master IDE Active */
 147         Idedmae         = 0x02,         /* IDE DMA Error  (R/WC) */
 148         Ideints         = 0x04,         /* IDE Interrupt Status (R/WC) */
 149         Dma0cap         = 0x20,         /* Drive 0 DMA Capable */
 150         Dma1cap         = 0x40,         /* Drive 0 DMA Capable */
 151 };
 152 enum {                                  /* Physical Region Descriptor */
 153         PrdEOT          = 0x80000000,   /* End of Transfer */
 154 };
 155
 156 enum {                                  /* offsets into the identify info. */
 157         Iconfig         = 0,            /* general configuration */
 158         Ilcyl           = 1,            /* logical cylinders */
 159         Ilhead          = 3,            /* logical heads */
 160         Ilsec           = 6,            /* logical sectors per logical track */
 161         Iserial         = 10,           /* serial number */
 162         Ifirmware       = 23,           /* firmware revision */
 163         Imodel          = 27,           /* model number */
 164         Imaxrwm         = 47,           /* max. read/write multiple sectors */
 165         Icapabilities   = 49,           /* capabilities */
 166         Istandby        = 50,           /* device specific standby timer */
 167         Ipiomode        = 51,           /* PIO data transfer mode number */
 168         Ivalid          = 53,
 169         Iccyl           = 54,           /* cylinders if (valid&0x01) */
 170         Ichead          = 55,           /* heads if (valid&0x01) */
 171         Icsec           = 56,           /* sectors if (valid&0x01) */
 172         Iccap           = 57,           /* capacity if (valid&0x01) */
 173         Irwm            = 59,           /* read/write multiple */
 174         Ilba            = 60,           /* LBA size */
 175         Imwdma          = 63,           /* multiword DMA mode */
 176         Iapiomode       = 64,           /* advanced PIO modes supported */
 177         Iminmwdma       = 65,           /* min. multiword DMA cycle time */
 178         Irecmwdma       = 66,           /* rec. multiword DMA cycle time */
 179         Iminpio         = 67,           /* min. PIO cycle w/o flow control */
 180         Iminiordy       = 68,           /* min. PIO cycle with IORDY */
 181         Ipcktbr         = 71,           /* time from PACKET to bus release */
 182         Iserbsy         = 72,           /* time from SERVICE to !Bsy */
 183         Iqdepth         = 75,           /* max. queue depth */
 184         Imajor          = 80,           /* major version number */
 185         Iminor          = 81,           /* minor version number */
 186         Icsfs           = 82,           /* command set/feature supported */
 187         Icsfe           = 85,           /* command set/feature enabled */
 188         Iudma           = 88,           /* ultra DMA mode */
 189         Ierase          = 89,           /* time for security erase */
 190         Ieerase         = 90,           /* time for enhanced security erase */
 191         Ipower          = 91,           /* current advanced power management */
 192         Ilba48          = 100,          /* 48-bit LBA size (64 bits in 100-103) */
 193         Irmsn           = 127,          /* removable status notification */
 194         Isecstat        = 128,          /* security status */
 195         Icfapwr         = 160,          /* CFA power mode */
 196         Imediaserial    = 176,          /* current media serial number */
 197         Icksum          = 255,          /* checksum */
 198 };
 199
 200 enum {                                  /* bit masks for config identify info */
 201         Mpktsz          = 0x0003,       /* packet command size */
 202         Mincomplete     = 0x0004,       /* incomplete information */
 203         Mdrq            = 0x0060,       /* DRQ type */
 204         Mrmdev          = 0x0080,       /* device is removable */
 205         Mtype           = 0x1F00,       /* device type */
 206         Mproto          = 0x8000,       /* command protocol */
 207 };
 208
 209 enum {                                  /* bit masks for capabilities identify info */
 210         Mdma            = 0x0100,       /* DMA supported */
 211         Mlba            = 0x0200,       /* LBA supported */
 212         Mnoiordy        = 0x0400,       /* IORDY may be disabled */
 213         Miordy          = 0x0800,       /* IORDY supported */
 214         Msoftrst        = 0x1000,       /* needs soft reset when Bsy */
 215         Mqueueing       = 0x4000,       /* queueing overlap supported */
 216         Midma           = 0x8000,       /* interleaved DMA supported */
 217 };
 218
 219 enum {                                  /* bit masks for supported/enabled features */
 220         Msmart          = 0x0001,
 221         Msecurity       = 0x0002,
 222         Mrmmedia        = 0x0004,
 223         Mpwrmgmt        = 0x0008,
 224         Mpkt            = 0x0010,
 225         Mwcache         = 0x0020,
 226         Mlookahead      = 0x0040,
 227         Mrelirq         = 0x0080,
 228         Msvcirq         = 0x0100,
 229         Mreset          = 0x0200,
 230         Mprotected      = 0x0400,
 231         Mwbuf           = 0x1000,
 232         Mrbuf           = 0x2000,
 233         Mnop            = 0x4000,
 234         Mmicrocode      = 0x0001,
 235         Mqueued         = 0x0002,
 236         Mcfa            = 0x0004,
 237         Mapm            = 0x0008,
 238         Mnotify         = 0x0010,
 239         Mspinup         = 0x0040,
 240         Mmaxsec         = 0x0100,
 241         Mautoacoustic   = 0x0200,
 242         Maddr48         = 0x0400,
 243         Mdevconfov      = 0x0800,
 244         Mflush          = 0x1000,
 245         Mflush48        = 0x2000,
 246         Msmarterror     = 0x0001,
 247         Msmartselftest  = 0x0002,
 248         Mmserial        = 0x0004,
 249         Mmpassthru      = 0x0008,
 250         Mlogging        = 0x0020,
 251 };
 252
 253 typedef struct Ctlr Ctlr;
 254 typedef struct Drive Drive;
 255
 256 typedef struct Prd {                    /* Physical Region Descriptor */
 257         ulong   pa;                     /* Physical Base Address */
 258         int     count;
 259 } Prd;
 260
 261 enum {
 262         BMspan          = 32*1024,      /* must be power of 2 <= 64*1024 */
 263
 264         Nprd            = SDmaxio/BMspan+2,
 265 };
 266
 267 typedef struct Ctlr {
 268         int     cmdport;
 269         int     ctlport;
 270         int     irq;
 271         int     tbdf;
 272         int     bmiba;                  /* bus master interface base address */
 273         int     maxio;                  /* sector count transfer maximum */
 274         int     span;                   /* don't span this boundary with dma */
 275         int     maxdma;                 /* don't attempt dma transfers bigger than this */
 276
 277         Pcidev* pcidev;
 278         void    (*ienable)(Ctlr*);
 279         void    (*idisable)(Ctlr*);
 280         SDev*   sdev;
 281
 282         Drive*  drive[2];
 283
 284         Prd*    prdt;                   /* physical region descriptor table */
 285         void    (*irqack)(Ctlr*);
 286
 287         QLock;                          /* current command */
 288         Drive*  curdrive;
 289         int     command;                /* last command issued (debugging) */
 290         Rendez;
 291         int     done;
 292         uint    nrq;
 293         uint    nildrive;
 294         uint    bsy;
 295
 296         Lock;                           /* register access */
 297 } Ctlr;
 298
 299 typedef struct Drive {
 300         Ctlr*   ctlr;
 301         SDunit  *unit;
 302
 303         int     dev;
 304         ushort  info[256];
 305         Sfis;
 306
 307         int     dma;                    /* DMA R/W possible */
 308         int     dmactl;
 309         int     rwm;                    /* read/write multiple possible */
 310         int     rwmctl;
 311
 312         int     pkt;                    /* PACKET device, length of pktcmd */
 313         uchar   pktcmd[16];
 314         int     pktdma;                 /* this PACKET command using dma */
 315
 316         uvlong  sectors;
 317         uint    secsize;
 318         char    serial[20+1];
 319         char    firmware[8+1];
 320         char    model[40+1];
 321
 322         QLock;                          /* drive access */
 323         int     command;                /* current command */
 324         int     write;
 325         uchar*  data;
 326         int     dlen;
 327         uchar*  limit;
 328         int     count;                  /* sectors */
 329         int     block;                  /* R/W bytes per block */
 330         int     status;
 331         int     error;
 332         int     flags;                  /* internal flags */
 333         uint    missirq;
 334         uint    spurloop;
 335         uint    irq;
 336         uint    bsy;
 337 } Drive;
 338
 339 enum {                                  /* internal flags */
 340         Lba48always     = 0x2,          /* ... */
 341         Online          = 0x4,          /* drive onlined */
 342 };
 343
 344 static void
 345 pc87415ienable(Ctlr* ctlr)
 346 {
 347         Pcidev *p;
 348         int x;
 349
 350         p = ctlr->pcidev;
 351         if(p == nil)
 352                 return;
 353
 354         x = pcicfgr32(p, 0x40);
 355         if(ctlr->cmdport == p->mem[0].bar)
 356                 x &= ~0x00000100;
 357         else
 358                 x &= ~0x00000200;
 359         pcicfgw32(p, 0x40, x);
 360 }
 361
 362 static void
 363 atadumpstate(Drive* drive, SDreq *r, uvlong lba, int count)
 364 {
 365         Prd *prd;
 366         Pcidev *p;
 367         Ctlr *ctlr;
 368         int i, bmiba, ccnt;
 369         uvlong clba;
 370
 371         if(!(DEBUG & DbgSTATE))
 372                 return;
 373
 374         ctlr = drive->ctlr;
 375         print("command %2.2uX\n", ctlr->command);
 376         print("data %8.8p limit %8.8p dlen %d status %uX error %uX\n",
 377                 drive->data, drive->limit, drive->dlen,
 378                 drive->status, drive->error);
 379         if(r->clen == -16)
 380                 clba = fisrw(nil, r->cmd, &ccnt);
 381         else
 382                 sdfakescsirw(r, &clba, &ccnt, 0);
 383         print("lba %llud -> %llud, count %d -> %d (%d)\n",
 384                 clba, lba, ccnt, count, drive->count);
 385         if(!(inb(ctlr->ctlport+As) & Bsy)){
 386                 for(i = 1; i < 7; i++)
 387                         print(" 0x%2.2uX", inb(ctlr->cmdport+i));
 388                 print(" 0x%2.2uX\n", inb(ctlr->ctlport+As));
 389         }
 390         if(drive->command == Cwd || drive->command == Crd
 391         || drive->command == (Pdma|Pin) || drive->command == (Pdma|Pout)){
 392                 bmiba = ctlr->bmiba;
 393                 prd = ctlr->prdt;
 394                 print("bmicx %2.2uX bmisx %2.2uX prdt %8.8p\n",
 395                         inb(bmiba+Bmicx), inb(bmiba+Bmisx), prd);
 396                 while(prd){
 397                         print("pa 0x%8.8luX count %8.8uX\n",
 398                                 prd->pa, prd->count);
 399                         if(prd->count & PrdEOT)
 400                                 break;
 401                         prd++;
 402                 }
 403         }
 404         if(ctlr->pcidev && ctlr->pcidev->vid == 0x8086){
 405                 p = ctlr->pcidev;
 406                 print("0x40: %4.4uX 0x42: %4.4uX ",
 407                         pcicfgr16(p, 0x40), pcicfgr16(p, 0x42));
 408                 print("0x48: %2.2uX\n", pcicfgr8(p, 0x48));
 409                 print("0x4A: %4.4uX\n", pcicfgr16(p, 0x4A));
 410         }
 411 }
 412
 413 static void
 414 atadebug(int cmdport, int ctlport, char* fmt, ...)
 415 {
 416         char *p, *e, buf[PRINTSIZE];
 417         int i;
 418         va_list arg;
 419
 420         if(!(DEBUG & DbgPROBE))
 421                 return;
 422
 423         p = buf;
 424         e = buf + sizeof buf;
 425         va_start(arg, fmt);
 426         p = vseprint(p, e, fmt, arg);
 427         va_end(arg);
 428
 429         if(cmdport){
 430                 if(p > buf && p[-1] == '\n')
 431                         p--;
 432                 p = seprint(p, e, " ataregs 0x%uX:", cmdport);
 433                 for(i = Features; i < Command; i++)
 434                         p = seprint(p, e, " 0x%2.2uX", inb(cmdport+i));
 435                 if(ctlport)
 436                         p = seprint(p, e, " 0x%2.2uX", inb(ctlport+As));
 437                 p = seprint(p, e, "\n");
 438         }
 439         putstrn(buf, p - buf);
 440 }
 441
 442 static int
 443 ataready(int cmdport, int ctlport, int dev, int reset, int ready, int m)
 444 {
 445         int as, m0;
 446
 447         atadebug(cmdport, ctlport, "ataready: dev %ux:%ux reset %ux ready %ux",
 448                 cmdport, dev, reset, ready);
 449         m0 = m;
 450         do{
 451                 /*
 452                  * Wait for the controller to become not busy and
 453                  * possibly for a status bit to become true (usually
 454                  * Drdy). Must change to the appropriate device
 455                  * register set if necessary before testing for ready.
 456                  * Always run through the loop at least once so it
 457                  * can be used as a test for !Bsy.
 458                  */
 459                 as = inb(ctlport+As);
 460                 if(as & reset){
 461                         /* nothing to do */
 462                 }
 463                 else if(dev){
 464                         outb(cmdport+Dh, dev);
 465                         dev = 0;
 466                 }
 467                 else if(ready == 0 || (as & ready)){
 468                         atadebug(0, 0, "ataready: %d:%d %#.2ux\n", m, m0, as);
 469                         return as;
 470                 }
 471                 microdelay(1);
 472         }while(m-- > 0);
 473         atadebug(0, 0, "ataready: timeout %d %#.2ux\n", m0, as);
 474         return -1;
 475 }
 476
 477 static int
 478 atadone(void* arg)
 479 {
 480         return ((Ctlr*)arg)->done;
 481 }
 482
 483 static int
 484 atarwmmode(Drive* drive, int cmdport, int ctlport, int dev)
 485 {
 486         int as, maxrwm, rwm;
 487
 488         maxrwm = drive->info[Imaxrwm] & 0xFF;
 489         if(maxrwm == 0)
 490                 return 0;
 491
 492         /*
 493          * Sometimes drives come up with the current count set
 494          * to 0; if so, set a suitable value, otherwise believe
 495          * the value in Irwm if the 0x100 bit is set.
 496          */
 497         if(drive->info[Irwm] & 0x100)
 498                 rwm = drive->info[Irwm] & 0xFF;
 499         else
 500                 rwm = 0;
 501         if(rwm == 0)
 502                 rwm = maxrwm;
 503         if(rwm > 16)
 504                 rwm = 16;
 505         if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 102*1000) < 0)
 506                 return 0;
 507         outb(cmdport+Count, rwm);
 508         outb(cmdport+Command, Csm);
 509         microdelay(1);
 510         as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 1000);
 511         inb(cmdport+Status);
 512         if(as < 0 || (as & (Df|Err)))
 513                 return 0;
 514
 515         drive->rwm = rwm;
 516
 517         return rwm;
 518 }
 519
 520 static int
 521 atadmamode(SDunit *unit, Drive* drive)
 522 {
 523         char buf[32], *s;
 524         int dma;
 525
 526         /*
 527          * Check if any DMA mode enabled.
 528          * Assumes the BIOS has picked and enabled the best.
 529          * This is completely passive at the moment, no attempt is
 530          * made to ensure the hardware is correctly set up.
 531          */
 532         dma = drive->info[Imwdma] & 0x0707;
 533         drive->dma = (dma>>8) & dma;
 534         if(drive->dma == 0 && (drive->info[Ivalid] & 0x04)){
 535                 dma = drive->info[Iudma] & 0x7F7F;
 536                 drive->dma = (dma>>8) & dma;
 537                 if(drive->dma)
 538                         drive->dma |= 'U'<<16;
 539         }
 540         if(unit != nil){
 541                 snprint(buf, sizeof buf, "*%sdma", unit->name);
 542                 s = getconf(buf);
 543                 if((s && !strcmp(s, "on")) || (!s && !getconf("*nodma")))
 544                         drive->dmactl = drive->dma;
 545         }
 546         return dma;
 547 }
 548
 549 static int
 550 ataidentify(Ctlr*, int cmdport, int ctlport, int dev, int pkt, void* info)
 551 {
 552         int as, command, drdy;
 553
 554         if(pkt){
 555                 command = Cidpkt;
 556                 drdy = 0;
 557         }
 558         else{
 559                 command = Cid;
 560                 drdy = Drdy;
 561         }
 562         dev &= ~Lba;
 563         as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
 564         if(as < 0)
 565                 return -1;
 566         outb(cmdport+Command, command);
 567         microdelay(1);
 568
 569         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
 570         if(as < 0 || (as & Err))
 571                 return as;
 572         memset(info, 0, 512);
 573         inss(cmdport+Data, info, 256);
 574         inb(cmdport+Status);
 575         return 0;
 576 }
 577
 578 static Drive*
 579 atadrive(SDunit *unit, Drive *drive, int cmdport, int ctlport, int dev)
 580 {
 581         int as, pkt, rlo, rhi;
 582         uchar buf[512], oserial[21];
 583         uvlong osectors;
 584         Ctlr *ctlr;
 585
 586         if(DEBUG & DbgIDENTIFY)
 587                 print("identify: port %ux dev %.2ux\n", cmdport, dev & ~Lba);
 588
 589         atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
 590         if(drive != nil){
 591                 osectors = drive->sectors;
 592                 memmove(oserial, drive->serial, sizeof drive->serial);
 593                 ctlr = drive->ctlr;
 594         }else{
 595                 osectors = 0;
 596                 memset(oserial, 0, sizeof drive->serial);
 597                 ctlr = nil;
 598
 599                 /* detect if theres a drive present */
 600                 outb(cmdport+Dh, dev & ~Lba);
 601                 microdelay(1);
 602                 outb(cmdport+Cyllo, 0xAA);
 603                 outb(cmdport+Cylhi, 0x55);
 604                 outb(cmdport+Sector, 0xFF);
 605                 rlo = inb(cmdport+Cyllo);
 606                 rhi = inb(cmdport+Cylhi);
 607                 if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55))
 608                         return nil;
 609         }
 610
 611         pkt = 1;
 612 retry:
 613         as = ataidentify(ctlr, cmdport, ctlport, dev, pkt, buf);
 614         if(as < 0)
 615                 return nil;
 616         if(as & Err){
 617                 if(pkt == 0)
 618                         return nil;
 619                 pkt = 0;
 620                 goto retry;
 621         }
 622
 623         if(drive == 0){
 624                 if((drive = malloc(sizeof(Drive))) == nil)
 625                         return nil;
 626                 drive->serial[0] = ' ';
 627                 drive->dev = dev;
 628         }
 629
 630         memmove(drive->info, buf, sizeof(drive->info));
 631
 632         setfissig(drive, pkt ? 0xeb140000 : 0x0101);
 633         drive->sectors = idfeat(drive, drive->info);
 634         drive->secsize = idss(drive, drive->info);
 635
 636         idmove(drive->serial, drive->info+10, 20);
 637         idmove(drive->firmware, drive->info+23, 8);
 638         idmove(drive->model, drive->info+27, 40);
 639         if(unit != nil){
 640                 memset(unit->inquiry, 0, sizeof unit->inquiry);
 641                 unit->inquiry[2] = 2;
 642                 unit->inquiry[3] = 2;
 643                 unit->inquiry[4] = sizeof unit->inquiry - 4;
 644                 memmove(unit->inquiry+8, drive->model, 40);
 645         }
 646
 647         if(pkt){
 648                 drive->pkt = 12;
 649                 if(drive->feat & Datapi16)
 650                         drive->pkt = 16;
 651         }else{
 652                 drive->pkt = 0;
 653                 if(drive->feat & Dlba)
 654                         drive->dev |= Lba;
 655                 atarwmmode(drive, cmdport, ctlport, dev);
 656         }
 657         atadmamode(unit, drive);
 658
 659         if(osectors != 0 && memcmp(oserial, drive->serial, sizeof oserial) != 0)
 660                 if(unit)
 661                         unit->sectors = 0;
 662         drive->unit = unit;
 663         if(DEBUG & DbgCONFIG){
 664                 print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
 665                         dev, cmdport, drive->info[Iconfig], drive->info[Icapabilities]);
 666                 print(" mwdma %4.4uX", drive->info[Imwdma]);
 667                 if(drive->info[Ivalid] & 0x04)
 668                         print(" udma %4.4uX", drive->info[Iudma]);
 669                 print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
 670                 if(drive->feat&Dllba)
 671                         print("\tLLBA sectors %llud", drive->sectors);
 672                 print("\n");
 673         }
 674
 675         return drive;
 676 }
 677
 678 static void
 679 atasrst(int ctlport)
 680 {
 681         int dc0;
 682
 683         /*
 684          * Srst is a big stick and may cause problems if further
 685          * commands are tried before the drives become ready again.
 686          * Also, there will be problems here if overlapped commands
 687          * are ever supported.
 688          */
 689         dc0 = inb(ctlport+Dc);
 690         microdelay(5);
 691         outb(ctlport+Dc, Srst|dc0);
 692         microdelay(5);
 693         outb(ctlport+Dc, dc0);
 694         microdelay(2*1000);
 695 }
 696
 697 static SDev*
 698 ataprobe(int cmdport, int ctlport, int irq, int map)
 699 {
 700         static int nonlegacy = 'C';
 701         Ctlr* ctlr;
 702         SDev *sdev;
 703
 704         if(ioalloc(cmdport, 8, 0, "atacmd") < 0) {
 705                 print("ataprobe: Cannot allocate %X\n", cmdport);
 706                 return nil;
 707         }
 708         if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
 709                 print("ataprobe: Cannot allocate %X\n", ctlport + As);
 710                 iofree(cmdport);
 711                 return nil;
 712         }
 713
 714         if((ctlr = malloc(sizeof(Ctlr))) == nil)
 715                 goto release;
 716         if((sdev = malloc(sizeof(SDev))) == nil){
 717                 free(ctlr);
 718                 goto release;
 719         }
 720
 721         if((map & 2) && (ctlr->drive[1] = atadrive(0, 0, cmdport, ctlport, Dev1)))
 722                 ctlr->drive[1]->ctlr = ctlr;
 723         if((map & 1) && (ctlr->drive[0] = atadrive(0, 0, cmdport, ctlport, Dev0)))
 724                 ctlr->drive[0]->ctlr = ctlr;
 725
 726         if(ctlr->drive[0] == nil && ctlr->drive[1] == nil){
 727                 free(ctlr->drive[0]);
 728                 free(ctlr->drive[1]);
 729                 free(ctlr);
 730                 free(sdev);
 731                 goto release;
 732         }
 733
 734         ctlr->cmdport = cmdport;
 735         ctlr->ctlport = ctlport;
 736         ctlr->irq = irq;
 737         ctlr->tbdf = BUSUNKNOWN;
 738         ctlr->command = Cnop;           /* debugging */
 739
 740         switch(cmdport){
 741         default:
 742                 sdev->idno = nonlegacy;
 743                 break;
 744         case 0x1F0:
 745                 sdev->idno = 'C';
 746                 nonlegacy = 'E';
 747                 break;
 748         case 0x170:
 749                 sdev->idno = 'D';
 750                 nonlegacy = 'E';
 751                 break;
 752         }
 753         sdev->ifc = &sdideifc;
 754         sdev->ctlr = ctlr;
 755         sdev->nunit = 2;
 756         ctlr->sdev = sdev;
 757
 758         return sdev;
 759
 760 release:
 761         iofree(cmdport);
 762         iofree(ctlport+As);
 763
 764         return nil;
 765 }
 766
 767 static void
 768 ataclear(SDev *sdev)
 769 {
 770         Ctlr* ctlr;
 771
 772         ctlr = sdev->ctlr;
 773         iofree(ctlr->cmdport);
 774         iofree(ctlr->ctlport + As);
 775
 776         if (ctlr->drive[0])
 777                 free(ctlr->drive[0]);
 778         if (ctlr->drive[1])
 779                 free(ctlr->drive[1]);
 780         if (sdev->name)
 781                 free(sdev->name);
 782         if (sdev->unitflg)
 783                 free(sdev->unitflg);
 784         if (sdev->unit)
 785                 free(sdev->unit);
 786         free(ctlr);
 787         free(sdev);
 788 }
 789
 790 static char *
 791 atastat(SDev *sdev, char *p, char *e)
 792 {
 793         Ctlr *ctlr;
 794
 795         ctlr = sdev->ctlr;
 796 //      return seprint(p, e, "%s ata port %X ctl %X irq %d %T\n",
 797 //                  sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq, ctlr->tbdf);
 798         return seprint(p, e, "%s ata port %X ctl %X irq %d\n",
 799                     sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq);
 800 }
 801
 802 static SDev*
 803 ataprobew(DevConf *cf)
 804 {
 805         char *p;
 806         ISAConf isa;
 807
 808         if (cf->nports != 2)
 809                 error(Ebadarg);
 810
 811         memset(&isa, 0, sizeof isa);
 812         isa.port = cf->ports[0].port;
 813         isa.irq = cf->intnum;
 814         if((p=strchr(cf->type, '/')) == nil || pcmspecial(p+1, &isa) < 0)
 815                 error("cannot find controller");
 816
 817         return ataprobe(cf->ports[0].port, cf->ports[1].port, cf->intnum, 3);
 818 }
 819
 820 static void atainterrupt(Ureg*, void*);
 821
 822 static int
 823 iowait(Drive *drive, int ms, int interrupt)
 824 {
 825         int msec, step;
 826         Ctlr *ctlr;
 827
 828         step = 1000;
 829         if(drive->missirq > 10)
 830                 step = 50;
 831         ctlr = drive->ctlr;
 832         for(msec = 0; msec < ms; msec += step){
 833                 while(waserror())
 834                         if(interrupt)
 835                                 return -1;
 836                 tsleep(ctlr, atadone, ctlr, step);
 837                 poperror();
 838                 if(ctlr->done)
 839                         break;
 840                 atainterrupt(nil, ctlr);
 841                 if(ctlr->done){
 842                         if(drive->missirq++ < 3)
 843                                 print("ide: caught missed irq\n");
 844                         break;
 845                 }else
 846                         drive->spurloop++;
 847         }
 848         return ctlr->done;
 849 }
 850
 851 static void
 852 atanop(Drive* drive, int subcommand)
 853 {
 854         Ctlr* ctlr;
 855         int as, cmdport, ctlport, timeo;
 856
 857         /*
 858          * Attempt to abort a command by using NOP.
 859          * In response, the drive is supposed to set Abrt
 860          * in the Error register, set (Drdy|Err) in Status
 861          * and clear Bsy when done. However, some drives
 862          * (e.g. ATAPI Zip) just go Bsy then clear Status
 863          * when done, hence the timeout loop only on Bsy
 864          * and the forced setting of drive->error.
 865          */
 866         ctlr = drive->ctlr;
 867         cmdport = ctlr->cmdport;
 868         outb(cmdport+Features, subcommand);
 869         outb(cmdport+Dh, drive->dev);
 870         ctlr->command = Cnop;           /* debugging */
 871         outb(cmdport+Command, Cnop);
 872
 873         microdelay(1);
 874         ctlport = ctlr->ctlport;
 875         for(timeo = 0; timeo < 1000; timeo++){
 876                 as = inb(ctlport+As);
 877                 if(!(as & Bsy))
 878                         break;
 879                 microdelay(1);
 880         }
 881         drive->error |= Abrt;
 882 }
 883
 884 static void
 885 ataabort(Drive* drive, int dolock)
 886 {
 887         /*
 888          * If NOP is available use it otherwise
 889          * must try a software reset.
 890          */
 891         if(dolock)
 892                 ilock(drive->ctlr);
 893         if(drive->feat & Dnop)
 894                 atanop(drive, 0);
 895         else{
 896                 atasrst(drive->ctlr->ctlport);
 897                 drive->error |= Abrt;
 898         }
 899         if(dolock)
 900                 iunlock(drive->ctlr);
 901 }
 902
 903 static int
 904 atadmasetup(Drive* drive, int len)
 905 {
 906         Prd *prd;
 907         ulong pa;
 908         Ctlr *ctlr;
 909         int bmiba, bmisx, count, i, span;
 910
 911         ctlr = drive->ctlr;
 912         pa = PCIWADDR(drive->data);
 913         if(pa & 0x03)
 914                 return -1;
 915         if(ctlr->maxdma && len > ctlr->maxdma)
 916                 return -1;
 917
 918         /*
 919          * Sometimes drives identify themselves as being DMA capable
 920          * although they are not on a busmastering controller.
 921          */
 922         prd = ctlr->prdt;
 923         if(prd == nil){
 924                 drive->dmactl = 0;
 925                 print("disabling dma: not on a busmastering controller\n");
 926                 return -1;
 927         }
 928
 929         for(i = 0; len && i < Nprd; i++){
 930                 prd->pa = pa;
 931                 span = ROUNDUP(pa, ctlr->span);
 932                 if(span == pa)
 933                         span += ctlr->span;
 934                 count = span - pa;
 935                 if(count >= len){
 936                         prd->count = PrdEOT|len;
 937                         break;
 938                 }
 939                 prd->count = count;
 940                 len -= count;
 941                 pa += count;
 942                 prd++;
 943         }
 944         if(i == Nprd)
 945                 return -1;
 946
 947         bmiba = ctlr->bmiba;
 948         outl(bmiba+Bmidtpx, PCIWADDR(ctlr->prdt));
 949         if(drive->write)
 950                 outb(bmiba+Bmicx, 0);
 951         else
 952                 outb(bmiba+Bmicx, Rwcon);
 953         bmisx = inb(bmiba+Bmisx);
 954         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
 955
 956         return 0;
 957 }
 958
 959 static void
 960 atadmastart(Ctlr* ctlr, int write)
 961 {
 962         if(write)
 963                 outb(ctlr->bmiba+Bmicx, Ssbm);
 964         else
 965                 outb(ctlr->bmiba+Bmicx, Rwcon|Ssbm);
 966 }
 967
 968 static int
 969 atadmastop(Ctlr* ctlr)
 970 {
 971         int bmiba;
 972
 973         bmiba = ctlr->bmiba;
 974         outb(bmiba+Bmicx, inb(bmiba+Bmicx) & ~Ssbm);
 975
 976         return inb(bmiba+Bmisx);
 977 }
 978
 979 static void
 980 atadmainterrupt(Drive* drive, int count)
 981 {
 982         Ctlr* ctlr;
 983         int bmiba, bmisx;
 984
 985         ctlr = drive->ctlr;
 986         bmiba = ctlr->bmiba;
 987         bmisx = inb(bmiba+Bmisx);
 988         switch(bmisx & (Ideints|Idedmae|Bmidea)){
 989         case Bmidea:
 990                 /*
 991                  * Data transfer still in progress, nothing to do
 992                  * (this should never happen).
 993                  */
 994                 return;
 995
 996         case Ideints:
 997         case Ideints|Bmidea:
 998                 /*
 999                  * Normal termination, tidy up.
1000                  */
1001                 drive->data += count;
1002                 break;
1003
1004         default:
1005                 /*
1006                  * What's left are error conditions (memory transfer
1007                  * problem) and the device is not done but the PRD is
1008                  * exhausted. For both cases must somehow tell the
1009                  * drive to abort.
1010                  */
1011                 ataabort(drive, 0);
1012                 break;
1013         }
1014         atadmastop(ctlr);
1015         ctlr->done = 1;
1016 }
1017
1018 static void
1019 atapktinterrupt(Drive* drive)
1020 {
1021         Ctlr* ctlr;
1022         int cmdport, len;
1023
1024         ctlr = drive->ctlr;
1025         cmdport = ctlr->cmdport;
1026         switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
1027         case Cd:
1028                 outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
1029                 break;
1030
1031         case 0:
1032                 if(drive->pktdma)
1033                         goto Pktdma;
1034                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1035                 if(drive->data+len > drive->limit){
1036                         atanop(drive, 0);
1037                         break;
1038                 }
1039                 outss(cmdport+Data, drive->data, len/2);
1040                 drive->data += len;
1041                 break;
1042
1043         case Io:
1044                 if(drive->pktdma)
1045                         goto Pktdma;
1046                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1047                 if(drive->data+len > drive->limit){
1048                         atanop(drive, 0);
1049                         break;
1050                 }
1051                 inss(cmdport+Data, drive->data, len/2);
1052                 drive->data += len;
1053                 break;
1054
1055         case Io|Cd:
1056                 if(drive->pktdma){
1057         Pktdma:
1058                         atadmainterrupt(drive, drive->dlen);
1059                 } else
1060                         ctlr->done = 1;
1061                 break;
1062         }
1063 }
1064
1065 static int
1066 atapktio0(Drive *drive, SDreq *r)
1067 {
1068         uchar *cmd;
1069         int as, len, cmdport, ctlport, rv;
1070         Ctlr *ctlr;
1071
1072         rv = SDok;
1073         cmd = r->cmd;
1074         drive->command = Cpkt;
1075         memmove(drive->pktcmd, cmd, r->clen);
1076         memset(drive->pktcmd+r->clen, 0, drive->pkt-r->clen);
1077         drive->limit = drive->data+drive->dlen;
1078
1079         ctlr = drive->ctlr;
1080         cmdport = ctlr->cmdport;
1081         ctlport = ctlr->ctlport;
1082
1083         as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 107*1000);
1084         /* used to test as&Chk as failure too, but some CD readers use that for media change */
1085         if(as < 0)
1086                 return SDnostatus;
1087
1088         ilock(ctlr);
1089         if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen))
1090                 drive->pktdma = Dma;
1091         else
1092                 drive->pktdma = 0;
1093         len = drive->secsize > 0 ? 16*drive->secsize : 0x8000;
1094         outb(cmdport+Features, drive->pktdma);
1095         outb(cmdport+Count, 0);
1096         outb(cmdport+Sector, 0);
1097         outb(cmdport+Bytelo, len);
1098         outb(cmdport+Bytehi, len>>8);
1099         outb(cmdport+Dh, drive->dev);
1100         ctlr->done = 0;
1101         ctlr->curdrive = drive;
1102         ctlr->command = Cpkt;           /* debugging */
1103         outb(cmdport+Command, Cpkt);
1104
1105         microdelay(1);
1106         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 400*1000);
1107         if(as < 0 || (as & (Bsy|Chk))){
1108                 drive->status = as<0 ? 0 : as;
1109                 ctlr->curdrive = nil;
1110                 ctlr->done = 1;
1111                 rv = SDtimeout;
1112         }else
1113                 atapktinterrupt(drive);
1114         if(drive->pktdma)
1115                 atadmastart(ctlr, drive->write);
1116         iunlock(ctlr);
1117
1118         if(iowait(drive, 30*1000, 0) <= 0){
1119                 ilock(ctlr);
1120                 ataabort(drive, 0);
1121         } else
1122                 ilock(ctlr);
1123         if(drive->error){
1124                 if(drive->pktdma)
1125                         atadmastop(ctlr);
1126                 drive->status |= Chk;
1127                 ctlr->curdrive = nil;
1128         }
1129         iunlock(ctlr);
1130
1131         if(drive->status & Chk){
1132                 rv = SDcheck;
1133                 if(drive->pktdma){
1134                         print("atapktio: disabling dma\n");
1135                         drive->dmactl = 0;
1136                         rv = SDretry;
1137                 }
1138         }
1139         return rv;
1140 }
1141
1142 static int
1143 atapktio(Drive* drive, SDreq *r)
1144 {
1145         int n;
1146         Ctlr *ctlr;
1147
1148         ctlr = drive->ctlr;
1149         qlock(ctlr);
1150         n = atapktio0(drive, r);
1151         qunlock(ctlr);
1152         return n;
1153 }
1154
1155 static uchar cmd48[256] = {
1156         [Crs]   Crs48,
1157         [Crd]   Crd48,
1158         [Crsm]  Crsm48,
1159         [Cws]   Cws48,
1160         [Cwd]   Cwd48,
1161         [Cwsm]  Cwsm48,
1162 };
1163
1164 enum{
1165         Last28  = (1<<28) - 1,
1166 };
1167
1168 static int
1169 atageniostart(Drive* drive, uvlong lba)
1170 {
1171         Ctlr *ctlr;
1172         uchar cmd;
1173         int as, c, cmdport, ctlport, h, len, s, use48;
1174
1175         use48 = 0;
1176         if((drive->flags&Lba48always) || (lba+drive->count) > Last28 || drive->count > 256){
1177                 if((drive->feat & Dllba) == 0)
1178                         return -1;
1179                 use48 = 1;
1180                 c = h = s = 0;
1181         }else if(drive->dev & Lba){
1182                 c = (lba>>8) & 0xFFFF;
1183                 h = (lba>>24) & 0x0F;
1184                 s = lba & 0xFF;
1185         }else{
1186                 if (drive->s == 0 || drive->h == 0){
1187                         print("sdide: chs address botch");
1188                         return -1;
1189                 }
1190                 c = lba/(drive->s*drive->h);
1191                 h = (lba/drive->s) % drive->h;
1192                 s = (lba % drive->s) + 1;
1193         }
1194
1195         ctlr = drive->ctlr;
1196         cmdport = ctlr->cmdport;
1197         ctlport = ctlr->ctlport;
1198         if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 101*1000) < 0)
1199                 return -1;
1200
1201         ilock(ctlr);
1202         if(drive->dmactl && !atadmasetup(drive, drive->count*drive->secsize)){
1203                 if(drive->write)
1204                         drive->command = Cwd;
1205                 else
1206                         drive->command = Crd;
1207         }
1208         else if(drive->rwmctl){
1209                 drive->block = drive->rwm*drive->secsize;
1210                 if(drive->write)
1211                         drive->command = Cwsm;
1212                 else
1213                         drive->command = Crsm;
1214         }
1215         else{
1216                 drive->block = drive->secsize;
1217                 if(drive->write)
1218                         drive->command = Cws;
1219                 else
1220                         drive->command = Crs;
1221         }
1222         drive->limit = drive->data + drive->count*drive->secsize;
1223         cmd = drive->command;
1224         if(use48){
1225                 outb(cmdport+Count, drive->count>>8);
1226                 outb(cmdport+Count, drive->count);
1227                 outb(cmdport+Lbalo, lba>>24);
1228                 outb(cmdport+Lbalo, lba);
1229                 outb(cmdport+Lbamid, lba>>32);
1230                 outb(cmdport+Lbamid, lba>>8);
1231                 outb(cmdport+Lbahi, lba>>40);
1232                 outb(cmdport+Lbahi, lba>>16);
1233                 outb(cmdport+Dh, drive->dev|Lba);
1234                 cmd = cmd48[cmd];
1235
1236                 if(DEBUG & Dbg48BIT)
1237                         print("using 48-bit commands\n");
1238         }else{
1239                 outb(cmdport+Count, drive->count);
1240                 outb(cmdport+Sector, s);
1241                 outb(cmdport+Cyllo, c);
1242                 outb(cmdport+Cylhi, c>>8);
1243                 outb(cmdport+Dh, drive->dev|h);
1244         }
1245         ctlr->done = 0;
1246         ctlr->curdrive = drive;
1247         ctlr->command = drive->command; /* debugging */
1248         outb(cmdport+Command, cmd);
1249
1250         switch(drive->command){
1251         case Cws:
1252         case Cwsm:
1253                 microdelay(1);
1254                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1255                 if(as < 0 || (as & Err)){
1256                         iunlock(ctlr);
1257                         return -1;
1258                 }
1259                 len = drive->block;
1260                 if(drive->data+len > drive->limit)
1261                         len = drive->limit-drive->data;
1262                 outss(cmdport+Data, drive->data, len/2);
1263                 break;
1264
1265         case Crd:
1266         case Cwd:
1267                 atadmastart(ctlr, drive->write);
1268                 break;
1269         }
1270         iunlock(ctlr);
1271
1272         return 0;
1273 }
1274
1275 static int
1276 atagenioretry(Drive* drive, SDreq *r, uvlong lba, int count)
1277 {
1278         char *s;
1279         int rv, count0, rw;
1280         uvlong lba0;
1281
1282         if(drive->dmactl){
1283                 drive->dmactl = 0;
1284                 s = "disabling dma";
1285                 rv = SDretry;
1286         }else if(drive->rwmctl){
1287                 drive->rwmctl = 0;
1288                 s = "disabling rwm";
1289                 rv = SDretry;
1290         }else{
1291                 s = "nondma";
1292                 rv = sdsetsense(r, SDcheck, 4, 8, drive->error);
1293         }
1294         sdfakescsirw(r, &lba0, &count0, &rw);
1295         print("atagenioretry: %s %c:%llud:%d @%llud:%d\n",
1296                 s, "rw"[rw], lba0, count0, lba, count);
1297         return rv;
1298 }
1299
1300 static int
1301 atagenio(Drive* drive, SDreq *r)
1302 {
1303         Ctlr *ctlr;
1304         uvlong lba;
1305         int i, rw, count, maxio;
1306
1307         if((i = sdfakescsi(r)) != SDnostatus)
1308                 return i;
1309         if((i = sdfakescsirw(r, &lba, &count, &rw)) != SDnostatus)
1310                 return i;
1311         ctlr = drive->ctlr;
1312         if(drive->data == nil)
1313                 return SDok;
1314         if(drive->dlen < count*drive->secsize)
1315                 count = drive->dlen/drive->secsize;
1316         qlock(ctlr);
1317         if(ctlr->maxio)
1318                 maxio = ctlr->maxio;
1319         else if(drive->feat & Dllba)
1320                 maxio = 65536;
1321         else
1322                 maxio = 256;
1323         while(count){
1324                 if(count > maxio)
1325                         drive->count = maxio;
1326                 else
1327                         drive->count = count;
1328                 if(atageniostart(drive, lba)){
1329                         ilock(ctlr);
1330                         atanop(drive, 0);
1331                         iunlock(ctlr);
1332                         qunlock(ctlr);
1333                         return atagenioretry(drive, r, lba, count);
1334                 }
1335                 iowait(drive, 30*1000, 0);
1336                 if(!ctlr->done){
1337                         /*
1338                          * What should the above timeout be? In
1339                          * standby and sleep modes it could take as
1340                          * long as 30 seconds for a drive to respond.
1341                          * Very hard to get out of this cleanly.
1342                          */
1343                         atadumpstate(drive, r, lba, count);
1344                         ataabort(drive, 1);
1345                         qunlock(ctlr);
1346                         return atagenioretry(drive, r, lba, count);
1347                 }
1348
1349                 if(drive->status & Err){
1350                         qunlock(ctlr);
1351                         print("atagenio: %llud:%d\n", lba, drive->count);
1352                         return sdsetsense(r, SDcheck, 4, 8, drive->error);
1353                 }
1354                 count -= drive->count;
1355                 lba += drive->count;
1356         }
1357         qunlock(ctlr);
1358
1359         return SDok;
1360 }
1361
1362 static int
1363 atario(SDreq* r)
1364 {
1365         uchar *p;
1366         int status;
1367         Ctlr *ctlr;
1368         Drive *drive;
1369         SDunit *unit;
1370
1371         unit = r->unit;
1372         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
1373                 return r->status = SDtimeout;
1374         drive = ctlr->drive[unit->subno];
1375         qlock(drive);
1376         for(;;){
1377                 drive->write = r->write;
1378                 drive->data = r->data;
1379                 drive->dlen = r->dlen;
1380                 drive->status = 0;
1381                 drive->error = 0;
1382                 if(drive->pkt)
1383                         status = atapktio(drive, r);
1384                 else
1385                         status = atagenio(drive, r);
1386                 if(status != SDretry)
1387                         break;
1388                 if(DbgDEBUG)
1389                         print("%s: retry: dma %8.8uX rwm %4.4uX\n",
1390                                 unit->name, drive->dmactl, drive->rwmctl);
1391         }
1392         if(status == SDok && r->rlen == 0 && (r->flags & SDvalidsense) == 0){
1393                 sdsetsense(r, SDok, 0, 0, 0);
1394                 if(drive->data){
1395                         p = r->data;
1396                         r->rlen = drive->data - p;
1397                 }
1398                 else
1399                         r->rlen = 0;
1400         }
1401         qunlock(drive);
1402         return status;
1403 }
1404
1405 /**/
1406 static int
1407 isdmacmd(Drive *d, SDreq *r)
1408 {
1409         switch(r->ataproto & Pprotom){
1410         default:
1411                 return 0;
1412         case Pdmq:
1413                 error("no queued support");
1414         case Pdma:
1415                 if(!(d->dmactl || d->rwmctl))
1416                         error("dma in non dma mode\n");
1417                 return 1;
1418         }
1419 }
1420
1421 static int
1422 atagenatastart(Drive* d, SDreq *r)
1423 {
1424         uchar u;
1425         int as, cmdport, ctlport, len, pr, isdma;
1426         Ctlr *ctlr;
1427
1428         isdma = isdmacmd(d, r);
1429         ctlr = d->ctlr;
1430         cmdport = ctlr->cmdport;
1431         ctlport = ctlr->ctlport;
1432         if(ataready(cmdport, ctlport, d->dev, Bsy|Drq, d->pkt ? 0 : Drdy, 101*1000) < 0)
1433                 return -1;
1434
1435         ilock(ctlr);
1436         if(isdma && atadmasetup(d, d->block)){
1437                 iunlock(ctlr);
1438                 return -1;
1439
1440         }
1441         if(d->feat & Dllba && (r->ataproto & P28) == 0){
1442                 outb(cmdport+Features, r->cmd[Ffeat8]);
1443                 outb(cmdport+Features, r->cmd[Ffeat]);
1444                 outb(cmdport+Count, r->cmd[Fsc8]);
1445                 outb(cmdport+Count, r->cmd[Fsc]);
1446                 outb(cmdport+Lbalo, r->cmd[Flba24]);
1447                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1448                 outb(cmdport+Lbamid, r->cmd[Flba32]);
1449                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1450                 outb(cmdport+Lbahi, r->cmd[Flba40]);
1451                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1452                 u = r->cmd[Fdev] & ~0xb0;
1453                 outb(cmdport+Dh, d->dev|u);
1454         }else{
1455                 outb(cmdport+Features, r->cmd[Ffeat]);
1456                 outb(cmdport+Count, r->cmd[Fsc]);
1457                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1458                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1459                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1460                 u = r->cmd[Fdev] & ~0xb0;
1461                 outb(cmdport+Dh, d->dev|u);
1462         }
1463         ctlr->done = 0;
1464         ctlr->curdrive = d;
1465         d->command = r->ataproto & (Pprotom|Pdatam);
1466         ctlr->command = r->cmd[Fcmd];
1467         outb(cmdport+Command, r->cmd[Fcmd]);
1468
1469         pr = r->ataproto & Pprotom;
1470         if(pr == Pnd || pr == Preset)
1471                 USED(d);
1472         else if(!isdma){
1473                 microdelay(1);
1474                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1475                 if(as < 0 || (as & Err)){
1476                         iunlock(ctlr);
1477                         return -1;
1478                 }
1479                 len = d->block;
1480                 if(r->write && len > 0)
1481                         outss(cmdport+Data, d->data, len/2);
1482         }else
1483                 atadmastart(ctlr, d->write);
1484         iunlock(ctlr);
1485         return 0;
1486 }
1487
1488 static void
1489 mkrfis(Drive *d, SDreq *r)
1490 {
1491         uchar *u;
1492         int cmdport;
1493         Ctlr *ctlr;
1494
1495         ctlr = d->ctlr;
1496         cmdport = ctlr->cmdport;
1497         u = r->cmd;
1498
1499         ilock(ctlr);
1500         u[Ftype] = 0x34;
1501         u[Fioport] = 0;
1502         if((d->feat & Dllba) && (r->ataproto & P28) == 0){
1503                 u[Frerror] = inb(cmdport+Error);
1504                 u[Fsc8] = inb(cmdport+Count);
1505                 u[Fsc] = inb(cmdport+Count);
1506                 u[Flba24] = inb(cmdport+Lbalo);
1507                 u[Flba0] = inb(cmdport+Lbalo);
1508                 u[Flba32] = inb(cmdport+Lbamid);
1509                 u[Flba8] = inb(cmdport+Lbamid);
1510                 u[Flba40] = inb(cmdport+Lbahi);
1511                 u[Flba16] = inb(cmdport+Lbahi);
1512                 u[Fdev] = inb(cmdport+Dh);
1513                 u[Fstatus] = inb(cmdport+Status);
1514         }else{
1515                 u[Frerror] = inb(cmdport+Error);
1516                 u[Fsc] = inb(cmdport+Count);
1517                 u[Flba0] = inb(cmdport+Lbalo);
1518                 u[Flba8] = inb(cmdport+Lbamid);
1519                 u[Flba16] = inb(cmdport+Lbahi);
1520                 u[Fdev] = inb(cmdport+Dh);
1521                 u[Fstatus] = inb(cmdport+Status);
1522         }
1523         iunlock(ctlr);
1524 }
1525
1526 static int
1527 atarstdone(Drive *d)
1528 {
1529         int as;
1530         Ctlr *c;
1531
1532         c = d->ctlr;
1533         as = ataready(c->cmdport, c->ctlport, 0, Bsy|Drq, 0, 5*1000);
1534         c->done = as >= 0;
1535         return c->done;
1536 }
1537
1538 static uint
1539 cmdss(Drive *d, SDreq *r)
1540 {
1541         switch(r->cmd[Fcmd]){
1542         case Cid:
1543         case Cidpkt:
1544                 return 512;
1545         default:
1546                 return d->secsize;
1547         }
1548 }
1549
1550 /*
1551  * various checks.  we should be craftier and
1552  * avoid figuring out how big stuff is supposed to be.
1553  */
1554 static uint
1555 patasizeck(Drive *d, SDreq *r)
1556 {
1557         uint count, maxio, secsize;
1558         Ctlr *ctlr;
1559
1560         secsize = cmdss(d, r);          /* BOTCH */
1561         if(secsize == 0)
1562                 error(Eio);
1563         count = r->dlen / secsize;
1564         ctlr = d->ctlr;
1565         if(ctlr->maxio)
1566                 maxio = ctlr->maxio;
1567         else if((d->feat & Dllba) && (r->ataproto & P28) == 0)
1568                 maxio = 65536;
1569         else
1570                 maxio = 256;
1571         if(count > maxio){
1572                 uprint("i/o too large, lim %d", maxio);
1573                 error(up->genbuf);
1574         }
1575         if(r->ataproto&Ppio && count > 1)
1576                 error("invalid # of sectors");
1577         return count;
1578 }
1579
1580 static int
1581 atapataio(Drive *d, SDreq *r)
1582 {
1583         int rv;
1584         Ctlr *ctlr;
1585
1586         d->count = 0;
1587         if(r->ataproto & Pdatam)
1588                 d->count = patasizeck(d, r);
1589         d->block = r->dlen;
1590         d->limit = d->data + r->dlen;
1591
1592         ctlr = d->ctlr;
1593         qlock(ctlr);
1594         if(waserror()){
1595                 qunlock(ctlr);
1596                 nexterror();
1597         }
1598         rv = atagenatastart(d, r);
1599         poperror();
1600         if(rv){
1601                 if(DEBUG & DbgAtazz)
1602                         print("sdide: !atageatastart\n");
1603                 ilock(ctlr);
1604                 atanop(d, 0);
1605                 iunlock(ctlr);
1606                 qunlock(ctlr);
1607                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1608         }
1609
1610         if((r->ataproto & Pprotom) == Preset)
1611                 atarstdone(d);
1612         else
1613                 while(iowait(d, 30*1000, 1) == 0)
1614                         ;
1615         if(!ctlr->done){
1616                 if(DEBUG & DbgAtazz){
1617                         print("sdide: !done\n");
1618                         atadumpstate(d, r, 0, d->count);
1619                 }
1620                 ataabort(d, 1);
1621                 qunlock(ctlr);
1622                 return sdsetsense(r, SDcheck, 11, 0, 6);        /* aborted; i/o process terminated */
1623         }
1624         mkrfis(d, r);
1625         if(d->status & Err){
1626                 if(DEBUG & DbgAtazz)
1627                         print("sdide: status&Err\n");
1628                 qunlock(ctlr);
1629                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1630         }
1631         qunlock(ctlr);
1632         return SDok;
1633 }
1634
1635 static int
1636 ataataio0(Drive *d, SDreq *r)
1637 {
1638         int i;
1639
1640         if((r->ataproto & Pprotom) == Ppkt){
1641                 if(r->clen > d->pkt)
1642                         error(Eio);
1643                 qlock(d->ctlr);
1644                 i = atapktio0(d, r);
1645                 d->block = d->data - (uchar*)r->data;
1646                 mkrfis(d, r);
1647                 qunlock(d->ctlr);
1648                 return i;
1649         }else
1650                 return atapataio(d, r);
1651 }
1652
1653 /*
1654  * hack to allow udma mode to be set or unset
1655  * via direct ata command.  it would be better
1656  * to move the assumptions about dma mode out
1657  * of some of the helper functions.
1658  */
1659 static int
1660 isudm(SDreq *r)
1661 {
1662         uchar *c;
1663
1664         c = r->cmd;
1665         if(c[Fcmd] == 0xef && c[Ffeat] == 0x03){
1666                 if(c[Fsc]&0x40)
1667                         return 1;
1668                 return -1;
1669         }
1670         return 0;
1671 }
1672
1673 static int
1674 fisreqchk(Sfis *f, SDreq *r)
1675 {
1676         if((r->ataproto & Pprotom) == Ppkt)
1677                 return SDnostatus;
1678         /*
1679          * handle oob requests;
1680          *    restrict & sanitize commands
1681          */
1682         if(r->clen != 16)
1683                 error(Eio);
1684         if(r->cmd[0] == 0xf0){
1685                 sigtofis(f, r->cmd);
1686                 r->status = SDok;
1687                 return SDok;
1688         }
1689         r->cmd[0] = 0x27;
1690         r->cmd[1] = 0x80;
1691         r->cmd[7] |= 0xa0;
1692         return SDnostatus;
1693 }
1694
1695 static int
1696 ataataio(SDreq *r)
1697 {
1698         int status, udm;
1699         Ctlr *c;
1700         Drive *d;
1701         SDunit *u;
1702
1703         u = r->unit;
1704         if((c = u->dev->ctlr) == nil || (d = c->drive[u->subno]) == nil){
1705                 r->status = SDtimeout;
1706                 return SDtimeout;
1707         }
1708         if((status = fisreqchk(d, r)) != SDnostatus)
1709                 return status;
1710         udm = isudm(r);
1711
1712         qlock(d);
1713         if(waserror()){
1714                 qunlock(d);
1715                 nexterror();
1716         }
1717 retry:
1718         d->write = r->write;
1719         d->data = r->data;
1720         d->dlen = r->dlen;
1721         d->status = 0;
1722         d->error = 0;
1723
1724         switch(status = ataataio0(d, r)){
1725         case SDretry:
1726                 if(DbgDEBUG)
1727                         print("%s: retry: dma %.8ux rwm %.4ux\n",
1728                                 u->name, d->dmactl, d->rwmctl);
1729                 goto retry;
1730         case SDok:
1731                 if(udm == 1)
1732                         d->dmactl = d->dma;
1733                 else if(udm == -1)
1734                         d->dmactl = 0;
1735                 sdsetsense(r, SDok, 0, 0, 0);
1736                 r->rlen = d->block;
1737                 break;
1738         }
1739         poperror();
1740         qunlock(d);
1741         r->status = status;
1742         return status;
1743 }
1744 /**/
1745
1746 static void
1747 ichirqack(Ctlr *ctlr)
1748 {
1749         int bmiba;
1750
1751         if(bmiba = ctlr->bmiba)
1752                 outb(bmiba+Bmisx, inb(bmiba+Bmisx));
1753 }
1754
1755 static void
1756 atainterrupt(Ureg*, void* arg)
1757 {
1758         Ctlr *ctlr;
1759         Drive *drive;
1760         int cmdport, len, status;
1761
1762         ctlr = arg;
1763
1764         ilock(ctlr);
1765         ctlr->nrq++;
1766         if(ctlr->curdrive)
1767                 ctlr->curdrive->irq++;
1768         if(inb(ctlr->ctlport+As) & Bsy){
1769                 ctlr->bsy++;
1770                 if(ctlr->curdrive)
1771                         ctlr->curdrive->bsy++;
1772                 iunlock(ctlr);
1773                 if(DEBUG & DbgBsy)
1774                         print("IBsy+");
1775                 return;
1776         }
1777         cmdport = ctlr->cmdport;
1778         status = inb(cmdport+Status);
1779         if((drive = ctlr->curdrive) == nil){
1780                 ctlr->nildrive++;
1781                 if(ctlr->irqack != nil)
1782                         ctlr->irqack(ctlr);
1783                 iunlock(ctlr);
1784                 return;
1785         }
1786         if(status & Err)
1787                 drive->error = inb(cmdport+Error);
1788         else switch(drive->command){
1789         default:
1790                 drive->error = Abrt;
1791                 break;
1792
1793         case Crs:
1794         case Crsm:
1795         case Ppio|Pin:
1796                 if(!(status & Drq)){
1797                         drive->error = Abrt;
1798                         break;
1799                 }
1800                 len = drive->block;
1801                 if(drive->data+len > drive->limit)
1802                         len = drive->limit-drive->data;
1803                 inss(cmdport+Data, drive->data, len/2);
1804                 drive->data += len;
1805                 if(drive->data >= drive->limit)
1806                         ctlr->done = 1;
1807                 break;
1808
1809         case Cws:
1810         case Cwsm:
1811         case Ppio|Pout:
1812                 len = drive->block;
1813                 if(drive->data+len > drive->limit)
1814                         len = drive->limit-drive->data;
1815                 drive->data += len;
1816                 if(drive->data >= drive->limit){
1817                         ctlr->done = 1;
1818                         break;
1819                 }
1820                 if(!(status & Drq)){
1821                         drive->error = Abrt;
1822                         break;
1823                 }
1824                 len = drive->block;
1825                 if(drive->data+len > drive->limit)
1826                         len = drive->limit-drive->data;
1827                 outss(cmdport+Data, drive->data, len/2);
1828                 break;
1829
1830         case Cpkt:
1831         case Ppkt|Pin:
1832         case Ppkt|Pout:
1833                 atapktinterrupt(drive);
1834                 break;
1835
1836         case Crd:
1837         case Cwd:
1838         case Pdma|Pin:
1839         case Pdma|Pout:
1840                 atadmainterrupt(drive, drive->count*drive->secsize);
1841                 break;
1842
1843         case Pnd:
1844         case Preset:
1845                 ctlr->done = 1;
1846                 break;
1847         }
1848         if(ctlr->irqack != nil)
1849                 ctlr->irqack(ctlr);
1850         iunlock(ctlr);
1851
1852         if(drive->error){
1853                 status |= Err;
1854                 ctlr->done = 1;
1855         }
1856
1857         if(ctlr->done){
1858                 ctlr->curdrive = nil;
1859                 drive->status = status;
1860                 wakeup(ctlr);
1861         }
1862 }
1863
1864 typedef struct Lchan Lchan;
1865 struct Lchan {
1866         int     cmdport;
1867         int     ctlport;
1868         int     irq;
1869         int     probed;
1870 };
1871 static Lchan lchan[2] = {
1872         0x1f0,  0x3f4,  IrqATA0,        0,
1873         0x170,  0x374,  IrqATA1,        0,
1874 };
1875
1876 static int
1877 badccru(Pcidev *p)
1878 {
1879         switch(p->did<<16 | p->did){
1880         case 0x439c<<16 | 0x1002:
1881         case 0x438c<<16 | 0x1002:
1882                 print("%T: allowing bad ccru %.2ux for suspected ide controller\n",
1883                         p->tbdf, p->ccru);
1884                 return 1;
1885         default:
1886                 return 0;
1887         }
1888 }
1889
1890 static SDev*
1891 atapnp(void)
1892 {
1893         char *s;
1894         int channel, map, ispc87415, maxio, pi, r, span, maxdma, tbdf;
1895         Ctlr *ctlr;
1896         Pcidev *p;
1897         SDev *sdev, *head, *tail;
1898         void (*irqack)(Ctlr*);
1899
1900         head = tail = nil;
1901         for(p = nil; p = pcimatch(p, 0, 0); ){
1902                 /*
1903                  * Look for devices with the correct class and sub-class
1904                  * code and known device and vendor ID; add native-mode
1905                  * channels to the list to be probed, save info for the
1906                  * compatibility mode channels.
1907                  * Note that the legacy devices should not be considered
1908                  * PCI devices by the interrupt controller.
1909                  * For both native and legacy, save info for busmastering
1910                  * if capable.
1911                  * Promise Ultra ATA/66 (PDC20262) appears to
1912                  * 1) give a sub-class of 'other mass storage controller'
1913                  *    instead of 'IDE controller', regardless of whether it's
1914                  *    the only controller or not;
1915                  * 2) put 0 in the programming interface byte (probably
1916                  *    as a consequence of 1) above).
1917                  * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
1918                  */
1919                 if(p->ccrb != 0x01)
1920                         continue;
1921                 if(!badccru(p))
1922                 if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
1923                         continue;
1924                 pi = p->ccrp;
1925                 map = 3;
1926                 ispc87415 = 0;
1927                 maxdma = 0;
1928                 maxio = 0;
1929                 if(s = getconf("*idemaxio"))
1930                         maxio = atoi(s);
1931                 span = BMspan;
1932                 irqack = nil;
1933
1934                 switch((p->did<<16)|p->vid){
1935                 default:
1936                         continue;
1937
1938                 case (0x0002<<16)|0x100B:       /* NS PC87415 */
1939                         /*
1940                          * Disable interrupts on both channels until
1941                          * after they are probed for drives.
1942                          * This must be called before interrupts are
1943                          * enabled because the IRQ may be shared.
1944                          */
1945                         ispc87415 = 1;
1946                         pcicfgw32(p, 0x40, 0x00000300);
1947                         break;
1948                 case (0x1000<<16)|0x1042:       /* PC-Tech RZ1000 */
1949                         /*
1950                          * Turn off prefetch. Overkill, but cheap.
1951                          */
1952                         r = pcicfgr32(p, 0x40);
1953                         r &= ~0x2000;
1954                         pcicfgw32(p, 0x40, r);
1955                         break;
1956                 case (0x4D38<<16)|0x105A:       /* Promise PDC20262 */
1957                 case (0x4D30<<16)|0x105A:       /* Promise PDC202xx */
1958                 case (0x4D68<<16)|0x105A:       /* Promise PDC20268 */
1959                 case (0x4D69<<16)|0x105A:       /* Promise Ultra/133 TX2 */
1960                 case (0x3373<<16)|0x105A:       /* Promise 20378 RAID */
1961                 case (0x3149<<16)|0x1106:       /* VIA VT8237 SATA/RAID */
1962                 case (0x3112<<16)|0x1095:       /* SiL 3112 SATA/RAID */
1963                         maxio = 15;
1964                         span = 8*1024;
1965                         /*FALLTHROUGH*/
1966                 case (0x3114<<16)|0x1095:       /* SiL 3114 SATA/RAID */
1967                 case (0x0680<<16)|0x1095:       /* SiI 0680/680A PATA133 ATAPI/RAID */
1968                         pi = 0x85;
1969                         break;
1970                 case (0x0004<<16)|0x1103:       /* HighPoint HPT366 */
1971                         pi = 0x85;
1972                         /*
1973                          * Turn off fast interrupt prediction.
1974                          */
1975                         if((r = pcicfgr8(p, 0x51)) & 0x80)
1976                                 pcicfgw8(p, 0x51, r & ~0x80);
1977                         if((r = pcicfgr8(p, 0x55)) & 0x80)
1978                                 pcicfgw8(p, 0x55, r & ~0x80);
1979                         break;
1980                 case (0x0640<<16)|0x1095:       /* CMD 640B */
1981                         /*
1982                          * Bugfix code here...
1983                          */
1984                         break;
1985                 case (0x7441<<16)|0x1022:       /* AMD 768 */
1986                 case (0x7800<<16)|0x1022:
1987                         /*
1988                          * Set:
1989                          *      0x41    prefetch, postwrite;
1990                          *      0x43    FIFO configuration 1/2 and 1/2;
1991                          *      0x44    status register read retry;
1992                          *      0x46    DMA read and end of sector flush.
1993                          */
1994                         r = pcicfgr8(p, 0x41);
1995                         pcicfgw8(p, 0x41, r|0xF0);
1996                         r = pcicfgr8(p, 0x43);
1997                         pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
1998                         r = pcicfgr8(p, 0x44);
1999                         pcicfgw8(p, 0x44, r|0x08);
2000                         r = pcicfgr8(p, 0x46);
2001                         pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
2002                         /*FALLTHROUGH*/
2003                 case (0x01BC<<16)|0x10DE:       /* nVidia nForce1 */
2004                 case (0x0065<<16)|0x10DE:       /* nVidia nForce2 */
2005                 case (0x0085<<16)|0x10DE:       /* nVidia nForce2 MCP */
2006                 case (0x00E3<<16)|0x10DE:       /* nVidia nForce2 250 SATA */
2007                 case (0x00D5<<16)|0x10DE:       /* nVidia nForce3 */
2008                 case (0x00E5<<16)|0x10DE:       /* nVidia nForce3 Pro */
2009                 case (0x00EE<<16)|0x10DE:       /* nVidia nForce3 250 SATA */
2010                 case (0x0035<<16)|0x10DE:       /* nVidia nForce3 MCP */
2011                 case (0x0053<<16)|0x10DE:       /* nVidia nForce4 */
2012                 case (0x0054<<16)|0x10DE:       /* nVidia nForce4 SATA */
2013                 case (0x0055<<16)|0x10DE:       /* nVidia nForce4 SATA */
2014                 case (0x0266<<16)|0x10DE:       /* nVidia nForce4 430 SATA */
2015                 case (0x0265<<16)|0x10DE:       /* nVidia nForce 51 MCP */
2016                 case (0x0267<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2017                 case (0x037f<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2018                 case (0x03ec<<16)|0x10DE:       /* nVidia nForce 61 MCP SATA */
2019                 case (0x03f6<<16)|0x10DE:       /* nVidia nForce 61 MCP PATA */
2020                 case (0x0448<<16)|0x10DE:       /* nVidia nForce 65 MCP SATA */
2021                 case (0x0560<<16)|0x10DE:       /* nVidia nForce 69 MCP SATA */
2022                         /*
2023                          * Ditto, although it may have a different base
2024                          * address for the registers (0x50?).
2025                          */
2026                         /*FALLTHROUGH*/
2027                 case (0x209A<<16)|0x1022:       /* AMD CS5536 */
2028                 case (0x7401<<16)|0x1022:       /* AMD 755 Cobra */
2029                 case (0x7409<<16)|0x1022:       /* AMD 756 Viper */
2030                 case (0x7410<<16)|0x1022:       /* AMD 766 Viper Plus */
2031                 case (0x7469<<16)|0x1022:       /* AMD 3111 */
2032                 case (0x4376<<16)|0x1002:       /* SB4xx pata */
2033                 case (0x4379<<16)|0x1002:       /* SB4xx sata */
2034                 case (0x437a<<16)|0x1002:       /* SB4xx sata ctlr #2 */
2035                 case (0x437c<<16)|0x1002:       /* Rx6xx pata */
2036                 case (0x438c<<16)|0x1002:       /* ATI SB600 PATA */
2037                 case (0x439c<<16)|0x1002:       /* SB7xx pata */
2038                         break;
2039
2040                 case (0x6101<<16)|0x11ab:       /* Marvell PATA */
2041                 case (0x6121<<16)|0x11ab:       /* Marvell PATA */
2042                 case (0x6123<<16)|0x11ab:       /* Marvell PATA */
2043                 case (0x6145<<16)|0x11ab:       /* Marvell PATA */
2044                 case (0x1b4b<<16)|0x91a0:       /* Marvell PATA */
2045                 case (0x1b4b<<16)|0x91a4:       /* Marvell PATA */
2046                         break;
2047
2048                 case (0x0211<<16)|0x1166:       /* ServerWorks IB6566 */
2049                         {
2050                                 Pcidev *sb;
2051
2052                                 sb = pcimatch(nil, 0x1166, 0x0200);
2053                                 if(sb == nil)
2054                                         break;
2055                                 r = pcicfgr32(sb, 0x64);
2056                                 r &= ~0x2000;
2057                                 pcicfgw32(sb, 0x64, r);
2058                         }
2059                         span = 32*1024;
2060                         break;
2061                 case (0x5229<<16)|0x10B9:       /* ALi M1543 */
2062                 case (0x5288<<16)|0x10B9:       /* ALi M5288 SATA */
2063                         /*FALLTHROUGH*/
2064                 case (0x5513<<16)|0x1039:       /* SiS 962 */
2065                 case (0x0646<<16)|0x1095:       /* CMD 646 */
2066                 case (0x0571<<16)|0x1106:       /* VIA 82C686 */
2067                 case (0x9001<<16)|0x1106:       /* VIA chipset in VIA PV530 */
2068                 case (0x0502<<16)|0x100b:       /* National Semiconductor SC1100/SCx200 */
2069                         break;
2070                 case (0x2360<<16)|0x197b:       /* jmicron jmb360 */
2071                 case (0x2361<<16)|0x197b:       /* jmicron jmb361 */
2072                 case (0x2363<<16)|0x197b:       /* jmicron jmb363 */
2073                 case (0x2365<<16)|0x197b:       /* jmicron jmb365 */
2074                 case (0x2366<<16)|0x197b:       /* jmicron jmb366 */
2075                 case (0x2368<<16)|0x197b:       /* jmicron jmb368 */
2076                         break;
2077                 case (0x7010<<16)|0x8086:       /* 82371SB (PIIX3) */
2078                 case (0x1230<<16)|0x8086:       /* 82371FB (PIIX) */
2079                 case (0x7111<<16)|0x8086:       /* 82371[AE]B (PIIX4[E]) */
2080                         maxdma = 0x20000;
2081                         break;
2082                 case (0x2411<<16)|0x8086:       /* 82801AA (ICH) */
2083                 case (0x2421<<16)|0x8086:       /* 82801AB (ICH0) */
2084                 case (0x244A<<16)|0x8086:       /* 82801BA (ICH2, Mobile) */
2085                 case (0x244B<<16)|0x8086:       /* 82801BA (ICH2, High-End) */
2086                 case (0x248A<<16)|0x8086:       /* 82801CA (ICH3, Mobile) */
2087                 case (0x248B<<16)|0x8086:       /* 82801CA (ICH3, High-End) */
2088                 case (0x24CA<<16)|0x8086:       /* 82801DBM (ICH4, Mobile) */
2089                 case (0x24CB<<16)|0x8086:       /* 82801DB (ICH4, High-End) */
2090                 case (0x24D1<<16)|0x8086:       /* 82801er (ich5) */
2091                 case (0x24DB<<16)|0x8086:       /* 82801EB (ICH5) */
2092                 case (0x25A2<<16)|0x8086:       /* 6300ESB pata */
2093                 case (0x25A3<<16)|0x8086:       /* 6300ESB (E7210) */
2094                 case (0x266F<<16)|0x8086:       /* 82801FB (ICH6) */
2095                 case (0x2651<<16)|0x8086:       /* 82801FB (ICH6) */
2096                 case (0x2653<<16)|0x8086:       /* 82801FBM (ICH6, Mobile) */
2097                 case (0x269e<<16)|0x8086:       /* 63xxESB (intel 5000) */
2098                 case (0x27DF<<16)|0x8086:       /* 82801G PATA (ICH7) */
2099                 case (0x27C0<<16)|0x8086:       /* 82801GB SATA (ICH7) */
2100                 case (0x27C4<<16)|0x8086:       /* 82801GBM SATA (ICH7) */
2101                 case (0x27C5<<16)|0x8086:       /* 82801GBM SATA AHCI (ICH7) */
2102                 case (0x2850<<16)|0x8086:       /* 82801HBM/HEM PATA */
2103                 case (0x2820<<16)|0x8086:       /* 82801HB/HR/HH/HO SATA IDE */
2104                 case (0x2828<<16)|0x8086:       /* 82801HBM SATA (ICH8-M) */
2105                 case (0x2829<<16)|0x8086:       /* 82801HBM SATA AHCI (ICH8-M) */
2106                 case (0x2920<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-3 */
2107                 case (0x2921<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-1 */
2108                 case (0x2926<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 4-5 */
2109                 case (0x2928<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1 */
2110                 case (0x2929<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1, 4-5 */
2111                 case (0x292d<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 4-5*/
2112                 case (0x3a20<<16)|0x8086:       /* 82801ji (ich10) */
2113                 case (0x3a26<<16)|0x8086:       /* 82801ji (ich10) */
2114                 case (0x3b20<<16)|0x8086:       /* 34x0 (pch) port 0-3 */
2115                 case (0x3b21<<16)|0x8086:       /* 34x0 (pch) port 4-5 */
2116                 case (0x3b28<<16)|0x8086:       /* 34x0pm (pch) port 0-1, 4-5 */
2117                 case (0x3b2e<<16)|0x8086:       /* 34x0pm (pch) port 0-3 */
2118                         map = 0;
2119                         if(pcicfgr16(p, 0x40) & 0x8000)
2120                                 map |= 1;
2121                         if(pcicfgr16(p, 0x42) & 0x8000)
2122                                 map |= 2;
2123                         irqack = ichirqack;
2124                         break;
2125                 case (0x811a<<16)|0x8086:       /* Intel SCH (Poulsbo) */
2126                         map = 1;
2127                         irqack = ichirqack;
2128                         break;
2129                 }
2130                 for(channel = 0; channel < 2; channel++){
2131                         if((map & 1<<channel) == 0)
2132                                 continue;
2133                         if(pi & 1<<2*channel){
2134                                 sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
2135                                                 p->mem[1+2*channel].bar & ~0x01,
2136                                                 p->intl, 3);
2137                                 tbdf = p->tbdf;
2138                         }
2139                         else if(lchan[channel].probed == 0){
2140                                 sdev = ataprobe(lchan[channel].cmdport,
2141                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2142                                 lchan[channel].probed = 1;
2143                                 tbdf = BUSUNKNOWN;
2144                         }
2145                         else
2146                                 continue;
2147                         if(sdev == nil)
2148                                 continue;
2149                         ctlr = sdev->ctlr;
2150                         if(ispc87415) {
2151                                 ctlr->ienable = pc87415ienable;
2152                                 print("pc87415disable: not yet implemented\n");
2153                         }
2154                         ctlr->tbdf = tbdf;
2155                         ctlr->pcidev = p;
2156                         ctlr->maxio = maxio;
2157                         ctlr->maxdma = maxdma;
2158                         ctlr->span = span;
2159                         ctlr->irqack = irqack;
2160                         if((pi & 0x80) && (p->mem[4].bar & 0x01))
2161                                 ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
2162                         if(head != nil)
2163                                 tail->next = sdev;
2164                         else
2165                                 head = sdev;
2166                         tail = sdev;
2167                 }
2168         }
2169
2170         if(lchan[0].probed + lchan[1].probed == 0)
2171                 for(channel = 0; channel < 2; channel++){
2172                         sdev = nil;
2173                         if(lchan[channel].probed == 0){
2174         //                      print("sdide: blind probe %.3ux\n", lchan[channel].cmdport);
2175                                 sdev = ataprobe(lchan[channel].cmdport,
2176                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2177                                 lchan[channel].probed = 1;
2178                         }
2179                         if(sdev == nil)
2180                                 continue;
2181                         if(head != nil)
2182                                 tail->next = sdev;
2183                         else
2184                                 head = sdev;
2185                         tail = sdev;
2186                 }
2187
2188 if(0){
2189         int port;
2190         ISAConf isa;
2191
2192         /*
2193          * Hack for PCMCIA drives.
2194          * This will be tidied once we figure out how the whole
2195          * removeable device thing is going to work.
2196          */
2197         memset(&isa, 0, sizeof(isa));
2198         isa.port = 0x180;               /* change this for your machine */
2199         isa.irq = 11;                   /* change this for your machine */
2200
2201         port = isa.port+0x0C;
2202         channel = pcmspecial("MK2001MPL", &isa);
2203         if(channel == -1)
2204                 channel = pcmspecial("SunDisk", &isa);
2205         if(channel == -1){
2206                 isa.irq = 10;
2207                 channel = pcmspecial("CF", &isa);
2208         }
2209         if(channel == -1){
2210                 isa.irq = 10;
2211                 channel = pcmspecial("OLYMPUS", &isa);
2212         }
2213         if(channel == -1){
2214                 port = isa.port+0x204;
2215                 channel = pcmspecial("ATA/ATAPI", &isa);
2216         }
2217         if(channel >= 0 && (sdev = ataprobe(isa.port, port, isa.irq, 3)) != nil){
2218                 if(head != nil)
2219                         tail->next = sdev;
2220                 else
2221                         head = sdev;
2222         }
2223 }
2224         return head;
2225 }
2226
2227 static void
2228 atadmaclr(Ctlr *ctlr)
2229 {
2230         int bmiba, bmisx;
2231
2232         if(ctlr->curdrive)
2233                 ataabort(ctlr->curdrive, 1);
2234         bmiba = ctlr->bmiba;
2235         if(bmiba == 0)
2236                 return;
2237         atadmastop(ctlr);
2238         outl(bmiba+Bmidtpx, 0);
2239         bmisx = inb(bmiba+Bmisx) & ~Bmidea;
2240         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
2241 //      pciintst(ctlr->pcidev);
2242 }
2243
2244 static int
2245 ataenable(SDev* sdev)
2246 {
2247         Ctlr *ctlr;
2248         char name[32];
2249
2250         ctlr = sdev->ctlr;
2251         if(ctlr->bmiba){
2252                 atadmaclr(ctlr);
2253                 if(ctlr->pcidev != nil)
2254                         pcisetbme(ctlr->pcidev);
2255                 /* Intel SCH requires 8 byte alignment, though datasheet says 4 m( */
2256                 ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 8, 0, 64*1024);
2257         }
2258         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2259         intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2260         outb(ctlr->ctlport+Dc, 0);
2261         if(ctlr->ienable)
2262                 ctlr->ienable(ctlr);
2263         return 1;
2264 }
2265
2266 static int
2267 atadisable(SDev *sdev)
2268 {
2269         Ctlr *ctlr;
2270         char name[32];
2271
2272         ctlr = sdev->ctlr;
2273         outb(ctlr->ctlport+Dc, Nien);           /* disable interrupts */
2274         if (ctlr->idisable)
2275                 ctlr->idisable(ctlr);
2276         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2277         intrdisable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2278         if(ctlr->bmiba) {
2279 //              atadmaclr(ctlr);
2280                 if (ctlr->pcidev)
2281                         pciclrbme(ctlr->pcidev);
2282                 free(ctlr->prdt);
2283                 ctlr->prdt = nil;
2284         }
2285         return 0;
2286 }
2287
2288 static int
2289 ataonline(SDunit *unit)
2290 {
2291         Drive *drive;
2292         Ctlr *ctlr;
2293         int ret;
2294
2295         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2296                 return 0;
2297         ret = 1;
2298         drive = ctlr->drive[unit->subno];
2299         if((drive->flags & Online) == 0){
2300                 drive->flags |= Online;
2301                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2302                 ret = 2;
2303         }
2304         if(drive->feat & Datapi){
2305                 ulong dma;
2306
2307                 dma = drive->dmactl;
2308                 drive->dmactl = 0;
2309                 ret = scsionline(unit);
2310                 drive->dmactl = dma;
2311         } else {
2312                 unit->sectors = drive->sectors;
2313                 unit->secsize = drive->secsize;
2314         }
2315         return ret;
2316 }
2317
2318 static int
2319 atarctl(SDunit* unit, char* p, int l)
2320 {
2321         Ctlr *ctlr;
2322         Drive *drive;
2323         char *e, *op;
2324
2325         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2326                 return 0;
2327         drive = ctlr->drive[unit->subno];
2328
2329         e = p+l;
2330         op = p;
2331         qlock(drive);
2332         p = seprint(p, e, "config %4.4uX capabilities %4.4uX", drive->info[Iconfig], drive->info[Icapabilities]);
2333         if(drive->dma)
2334                 p = seprint(p, e, " dma %8.8uX dmactl %8.8uX", drive->dma, drive->dmactl);
2335         if(drive->rwm)
2336                 p = seprint(p, e, " rwm %ud rwmctl %ud", drive->rwm, drive->rwmctl);
2337         if(drive->feat & Dllba)
2338                 p = seprint(p, e, " lba48always %s", (drive->flags&Lba48always) ? "on" : "off");
2339         p = seprint(p, e, "\n");
2340         p = seprint(p, e, "model        %s\n", drive->model);
2341         p = seprint(p, e, "serial       %s\n", drive->serial);
2342         p = seprint(p, e, "firm %s\n", drive->firmware);
2343         p = seprint(p, e, "feat ");
2344         p = pflag(p, e, drive);
2345         if(drive->sectors){
2346                 p = seprint(p, e, "geometry %llud %d", drive->sectors, drive->secsize);
2347                 if(drive->pkt == 0 && (drive->feat & Dlba) == 0)
2348                         p = seprint(p, e, " %d %d %d", drive->c, drive->h, drive->s);
2349                 p = seprint(p, e, "\n");
2350                 p = seprint(p, e, "alignment %d %d\n",
2351                         drive->secsize<<drive->physshift, drive->physalign);
2352         }
2353         p = seprint(p, e, "missirq      %ud\n", drive->missirq);
2354         p = seprint(p, e, "sloop        %ud\n", drive->spurloop);
2355         p = seprint(p, e, "irq  %ud %ud\n", ctlr->nrq, drive->irq);
2356         p = seprint(p, e, "bsy  %ud %ud\n", ctlr->bsy, drive->bsy);
2357         p = seprint(p, e, "nildrive     %ud\n", ctlr->nildrive);
2358         qunlock(drive);
2359
2360         return p - op;
2361 }
2362
2363 static int
2364 atawctl(SDunit* unit, Cmdbuf* cb)
2365 {
2366         Ctlr *ctlr;
2367         Drive *drive;
2368
2369         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2370                 return 0;
2371         drive = ctlr->drive[unit->subno];
2372
2373         qlock(drive);
2374         if(waserror()){
2375                 qunlock(drive);
2376                 nexterror();
2377         }
2378
2379         /*
2380          * Dma and rwm control is passive at the moment,
2381          * i.e. it is assumed that the hardware is set up
2382          * correctly already either by the BIOS or when
2383          * the drive was initially identified.
2384          */
2385         if(strcmp(cb->f[0], "dma") == 0){
2386                 if(cb->nf != 2 || drive->dma == 0)
2387                         error(Ebadctl);
2388                 if(strcmp(cb->f[1], "on") == 0)
2389                         drive->dmactl = drive->dma;
2390                 else if(strcmp(cb->f[1], "off") == 0)
2391                         drive->dmactl = 0;
2392                 else
2393                         error(Ebadctl);
2394         }
2395         else if(strcmp(cb->f[0], "rwm") == 0){
2396                 if(cb->nf != 2 || drive->rwm == 0)
2397                         error(Ebadctl);
2398                 if(strcmp(cb->f[1], "on") == 0)
2399                         drive->rwmctl = drive->rwm;
2400                 else if(strcmp(cb->f[1], "off") == 0)
2401                         drive->rwmctl = 0;
2402                 else
2403                         error(Ebadctl);
2404         }
2405         else if(strcmp(cb->f[0], "lba48always") == 0){
2406                 if(cb->nf != 2 || !(drive->feat & Dllba))
2407                         error(Ebadctl);
2408                 if(strcmp(cb->f[1], "on") == 0)
2409                         drive->flags |= Lba48always;
2410                 else if(strcmp(cb->f[1], "off") == 0)
2411                         drive->flags &= ~Lba48always;
2412                 else
2413                         error(Ebadctl);
2414         }
2415         else if(strcmp(cb->f[0], "identify") == 0){
2416                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2417         }
2418         else
2419                 error(Ebadctl);
2420         qunlock(drive);
2421         poperror();
2422
2423         return 0;
2424 }
2425
2426 SDifc sdideifc = {
2427         "ide",                          /* name */
2428
2429         atapnp,                         /* pnp */
2430         nil,                            /* legacy */
2431         ataenable,                      /* enable */
2432         atadisable,                     /* disable */
2433
2434         scsiverify,                     /* verify */
2435         ataonline,                      /* online */
2436         atario,                         /* rio */
2437         atarctl,                        /* rctl */
2438         atawctl,                        /* wctl */
2439
2440         scsibio,                        /* bio */
2441         ataprobew,                      /* probe */
2442         ataclear,                       /* clear */
2443         atastat,                        /* rtopctl */
2444         nil,                            /* wtopctl */
2445         ataataio,
2446 };