sys/src/9/pc/sdide.c

   1 #include "u.h"
   2 #include "../port/lib.h"
   3 #include "mem.h"
   4 #include "dat.h"
   5 #include "fns.h"
   6 #include "io.h"
   7 #include "ureg.h"
   8 #include "../port/error.h"
   9
  10 #include "../port/sd.h"
  11 #include <fis.h>
  12
  13 #define HOWMANY(x, y)   (((x)+((y)-1))/(y))
  14 #define ROUNDUP(x, y)   (HOWMANY((x), (y))*(y))
  15 #define uprint(...)     snprint(up->genbuf, sizeof up->genbuf, __VA_ARGS__);
  16 #pragma varargck        argpos  atadebug                3
  17
  18 extern SDifc sdideifc;
  19
  20 enum {
  21         DbgCONFIG       = 0x0001,       /* detected drive config info */
  22         DbgIDENTIFY     = 0x0002,       /* detected drive identify info */
  23         DbgSTATE        = 0x0004,       /* dump state on panic */
  24         DbgPROBE        = 0x0008,       /* trace device probing */
  25         DbgDEBUG        = 0x0080,       /* the current problem... */
  26         DbgINL          = 0x0100,       /* That Inil20+ message we hate */
  27         Dbg48BIT        = 0x0200,       /* 48-bit LBA */
  28         DbgBsy          = 0x0400,       /* interrupt but Bsy (shared IRQ) */
  29         DbgAtazz        = 0x0800,       /* debug raw ata io */
  30 };
  31 #define DEBUG           (DbgDEBUG|DbgSTATE)
  32
  33 enum {                                  /* I/O ports */
  34         Data            = 0,
  35         Error           = 1,            /* (read) */
  36         Features        = 1,            /* (write) */
  37         Count           = 2,            /* sector count<7-0>, sector count<15-8> */
  38         Ir              = 2,            /* interrupt reason (PACKET) */
  39         Sector          = 3,            /* sector number */
  40         Lbalo           = 3,            /* LBA<7-0>, LBA<31-24> */
  41         Cyllo           = 4,            /* cylinder low */
  42         Bytelo          = 4,            /* byte count low (PACKET) */
  43         Lbamid          = 4,            /* LBA<15-8>, LBA<39-32> */
  44         Cylhi           = 5,            /* cylinder high */
  45         Bytehi          = 5,            /* byte count hi (PACKET) */
  46         Lbahi           = 5,            /* LBA<23-16>, LBA<47-40> */
  47         Dh              = 6,            /* Device/Head, LBA<27-24> */
  48         Status          = 7,            /* (read) */
  49         Command         = 7,            /* (write) */
  50
  51         As              = 2,            /* Alternate Status (read) */
  52         Dc              = 2,            /* Device Control (write) */
  53 };
  54
  55 enum {                                  /* Error */
  56         Med             = 0x01,         /* Media error */
  57         Ili             = 0x01,         /* command set specific (PACKET) */
  58         Nm              = 0x02,         /* No Media */
  59         Eom             = 0x02,         /* command set specific (PACKET) */
  60         Abrt            = 0x04,         /* Aborted command */
  61         Mcr             = 0x08,         /* Media Change Request */
  62         Idnf            = 0x10,         /* no user-accessible address */
  63         Mc              = 0x20,         /* Media Change */
  64         Unc             = 0x40,         /* Uncorrectable data error */
  65         Wp              = 0x40,         /* Write Protect */
  66         Icrc            = 0x80,         /* Interface CRC error */
  67 };
  68
  69 enum {                                  /* Features */
  70         Dma             = 0x01,         /* data transfer via DMA (PACKET) */
  71         Ovl             = 0x02,         /* command overlapped (PACKET) */
  72 };
  73
  74 enum {                                  /* Interrupt Reason */
  75         Cd              = 0x01,         /* Command/Data */
  76         Io              = 0x02,         /* I/O direction */
  77         Rel             = 0x04,         /* Bus Release */
  78 };
  79
  80 enum {                                  /* Device/Head */
  81         Dev0            = 0xA0,         /* Master */
  82         Dev1            = 0xB0,         /* Slave */
  83         Devs            = Dev0 | Dev1,
  84         Lba             = 0x40,         /* LBA mode */
  85 };
  86
  87 enum {                                  /* Status, Alternate Status */
  88         Err             = 0x01,         /* Error */
  89         Chk             = 0x01,         /* Check error (PACKET) */
  90         Drq             = 0x08,         /* Data Request */
  91         Dsc             = 0x10,         /* Device Seek Complete */
  92         Serv            = 0x10,         /* Service */
  93         Df              = 0x20,         /* Device Fault */
  94         Dmrd            = 0x20,         /* DMA ready (PACKET) */
  95         Drdy            = 0x40,         /* Device Ready */
  96         Bsy             = 0x80,         /* Busy */
  97 };
  98
  99 enum {                                  /* Command */
 100         Cnop            = 0x00,         /* NOP */
 101         Crs             = 0x20,         /* Read Sectors */
 102         Crs48           = 0x24,         /* Read Sectors Ext */
 103         Crd48           = 0x25,         /* Read w/ DMA Ext */
 104         Crsm48          = 0x29,         /* Read Multiple Ext */
 105         Cws             = 0x30,         /* Write Sectors */
 106         Cws48           = 0x34,         /* Write Sectors Ext */
 107         Cwd48           = 0x35,         /* Write w/ DMA Ext */
 108         Cwsm48          = 0x39,         /* Write Multiple Ext */
 109         Cedd            = 0x90,         /* Execute Device Diagnostics */
 110         Cpkt            = 0xA0,         /* Packet */
 111         Cidpkt          = 0xA1,         /* Identify Packet Device */
 112         Crsm            = 0xC4,         /* Read Multiple */
 113         Cwsm            = 0xC5,         /* Write Multiple */
 114         Csm             = 0xC6,         /* Set Multiple */
 115         Crd             = 0xC8,         /* Read DMA */
 116         Cwd             = 0xCA,         /* Write DMA */
 117         Cid             = 0xEC,         /* Identify Device */
 118 };
 119
 120 enum {                                  /* Device Control */
 121         Nien            = 0x02,         /* (not) Interrupt Enable */
 122         Srst            = 0x04,         /* Software Reset */
 123         Hob             = 0x80,         /* High Order Bit [sic] */
 124 };
 125
 126 enum {                                  /* PCI Configuration Registers */
 127         Bmiba           = 0x20,         /* Bus Master Interface Base Address */
 128         Idetim          = 0x40,         /* IE Timing */
 129         Sidetim         = 0x44,         /* Slave IE Timing */
 130         Udmactl         = 0x48,         /* Ultra DMA/33 Control */
 131         Udmatim         = 0x4A,         /* Ultra DMA/33 Timing */
 132 };
 133
 134 enum {                                  /* Bus Master IDE I/O Ports */
 135         Bmicx           = 0,            /* Command */
 136         Bmisx           = 2,            /* Status */
 137         Bmidtpx         = 4,            /* Descriptor Table Pointer */
 138 };
 139
 140 enum {                                  /* Bmicx */
 141         Ssbm            = 0x01,         /* Start/Stop Bus Master */
 142         Rwcon           = 0x08,         /* Read/Write Control */
 143 };
 144
 145 enum {                                  /* Bmisx */
 146         Bmidea          = 0x01,         /* Bus Master IDE Active */
 147         Idedmae         = 0x02,         /* IDE DMA Error  (R/WC) */
 148         Ideints         = 0x04,         /* IDE Interrupt Status (R/WC) */
 149         Dma0cap         = 0x20,         /* Drive 0 DMA Capable */
 150         Dma1cap         = 0x40,         /* Drive 0 DMA Capable */
 151 };
 152 enum {                                  /* Physical Region Descriptor */
 153         PrdEOT          = 0x80000000,   /* End of Transfer */
 154 };
 155
 156 enum {                                  /* offsets into the identify info. */
 157         Iconfig         = 0,            /* general configuration */
 158         Ilcyl           = 1,            /* logical cylinders */
 159         Ilhead          = 3,            /* logical heads */
 160         Ilsec           = 6,            /* logical sectors per logical track */
 161         Iserial         = 10,           /* serial number */
 162         Ifirmware       = 23,           /* firmware revision */
 163         Imodel          = 27,           /* model number */
 164         Imaxrwm         = 47,           /* max. read/write multiple sectors */
 165         Icapabilities   = 49,           /* capabilities */
 166         Istandby        = 50,           /* device specific standby timer */
 167         Ipiomode        = 51,           /* PIO data transfer mode number */
 168         Ivalid          = 53,
 169         Iccyl           = 54,           /* cylinders if (valid&0x01) */
 170         Ichead          = 55,           /* heads if (valid&0x01) */
 171         Icsec           = 56,           /* sectors if (valid&0x01) */
 172         Iccap           = 57,           /* capacity if (valid&0x01) */
 173         Irwm            = 59,           /* read/write multiple */
 174         Ilba            = 60,           /* LBA size */
 175         Imwdma          = 63,           /* multiword DMA mode */
 176         Iapiomode       = 64,           /* advanced PIO modes supported */
 177         Iminmwdma       = 65,           /* min. multiword DMA cycle time */
 178         Irecmwdma       = 66,           /* rec. multiword DMA cycle time */
 179         Iminpio         = 67,           /* min. PIO cycle w/o flow control */
 180         Iminiordy       = 68,           /* min. PIO cycle with IORDY */
 181         Ipcktbr         = 71,           /* time from PACKET to bus release */
 182         Iserbsy         = 72,           /* time from SERVICE to !Bsy */
 183         Iqdepth         = 75,           /* max. queue depth */
 184         Imajor          = 80,           /* major version number */
 185         Iminor          = 81,           /* minor version number */
 186         Icsfs           = 82,           /* command set/feature supported */
 187         Icsfe           = 85,           /* command set/feature enabled */
 188         Iudma           = 88,           /* ultra DMA mode */
 189         Ierase          = 89,           /* time for security erase */
 190         Ieerase         = 90,           /* time for enhanced security erase */
 191         Ipower          = 91,           /* current advanced power management */
 192         Ilba48          = 100,          /* 48-bit LBA size (64 bits in 100-103) */
 193         Irmsn           = 127,          /* removable status notification */
 194         Isecstat        = 128,          /* security status */
 195         Icfapwr         = 160,          /* CFA power mode */
 196         Imediaserial    = 176,          /* current media serial number */
 197         Icksum          = 255,          /* checksum */
 198 };
 199
 200 enum {                                  /* bit masks for config identify info */
 201         Mpktsz          = 0x0003,       /* packet command size */
 202         Mincomplete     = 0x0004,       /* incomplete information */
 203         Mdrq            = 0x0060,       /* DRQ type */
 204         Mrmdev          = 0x0080,       /* device is removable */
 205         Mtype           = 0x1F00,       /* device type */
 206         Mproto          = 0x8000,       /* command protocol */
 207 };
 208
 209 enum {                                  /* bit masks for capabilities identify info */
 210         Mdma            = 0x0100,       /* DMA supported */
 211         Mlba            = 0x0200,       /* LBA supported */
 212         Mnoiordy        = 0x0400,       /* IORDY may be disabled */
 213         Miordy          = 0x0800,       /* IORDY supported */
 214         Msoftrst        = 0x1000,       /* needs soft reset when Bsy */
 215         Mqueueing       = 0x4000,       /* queueing overlap supported */
 216         Midma           = 0x8000,       /* interleaved DMA supported */
 217 };
 218
 219 enum {                                  /* bit masks for supported/enabled features */
 220         Msmart          = 0x0001,
 221         Msecurity       = 0x0002,
 222         Mrmmedia        = 0x0004,
 223         Mpwrmgmt        = 0x0008,
 224         Mpkt            = 0x0010,
 225         Mwcache         = 0x0020,
 226         Mlookahead      = 0x0040,
 227         Mrelirq         = 0x0080,
 228         Msvcirq         = 0x0100,
 229         Mreset          = 0x0200,
 230         Mprotected      = 0x0400,
 231         Mwbuf           = 0x1000,
 232         Mrbuf           = 0x2000,
 233         Mnop            = 0x4000,
 234         Mmicrocode      = 0x0001,
 235         Mqueued         = 0x0002,
 236         Mcfa            = 0x0004,
 237         Mapm            = 0x0008,
 238         Mnotify         = 0x0010,
 239         Mspinup         = 0x0040,
 240         Mmaxsec         = 0x0100,
 241         Mautoacoustic   = 0x0200,
 242         Maddr48         = 0x0400,
 243         Mdevconfov      = 0x0800,
 244         Mflush          = 0x1000,
 245         Mflush48        = 0x2000,
 246         Msmarterror     = 0x0001,
 247         Msmartselftest  = 0x0002,
 248         Mmserial        = 0x0004,
 249         Mmpassthru      = 0x0008,
 250         Mlogging        = 0x0020,
 251 };
 252
 253 typedef struct Ctlr Ctlr;
 254 typedef struct Drive Drive;
 255
 256 typedef struct Prd {                    /* Physical Region Descriptor */
 257         ulong   pa;                     /* Physical Base Address */
 258         int     count;
 259 } Prd;
 260
 261 enum {
 262         BMspan          = 32*1024,      /* must be power of 2 <= 64*1024 */
 263
 264         Nprd            = SDmaxio/BMspan+2,
 265 };
 266
 267 typedef struct Ctlr {
 268         int     cmdport;
 269         int     ctlport;
 270         int     irq;
 271         int     tbdf;
 272         int     bmiba;                  /* bus master interface base address */
 273         int     maxio;                  /* sector count transfer maximum */
 274         int     span;                   /* don't span this boundary with dma */
 275         int     maxdma;                 /* don't attempt dma transfers bigger than this */
 276
 277         Pcidev* pcidev;
 278         void    (*ienable)(Ctlr*);
 279         void    (*idisable)(Ctlr*);
 280         SDev*   sdev;
 281
 282         Drive*  drive[2];
 283
 284         Prd*    prdt;                   /* physical region descriptor table */
 285         void    (*irqack)(Ctlr*);
 286
 287         QLock;                          /* current command */
 288         Drive*  curdrive;
 289         int     command;                /* last command issued (debugging) */
 290         Rendez;
 291         int     done;
 292         uint    nrq;
 293         uint    nildrive;
 294         uint    bsy;
 295
 296         Lock;                           /* register access */
 297 } Ctlr;
 298
 299 typedef struct Drive {
 300         Ctlr*   ctlr;
 301         SDunit  *unit;
 302
 303         int     dev;
 304         ushort  info[256];
 305         Sfis;
 306
 307         int     dma;                    /* DMA R/W possible */
 308         int     dmactl;
 309         int     rwm;                    /* read/write multiple possible */
 310         int     rwmctl;
 311
 312         int     pkt;                    /* PACKET device, length of pktcmd */
 313         uchar   pktcmd[16];
 314         int     pktdma;                 /* this PACKET command using dma */
 315
 316         uvlong  sectors;
 317         uint    secsize;
 318         char    serial[20+1];
 319         char    firmware[8+1];
 320         char    model[40+1];
 321
 322         QLock;                          /* drive access */
 323         int     command;                /* current command */
 324         int     write;
 325         uchar*  data;
 326         int     dlen;
 327         uchar*  limit;
 328         int     count;                  /* sectors */
 329         int     block;                  /* R/W bytes per block */
 330         int     status;
 331         int     error;
 332         int     flags;                  /* internal flags */
 333         uint    missirq;
 334         uint    spurloop;
 335         uint    irq;
 336         uint    bsy;
 337 } Drive;
 338
 339 enum {                                  /* internal flags */
 340         Lba48always     = 0x2,          /* ... */
 341         Online          = 0x4,          /* drive onlined */
 342 };
 343
 344 static void
 345 pc87415ienable(Ctlr* ctlr)
 346 {
 347         Pcidev *p;
 348         int x;
 349
 350         p = ctlr->pcidev;
 351         if(p == nil)
 352                 return;
 353
 354         x = pcicfgr32(p, 0x40);
 355         if(ctlr->cmdport == p->mem[0].bar)
 356                 x &= ~0x00000100;
 357         else
 358                 x &= ~0x00000200;
 359         pcicfgw32(p, 0x40, x);
 360 }
 361
 362 static void
 363 atadumpstate(Drive* drive, SDreq *r, uvlong lba, int count)
 364 {
 365         Prd *prd;
 366         Pcidev *p;
 367         Ctlr *ctlr;
 368         int i, bmiba, ccnt;
 369         uvlong clba;
 370
 371         if(!(DEBUG & DbgSTATE))
 372                 return;
 373
 374         ctlr = drive->ctlr;
 375         print("command %2.2uX\n", ctlr->command);
 376         print("data %8.8p limit %8.8p dlen %d status %uX error %uX\n",
 377                 drive->data, drive->limit, drive->dlen,
 378                 drive->status, drive->error);
 379         if(r->clen == -16)
 380                 clba = fisrw(nil, r->cmd, &ccnt);
 381         else
 382                 sdfakescsirw(r, &clba, &ccnt, 0);
 383         print("lba %llud -> %llud, count %d -> %d (%d)\n",
 384                 clba, lba, ccnt, count, drive->count);
 385         if(!(inb(ctlr->ctlport+As) & Bsy)){
 386                 for(i = 1; i < 7; i++)
 387                         print(" 0x%2.2uX", inb(ctlr->cmdport+i));
 388                 print(" 0x%2.2uX\n", inb(ctlr->ctlport+As));
 389         }
 390         if(drive->command == Cwd || drive->command == Crd
 391         || drive->command == (Pdma|Pin) || drive->command == (Pdma|Pout)){
 392                 bmiba = ctlr->bmiba;
 393                 prd = ctlr->prdt;
 394                 print("bmicx %2.2uX bmisx %2.2uX prdt %8.8p\n",
 395                         inb(bmiba+Bmicx), inb(bmiba+Bmisx), prd);
 396                 while(prd){
 397                         print("pa 0x%8.8luX count %8.8uX\n",
 398                                 prd->pa, prd->count);
 399                         if(prd->count & PrdEOT)
 400                                 break;
 401                         prd++;
 402                 }
 403         }
 404         if(ctlr->pcidev && ctlr->pcidev->vid == 0x8086){
 405                 p = ctlr->pcidev;
 406                 print("0x40: %4.4uX 0x42: %4.4uX ",
 407                         pcicfgr16(p, 0x40), pcicfgr16(p, 0x42));
 408                 print("0x48: %2.2uX\n", pcicfgr8(p, 0x48));
 409                 print("0x4A: %4.4uX\n", pcicfgr16(p, 0x4A));
 410         }
 411 }
 412
 413 static void
 414 atadebug(int cmdport, int ctlport, char* fmt, ...)
 415 {
 416         char *p, *e, buf[PRINTSIZE];
 417         int i;
 418         va_list arg;
 419
 420         if(!(DEBUG & DbgPROBE))
 421                 return;
 422
 423         p = buf;
 424         e = buf + sizeof buf;
 425         va_start(arg, fmt);
 426         p = vseprint(p, e, fmt, arg);
 427         va_end(arg);
 428
 429         if(cmdport){
 430                 if(p > buf && p[-1] == '\n')
 431                         p--;
 432                 p = seprint(p, e, " ataregs 0x%uX:", cmdport);
 433                 for(i = Features; i < Command; i++)
 434                         p = seprint(p, e, " 0x%2.2uX", inb(cmdport+i));
 435                 if(ctlport)
 436                         p = seprint(p, e, " 0x%2.2uX", inb(ctlport+As));
 437                 p = seprint(p, e, "\n");
 438         }
 439         putstrn(buf, p - buf);
 440 }
 441
 442 static int
 443 ataready(int cmdport, int ctlport, int dev, int reset, int ready, int m)
 444 {
 445         int as, m0;
 446
 447         atadebug(cmdport, ctlport, "ataready: dev %ux:%ux reset %ux ready %ux",
 448                 cmdport, dev, reset, ready);
 449         m0 = m;
 450         do{
 451                 /*
 452                  * Wait for the controller to become not busy and
 453                  * possibly for a status bit to become true (usually
 454                  * Drdy). Must change to the appropriate device
 455                  * register set if necessary before testing for ready.
 456                  * Always run through the loop at least once so it
 457                  * can be used as a test for !Bsy.
 458                  */
 459                 as = inb(ctlport+As);
 460                 if(as & reset){
 461                         /* nothing to do */
 462                 }
 463                 else if(dev){
 464                         outb(cmdport+Dh, dev);
 465                         dev = 0;
 466                 }
 467                 else if(ready == 0 || (as & ready)){
 468                         atadebug(0, 0, "ataready: %d:%d %#.2ux\n", m, m0, as);
 469                         return as;
 470                 }
 471                 microdelay(1);
 472         }while(m-- > 0);
 473         atadebug(0, 0, "ataready: timeout %d %#.2ux\n", m0, as);
 474         return -1;
 475 }
 476
 477 static int
 478 atadone(void* arg)
 479 {
 480         return ((Ctlr*)arg)->done;
 481 }
 482
 483 static int
 484 atarwmmode(Drive* drive, int cmdport, int ctlport, int dev)
 485 {
 486         int as, maxrwm, rwm;
 487
 488         maxrwm = drive->info[Imaxrwm] & 0xFF;
 489         if(maxrwm == 0)
 490                 return 0;
 491
 492         /*
 493          * Sometimes drives come up with the current count set
 494          * to 0; if so, set a suitable value, otherwise believe
 495          * the value in Irwm if the 0x100 bit is set.
 496          */
 497         if(drive->info[Irwm] & 0x100)
 498                 rwm = drive->info[Irwm] & 0xFF;
 499         else
 500                 rwm = 0;
 501         if(rwm == 0)
 502                 rwm = maxrwm;
 503         if(rwm > 16)
 504                 rwm = 16;
 505         if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 102*1000) < 0)
 506                 return 0;
 507         outb(cmdport+Count, rwm);
 508         outb(cmdport+Command, Csm);
 509         microdelay(1);
 510         as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 1000);
 511         inb(cmdport+Status);
 512         if(as < 0 || (as & (Df|Err)))
 513                 return 0;
 514
 515         drive->rwm = rwm;
 516
 517         return rwm;
 518 }
 519
 520 static int
 521 atadmamode(SDunit *unit, Drive* drive)
 522 {
 523         char buf[32], *s;
 524         int dma;
 525
 526         /*
 527          * Check if any DMA mode enabled.
 528          * Assumes the BIOS has picked and enabled the best.
 529          * This is completely passive at the moment, no attempt is
 530          * made to ensure the hardware is correctly set up.
 531          */
 532         dma = drive->info[Imwdma] & 0x0707;
 533         drive->dma = (dma>>8) & dma;
 534         if(drive->dma == 0 && (drive->info[Ivalid] & 0x04)){
 535                 dma = drive->info[Iudma] & 0x7F7F;
 536                 drive->dma = (dma>>8) & dma;
 537                 if(drive->dma)
 538                         drive->dma |= 'U'<<16;
 539         }
 540         if(unit != nil){
 541                 snprint(buf, sizeof buf, "*%sdma", unit->name);
 542                 s = getconf(buf);
 543                 if((s && !strcmp(s, "on")) || (!s && !getconf("*nodma")))
 544                         drive->dmactl = drive->dma;
 545         }
 546         return dma;
 547 }
 548
 549 static int
 550 ataidentify(Ctlr*, int cmdport, int ctlport, int dev, int pkt, void* info)
 551 {
 552         int as, command, drdy;
 553
 554         if(pkt){
 555                 command = Cidpkt;
 556                 drdy = 0;
 557         }
 558         else{
 559                 command = Cid;
 560                 drdy = Drdy;
 561         }
 562         dev &= ~Lba;
 563         as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
 564         if(as < 0)
 565                 return -1;
 566         outb(cmdport+Command, command);
 567         microdelay(1);
 568
 569         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
 570         if(as < 0 || (as & Err))
 571                 return as;
 572         memset(info, 0, 512);
 573         inss(cmdport+Data, info, 256);
 574         inb(cmdport+Status);
 575         return 0;
 576 }
 577
 578 static Drive*
 579 atadrive(SDunit *unit, Drive *drive, int cmdport, int ctlport, int dev)
 580 {
 581         int as, pkt, rlo, rhi;
 582         uchar buf[512], oserial[21];
 583         uvlong osectors;
 584         Ctlr *ctlr;
 585
 586         if(DEBUG & DbgIDENTIFY)
 587                 print("identify: port %ux dev %.2ux\n", cmdport, dev & ~Lba);
 588
 589         atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
 590         if(drive != nil){
 591                 osectors = drive->sectors;
 592                 memmove(oserial, drive->serial, sizeof drive->serial);
 593                 ctlr = drive->ctlr;
 594         }else{
 595                 osectors = 0;
 596                 memset(oserial, 0, sizeof drive->serial);
 597                 ctlr = nil;
 598
 599                 /* detect if theres a drive present */
 600                 outb(cmdport+Dh, dev & ~Lba);
 601                 microdelay(1);
 602                 outb(cmdport+Cyllo, 0xAA);
 603                 outb(cmdport+Cylhi, 0x55);
 604                 outb(cmdport+Sector, 0xFF);
 605                 rlo = inb(cmdport+Cyllo);
 606                 rhi = inb(cmdport+Cylhi);
 607                 if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55))
 608                         return nil;
 609         }
 610
 611         pkt = 1;
 612 retry:
 613         as = ataidentify(ctlr, cmdport, ctlport, dev, pkt, buf);
 614         if(as < 0)
 615                 return nil;
 616         if(as & Err){
 617                 if(pkt == 0)
 618                         return nil;
 619                 pkt = 0;
 620                 goto retry;
 621         }
 622
 623         if(drive == 0){
 624                 if((drive = malloc(sizeof(Drive))) == nil)
 625                         return nil;
 626                 drive->serial[0] = ' ';
 627                 drive->dev = dev;
 628         }
 629
 630         memmove(drive->info, buf, sizeof(drive->info));
 631
 632         setfissig(drive, pkt ? 0xeb140000 : 0x0101);
 633         drive->sectors = idfeat(drive, drive->info);
 634         drive->secsize = idss(drive, drive->info);
 635
 636         idmove(drive->serial, drive->info+10, 20);
 637         idmove(drive->firmware, drive->info+23, 8);
 638         idmove(drive->model, drive->info+27, 40);
 639         if(unit != nil){
 640                 memset(unit->inquiry, 0, sizeof unit->inquiry);
 641                 unit->inquiry[2] = 2;
 642                 unit->inquiry[3] = 2;
 643                 unit->inquiry[4] = sizeof unit->inquiry - 4;
 644                 memmove(unit->inquiry+8, drive->model, 40);
 645         }
 646
 647         if(pkt){
 648                 drive->pkt = 12;
 649                 if(drive->feat & Datapi16)
 650                         drive->pkt = 16;
 651         }else{
 652                 drive->pkt = 0;
 653                 if(drive->feat & Dlba)
 654                         drive->dev |= Lba;
 655                 atarwmmode(drive, cmdport, ctlport, dev);
 656         }
 657         atadmamode(unit, drive);
 658
 659         if(osectors != 0 && memcmp(oserial, drive->serial, sizeof oserial) != 0)
 660                 if(unit)
 661                         unit->sectors = 0;
 662         drive->unit = unit;
 663         if(DEBUG & DbgCONFIG){
 664                 print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
 665                         dev, cmdport, drive->info[Iconfig], drive->info[Icapabilities]);
 666                 print(" mwdma %4.4uX", drive->info[Imwdma]);
 667                 if(drive->info[Ivalid] & 0x04)
 668                         print(" udma %4.4uX", drive->info[Iudma]);
 669                 print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
 670                 if(drive->feat&Dllba)
 671                         print("\tLLBA sectors %llud", drive->sectors);
 672                 print("\n");
 673         }
 674
 675         return drive;
 676 }
 677
 678 static void
 679 atasrst(int ctlport)
 680 {
 681         int dc0;
 682
 683         /*
 684          * Srst is a big stick and may cause problems if further
 685          * commands are tried before the drives become ready again.
 686          * Also, there will be problems here if overlapped commands
 687          * are ever supported.
 688          */
 689         dc0 = inb(ctlport+Dc);
 690         microdelay(5);
 691         outb(ctlport+Dc, Srst|dc0);
 692         microdelay(5);
 693         outb(ctlport+Dc, dc0);
 694         microdelay(2*1000);
 695 }
 696
 697 static SDev*
 698 ataprobe(int cmdport, int ctlport, int irq, int map)
 699 {
 700         static int nonlegacy = 'C';
 701         Ctlr* ctlr;
 702         SDev *sdev;
 703
 704         if(ioalloc(cmdport, 8, 0, "atacmd") < 0) {
 705                 print("ataprobe: Cannot allocate %X\n", cmdport);
 706                 return nil;
 707         }
 708         if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
 709                 print("ataprobe: Cannot allocate %X\n", ctlport + As);
 710                 iofree(cmdport);
 711                 return nil;
 712         }
 713
 714         if((ctlr = malloc(sizeof(Ctlr))) == nil)
 715                 goto release;
 716         if((sdev = malloc(sizeof(SDev))) == nil){
 717                 free(ctlr);
 718                 goto release;
 719         }
 720
 721         if((map & 2) && (ctlr->drive[1] = atadrive(0, 0, cmdport, ctlport, Dev1)))
 722                 ctlr->drive[1]->ctlr = ctlr;
 723         if((map & 1) && (ctlr->drive[0] = atadrive(0, 0, cmdport, ctlport, Dev0)))
 724                 ctlr->drive[0]->ctlr = ctlr;
 725
 726         if(ctlr->drive[0] == nil && ctlr->drive[1] == nil){
 727                 free(ctlr->drive[0]);
 728                 free(ctlr->drive[1]);
 729                 free(ctlr);
 730                 free(sdev);
 731                 goto release;
 732         }
 733
 734         ctlr->cmdport = cmdport;
 735         ctlr->ctlport = ctlport;
 736         ctlr->irq = irq;
 737         ctlr->tbdf = BUSUNKNOWN;
 738         ctlr->command = Cnop;           /* debugging */
 739
 740         switch(cmdport){
 741         default:
 742                 sdev->idno = nonlegacy;
 743                 break;
 744         case 0x1F0:
 745                 sdev->idno = 'C';
 746                 nonlegacy = 'E';
 747                 break;
 748         case 0x170:
 749                 sdev->idno = 'D';
 750                 nonlegacy = 'E';
 751                 break;
 752         }
 753         sdev->ifc = &sdideifc;
 754         sdev->ctlr = ctlr;
 755         sdev->nunit = 2;
 756         ctlr->sdev = sdev;
 757
 758         return sdev;
 759
 760 release:
 761         iofree(cmdport);
 762         iofree(ctlport+As);
 763
 764         return nil;
 765 }
 766
 767 static void
 768 ataclear(SDev *sdev)
 769 {
 770         Ctlr* ctlr;
 771
 772         ctlr = sdev->ctlr;
 773         iofree(ctlr->cmdport);
 774         iofree(ctlr->ctlport + As);
 775
 776         if (ctlr->drive[0])
 777                 free(ctlr->drive[0]);
 778         if (ctlr->drive[1])
 779                 free(ctlr->drive[1]);
 780         if (sdev->name)
 781                 free(sdev->name);
 782         if (sdev->unitflg)
 783                 free(sdev->unitflg);
 784         if (sdev->unit)
 785                 free(sdev->unit);
 786         free(ctlr);
 787         free(sdev);
 788 }
 789
 790 static char *
 791 atastat(SDev *sdev, char *p, char *e)
 792 {
 793         Ctlr *ctlr;
 794
 795         ctlr = sdev->ctlr;
 796 //      return seprint(p, e, "%s ata port %X ctl %X irq %d %T\n",
 797 //                  sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq, ctlr->tbdf);
 798         return seprint(p, e, "%s ata port %X ctl %X irq %d\n",
 799                     sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq);
 800 }
 801
 802 static SDev*
 803 ataprobew(DevConf *cf)
 804 {
 805         char *p;
 806         ISAConf isa;
 807
 808         if (cf->nports != 2)
 809                 error(Ebadarg);
 810
 811         memset(&isa, 0, sizeof isa);
 812         isa.port = cf->ports[0].port;
 813         isa.irq = cf->intnum;
 814         if((p=strchr(cf->type, '/')) == nil || pcmspecial(p+1, &isa) < 0)
 815                 error("cannot find controller");
 816
 817         return ataprobe(cf->ports[0].port, cf->ports[1].port, cf->intnum, 3);
 818 }
 819
 820 static void atainterrupt(Ureg*, void*);
 821
 822 static int
 823 iowait(Drive *drive, int ms, int interrupt)
 824 {
 825         int msec, step;
 826         Ctlr *ctlr;
 827
 828         step = 1000;
 829         if(drive->missirq > 10)
 830                 step = 50;
 831         ctlr = drive->ctlr;
 832         for(msec = 0; msec < ms; msec += step){
 833                 while(waserror())
 834                         if(interrupt)
 835                                 return -1;
 836                 tsleep(ctlr, atadone, ctlr, step);
 837                 poperror();
 838                 if(ctlr->done)
 839                         break;
 840                 atainterrupt(nil, ctlr);
 841                 if(ctlr->done){
 842                         if(drive->missirq++ < 3)
 843                                 print("ide: caught missed irq\n");
 844                         break;
 845                 }else
 846                         drive->spurloop++;
 847         }
 848         return ctlr->done;
 849 }
 850
 851 static void
 852 atanop(Drive* drive, int subcommand)
 853 {
 854         Ctlr* ctlr;
 855         int as, cmdport, ctlport, timeo;
 856
 857         /*
 858          * Attempt to abort a command by using NOP.
 859          * In response, the drive is supposed to set Abrt
 860          * in the Error register, set (Drdy|Err) in Status
 861          * and clear Bsy when done. However, some drives
 862          * (e.g. ATAPI Zip) just go Bsy then clear Status
 863          * when done, hence the timeout loop only on Bsy
 864          * and the forced setting of drive->error.
 865          */
 866         ctlr = drive->ctlr;
 867         cmdport = ctlr->cmdport;
 868         outb(cmdport+Features, subcommand);
 869         outb(cmdport+Dh, drive->dev);
 870         ctlr->command = Cnop;           /* debugging */
 871         outb(cmdport+Command, Cnop);
 872
 873         microdelay(1);
 874         ctlport = ctlr->ctlport;
 875         for(timeo = 0; timeo < 1000; timeo++){
 876                 as = inb(ctlport+As);
 877                 if(!(as & Bsy))
 878                         break;
 879                 microdelay(1);
 880         }
 881         drive->error |= Abrt;
 882 }
 883
 884 static void
 885 ataabort(Drive* drive, int dolock)
 886 {
 887         /*
 888          * If NOP is available use it otherwise
 889          * must try a software reset.
 890          */
 891         if(dolock)
 892                 ilock(drive->ctlr);
 893         if(drive->feat & Dnop)
 894                 atanop(drive, 0);
 895         else{
 896                 atasrst(drive->ctlr->ctlport);
 897                 drive->error |= Abrt;
 898         }
 899         if(dolock)
 900                 iunlock(drive->ctlr);
 901 }
 902
 903 static int
 904 atadmasetup(Drive* drive, int len)
 905 {
 906         Prd *prd;
 907         ulong pa;
 908         Ctlr *ctlr;
 909         int bmiba, bmisx, count, i, span;
 910
 911         ctlr = drive->ctlr;
 912         pa = PCIWADDR(drive->data);
 913         if(pa & 0x03)
 914                 return -1;
 915         if(ctlr->maxdma && len > ctlr->maxdma)
 916                 return -1;
 917
 918         /*
 919          * Sometimes drives identify themselves as being DMA capable
 920          * although they are not on a busmastering controller.
 921          */
 922         prd = ctlr->prdt;
 923         if(prd == nil){
 924                 drive->dmactl = 0;
 925                 print("disabling dma: not on a busmastering controller\n");
 926                 return -1;
 927         }
 928
 929         for(i = 0; len && i < Nprd; i++){
 930                 prd->pa = pa;
 931                 span = ROUNDUP(pa, ctlr->span);
 932                 if(span == pa)
 933                         span += ctlr->span;
 934                 count = span - pa;
 935                 if(count >= len){
 936                         prd->count = PrdEOT|len;
 937                         break;
 938                 }
 939                 prd->count = count;
 940                 len -= count;
 941                 pa += count;
 942                 prd++;
 943         }
 944         if(i == Nprd)
 945                 return -1;
 946
 947         bmiba = ctlr->bmiba;
 948         outl(bmiba+Bmidtpx, PCIWADDR(ctlr->prdt));
 949         if(drive->write)
 950                 outb(bmiba+Bmicx, 0);
 951         else
 952                 outb(bmiba+Bmicx, Rwcon);
 953         bmisx = inb(bmiba+Bmisx);
 954         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
 955
 956         return 0;
 957 }
 958
 959 static void
 960 atadmastart(Ctlr* ctlr, int write)
 961 {
 962         if(write)
 963                 outb(ctlr->bmiba+Bmicx, Ssbm);
 964         else
 965                 outb(ctlr->bmiba+Bmicx, Rwcon|Ssbm);
 966 }
 967
 968 static int
 969 atadmastop(Ctlr* ctlr)
 970 {
 971         int bmiba;
 972
 973         bmiba = ctlr->bmiba;
 974         outb(bmiba+Bmicx, inb(bmiba+Bmicx) & ~Ssbm);
 975
 976         return inb(bmiba+Bmisx);
 977 }
 978
 979 static void
 980 atadmainterrupt(Drive* drive, int count)
 981 {
 982         Ctlr* ctlr;
 983         int bmiba, bmisx;
 984
 985         ctlr = drive->ctlr;
 986         bmiba = ctlr->bmiba;
 987         bmisx = inb(bmiba+Bmisx);
 988         switch(bmisx & (Ideints|Idedmae|Bmidea)){
 989         case Bmidea:
 990                 /*
 991                  * Data transfer still in progress, nothing to do
 992                  * (this should never happen).
 993                  */
 994                 return;
 995
 996         case Ideints:
 997         case Ideints|Bmidea:
 998                 /*
 999                  * Normal termination, tidy up.
1000                  */
1001                 drive->data += count;
1002                 break;
1003
1004         default:
1005                 /*
1006                  * What's left are error conditions (memory transfer
1007                  * problem) and the device is not done but the PRD is
1008                  * exhausted. For both cases must somehow tell the
1009                  * drive to abort.
1010                  */
1011                 ataabort(drive, 0);
1012                 break;
1013         }
1014         atadmastop(ctlr);
1015         ctlr->done = 1;
1016 }
1017
1018 static void
1019 atapktinterrupt(Drive* drive)
1020 {
1021         Ctlr* ctlr;
1022         int cmdport, len;
1023
1024         ctlr = drive->ctlr;
1025         cmdport = ctlr->cmdport;
1026         switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
1027         case Cd:
1028                 outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
1029                 break;
1030
1031         case 0:
1032                 if(drive->pktdma)
1033                         goto Pktdma;
1034                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1035                 if(drive->data+len > drive->limit){
1036                         atanop(drive, 0);
1037                         break;
1038                 }
1039                 outss(cmdport+Data, drive->data, len/2);
1040                 drive->data += len;
1041                 break;
1042
1043         case Io:
1044                 if(drive->pktdma)
1045                         goto Pktdma;
1046                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1047                 if(drive->data+len > drive->limit){
1048                         atanop(drive, 0);
1049                         break;
1050                 }
1051                 inss(cmdport+Data, drive->data, len/2);
1052                 drive->data += len;
1053                 break;
1054
1055         case Io|Cd:
1056                 if(drive->pktdma){
1057         Pktdma:
1058                         atadmainterrupt(drive, drive->dlen);
1059                 } else
1060                         ctlr->done = 1;
1061                 break;
1062         }
1063 }
1064
1065 static int
1066 atapktio0(Drive *drive, SDreq *r)
1067 {
1068         uchar *cmd;
1069         int as, len, cmdport, ctlport, rv;
1070         Ctlr *ctlr;
1071
1072         rv = SDok;
1073         cmd = r->cmd;
1074         drive->command = Cpkt;
1075         memmove(drive->pktcmd, cmd, r->clen);
1076         memset(drive->pktcmd+r->clen, 0, drive->pkt-r->clen);
1077         drive->limit = drive->data+drive->dlen;
1078
1079         ctlr = drive->ctlr;
1080         cmdport = ctlr->cmdport;
1081         ctlport = ctlr->ctlport;
1082
1083         as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 107*1000);
1084         /* used to test as&Chk as failure too, but some CD readers use that for media change */
1085         if(as < 0)
1086                 return SDnostatus;
1087
1088         ilock(ctlr);
1089         if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen))
1090                 drive->pktdma = Dma;
1091         else
1092                 drive->pktdma = 0;
1093         len = drive->secsize > 0 ? 16*drive->secsize : 0x8000;
1094         outb(cmdport+Features, drive->pktdma);
1095         outb(cmdport+Count, 0);
1096         outb(cmdport+Sector, 0);
1097         outb(cmdport+Bytelo, len);
1098         outb(cmdport+Bytehi, len>>8);
1099         outb(cmdport+Dh, drive->dev);
1100         ctlr->done = 0;
1101         ctlr->curdrive = drive;
1102         ctlr->command = Cpkt;           /* debugging */
1103         outb(cmdport+Command, Cpkt);
1104
1105         microdelay(1);
1106         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 400*1000);
1107         if(as < 0 || (as & (Bsy|Chk))){
1108                 drive->status = as<0 ? 0 : as;
1109                 ctlr->curdrive = nil;
1110                 ctlr->done = 1;
1111                 rv = SDtimeout;
1112         }else
1113                 atapktinterrupt(drive);
1114         if(drive->pktdma)
1115                 atadmastart(ctlr, drive->write);
1116         iunlock(ctlr);
1117
1118         while(iowait(drive, 30*1000, 1) == 0)
1119                 ;
1120
1121         ilock(ctlr);
1122         if(!ctlr->done){
1123                 rv = SDcheck;
1124                 ataabort(drive, 0);
1125         }
1126         if(drive->error){
1127                 if(drive->pktdma)
1128                         atadmastop(ctlr);
1129                 drive->status |= Chk;
1130                 ctlr->curdrive = nil;
1131         }
1132         iunlock(ctlr);
1133
1134         if(rv != SDcheck && drive->status & Chk){
1135                 rv = SDcheck;
1136                 if(drive->pktdma){
1137                         print("atapktio: disabling dma\n");
1138                         drive->dmactl = 0;
1139                 }
1140         }
1141         return rv;
1142 }
1143
1144 static int
1145 atapktio(Drive* drive, SDreq *r)
1146 {
1147         int n;
1148         Ctlr *ctlr;
1149
1150         ctlr = drive->ctlr;
1151         qlock(ctlr);
1152         n = atapktio0(drive, r);
1153         qunlock(ctlr);
1154         return n;
1155 }
1156
1157 static uchar cmd48[256] = {
1158         [Crs]   Crs48,
1159         [Crd]   Crd48,
1160         [Crsm]  Crsm48,
1161         [Cws]   Cws48,
1162         [Cwd]   Cwd48,
1163         [Cwsm]  Cwsm48,
1164 };
1165
1166 enum{
1167         Last28  = (1<<28) - 1,
1168 };
1169
1170 static int
1171 atageniostart(Drive* drive, uvlong lba)
1172 {
1173         Ctlr *ctlr;
1174         uchar cmd;
1175         int as, c, cmdport, ctlport, h, len, s, use48;
1176
1177         use48 = 0;
1178         if((drive->flags&Lba48always) || (lba+drive->count) > Last28 || drive->count > 256){
1179                 if((drive->feat & Dllba) == 0)
1180                         return -1;
1181                 use48 = 1;
1182                 c = h = s = 0;
1183         }else if(drive->dev & Lba){
1184                 c = (lba>>8) & 0xFFFF;
1185                 h = (lba>>24) & 0x0F;
1186                 s = lba & 0xFF;
1187         }else{
1188                 if (drive->s == 0 || drive->h == 0){
1189                         print("sdide: chs address botch");
1190                         return -1;
1191                 }
1192                 c = lba/(drive->s*drive->h);
1193                 h = (lba/drive->s) % drive->h;
1194                 s = (lba % drive->s) + 1;
1195         }
1196
1197         ctlr = drive->ctlr;
1198         cmdport = ctlr->cmdport;
1199         ctlport = ctlr->ctlport;
1200         if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 101*1000) < 0)
1201                 return -1;
1202
1203         ilock(ctlr);
1204         if(drive->dmactl && !atadmasetup(drive, drive->count*drive->secsize)){
1205                 if(drive->write)
1206                         drive->command = Cwd;
1207                 else
1208                         drive->command = Crd;
1209         }
1210         else if(drive->rwmctl){
1211                 drive->block = drive->rwm*drive->secsize;
1212                 if(drive->write)
1213                         drive->command = Cwsm;
1214                 else
1215                         drive->command = Crsm;
1216         }
1217         else{
1218                 drive->block = drive->secsize;
1219                 if(drive->write)
1220                         drive->command = Cws;
1221                 else
1222                         drive->command = Crs;
1223         }
1224         drive->limit = drive->data + drive->count*drive->secsize;
1225         cmd = drive->command;
1226         if(use48){
1227                 outb(cmdport+Count, drive->count>>8);
1228                 outb(cmdport+Count, drive->count);
1229                 outb(cmdport+Lbalo, lba>>24);
1230                 outb(cmdport+Lbalo, lba);
1231                 outb(cmdport+Lbamid, lba>>32);
1232                 outb(cmdport+Lbamid, lba>>8);
1233                 outb(cmdport+Lbahi, lba>>40);
1234                 outb(cmdport+Lbahi, lba>>16);
1235                 outb(cmdport+Dh, drive->dev|Lba);
1236                 cmd = cmd48[cmd];
1237
1238                 if(DEBUG & Dbg48BIT)
1239                         print("using 48-bit commands\n");
1240         }else{
1241                 outb(cmdport+Count, drive->count);
1242                 outb(cmdport+Sector, s);
1243                 outb(cmdport+Cyllo, c);
1244                 outb(cmdport+Cylhi, c>>8);
1245                 outb(cmdport+Dh, drive->dev|h);
1246         }
1247         ctlr->done = 0;
1248         ctlr->curdrive = drive;
1249         ctlr->command = drive->command; /* debugging */
1250         outb(cmdport+Command, cmd);
1251
1252         switch(drive->command){
1253         case Cws:
1254         case Cwsm:
1255                 microdelay(1);
1256                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1257                 if(as < 0 || (as & Err)){
1258                         iunlock(ctlr);
1259                         return -1;
1260                 }
1261                 len = drive->block;
1262                 if(drive->data+len > drive->limit)
1263                         len = drive->limit-drive->data;
1264                 outss(cmdport+Data, drive->data, len/2);
1265                 break;
1266
1267         case Crd:
1268         case Cwd:
1269                 atadmastart(ctlr, drive->write);
1270                 break;
1271         }
1272         iunlock(ctlr);
1273
1274         return 0;
1275 }
1276
1277 static int
1278 atagenioretry(Drive* drive, SDreq *r, uvlong lba, int count)
1279 {
1280         char *s;
1281         int rv, count0, rw;
1282         uvlong lba0;
1283
1284         if(drive->dmactl){
1285                 drive->dmactl = 0;
1286                 s = "disabling dma";
1287                 rv = SDretry;
1288         }else if(drive->rwmctl){
1289                 drive->rwmctl = 0;
1290                 s = "disabling rwm";
1291                 rv = SDretry;
1292         }else{
1293                 s = "nondma";
1294                 rv = sdsetsense(r, SDcheck, 4, 8, drive->error);
1295         }
1296         sdfakescsirw(r, &lba0, &count0, &rw);
1297         print("atagenioretry: %s %c:%llud:%d @%llud:%d\n",
1298                 s, "rw"[rw], lba0, count0, lba, count);
1299         return rv;
1300 }
1301
1302 static int
1303 atagenio(Drive* drive, SDreq *r)
1304 {
1305         Ctlr *ctlr;
1306         uvlong lba;
1307         int i, rw, count, maxio;
1308
1309         if((i = sdfakescsi(r)) != SDnostatus)
1310                 return i;
1311         if((i = sdfakescsirw(r, &lba, &count, &rw)) != SDnostatus)
1312                 return i;
1313         ctlr = drive->ctlr;
1314         if(drive->data == nil)
1315                 return SDok;
1316         if(drive->dlen < count*drive->secsize)
1317                 count = drive->dlen/drive->secsize;
1318         qlock(ctlr);
1319         if(ctlr->maxio)
1320                 maxio = ctlr->maxio;
1321         else if(drive->feat & Dllba)
1322                 maxio = 65536;
1323         else
1324                 maxio = 256;
1325         while(count){
1326                 if(count > maxio)
1327                         drive->count = maxio;
1328                 else
1329                         drive->count = count;
1330                 if(atageniostart(drive, lba)){
1331                         ilock(ctlr);
1332                         atanop(drive, 0);
1333                         iunlock(ctlr);
1334                         qunlock(ctlr);
1335                         return atagenioretry(drive, r, lba, count);
1336                 }
1337                 iowait(drive, 30*1000, 0);
1338                 if(!ctlr->done){
1339                         /*
1340                          * What should the above timeout be? In
1341                          * standby and sleep modes it could take as
1342                          * long as 30 seconds for a drive to respond.
1343                          * Very hard to get out of this cleanly.
1344                          */
1345                         atadumpstate(drive, r, lba, count);
1346                         ataabort(drive, 1);
1347                         qunlock(ctlr);
1348                         return atagenioretry(drive, r, lba, count);
1349                 }
1350
1351                 if(drive->status & Err){
1352                         qunlock(ctlr);
1353                         print("atagenio: %llud:%d\n", lba, drive->count);
1354                         return sdsetsense(r, SDcheck, 4, 8, drive->error);
1355                 }
1356                 count -= drive->count;
1357                 lba += drive->count;
1358         }
1359         qunlock(ctlr);
1360
1361         return SDok;
1362 }
1363
1364 static int
1365 atario(SDreq* r)
1366 {
1367         uchar *p;
1368         int status;
1369         Ctlr *ctlr;
1370         Drive *drive;
1371         SDunit *unit;
1372
1373         unit = r->unit;
1374         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
1375                 return r->status = SDtimeout;
1376         drive = ctlr->drive[unit->subno];
1377         qlock(drive);
1378         for(;;){
1379                 drive->write = r->write;
1380                 drive->data = r->data;
1381                 drive->dlen = r->dlen;
1382                 drive->status = 0;
1383                 drive->error = 0;
1384                 if(drive->pkt)
1385                         status = atapktio(drive, r);
1386                 else
1387                         status = atagenio(drive, r);
1388                 if(status != SDretry)
1389                         break;
1390                 if(DbgDEBUG)
1391                         print("%s: retry: dma %8.8uX rwm %4.4uX\n",
1392                                 unit->name, drive->dmactl, drive->rwmctl);
1393         }
1394         if(status == SDok && r->rlen == 0 && (r->flags & SDvalidsense) == 0){
1395                 sdsetsense(r, SDok, 0, 0, 0);
1396                 if(drive->data){
1397                         p = r->data;
1398                         r->rlen = drive->data - p;
1399                 }
1400                 else
1401                         r->rlen = 0;
1402         }
1403         qunlock(drive);
1404         return status;
1405 }
1406
1407 /**/
1408 static int
1409 isdmacmd(Drive *d, SDreq *r)
1410 {
1411         switch(r->ataproto & Pprotom){
1412         default:
1413                 return 0;
1414         case Pdmq:
1415                 error("no queued support");
1416         case Pdma:
1417                 if(!(d->dmactl || d->rwmctl))
1418                         error("dma in non dma mode\n");
1419                 return 1;
1420         }
1421 }
1422
1423 static int
1424 atagenatastart(Drive* d, SDreq *r)
1425 {
1426         uchar u;
1427         int as, cmdport, ctlport, len, pr, isdma;
1428         Ctlr *ctlr;
1429
1430         isdma = isdmacmd(d, r);
1431         ctlr = d->ctlr;
1432         cmdport = ctlr->cmdport;
1433         ctlport = ctlr->ctlport;
1434         if(ataready(cmdport, ctlport, d->dev, Bsy|Drq, d->pkt ? 0 : Drdy, 101*1000) < 0)
1435                 return -1;
1436
1437         ilock(ctlr);
1438         if(isdma && atadmasetup(d, d->block)){
1439                 iunlock(ctlr);
1440                 return -1;
1441
1442         }
1443         if(d->feat & Dllba && (r->ataproto & P28) == 0){
1444                 outb(cmdport+Features, r->cmd[Ffeat8]);
1445                 outb(cmdport+Features, r->cmd[Ffeat]);
1446                 outb(cmdport+Count, r->cmd[Fsc8]);
1447                 outb(cmdport+Count, r->cmd[Fsc]);
1448                 outb(cmdport+Lbalo, r->cmd[Flba24]);
1449                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1450                 outb(cmdport+Lbamid, r->cmd[Flba32]);
1451                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1452                 outb(cmdport+Lbahi, r->cmd[Flba40]);
1453                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1454                 u = r->cmd[Fdev] & ~0xb0;
1455                 outb(cmdport+Dh, d->dev|u);
1456         }else{
1457                 outb(cmdport+Features, r->cmd[Ffeat]);
1458                 outb(cmdport+Count, r->cmd[Fsc]);
1459                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1460                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1461                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1462                 u = r->cmd[Fdev] & ~0xb0;
1463                 outb(cmdport+Dh, d->dev|u);
1464         }
1465         ctlr->done = 0;
1466         ctlr->curdrive = d;
1467         d->command = r->ataproto & (Pprotom|Pdatam);
1468         ctlr->command = r->cmd[Fcmd];
1469         outb(cmdport+Command, r->cmd[Fcmd]);
1470
1471         pr = r->ataproto & Pprotom;
1472         if(pr == Pnd || pr == Preset)
1473                 USED(d);
1474         else if(!isdma){
1475                 microdelay(1);
1476                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1477                 if(as < 0 || (as & Err)){
1478                         iunlock(ctlr);
1479                         return -1;
1480                 }
1481                 len = d->block;
1482                 if(r->write && len > 0)
1483                         outss(cmdport+Data, d->data, len/2);
1484         }else
1485                 atadmastart(ctlr, d->write);
1486         iunlock(ctlr);
1487         return 0;
1488 }
1489
1490 static void
1491 mkrfis(Drive *d, SDreq *r)
1492 {
1493         uchar *u;
1494         int cmdport;
1495         Ctlr *ctlr;
1496
1497         ctlr = d->ctlr;
1498         cmdport = ctlr->cmdport;
1499         u = r->cmd;
1500
1501         ilock(ctlr);
1502         u[Ftype] = 0x34;
1503         u[Fioport] = 0;
1504         if((d->feat & Dllba) && (r->ataproto & P28) == 0){
1505                 u[Frerror] = inb(cmdport+Error);
1506                 u[Fsc8] = inb(cmdport+Count);
1507                 u[Fsc] = inb(cmdport+Count);
1508                 u[Flba24] = inb(cmdport+Lbalo);
1509                 u[Flba0] = inb(cmdport+Lbalo);
1510                 u[Flba32] = inb(cmdport+Lbamid);
1511                 u[Flba8] = inb(cmdport+Lbamid);
1512                 u[Flba40] = inb(cmdport+Lbahi);
1513                 u[Flba16] = inb(cmdport+Lbahi);
1514                 u[Fdev] = inb(cmdport+Dh);
1515                 u[Fstatus] = inb(cmdport+Status);
1516         }else{
1517                 u[Frerror] = inb(cmdport+Error);
1518                 u[Fsc] = inb(cmdport+Count);
1519                 u[Flba0] = inb(cmdport+Lbalo);
1520                 u[Flba8] = inb(cmdport+Lbamid);
1521                 u[Flba16] = inb(cmdport+Lbahi);
1522                 u[Fdev] = inb(cmdport+Dh);
1523                 u[Fstatus] = inb(cmdport+Status);
1524         }
1525         iunlock(ctlr);
1526 }
1527
1528 static int
1529 atarstdone(Drive *d)
1530 {
1531         int as;
1532         Ctlr *c;
1533
1534         c = d->ctlr;
1535         as = ataready(c->cmdport, c->ctlport, 0, Bsy|Drq, 0, 5*1000);
1536         c->done = as >= 0;
1537         return c->done;
1538 }
1539
1540 static uint
1541 cmdss(Drive *d, SDreq *r)
1542 {
1543         switch(r->cmd[Fcmd]){
1544         case Cid:
1545         case Cidpkt:
1546                 return 512;
1547         default:
1548                 return d->secsize;
1549         }
1550 }
1551
1552 /*
1553  * various checks.  we should be craftier and
1554  * avoid figuring out how big stuff is supposed to be.
1555  */
1556 static uint
1557 patasizeck(Drive *d, SDreq *r)
1558 {
1559         uint count, maxio, secsize;
1560         Ctlr *ctlr;
1561
1562         secsize = cmdss(d, r);          /* BOTCH */
1563         if(secsize == 0)
1564                 error(Eio);
1565         count = r->dlen / secsize;
1566         ctlr = d->ctlr;
1567         if(ctlr->maxio)
1568                 maxio = ctlr->maxio;
1569         else if((d->feat & Dllba) && (r->ataproto & P28) == 0)
1570                 maxio = 65536;
1571         else
1572                 maxio = 256;
1573         if(count > maxio){
1574                 uprint("i/o too large, lim %d", maxio);
1575                 error(up->genbuf);
1576         }
1577         if(r->ataproto&Ppio && count > 1)
1578                 error("invalid # of sectors");
1579         return count;
1580 }
1581
1582 static int
1583 atapataio(Drive *d, SDreq *r)
1584 {
1585         int rv;
1586         Ctlr *ctlr;
1587
1588         d->count = 0;
1589         if(r->ataproto & Pdatam)
1590                 d->count = patasizeck(d, r);
1591         d->block = r->dlen;
1592         d->limit = d->data + r->dlen;
1593
1594         ctlr = d->ctlr;
1595         qlock(ctlr);
1596         if(waserror()){
1597                 qunlock(ctlr);
1598                 nexterror();
1599         }
1600         rv = atagenatastart(d, r);
1601         poperror();
1602         if(rv){
1603                 if(DEBUG & DbgAtazz)
1604                         print("sdide: !atageatastart\n");
1605                 ilock(ctlr);
1606                 atanop(d, 0);
1607                 iunlock(ctlr);
1608                 qunlock(ctlr);
1609                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1610         }
1611
1612         if((r->ataproto & Pprotom) == Preset)
1613                 atarstdone(d);
1614         else
1615                 while(iowait(d, 30*1000, 1) == 0)
1616                         ;
1617         if(!ctlr->done){
1618                 if(DEBUG & DbgAtazz){
1619                         print("sdide: !done\n");
1620                         atadumpstate(d, r, 0, d->count);
1621                 }
1622                 ataabort(d, 1);
1623                 qunlock(ctlr);
1624                 return sdsetsense(r, SDcheck, 11, 0, 6);        /* aborted; i/o process terminated */
1625         }
1626         mkrfis(d, r);
1627         if(d->status & Err){
1628                 if(DEBUG & DbgAtazz)
1629                         print("sdide: status&Err\n");
1630                 qunlock(ctlr);
1631                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1632         }
1633         qunlock(ctlr);
1634         return SDok;
1635 }
1636
1637 static int
1638 ataataio0(Drive *d, SDreq *r)
1639 {
1640         int i;
1641
1642         if((r->ataproto & Pprotom) == Ppkt){
1643                 if(r->clen > d->pkt)
1644                         error(Eio);
1645                 qlock(d->ctlr);
1646                 i = atapktio0(d, r);
1647                 d->block = d->data - (uchar*)r->data;
1648                 mkrfis(d, r);
1649                 qunlock(d->ctlr);
1650                 return i;
1651         }else
1652                 return atapataio(d, r);
1653 }
1654
1655 /*
1656  * hack to allow udma mode to be set or unset
1657  * via direct ata command.  it would be better
1658  * to move the assumptions about dma mode out
1659  * of some of the helper functions.
1660  */
1661 static int
1662 isudm(SDreq *r)
1663 {
1664         uchar *c;
1665
1666         c = r->cmd;
1667         if(c[Fcmd] == 0xef && c[Ffeat] == 0x03){
1668                 if(c[Fsc]&0x40)
1669                         return 1;
1670                 return -1;
1671         }
1672         return 0;
1673 }
1674
1675 static int
1676 fisreqchk(Sfis *f, SDreq *r)
1677 {
1678         if((r->ataproto & Pprotom) == Ppkt)
1679                 return SDnostatus;
1680         /*
1681          * handle oob requests;
1682          *    restrict & sanitize commands
1683          */
1684         if(r->clen != 16)
1685                 error(Eio);
1686         if(r->cmd[0] == 0xf0){
1687                 sigtofis(f, r->cmd);
1688                 r->status = SDok;
1689                 return SDok;
1690         }
1691         r->cmd[0] = 0x27;
1692         r->cmd[1] = 0x80;
1693         r->cmd[7] |= 0xa0;
1694         return SDnostatus;
1695 }
1696
1697 static int
1698 ataataio(SDreq *r)
1699 {
1700         int status, udm;
1701         Ctlr *c;
1702         Drive *d;
1703         SDunit *u;
1704
1705         u = r->unit;
1706         if((c = u->dev->ctlr) == nil || (d = c->drive[u->subno]) == nil){
1707                 r->status = SDtimeout;
1708                 return SDtimeout;
1709         }
1710         if((status = fisreqchk(d, r)) != SDnostatus)
1711                 return status;
1712         udm = isudm(r);
1713
1714         qlock(d);
1715         if(waserror()){
1716                 qunlock(d);
1717                 nexterror();
1718         }
1719 retry:
1720         d->write = r->write;
1721         d->data = r->data;
1722         d->dlen = r->dlen;
1723         d->status = 0;
1724         d->error = 0;
1725
1726         switch(status = ataataio0(d, r)){
1727         case SDretry:
1728                 if(DbgDEBUG)
1729                         print("%s: retry: dma %.8ux rwm %.4ux\n",
1730                                 u->name, d->dmactl, d->rwmctl);
1731                 goto retry;
1732         case SDok:
1733                 if(udm == 1)
1734                         d->dmactl = d->dma;
1735                 else if(udm == -1)
1736                         d->dmactl = 0;
1737                 sdsetsense(r, SDok, 0, 0, 0);
1738                 r->rlen = d->block;
1739                 break;
1740         }
1741         poperror();
1742         qunlock(d);
1743         r->status = status;
1744         return status;
1745 }
1746 /**/
1747
1748 static void
1749 ichirqack(Ctlr *ctlr)
1750 {
1751         int bmiba;
1752
1753         if(bmiba = ctlr->bmiba)
1754                 outb(bmiba+Bmisx, inb(bmiba+Bmisx));
1755 }
1756
1757 static void
1758 atainterrupt(Ureg*, void* arg)
1759 {
1760         Ctlr *ctlr;
1761         Drive *drive;
1762         int cmdport, len, status;
1763
1764         ctlr = arg;
1765
1766         ilock(ctlr);
1767         ctlr->nrq++;
1768         if(ctlr->curdrive)
1769                 ctlr->curdrive->irq++;
1770         if(inb(ctlr->ctlport+As) & Bsy){
1771                 ctlr->bsy++;
1772                 if(ctlr->curdrive)
1773                         ctlr->curdrive->bsy++;
1774                 iunlock(ctlr);
1775                 if(DEBUG & DbgBsy)
1776                         print("IBsy+");
1777                 return;
1778         }
1779         cmdport = ctlr->cmdport;
1780         status = inb(cmdport+Status);
1781         if((drive = ctlr->curdrive) == nil){
1782                 ctlr->nildrive++;
1783                 if(ctlr->irqack != nil)
1784                         ctlr->irqack(ctlr);
1785                 iunlock(ctlr);
1786                 return;
1787         }
1788         if(status & Err)
1789                 drive->error = inb(cmdport+Error);
1790         else switch(drive->command){
1791         default:
1792                 drive->error = Abrt;
1793                 break;
1794
1795         case Crs:
1796         case Crsm:
1797         case Ppio|Pin:
1798                 if(!(status & Drq)){
1799                         drive->error = Abrt;
1800                         break;
1801                 }
1802                 len = drive->block;
1803                 if(drive->data+len > drive->limit)
1804                         len = drive->limit-drive->data;
1805                 inss(cmdport+Data, drive->data, len/2);
1806                 drive->data += len;
1807                 if(drive->data >= drive->limit)
1808                         ctlr->done = 1;
1809                 break;
1810
1811         case Cws:
1812         case Cwsm:
1813         case Ppio|Pout:
1814                 len = drive->block;
1815                 if(drive->data+len > drive->limit)
1816                         len = drive->limit-drive->data;
1817                 drive->data += len;
1818                 if(drive->data >= drive->limit){
1819                         ctlr->done = 1;
1820                         break;
1821                 }
1822                 if(!(status & Drq)){
1823                         drive->error = Abrt;
1824                         break;
1825                 }
1826                 len = drive->block;
1827                 if(drive->data+len > drive->limit)
1828                         len = drive->limit-drive->data;
1829                 outss(cmdport+Data, drive->data, len/2);
1830                 break;
1831
1832         case Cpkt:
1833         case Ppkt|Pin:
1834         case Ppkt|Pout:
1835                 atapktinterrupt(drive);
1836                 break;
1837
1838         case Crd:
1839         case Cwd:
1840         case Pdma|Pin:
1841         case Pdma|Pout:
1842                 atadmainterrupt(drive, drive->count*drive->secsize);
1843                 break;
1844
1845         case Pnd:
1846         case Preset:
1847                 ctlr->done = 1;
1848                 break;
1849         }
1850         if(ctlr->irqack != nil)
1851                 ctlr->irqack(ctlr);
1852         iunlock(ctlr);
1853
1854         if(drive->error){
1855                 status |= Err;
1856                 ctlr->done = 1;
1857         }
1858
1859         if(ctlr->done){
1860                 ctlr->curdrive = nil;
1861                 drive->status = status;
1862                 wakeup(ctlr);
1863         }
1864 }
1865
1866 typedef struct Lchan Lchan;
1867 struct Lchan {
1868         int     cmdport;
1869         int     ctlport;
1870         int     irq;
1871         int     probed;
1872 };
1873 static Lchan lchan[2] = {
1874         0x1f0,  0x3f4,  IrqATA0,        0,
1875         0x170,  0x374,  IrqATA1,        0,
1876 };
1877
1878 static int
1879 badccru(Pcidev *p)
1880 {
1881         switch(p->did<<16 | p->did){
1882         case 0x439c<<16 | 0x1002:
1883         case 0x438c<<16 | 0x1002:
1884                 print("%T: allowing bad ccru %.2ux for suspected ide controller\n",
1885                         p->tbdf, p->ccru);
1886                 return 1;
1887         default:
1888                 return 0;
1889         }
1890 }
1891
1892 static SDev*
1893 atapnp(void)
1894 {
1895         char *s;
1896         int channel, map, ispc87415, maxio, pi, r, span, maxdma, tbdf;
1897         Ctlr *ctlr;
1898         Pcidev *p;
1899         SDev *sdev, *head, *tail;
1900         void (*irqack)(Ctlr*);
1901
1902         head = tail = nil;
1903         for(p = nil; p = pcimatch(p, 0, 0); ){
1904                 /*
1905                  * Look for devices with the correct class and sub-class
1906                  * code and known device and vendor ID; add native-mode
1907                  * channels to the list to be probed, save info for the
1908                  * compatibility mode channels.
1909                  * Note that the legacy devices should not be considered
1910                  * PCI devices by the interrupt controller.
1911                  * For both native and legacy, save info for busmastering
1912                  * if capable.
1913                  * Promise Ultra ATA/66 (PDC20262) appears to
1914                  * 1) give a sub-class of 'other mass storage controller'
1915                  *    instead of 'IDE controller', regardless of whether it's
1916                  *    the only controller or not;
1917                  * 2) put 0 in the programming interface byte (probably
1918                  *    as a consequence of 1) above).
1919                  * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
1920                  */
1921                 if(p->ccrb != 0x01)
1922                         continue;
1923                 if(!badccru(p))
1924                 if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
1925                         continue;
1926                 pi = p->ccrp;
1927                 map = 3;
1928                 ispc87415 = 0;
1929                 maxdma = 0;
1930                 maxio = 0;
1931                 if(s = getconf("*idemaxio"))
1932                         maxio = atoi(s);
1933                 span = BMspan;
1934                 irqack = nil;
1935
1936                 switch((p->did<<16)|p->vid){
1937                 default:
1938                         continue;
1939
1940                 case (0x0002<<16)|0x100B:       /* NS PC87415 */
1941                         /*
1942                          * Disable interrupts on both channels until
1943                          * after they are probed for drives.
1944                          * This must be called before interrupts are
1945                          * enabled because the IRQ may be shared.
1946                          */
1947                         ispc87415 = 1;
1948                         pcicfgw32(p, 0x40, 0x00000300);
1949                         break;
1950                 case (0x1000<<16)|0x1042:       /* PC-Tech RZ1000 */
1951                         /*
1952                          * Turn off prefetch. Overkill, but cheap.
1953                          */
1954                         r = pcicfgr32(p, 0x40);
1955                         r &= ~0x2000;
1956                         pcicfgw32(p, 0x40, r);
1957                         break;
1958                 case (0x4D38<<16)|0x105A:       /* Promise PDC20262 */
1959                 case (0x4D30<<16)|0x105A:       /* Promise PDC202xx */
1960                 case (0x4D68<<16)|0x105A:       /* Promise PDC20268 */
1961                 case (0x4D69<<16)|0x105A:       /* Promise Ultra/133 TX2 */
1962                 case (0x3373<<16)|0x105A:       /* Promise 20378 RAID */
1963                 case (0x3149<<16)|0x1106:       /* VIA VT8237 SATA/RAID */
1964                 case (0x0415<<16)|0x1106:       /* VIA VT6415 PATA IDE */
1965                 case (0x3112<<16)|0x1095:       /* SiL 3112 SATA/RAID */
1966                         maxio = 15;
1967                         span = 8*1024;
1968                         /*FALLTHROUGH*/
1969                 case (0x3114<<16)|0x1095:       /* SiL 3114 SATA/RAID */
1970                 case (0x0680<<16)|0x1095:       /* SiI 0680/680A PATA133 ATAPI/RAID */
1971                         pi = 0x85;
1972                         break;
1973                 case (0x0004<<16)|0x1103:       /* HighPoint HPT366 */
1974                         pi = 0x85;
1975                         /*
1976                          * Turn off fast interrupt prediction.
1977                          */
1978                         if((r = pcicfgr8(p, 0x51)) & 0x80)
1979                                 pcicfgw8(p, 0x51, r & ~0x80);
1980                         if((r = pcicfgr8(p, 0x55)) & 0x80)
1981                                 pcicfgw8(p, 0x55, r & ~0x80);
1982                         break;
1983                 case (0x0640<<16)|0x1095:       /* CMD 640B */
1984                         /*
1985                          * Bugfix code here...
1986                          */
1987                         break;
1988                 case (0x7441<<16)|0x1022:       /* AMD 768 */
1989                 case (0x7800<<16)|0x1022:
1990                         /*
1991                          * Set:
1992                          *      0x41    prefetch, postwrite;
1993                          *      0x43    FIFO configuration 1/2 and 1/2;
1994                          *      0x44    status register read retry;
1995                          *      0x46    DMA read and end of sector flush.
1996                          */
1997                         r = pcicfgr8(p, 0x41);
1998                         pcicfgw8(p, 0x41, r|0xF0);
1999                         r = pcicfgr8(p, 0x43);
2000                         pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
2001                         r = pcicfgr8(p, 0x44);
2002                         pcicfgw8(p, 0x44, r|0x08);
2003                         r = pcicfgr8(p, 0x46);
2004                         pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
2005                         /*FALLTHROUGH*/
2006                 case (0x01BC<<16)|0x10DE:       /* nVidia nForce1 */
2007                 case (0x0065<<16)|0x10DE:       /* nVidia nForce2 */
2008                 case (0x0085<<16)|0x10DE:       /* nVidia nForce2 MCP */
2009                 case (0x00E3<<16)|0x10DE:       /* nVidia nForce2 250 SATA */
2010                 case (0x00D5<<16)|0x10DE:       /* nVidia nForce3 */
2011                 case (0x00E5<<16)|0x10DE:       /* nVidia nForce3 Pro */
2012                 case (0x00EE<<16)|0x10DE:       /* nVidia nForce3 250 SATA */
2013                 case (0x0035<<16)|0x10DE:       /* nVidia nForce3 MCP */
2014                 case (0x0053<<16)|0x10DE:       /* nVidia nForce4 */
2015                 case (0x0054<<16)|0x10DE:       /* nVidia nForce4 SATA */
2016                 case (0x0055<<16)|0x10DE:       /* nVidia nForce4 SATA */
2017                 case (0x0266<<16)|0x10DE:       /* nVidia nForce4 430 SATA */
2018                 case (0x0265<<16)|0x10DE:       /* nVidia nForce 51 MCP */
2019                 case (0x0267<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2020                 case (0x037f<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2021                 case (0x03ec<<16)|0x10DE:       /* nVidia nForce 61 MCP SATA */
2022                 case (0x03f6<<16)|0x10DE:       /* nVidia nForce 61 MCP PATA */
2023                 case (0x0448<<16)|0x10DE:       /* nVidia nForce 65 MCP SATA */
2024                 case (0x0560<<16)|0x10DE:       /* nVidia nForce 69 MCP SATA */
2025                         /*
2026                          * Ditto, although it may have a different base
2027                          * address for the registers (0x50?).
2028                          */
2029                         /*FALLTHROUGH*/
2030                 case (0x209A<<16)|0x1022:       /* AMD CS5536 */
2031                 case (0x7401<<16)|0x1022:       /* AMD 755 Cobra */
2032                 case (0x7409<<16)|0x1022:       /* AMD 756 Viper */
2033                 case (0x7410<<16)|0x1022:       /* AMD 766 Viper Plus */
2034                 case (0x7469<<16)|0x1022:       /* AMD 3111 */
2035                 case (0x4376<<16)|0x1002:       /* SB4xx pata */
2036                 case (0x4379<<16)|0x1002:       /* SB4xx sata */
2037                 case (0x437a<<16)|0x1002:       /* SB4xx sata ctlr #2 */
2038                 case (0x437c<<16)|0x1002:       /* Rx6xx pata */
2039                 case (0x438c<<16)|0x1002:       /* ATI SB600 PATA */
2040                 case (0x439c<<16)|0x1002:       /* SB7xx pata */
2041                         break;
2042
2043                 case (0x6101<<16)|0x11ab:       /* Marvell PATA */
2044                 case (0x6121<<16)|0x11ab:       /* Marvell PATA */
2045                 case (0x6123<<16)|0x11ab:       /* Marvell PATA */
2046                 case (0x6145<<16)|0x11ab:       /* Marvell PATA */
2047                 case (0x1b4b<<16)|0x91a0:       /* Marvell PATA */
2048                 case (0x1b4b<<16)|0x91a4:       /* Marvell PATA */
2049                         break;
2050
2051                 case (0x0211<<16)|0x1166:       /* ServerWorks IB6566 */
2052                         {
2053                                 Pcidev *sb;
2054
2055                                 sb = pcimatch(nil, 0x1166, 0x0200);
2056                                 if(sb == nil)
2057                                         break;
2058                                 r = pcicfgr32(sb, 0x64);
2059                                 r &= ~0x2000;
2060                                 pcicfgw32(sb, 0x64, r);
2061                         }
2062                         span = 32*1024;
2063                         break;
2064                 case (0x5229<<16)|0x10B9:       /* ALi M1543 */
2065                 case (0x5288<<16)|0x10B9:       /* ALi M5288 SATA */
2066                         /*FALLTHROUGH*/
2067                 case (0x5513<<16)|0x1039:       /* SiS 962 */
2068                 case (0x0646<<16)|0x1095:       /* CMD 646 */
2069                 case (0x0571<<16)|0x1106:       /* VIA 82C686 */
2070                 case (0x9001<<16)|0x1106:       /* VIA chipset in VIA PV530 */
2071                 case (0x0502<<16)|0x100b:       /* National Semiconductor SC1100/SCx200 */
2072                         break;
2073                 case (0x2360<<16)|0x197b:       /* jmicron jmb360 */
2074                 case (0x2361<<16)|0x197b:       /* jmicron jmb361 */
2075                 case (0x2363<<16)|0x197b:       /* jmicron jmb363 */
2076                 case (0x2365<<16)|0x197b:       /* jmicron jmb365 */
2077                 case (0x2366<<16)|0x197b:       /* jmicron jmb366 */
2078                 case (0x2368<<16)|0x197b:       /* jmicron jmb368 */
2079                         break;
2080                 case (0x7010<<16)|0x8086:       /* 82371SB (PIIX3) */
2081                 case (0x1230<<16)|0x8086:       /* 82371FB (PIIX) */
2082                 case (0x7111<<16)|0x8086:       /* 82371[AE]B (PIIX4[E]) */
2083                         maxdma = 0x20000;
2084                         break;
2085                 case (0x1c00<<16)|0x8086:       /* SERIES6 SATA */
2086                 case (0x1c01<<16)|0x8086:       /* SERIES6 SATA */
2087                 case (0x1c08<<16)|0x8086:       /* SERIES6 SATA */
2088                 case (0x1c09<<16)|0x8086:       /* SERIES6 SATA */
2089                 case (0x2411<<16)|0x8086:       /* 82801AA (ICH) */
2090                 case (0x2421<<16)|0x8086:       /* 82801AB (ICH0) */
2091                 case (0x244A<<16)|0x8086:       /* 82801BA (ICH2, Mobile) */
2092                 case (0x244B<<16)|0x8086:       /* 82801BA (ICH2, High-End) */
2093                 case (0x248A<<16)|0x8086:       /* 82801CA (ICH3, Mobile) */
2094                 case (0x248B<<16)|0x8086:       /* 82801CA (ICH3, High-End) */
2095                 case (0x24CA<<16)|0x8086:       /* 82801DBM (ICH4, Mobile) */
2096                 case (0x24CB<<16)|0x8086:       /* 82801DB (ICH4, High-End) */
2097                 case (0x24D1<<16)|0x8086:       /* 82801er (ich5) */
2098                 case (0x24DB<<16)|0x8086:       /* 82801EB (ICH5) */
2099                 case (0x25A2<<16)|0x8086:       /* 6300ESB pata */
2100                 case (0x25A3<<16)|0x8086:       /* 6300ESB (E7210) */
2101                 case (0x266F<<16)|0x8086:       /* 82801FB (ICH6) */
2102                 case (0x2651<<16)|0x8086:       /* 82801FB (ICH6) */
2103                 case (0x2653<<16)|0x8086:       /* 82801FBM (ICH6, Mobile) */
2104                 case (0x269e<<16)|0x8086:       /* 63xxESB (intel 5000) */
2105                 case (0x27DF<<16)|0x8086:       /* 82801G PATA (ICH7) */
2106                 case (0x27C0<<16)|0x8086:       /* 82801GB SATA (ICH7) */
2107                 case (0x27C4<<16)|0x8086:       /* 82801GBM SATA (ICH7) */
2108                 case (0x27C5<<16)|0x8086:       /* 82801GBM SATA AHCI (ICH7) */
2109                 case (0x2850<<16)|0x8086:       /* 82801HBM/HEM PATA */
2110                 case (0x2820<<16)|0x8086:       /* 82801HB/HR/HH/HO SATA IDE */
2111                 case (0x2828<<16)|0x8086:       /* 82801HBM SATA (ICH8-M) */
2112                 case (0x2829<<16)|0x8086:       /* 82801HBM SATA AHCI (ICH8-M) */
2113                 case (0x2920<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-3 */
2114                 case (0x2921<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-1 */
2115                 case (0x2926<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 4-5 */
2116                 case (0x2928<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1 */
2117                 case (0x2929<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1, 4-5 */
2118                 case (0x292d<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 4-5*/
2119                 case (0x3a20<<16)|0x8086:       /* 82801ji (ich10) */
2120                 case (0x3a26<<16)|0x8086:       /* 82801ji (ich10) */
2121                 case (0x3b20<<16)|0x8086:       /* 34x0 (pch) port 0-3 */
2122                 case (0x3b21<<16)|0x8086:       /* 34x0 (pch) port 4-5 */
2123                 case (0x3b28<<16)|0x8086:       /* 34x0pm (pch) port 0-1, 4-5 */
2124                 case (0x3b2e<<16)|0x8086:       /* 34x0pm (pch) port 0-3 */
2125                         map = 0;
2126                         if(pcicfgr16(p, 0x40) & 0x8000)
2127                                 map |= 1;
2128                         if(pcicfgr16(p, 0x42) & 0x8000)
2129                                 map |= 2;
2130                         irqack = ichirqack;
2131                         break;
2132                 case (0x811a<<16)|0x8086:       /* Intel SCH (Poulsbo) */
2133                         map = 1;
2134                         irqack = ichirqack;
2135                         break;
2136                 }
2137                 for(channel = 0; channel < 2; channel++){
2138                         if((map & 1<<channel) == 0)
2139                                 continue;
2140                         if(pi & 1<<2*channel){
2141                                 sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
2142                                                 p->mem[1+2*channel].bar & ~0x01,
2143                                                 p->intl, 3);
2144                                 tbdf = p->tbdf;
2145                         }
2146                         else if(lchan[channel].probed == 0){
2147                                 sdev = ataprobe(lchan[channel].cmdport,
2148                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2149                                 lchan[channel].probed = 1;
2150                                 tbdf = BUSUNKNOWN;
2151                         }
2152                         else
2153                                 continue;
2154                         if(sdev == nil)
2155                                 continue;
2156                         ctlr = sdev->ctlr;
2157                         if(ispc87415) {
2158                                 ctlr->ienable = pc87415ienable;
2159                                 print("pc87415disable: not yet implemented\n");
2160                         }
2161                         ctlr->tbdf = tbdf;
2162                         ctlr->pcidev = p;
2163                         ctlr->maxio = maxio;
2164                         ctlr->maxdma = maxdma;
2165                         ctlr->span = span;
2166                         ctlr->irqack = irqack;
2167                         if((pi & 0x80) && (p->mem[4].bar & 0x01))
2168                                 ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
2169                         if(head != nil)
2170                                 tail->next = sdev;
2171                         else
2172                                 head = sdev;
2173                         tail = sdev;
2174                 }
2175         }
2176
2177         if(lchan[0].probed + lchan[1].probed == 0)
2178                 for(channel = 0; channel < 2; channel++){
2179                         sdev = nil;
2180                         if(lchan[channel].probed == 0){
2181         //                      print("sdide: blind probe %.3ux\n", lchan[channel].cmdport);
2182                                 sdev = ataprobe(lchan[channel].cmdport,
2183                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2184                                 lchan[channel].probed = 1;
2185                         }
2186                         if(sdev == nil)
2187                                 continue;
2188                         if(head != nil)
2189                                 tail->next = sdev;
2190                         else
2191                                 head = sdev;
2192                         tail = sdev;
2193                 }
2194
2195 if(0){
2196         int port;
2197         ISAConf isa;
2198
2199         /*
2200          * Hack for PCMCIA drives.
2201          * This will be tidied once we figure out how the whole
2202          * removeable device thing is going to work.
2203          */
2204         memset(&isa, 0, sizeof(isa));
2205         isa.port = 0x180;               /* change this for your machine */
2206         isa.irq = 11;                   /* change this for your machine */
2207
2208         port = isa.port+0x0C;
2209         channel = pcmspecial("MK2001MPL", &isa);
2210         if(channel == -1)
2211                 channel = pcmspecial("SunDisk", &isa);
2212         if(channel == -1){
2213                 isa.irq = 10;
2214                 channel = pcmspecial("CF", &isa);
2215         }
2216         if(channel == -1){
2217                 isa.irq = 10;
2218                 channel = pcmspecial("OLYMPUS", &isa);
2219         }
2220         if(channel == -1){
2221                 port = isa.port+0x204;
2222                 channel = pcmspecial("ATA/ATAPI", &isa);
2223         }
2224         if(channel >= 0 && (sdev = ataprobe(isa.port, port, isa.irq, 3)) != nil){
2225                 if(head != nil)
2226                         tail->next = sdev;
2227                 else
2228                         head = sdev;
2229         }
2230 }
2231         return head;
2232 }
2233
2234 static void
2235 atadmaclr(Ctlr *ctlr)
2236 {
2237         int bmiba, bmisx;
2238
2239         if(ctlr->curdrive)
2240                 ataabort(ctlr->curdrive, 1);
2241         bmiba = ctlr->bmiba;
2242         if(bmiba == 0)
2243                 return;
2244         atadmastop(ctlr);
2245         outl(bmiba+Bmidtpx, 0);
2246         bmisx = inb(bmiba+Bmisx) & ~Bmidea;
2247         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
2248 //      pciintst(ctlr->pcidev);
2249 }
2250
2251 static int
2252 ataenable(SDev* sdev)
2253 {
2254         Ctlr *ctlr;
2255         char name[32];
2256
2257         ctlr = sdev->ctlr;
2258         if(ctlr->bmiba){
2259                 atadmaclr(ctlr);
2260                 if(ctlr->pcidev != nil)
2261                         pcisetbme(ctlr->pcidev);
2262                 /* Intel SCH requires 8 byte alignment, though datasheet says 4 m( */
2263                 ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 8, 0, 64*1024);
2264         }
2265         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2266         intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2267         outb(ctlr->ctlport+Dc, 0);
2268         if(ctlr->ienable)
2269                 ctlr->ienable(ctlr);
2270         return 1;
2271 }
2272
2273 static int
2274 atadisable(SDev *sdev)
2275 {
2276         Ctlr *ctlr;
2277         char name[32];
2278
2279         ctlr = sdev->ctlr;
2280         outb(ctlr->ctlport+Dc, Nien);           /* disable interrupts */
2281         if (ctlr->idisable)
2282                 ctlr->idisable(ctlr);
2283         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2284         intrdisable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2285         if(ctlr->bmiba) {
2286 //              atadmaclr(ctlr);
2287                 if (ctlr->pcidev)
2288                         pciclrbme(ctlr->pcidev);
2289                 free(ctlr->prdt);
2290                 ctlr->prdt = nil;
2291         }
2292         return 0;
2293 }
2294
2295 static int
2296 ataonline(SDunit *unit)
2297 {
2298         Drive *drive;
2299         Ctlr *ctlr;
2300         int ret;
2301
2302         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2303                 return 0;
2304         ret = 1;
2305         drive = ctlr->drive[unit->subno];
2306         if((drive->flags & Online) == 0){
2307                 drive->flags |= Online;
2308                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2309                 ret = 2;
2310         }
2311         if(drive->feat & Datapi){
2312                 ulong dma;
2313
2314                 dma = drive->dmactl;
2315                 drive->dmactl = 0;
2316                 ret = scsionline(unit);
2317                 drive->dmactl = dma;
2318         } else {
2319                 unit->sectors = drive->sectors;
2320                 unit->secsize = drive->secsize;
2321         }
2322         return ret;
2323 }
2324
2325 static int
2326 atarctl(SDunit* unit, char* p, int l)
2327 {
2328         Ctlr *ctlr;
2329         Drive *drive;
2330         char *e, *op;
2331
2332         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2333                 return 0;
2334         drive = ctlr->drive[unit->subno];
2335
2336         e = p+l;
2337         op = p;
2338         qlock(drive);
2339         p = seprint(p, e, "config %4.4uX capabilities %4.4uX", drive->info[Iconfig], drive->info[Icapabilities]);
2340         if(drive->dma)
2341                 p = seprint(p, e, " dma %8.8uX dmactl %8.8uX", drive->dma, drive->dmactl);
2342         if(drive->rwm)
2343                 p = seprint(p, e, " rwm %ud rwmctl %ud", drive->rwm, drive->rwmctl);
2344         if(drive->feat & Dllba)
2345                 p = seprint(p, e, " lba48always %s", (drive->flags&Lba48always) ? "on" : "off");
2346         p = seprint(p, e, "\n");
2347         p = seprint(p, e, "model        %s\n", drive->model);
2348         p = seprint(p, e, "serial       %s\n", drive->serial);
2349         p = seprint(p, e, "firm %s\n", drive->firmware);
2350         p = seprint(p, e, "feat ");
2351         p = pflag(p, e, drive);
2352         if(drive->sectors){
2353                 p = seprint(p, e, "geometry %llud %d", drive->sectors, drive->secsize);
2354                 if(drive->pkt == 0 && (drive->feat & Dlba) == 0)
2355                         p = seprint(p, e, " %d %d %d", drive->c, drive->h, drive->s);
2356                 p = seprint(p, e, "\n");
2357                 p = seprint(p, e, "alignment %d %d\n",
2358                         drive->secsize<<drive->physshift, drive->physalign);
2359         }
2360         p = seprint(p, e, "missirq      %ud\n", drive->missirq);
2361         p = seprint(p, e, "sloop        %ud\n", drive->spurloop);
2362         p = seprint(p, e, "irq  %ud %ud\n", ctlr->nrq, drive->irq);
2363         p = seprint(p, e, "bsy  %ud %ud\n", ctlr->bsy, drive->bsy);
2364         p = seprint(p, e, "nildrive     %ud\n", ctlr->nildrive);
2365         qunlock(drive);
2366
2367         return p - op;
2368 }
2369
2370 static int
2371 atawctl(SDunit* unit, Cmdbuf* cb)
2372 {
2373         Ctlr *ctlr;
2374         Drive *drive;
2375
2376         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2377                 return 0;
2378         drive = ctlr->drive[unit->subno];
2379
2380         qlock(drive);
2381         if(waserror()){
2382                 qunlock(drive);
2383                 nexterror();
2384         }
2385
2386         /*
2387          * Dma and rwm control is passive at the moment,
2388          * i.e. it is assumed that the hardware is set up
2389          * correctly already either by the BIOS or when
2390          * the drive was initially identified.
2391          */
2392         if(strcmp(cb->f[0], "dma") == 0){
2393                 if(cb->nf != 2 || drive->dma == 0)
2394                         error(Ebadctl);
2395                 if(strcmp(cb->f[1], "on") == 0)
2396                         drive->dmactl = drive->dma;
2397                 else if(strcmp(cb->f[1], "off") == 0)
2398                         drive->dmactl = 0;
2399                 else
2400                         error(Ebadctl);
2401         }
2402         else if(strcmp(cb->f[0], "rwm") == 0){
2403                 if(cb->nf != 2 || drive->rwm == 0)
2404                         error(Ebadctl);
2405                 if(strcmp(cb->f[1], "on") == 0)
2406                         drive->rwmctl = drive->rwm;
2407                 else if(strcmp(cb->f[1], "off") == 0)
2408                         drive->rwmctl = 0;
2409                 else
2410                         error(Ebadctl);
2411         }
2412         else if(strcmp(cb->f[0], "lba48always") == 0){
2413                 if(cb->nf != 2 || !(drive->feat & Dllba))
2414                         error(Ebadctl);
2415                 if(strcmp(cb->f[1], "on") == 0)
2416                         drive->flags |= Lba48always;
2417                 else if(strcmp(cb->f[1], "off") == 0)
2418                         drive->flags &= ~Lba48always;
2419                 else
2420                         error(Ebadctl);
2421         }
2422         else if(strcmp(cb->f[0], "identify") == 0){
2423                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2424         }
2425         else
2426                 error(Ebadctl);
2427         qunlock(drive);
2428         poperror();
2429
2430         return 0;
2431 }
2432
2433 SDifc sdideifc = {
2434         "ide",                          /* name */
2435
2436         atapnp,                         /* pnp */
2437         nil,                            /* legacy */
2438         ataenable,                      /* enable */
2439         atadisable,                     /* disable */
2440
2441         scsiverify,                     /* verify */
2442         ataonline,                      /* online */
2443         atario,                         /* rio */
2444         atarctl,                        /* rctl */
2445         atawctl,                        /* wctl */
2446
2447         scsibio,                        /* bio */
2448         ataprobew,                      /* probe */
2449         ataclear,                       /* clear */
2450         atastat,                        /* rtopctl */
2451         nil,                            /* wtopctl */
2452         ataataio,
2453 };