2 #include "../port/lib.h"
8 #include "../port/error.h"
10 #include "../port/sd.h"
13 #define HOWMANY(x, y) (((x)+((y)-1))/(y))
14 #define ROUNDUP(x, y) (HOWMANY((x), (y))*(y))
15 #define uprint(...) snprint(up->genbuf, sizeof up->genbuf, __VA_ARGS__);
16 #pragma varargck argpos atadebug 3
18 extern SDifc sdideifc;
21 DbgCONFIG = 0x0001, /* detected drive config info */
22 DbgIDENTIFY = 0x0002, /* detected drive identify info */
23 DbgSTATE = 0x0004, /* dump state on panic */
24 DbgPROBE = 0x0008, /* trace device probing */
25 DbgDEBUG = 0x0080, /* the current problem... */
26 DbgINL = 0x0100, /* That Inil20+ message we hate */
27 Dbg48BIT = 0x0200, /* 48-bit LBA */
28 DbgBsy = 0x0400, /* interrupt but Bsy (shared IRQ) */
29 DbgAtazz = 0x0800, /* debug raw ata io */
31 #define DEBUG (DbgDEBUG|DbgSTATE)
33 enum { /* I/O ports */
35 Error = 1, /* (read) */
36 Features = 1, /* (write) */
37 Count = 2, /* sector count<7-0>, sector count<15-8> */
38 Ir = 2, /* interrupt reason (PACKET) */
39 Sector = 3, /* sector number */
40 Lbalo = 3, /* LBA<7-0>, LBA<31-24> */
41 Cyllo = 4, /* cylinder low */
42 Bytelo = 4, /* byte count low (PACKET) */
43 Lbamid = 4, /* LBA<15-8>, LBA<39-32> */
44 Cylhi = 5, /* cylinder high */
45 Bytehi = 5, /* byte count hi (PACKET) */
46 Lbahi = 5, /* LBA<23-16>, LBA<47-40> */
47 Dh = 6, /* Device/Head, LBA<27-24> */
48 Status = 7, /* (read) */
49 Command = 7, /* (write) */
51 As = 2, /* Alternate Status (read) */
52 Dc = 2, /* Device Control (write) */
56 Med = 0x01, /* Media error */
57 Ili = 0x01, /* command set specific (PACKET) */
58 Nm = 0x02, /* No Media */
59 Eom = 0x02, /* command set specific (PACKET) */
60 Abrt = 0x04, /* Aborted command */
61 Mcr = 0x08, /* Media Change Request */
62 Idnf = 0x10, /* no user-accessible address */
63 Mc = 0x20, /* Media Change */
64 Unc = 0x40, /* Uncorrectable data error */
65 Wp = 0x40, /* Write Protect */
66 Icrc = 0x80, /* Interface CRC error */
70 Dma = 0x01, /* data transfer via DMA (PACKET) */
71 Ovl = 0x02, /* command overlapped (PACKET) */
74 enum { /* Interrupt Reason */
75 Cd = 0x01, /* Command/Data */
76 Io = 0x02, /* I/O direction */
77 Rel = 0x04, /* Bus Release */
80 enum { /* Device/Head */
81 Dev0 = 0xA0, /* Master */
82 Dev1 = 0xB0, /* Slave */
84 Lba = 0x40, /* LBA mode */
87 enum { /* Status, Alternate Status */
88 Err = 0x01, /* Error */
89 Chk = 0x01, /* Check error (PACKET) */
90 Drq = 0x08, /* Data Request */
91 Dsc = 0x10, /* Device Seek Complete */
92 Serv = 0x10, /* Service */
93 Df = 0x20, /* Device Fault */
94 Dmrd = 0x20, /* DMA ready (PACKET) */
95 Drdy = 0x40, /* Device Ready */
96 Bsy = 0x80, /* Busy */
100 Cnop = 0x00, /* NOP */
101 Crs = 0x20, /* Read Sectors */
102 Crs48 = 0x24, /* Read Sectors Ext */
103 Crd48 = 0x25, /* Read w/ DMA Ext */
104 Crsm48 = 0x29, /* Read Multiple Ext */
105 Cws = 0x30, /* Write Sectors */
106 Cws48 = 0x34, /* Write Sectors Ext */
107 Cwd48 = 0x35, /* Write w/ DMA Ext */
108 Cwsm48 = 0x39, /* Write Multiple Ext */
109 Cedd = 0x90, /* Execute Device Diagnostics */
110 Cpkt = 0xA0, /* Packet */
111 Cidpkt = 0xA1, /* Identify Packet Device */
112 Crsm = 0xC4, /* Read Multiple */
113 Cwsm = 0xC5, /* Write Multiple */
114 Csm = 0xC6, /* Set Multiple */
115 Crd = 0xC8, /* Read DMA */
116 Cwd = 0xCA, /* Write DMA */
117 Cid = 0xEC, /* Identify Device */
120 enum { /* Device Control */
121 Nien = 0x02, /* (not) Interrupt Enable */
122 Srst = 0x04, /* Software Reset */
123 Hob = 0x80, /* High Order Bit [sic] */
126 enum { /* PCI Configuration Registers */
127 Bmiba = 0x20, /* Bus Master Interface Base Address */
128 Idetim = 0x40, /* IE Timing */
129 Sidetim = 0x44, /* Slave IE Timing */
130 Udmactl = 0x48, /* Ultra DMA/33 Control */
131 Udmatim = 0x4A, /* Ultra DMA/33 Timing */
134 enum { /* Bus Master IDE I/O Ports */
135 Bmicx = 0, /* Command */
136 Bmisx = 2, /* Status */
137 Bmidtpx = 4, /* Descriptor Table Pointer */
141 Ssbm = 0x01, /* Start/Stop Bus Master */
142 Rwcon = 0x08, /* Read/Write Control */
146 Bmidea = 0x01, /* Bus Master IDE Active */
147 Idedmae = 0x02, /* IDE DMA Error (R/WC) */
148 Ideints = 0x04, /* IDE Interrupt Status (R/WC) */
149 Dma0cap = 0x20, /* Drive 0 DMA Capable */
150 Dma1cap = 0x40, /* Drive 0 DMA Capable */
152 enum { /* Physical Region Descriptor */
153 PrdEOT = 0x80000000, /* End of Transfer */
156 enum { /* offsets into the identify info. */
157 Iconfig = 0, /* general configuration */
158 Ilcyl = 1, /* logical cylinders */
159 Ilhead = 3, /* logical heads */
160 Ilsec = 6, /* logical sectors per logical track */
161 Iserial = 10, /* serial number */
162 Ifirmware = 23, /* firmware revision */
163 Imodel = 27, /* model number */
164 Imaxrwm = 47, /* max. read/write multiple sectors */
165 Icapabilities = 49, /* capabilities */
166 Istandby = 50, /* device specific standby timer */
167 Ipiomode = 51, /* PIO data transfer mode number */
169 Iccyl = 54, /* cylinders if (valid&0x01) */
170 Ichead = 55, /* heads if (valid&0x01) */
171 Icsec = 56, /* sectors if (valid&0x01) */
172 Iccap = 57, /* capacity if (valid&0x01) */
173 Irwm = 59, /* read/write multiple */
174 Ilba = 60, /* LBA size */
175 Imwdma = 63, /* multiword DMA mode */
176 Iapiomode = 64, /* advanced PIO modes supported */
177 Iminmwdma = 65, /* min. multiword DMA cycle time */
178 Irecmwdma = 66, /* rec. multiword DMA cycle time */
179 Iminpio = 67, /* min. PIO cycle w/o flow control */
180 Iminiordy = 68, /* min. PIO cycle with IORDY */
181 Ipcktbr = 71, /* time from PACKET to bus release */
182 Iserbsy = 72, /* time from SERVICE to !Bsy */
183 Iqdepth = 75, /* max. queue depth */
184 Imajor = 80, /* major version number */
185 Iminor = 81, /* minor version number */
186 Icsfs = 82, /* command set/feature supported */
187 Icsfe = 85, /* command set/feature enabled */
188 Iudma = 88, /* ultra DMA mode */
189 Ierase = 89, /* time for security erase */
190 Ieerase = 90, /* time for enhanced security erase */
191 Ipower = 91, /* current advanced power management */
192 Ilba48 = 100, /* 48-bit LBA size (64 bits in 100-103) */
193 Irmsn = 127, /* removable status notification */
194 Isecstat = 128, /* security status */
195 Icfapwr = 160, /* CFA power mode */
196 Imediaserial = 176, /* current media serial number */
197 Icksum = 255, /* checksum */
200 enum { /* bit masks for config identify info */
201 Mpktsz = 0x0003, /* packet command size */
202 Mincomplete = 0x0004, /* incomplete information */
203 Mdrq = 0x0060, /* DRQ type */
204 Mrmdev = 0x0080, /* device is removable */
205 Mtype = 0x1F00, /* device type */
206 Mproto = 0x8000, /* command protocol */
209 enum { /* bit masks for capabilities identify info */
210 Mdma = 0x0100, /* DMA supported */
211 Mlba = 0x0200, /* LBA supported */
212 Mnoiordy = 0x0400, /* IORDY may be disabled */
213 Miordy = 0x0800, /* IORDY supported */
214 Msoftrst = 0x1000, /* needs soft reset when Bsy */
215 Mqueueing = 0x4000, /* queueing overlap supported */
216 Midma = 0x8000, /* interleaved DMA supported */
219 enum { /* bit masks for supported/enabled features */
241 Mautoacoustic = 0x0200,
246 Msmarterror = 0x0001,
247 Msmartselftest = 0x0002,
253 typedef struct Ctlr Ctlr;
254 typedef struct Drive Drive;
256 typedef struct Prd { /* Physical Region Descriptor */
257 ulong pa; /* Physical Base Address */
262 BMspan = 32*1024, /* must be power of 2 <= 64*1024 */
264 Nprd = SDmaxio/BMspan+2,
267 typedef struct Ctlr {
272 int bmiba; /* bus master interface base address */
273 int maxio; /* sector count transfer maximum */
274 int span; /* don't span this boundary with dma */
275 int maxdma; /* don't attempt dma transfers bigger than this */
278 void (*ienable)(Ctlr*);
279 void (*idisable)(Ctlr*);
284 Prd* prdt; /* physical region descriptor table */
285 void (*irqack)(Ctlr*);
287 QLock; /* current command */
289 int command; /* last command issued (debugging) */
296 Lock; /* register access */
299 typedef struct Drive {
307 int dma; /* DMA R/W possible */
309 int rwm; /* read/write multiple possible */
312 int pkt; /* PACKET device, length of pktcmd */
314 int pktdma; /* this PACKET command using dma */
322 QLock; /* drive access */
323 int command; /* current command */
328 int count; /* sectors */
329 int block; /* R/W bytes per block */
332 int flags; /* internal flags */
339 enum { /* internal flags */
340 Lba48always = 0x2, /* ... */
341 Online = 0x4, /* drive onlined */
345 pc87415ienable(Ctlr* ctlr)
354 x = pcicfgr32(p, 0x40);
355 if(ctlr->cmdport == p->mem[0].bar)
359 pcicfgw32(p, 0x40, x);
363 atadumpstate(Drive* drive, SDreq *r, uvlong lba, int count)
371 if(!(DEBUG & DbgSTATE))
375 print("command %2.2uX\n", ctlr->command);
376 print("data %8.8p limit %8.8p dlen %d status %uX error %uX\n",
377 drive->data, drive->limit, drive->dlen,
378 drive->status, drive->error);
380 clba = fisrw(nil, r->cmd, &ccnt);
382 sdfakescsirw(r, &clba, &ccnt, 0);
383 print("lba %llud -> %llud, count %d -> %d (%d)\n",
384 clba, lba, ccnt, count, drive->count);
385 if(!(inb(ctlr->ctlport+As) & Bsy)){
386 for(i = 1; i < 7; i++)
387 print(" 0x%2.2uX", inb(ctlr->cmdport+i));
388 print(" 0x%2.2uX\n", inb(ctlr->ctlport+As));
390 if(drive->command == Cwd || drive->command == Crd
391 || drive->command == (Pdma|Pin) || drive->command == (Pdma|Pout)){
394 print("bmicx %2.2uX bmisx %2.2uX prdt %8.8p\n",
395 inb(bmiba+Bmicx), inb(bmiba+Bmisx), prd);
397 print("pa 0x%8.8luX count %8.8uX\n",
398 prd->pa, prd->count);
399 if(prd->count & PrdEOT)
404 if(ctlr->pcidev && ctlr->pcidev->vid == 0x8086){
406 print("0x40: %4.4uX 0x42: %4.4uX ",
407 pcicfgr16(p, 0x40), pcicfgr16(p, 0x42));
408 print("0x48: %2.2uX\n", pcicfgr8(p, 0x48));
409 print("0x4A: %4.4uX\n", pcicfgr16(p, 0x4A));
414 atadebug(int cmdport, int ctlport, char* fmt, ...)
416 char *p, *e, buf[PRINTSIZE];
420 if(!(DEBUG & DbgPROBE))
424 e = buf + sizeof buf;
426 p = vseprint(p, e, fmt, arg);
430 if(p > buf && p[-1] == '\n')
432 p = seprint(p, e, " ataregs 0x%uX:", cmdport);
433 for(i = Features; i < Command; i++)
434 p = seprint(p, e, " 0x%2.2uX", inb(cmdport+i));
436 p = seprint(p, e, " 0x%2.2uX", inb(ctlport+As));
437 p = seprint(p, e, "\n");
439 putstrn(buf, p - buf);
443 ataready(int cmdport, int ctlport, int dev, int reset, int ready, int m)
447 atadebug(cmdport, ctlport, "ataready: dev %ux:%ux reset %ux ready %ux",
448 cmdport, dev, reset, ready);
452 * Wait for the controller to become not busy and
453 * possibly for a status bit to become true (usually
454 * Drdy). Must change to the appropriate device
455 * register set if necessary before testing for ready.
456 * Always run through the loop at least once so it
457 * can be used as a test for !Bsy.
459 as = inb(ctlport+As);
464 outb(cmdport+Dh, dev);
467 else if(ready == 0 || (as & ready)){
468 atadebug(0, 0, "ataready: %d:%d %#.2ux\n", m, m0, as);
473 atadebug(0, 0, "ataready: timeout %d %#.2ux\n", m0, as);
480 return ((Ctlr*)arg)->done;
484 atarwmmode(Drive* drive, int cmdport, int ctlport, int dev)
488 maxrwm = drive->info[Imaxrwm] & 0xFF;
493 * Sometimes drives come up with the current count set
494 * to 0; if so, set a suitable value, otherwise believe
495 * the value in Irwm if the 0x100 bit is set.
497 if(drive->info[Irwm] & 0x100)
498 rwm = drive->info[Irwm] & 0xFF;
505 if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 102*1000) < 0)
507 outb(cmdport+Count, rwm);
508 outb(cmdport+Command, Csm);
510 as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 1000);
512 if(as < 0 || (as & (Df|Err)))
521 atadmamode(SDunit *unit, Drive* drive)
527 * Check if any DMA mode enabled.
528 * Assumes the BIOS has picked and enabled the best.
529 * This is completely passive at the moment, no attempt is
530 * made to ensure the hardware is correctly set up.
532 dma = drive->info[Imwdma] & 0x0707;
533 drive->dma = (dma>>8) & dma;
534 if(drive->dma == 0 && (drive->info[Ivalid] & 0x04)){
535 dma = drive->info[Iudma] & 0x7F7F;
536 drive->dma = (dma>>8) & dma;
538 drive->dma |= 'U'<<16;
541 snprint(buf, sizeof buf, "*%sdma", unit->name);
543 if((s && !strcmp(s, "on")) || (!s && !getconf("*nodma")))
544 drive->dmactl = drive->dma;
550 ataidentify(Ctlr*, int cmdport, int ctlport, int dev, int pkt, void* info)
552 int as, command, drdy;
563 as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
566 outb(cmdport+Command, command);
569 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
570 if(as < 0 || (as & Err))
572 memset(info, 0, 512);
573 inss(cmdport+Data, info, 256);
579 atadrive(SDunit *unit, Drive *drive, int cmdport, int ctlport, int dev)
581 int as, pkt, rlo, rhi;
582 uchar buf[512], oserial[21];
586 if(DEBUG & DbgIDENTIFY)
587 print("identify: port %ux dev %.2ux\n", cmdport, dev & ~Lba);
589 atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
591 osectors = drive->sectors;
592 memmove(oserial, drive->serial, sizeof drive->serial);
596 memset(oserial, 0, sizeof drive->serial);
599 /* detect if theres a drive present */
600 outb(cmdport+Dh, dev & ~Lba);
602 outb(cmdport+Cyllo, 0xAA);
603 outb(cmdport+Cylhi, 0x55);
604 outb(cmdport+Sector, 0xFF);
605 rlo = inb(cmdport+Cyllo);
606 rhi = inb(cmdport+Cylhi);
607 if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55))
613 as = ataidentify(ctlr, cmdport, ctlport, dev, pkt, buf);
624 if((drive = malloc(sizeof(Drive))) == nil)
626 drive->serial[0] = ' ';
630 memmove(drive->info, buf, sizeof(drive->info));
632 setfissig(drive, pkt ? 0xeb140000 : 0x0101);
633 drive->sectors = idfeat(drive, drive->info);
634 drive->secsize = idss(drive, drive->info);
636 idmove(drive->serial, drive->info+10, 20);
637 idmove(drive->firmware, drive->info+23, 8);
638 idmove(drive->model, drive->info+27, 40);
640 memset(unit->inquiry, 0, sizeof unit->inquiry);
641 unit->inquiry[2] = 2;
642 unit->inquiry[3] = 2;
643 unit->inquiry[4] = sizeof unit->inquiry - 4;
644 memmove(unit->inquiry+8, drive->model, 40);
649 if(drive->feat & Datapi16)
653 if(drive->feat & Dlba)
655 atarwmmode(drive, cmdport, ctlport, dev);
657 atadmamode(unit, drive);
659 if(osectors != 0 && memcmp(oserial, drive->serial, sizeof oserial) != 0)
663 if(DEBUG & DbgCONFIG){
664 print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
665 dev, cmdport, drive->info[Iconfig], drive->info[Icapabilities]);
666 print(" mwdma %4.4uX", drive->info[Imwdma]);
667 if(drive->info[Ivalid] & 0x04)
668 print(" udma %4.4uX", drive->info[Iudma]);
669 print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
670 if(drive->feat&Dllba)
671 print("\tLLBA sectors %llud", drive->sectors);
684 * Srst is a big stick and may cause problems if further
685 * commands are tried before the drives become ready again.
686 * Also, there will be problems here if overlapped commands
687 * are ever supported.
689 dc0 = inb(ctlport+Dc);
691 outb(ctlport+Dc, Srst|dc0);
693 outb(ctlport+Dc, dc0);
698 ataprobe(int cmdport, int ctlport, int irq, int map)
700 static int nonlegacy = 'C';
704 if(ioalloc(cmdport, 8, 0, "atacmd") < 0) {
705 print("ataprobe: Cannot allocate %X\n", cmdport);
708 if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
709 print("ataprobe: Cannot allocate %X\n", ctlport + As);
714 if((ctlr = malloc(sizeof(Ctlr))) == nil)
716 if((sdev = malloc(sizeof(SDev))) == nil){
721 if((map & 2) && (ctlr->drive[1] = atadrive(0, 0, cmdport, ctlport, Dev1)))
722 ctlr->drive[1]->ctlr = ctlr;
723 if((map & 1) && (ctlr->drive[0] = atadrive(0, 0, cmdport, ctlport, Dev0)))
724 ctlr->drive[0]->ctlr = ctlr;
726 if(ctlr->drive[0] == nil && ctlr->drive[1] == nil){
727 free(ctlr->drive[0]);
728 free(ctlr->drive[1]);
734 ctlr->cmdport = cmdport;
735 ctlr->ctlport = ctlport;
737 ctlr->tbdf = BUSUNKNOWN;
738 ctlr->command = Cnop; /* debugging */
742 sdev->idno = nonlegacy;
753 sdev->ifc = &sdideifc;
773 iofree(ctlr->cmdport);
774 iofree(ctlr->ctlport + As);
777 free(ctlr->drive[0]);
779 free(ctlr->drive[1]);
791 atastat(SDev *sdev, char *p, char *e)
796 // return seprint(p, e, "%s ata port %X ctl %X irq %d %T\n",
797 // sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq, ctlr->tbdf);
798 return seprint(p, e, "%s ata port %X ctl %X irq %d\n",
799 sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq);
803 ataprobew(DevConf *cf)
811 memset(&isa, 0, sizeof isa);
812 isa.port = cf->ports[0].port;
813 isa.irq = cf->intnum;
814 if((p=strchr(cf->type, '/')) == nil || pcmspecial(p+1, &isa) < 0)
815 error("cannot find controller");
817 return ataprobe(cf->ports[0].port, cf->ports[1].port, cf->intnum, 3);
820 static void atainterrupt(Ureg*, void*);
823 iowait(Drive *drive, int ms, int interrupt)
829 if(drive->missirq > 10)
832 for(msec = 0; msec < ms; msec += step){
836 tsleep(ctlr, atadone, ctlr, step);
840 atainterrupt(nil, ctlr);
842 if(drive->missirq++ < 3)
843 print("ide: caught missed irq\n");
852 atanop(Drive* drive, int subcommand)
855 int as, cmdport, ctlport, timeo;
858 * Attempt to abort a command by using NOP.
859 * In response, the drive is supposed to set Abrt
860 * in the Error register, set (Drdy|Err) in Status
861 * and clear Bsy when done. However, some drives
862 * (e.g. ATAPI Zip) just go Bsy then clear Status
863 * when done, hence the timeout loop only on Bsy
864 * and the forced setting of drive->error.
867 cmdport = ctlr->cmdport;
868 outb(cmdport+Features, subcommand);
869 outb(cmdport+Dh, drive->dev);
870 ctlr->command = Cnop; /* debugging */
871 outb(cmdport+Command, Cnop);
874 ctlport = ctlr->ctlport;
875 for(timeo = 0; timeo < 1000; timeo++){
876 as = inb(ctlport+As);
881 drive->error |= Abrt;
885 ataabort(Drive* drive, int dolock)
888 * If NOP is available use it otherwise
889 * must try a software reset.
893 if(drive->feat & Dnop)
896 atasrst(drive->ctlr->ctlport);
897 drive->error |= Abrt;
900 iunlock(drive->ctlr);
904 atadmasetup(Drive* drive, int len)
909 int bmiba, bmisx, count, i, span;
912 pa = PCIWADDR(drive->data);
915 if(ctlr->maxdma && len > ctlr->maxdma)
919 * Sometimes drives identify themselves as being DMA capable
920 * although they are not on a busmastering controller.
925 print("disabling dma: not on a busmastering controller\n");
929 for(i = 0; len && i < Nprd; i++){
931 span = ROUNDUP(pa, ctlr->span);
936 prd->count = PrdEOT|len;
948 outl(bmiba+Bmidtpx, PCIWADDR(ctlr->prdt));
950 outb(bmiba+Bmicx, 0);
952 outb(bmiba+Bmicx, Rwcon);
953 bmisx = inb(bmiba+Bmisx);
954 outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
960 atadmastart(Ctlr* ctlr, int write)
963 outb(ctlr->bmiba+Bmicx, Ssbm);
965 outb(ctlr->bmiba+Bmicx, Rwcon|Ssbm);
969 atadmastop(Ctlr* ctlr)
974 outb(bmiba+Bmicx, inb(bmiba+Bmicx) & ~Ssbm);
976 return inb(bmiba+Bmisx);
980 atadmainterrupt(Drive* drive, int count)
987 bmisx = inb(bmiba+Bmisx);
988 switch(bmisx & (Ideints|Idedmae|Bmidea)){
991 * Data transfer still in progress, nothing to do
992 * (this should never happen).
999 * Normal termination, tidy up.
1001 drive->data += count;
1006 * What's left are error conditions (memory transfer
1007 * problem) and the device is not done but the PRD is
1008 * exhausted. For both cases must somehow tell the
1019 atapktinterrupt(Drive* drive)
1025 cmdport = ctlr->cmdport;
1026 switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
1028 outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
1034 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1035 if(drive->data+len > drive->limit){
1039 outss(cmdport+Data, drive->data, len/2);
1046 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1047 if(drive->data+len > drive->limit){
1051 inss(cmdport+Data, drive->data, len/2);
1058 atadmainterrupt(drive, drive->dlen);
1066 atapktio0(Drive *drive, SDreq *r)
1069 int as, cmdport, ctlport, len, rv;
1074 drive->command = Cpkt;
1075 memmove(drive->pktcmd, cmd, r->clen);
1076 memset(drive->pktcmd+r->clen, 0, drive->pkt-r->clen);
1077 drive->limit = drive->data+drive->dlen;
1080 cmdport = ctlr->cmdport;
1081 ctlport = ctlr->ctlport;
1083 as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 107*1000);
1084 /* used to test as&Chk as failure too, but some CD readers use that for media change */
1089 if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen)){
1090 drive->pktdma = Dma;
1091 len = 0; /* bytecount should be 0 for dma */
1095 len = 16*drive->secsize;
1099 outb(cmdport+Features, drive->pktdma);
1100 outb(cmdport+Count, 0);
1101 outb(cmdport+Sector, 0);
1102 outb(cmdport+Bytelo, len);
1103 outb(cmdport+Bytehi, len>>8);
1104 outb(cmdport+Dh, drive->dev);
1106 ctlr->curdrive = drive;
1107 ctlr->command = Cpkt; /* debugging */
1108 outb(cmdport+Command, Cpkt);
1111 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 400*1000);
1112 if(as < 0 || (as & (Bsy|Chk))){
1113 drive->status = as<0 ? 0 : as;
1114 ctlr->curdrive = nil;
1118 atapktinterrupt(drive);
1120 atadmastart(ctlr, drive->write);
1123 if(iowait(drive, 30*1000, 0) <= 0){
1131 drive->status |= Chk;
1132 ctlr->curdrive = nil;
1136 if(drive->status & Chk){
1139 print("atapktio: disabling dma\n");
1148 atapktio(Drive* drive, SDreq *r)
1155 n = atapktio0(drive, r);
1160 static uchar cmd48[256] = {
1170 Last28 = (1<<28) - 1,
1174 atageniostart(Drive* drive, uvlong lba)
1178 int as, c, cmdport, ctlport, h, len, s, use48;
1181 if((drive->flags&Lba48always) || (lba+drive->count) > Last28 || drive->count > 256){
1182 if((drive->feat & Dllba) == 0)
1186 }else if(drive->dev & Lba){
1187 c = (lba>>8) & 0xFFFF;
1188 h = (lba>>24) & 0x0F;
1191 if (drive->s == 0 || drive->h == 0){
1192 print("sdide: chs address botch");
1195 c = lba/(drive->s*drive->h);
1196 h = (lba/drive->s) % drive->h;
1197 s = (lba % drive->s) + 1;
1201 cmdport = ctlr->cmdport;
1202 ctlport = ctlr->ctlport;
1203 if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 101*1000) < 0)
1207 if(drive->dmactl && !atadmasetup(drive, drive->count*drive->secsize)){
1209 drive->command = Cwd;
1211 drive->command = Crd;
1213 else if(drive->rwmctl){
1214 drive->block = drive->rwm*drive->secsize;
1216 drive->command = Cwsm;
1218 drive->command = Crsm;
1221 drive->block = drive->secsize;
1223 drive->command = Cws;
1225 drive->command = Crs;
1227 drive->limit = drive->data + drive->count*drive->secsize;
1228 cmd = drive->command;
1230 outb(cmdport+Count, drive->count>>8);
1231 outb(cmdport+Count, drive->count);
1232 outb(cmdport+Lbalo, lba>>24);
1233 outb(cmdport+Lbalo, lba);
1234 outb(cmdport+Lbamid, lba>>32);
1235 outb(cmdport+Lbamid, lba>>8);
1236 outb(cmdport+Lbahi, lba>>40);
1237 outb(cmdport+Lbahi, lba>>16);
1238 outb(cmdport+Dh, drive->dev|Lba);
1241 if(DEBUG & Dbg48BIT)
1242 print("using 48-bit commands\n");
1244 outb(cmdport+Count, drive->count);
1245 outb(cmdport+Sector, s);
1246 outb(cmdport+Cyllo, c);
1247 outb(cmdport+Cylhi, c>>8);
1248 outb(cmdport+Dh, drive->dev|h);
1251 ctlr->curdrive = drive;
1252 ctlr->command = drive->command; /* debugging */
1253 outb(cmdport+Command, cmd);
1255 switch(drive->command){
1259 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1260 if(as < 0 || (as & Err)){
1265 if(drive->data+len > drive->limit)
1266 len = drive->limit-drive->data;
1267 outss(cmdport+Data, drive->data, len/2);
1272 atadmastart(ctlr, drive->write);
1281 atagenioretry(Drive* drive, SDreq *r, uvlong lba, int count)
1289 s = "disabling dma";
1291 }else if(drive->rwmctl){
1293 s = "disabling rwm";
1297 rv = sdsetsense(r, SDcheck, 4, 8, drive->error);
1299 sdfakescsirw(r, &lba0, &count0, &rw);
1300 print("atagenioretry: %s %c:%llud:%d @%llud:%d\n",
1301 s, "rw"[rw], lba0, count0, lba, count);
1306 atagenio(Drive* drive, SDreq *r)
1310 int i, rw, count, maxio;
1312 if((i = sdfakescsi(r)) != SDnostatus)
1314 if((i = sdfakescsirw(r, &lba, &count, &rw)) != SDnostatus)
1317 if(drive->data == nil)
1319 if(drive->dlen < count*drive->secsize)
1320 count = drive->dlen/drive->secsize;
1323 maxio = ctlr->maxio;
1324 else if(drive->feat & Dllba)
1330 drive->count = maxio;
1332 drive->count = count;
1333 if(atageniostart(drive, lba)){
1338 return atagenioretry(drive, r, lba, count);
1340 iowait(drive, 30*1000, 0);
1343 * What should the above timeout be? In
1344 * standby and sleep modes it could take as
1345 * long as 30 seconds for a drive to respond.
1346 * Very hard to get out of this cleanly.
1348 atadumpstate(drive, r, lba, count);
1351 return atagenioretry(drive, r, lba, count);
1354 if(drive->status & Err){
1356 print("atagenio: %llud:%d\n", lba, drive->count);
1357 return sdsetsense(r, SDcheck, 4, 8, drive->error);
1359 count -= drive->count;
1360 lba += drive->count;
1377 if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil){
1378 r->status = SDtimeout;
1381 drive = ctlr->drive[unit->subno];
1384 drive->write = r->write;
1385 drive->data = r->data;
1386 drive->dlen = r->dlen;
1390 status = atapktio(drive, r);
1392 status = atagenio(drive, r);
1393 if(status != SDretry)
1396 print("%s: retry: dma %8.8uX rwm %4.4uX\n",
1397 unit->name, drive->dmactl, drive->rwmctl);
1399 if(status == SDok && r->rlen == 0 && (r->flags & SDvalidsense) == 0){
1400 sdsetsense(r, SDok, 0, 0, 0);
1403 r->rlen = drive->data - p;
1414 isdmacmd(Drive *d, SDreq *r)
1416 switch(r->ataproto & Pprotom){
1420 error("no queued support");
1422 if(!(d->dmactl || d->rwmctl))
1423 error("dma in non dma mode\n");
1429 atagenatastart(Drive* d, SDreq *r)
1432 int as, cmdport, ctlport, len, pr, isdma;
1435 isdma = isdmacmd(d, r);
1437 cmdport = ctlr->cmdport;
1438 ctlport = ctlr->ctlport;
1439 if(ataready(cmdport, ctlport, d->dev, Bsy|Drq, d->pkt ? 0 : Drdy, 101*1000) < 0)
1443 if(isdma && atadmasetup(d, d->block)){
1448 if(d->feat & Dllba && (r->ataproto & P28) == 0){
1449 outb(cmdport+Features, r->cmd[Ffeat8]);
1450 outb(cmdport+Features, r->cmd[Ffeat]);
1451 outb(cmdport+Count, r->cmd[Fsc8]);
1452 outb(cmdport+Count, r->cmd[Fsc]);
1453 outb(cmdport+Lbalo, r->cmd[Flba24]);
1454 outb(cmdport+Lbalo, r->cmd[Flba0]);
1455 outb(cmdport+Lbamid, r->cmd[Flba32]);
1456 outb(cmdport+Lbamid, r->cmd[Flba8]);
1457 outb(cmdport+Lbahi, r->cmd[Flba40]);
1458 outb(cmdport+Lbahi, r->cmd[Flba16]);
1459 u = r->cmd[Fdev] & ~0xb0;
1460 outb(cmdport+Dh, d->dev|u);
1462 outb(cmdport+Features, r->cmd[Ffeat]);
1463 outb(cmdport+Count, r->cmd[Fsc]);
1464 outb(cmdport+Lbalo, r->cmd[Flba0]);
1465 outb(cmdport+Lbamid, r->cmd[Flba8]);
1466 outb(cmdport+Lbahi, r->cmd[Flba16]);
1467 u = r->cmd[Fdev] & ~0xb0;
1468 outb(cmdport+Dh, d->dev|u);
1472 d->command = r->ataproto & (Pprotom|Pdatam);
1473 ctlr->command = r->cmd[Fcmd];
1474 outb(cmdport+Command, r->cmd[Fcmd]);
1476 pr = r->ataproto & Pprotom;
1477 if(pr == Pnd || pr == Preset)
1481 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1482 if(as < 0 || (as & Err)){
1487 if(r->write && len > 0)
1488 outss(cmdport+Data, d->data, len/2);
1490 atadmastart(ctlr, d->write);
1496 mkrfis(Drive *d, SDreq *r)
1503 cmdport = ctlr->cmdport;
1509 if((d->feat & Dllba) && (r->ataproto & P28) == 0){
1510 u[Frerror] = inb(cmdport+Error);
1511 u[Fsc8] = inb(cmdport+Count);
1512 u[Fsc] = inb(cmdport+Count);
1513 u[Flba24] = inb(cmdport+Lbalo);
1514 u[Flba0] = inb(cmdport+Lbalo);
1515 u[Flba32] = inb(cmdport+Lbamid);
1516 u[Flba8] = inb(cmdport+Lbamid);
1517 u[Flba40] = inb(cmdport+Lbahi);
1518 u[Flba16] = inb(cmdport+Lbahi);
1519 u[Fdev] = inb(cmdport+Dh);
1520 u[Fstatus] = inb(cmdport+Status);
1522 u[Frerror] = inb(cmdport+Error);
1523 u[Fsc] = inb(cmdport+Count);
1524 u[Flba0] = inb(cmdport+Lbalo);
1525 u[Flba8] = inb(cmdport+Lbamid);
1526 u[Flba16] = inb(cmdport+Lbahi);
1527 u[Fdev] = inb(cmdport+Dh);
1528 u[Fstatus] = inb(cmdport+Status);
1534 atarstdone(Drive *d)
1540 as = ataready(c->cmdport, c->ctlport, 0, Bsy|Drq, 0, 5*1000);
1546 cmdss(Drive *d, SDreq *r)
1548 switch(r->cmd[Fcmd]){
1558 * various checks. we should be craftier and
1559 * avoid figuring out how big stuff is supposed to be.
1562 patasizeck(Drive *d, SDreq *r)
1564 uint count, maxio, secsize;
1567 secsize = cmdss(d, r); /* BOTCH */
1570 count = r->dlen / secsize;
1573 maxio = ctlr->maxio;
1574 else if((d->feat & Dllba) && (r->ataproto & P28) == 0)
1579 uprint("i/o too large, lim %d", maxio);
1582 if(r->ataproto&Ppio && count > 1)
1583 error("invalid # of sectors");
1588 atapataio(Drive *d, SDreq *r)
1594 if(r->ataproto & Pdatam)
1595 d->count = patasizeck(d, r);
1597 d->limit = d->data + r->dlen;
1605 rv = atagenatastart(d, r);
1608 if(DEBUG & DbgAtazz)
1609 print("sdide: !atageatastart\n");
1614 return sdsetsense(r, SDcheck, 4, 8, d->error);
1617 if((r->ataproto & Pprotom) == Preset)
1620 while(iowait(d, 30*1000, 1) == 0)
1623 if(DEBUG & DbgAtazz){
1624 print("sdide: !done\n");
1625 atadumpstate(d, r, 0, d->count);
1629 return sdsetsense(r, SDcheck, 11, 0, 6); /* aborted; i/o process terminated */
1632 if(d->status & Err){
1633 if(DEBUG & DbgAtazz)
1634 print("sdide: status&Err\n");
1636 return sdsetsense(r, SDcheck, 4, 8, d->error);
1643 ataataio0(Drive *d, SDreq *r)
1647 if((r->ataproto & Pprotom) == Ppkt){
1648 if(r->clen > d->pkt)
1651 i = atapktio0(d, r);
1652 d->block = d->data - (uchar*)r->data;
1657 return atapataio(d, r);
1661 * hack to allow udma mode to be set or unset
1662 * via direct ata command. it would be better
1663 * to move the assumptions about dma mode out
1664 * of some of the helper functions.
1672 if(c[Fcmd] == 0xef && c[Ffeat] == 0x03){
1681 fisreqchk(Sfis *f, SDreq *r)
1683 if((r->ataproto & Pprotom) == Ppkt)
1686 * handle oob requests;
1687 * restrict & sanitize commands
1691 if(r->cmd[0] == 0xf0){
1692 sigtofis(f, r->cmd);
1711 if((c = u->dev->ctlr) == nil || (d = c->drive[u->subno]) == nil){
1712 r->status = SDtimeout;
1715 if((status = fisreqchk(d, r)) != SDnostatus)
1725 d->write = r->write;
1731 switch(status = ataataio0(d, r)){
1734 print("%s: retry: dma %.8ux rwm %.4ux\n",
1735 u->name, d->dmactl, d->rwmctl);
1742 sdsetsense(r, SDok, 0, 0, 0);
1754 ichirqack(Ctlr *ctlr)
1758 if(bmiba = ctlr->bmiba)
1759 outb(bmiba+Bmisx, inb(bmiba+Bmisx));
1763 atainterrupt(Ureg*, void* arg)
1767 int cmdport, len, status;
1774 ctlr->curdrive->irq++;
1775 if(inb(ctlr->ctlport+As) & Bsy){
1778 ctlr->curdrive->bsy++;
1784 cmdport = ctlr->cmdport;
1785 status = inb(cmdport+Status);
1786 if((drive = ctlr->curdrive) == nil){
1788 if(ctlr->irqack != nil)
1794 drive->error = inb(cmdport+Error);
1795 else switch(drive->command){
1797 drive->error = Abrt;
1803 if(!(status & Drq)){
1804 drive->error = Abrt;
1808 if(drive->data+len > drive->limit)
1809 len = drive->limit-drive->data;
1810 inss(cmdport+Data, drive->data, len/2);
1812 if(drive->data >= drive->limit)
1820 if(drive->data+len > drive->limit)
1821 len = drive->limit-drive->data;
1823 if(drive->data >= drive->limit){
1827 if(!(status & Drq)){
1828 drive->error = Abrt;
1832 if(drive->data+len > drive->limit)
1833 len = drive->limit-drive->data;
1834 outss(cmdport+Data, drive->data, len/2);
1840 atapktinterrupt(drive);
1847 atadmainterrupt(drive, drive->count*drive->secsize);
1855 if(ctlr->irqack != nil)
1865 ctlr->curdrive = nil;
1866 drive->status = status;
1871 typedef struct Lchan Lchan;
1878 static Lchan lchan[2] = {
1879 0x1f0, 0x3f4, IrqATA0, 0,
1880 0x170, 0x374, IrqATA1, 0,
1886 switch(p->did<<16 | p->did){
1887 case 0x439c<<16 | 0x1002:
1888 case 0x438c<<16 | 0x1002:
1889 print("%T: allowing bad ccru %.2ux for suspected ide controller\n",
1901 int channel, map, ispc87415, maxio, pi, r, span, maxdma, tbdf;
1904 SDev *sdev, *head, *tail;
1905 void (*irqack)(Ctlr*);
1908 for(p = nil; p = pcimatch(p, 0, 0); ){
1910 * Look for devices with the correct class and sub-class
1911 * code and known device and vendor ID; add native-mode
1912 * channels to the list to be probed, save info for the
1913 * compatibility mode channels.
1914 * Note that the legacy devices should not be considered
1915 * PCI devices by the interrupt controller.
1916 * For both native and legacy, save info for busmastering
1918 * Promise Ultra ATA/66 (PDC20262) appears to
1919 * 1) give a sub-class of 'other mass storage controller'
1920 * instead of 'IDE controller', regardless of whether it's
1921 * the only controller or not;
1922 * 2) put 0 in the programming interface byte (probably
1923 * as a consequence of 1) above).
1924 * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
1929 if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
1936 if(s = getconf("*idemaxio"))
1941 switch((p->did<<16)|p->vid){
1945 case (0x0002<<16)|0x100B: /* NS PC87415 */
1947 * Disable interrupts on both channels until
1948 * after they are probed for drives.
1949 * This must be called before interrupts are
1950 * enabled because the IRQ may be shared.
1953 pcicfgw32(p, 0x40, 0x00000300);
1955 case (0x1000<<16)|0x1042: /* PC-Tech RZ1000 */
1957 * Turn off prefetch. Overkill, but cheap.
1959 r = pcicfgr32(p, 0x40);
1961 pcicfgw32(p, 0x40, r);
1963 case (0x4D38<<16)|0x105A: /* Promise PDC20262 */
1964 case (0x4D30<<16)|0x105A: /* Promise PDC202xx */
1965 case (0x4D68<<16)|0x105A: /* Promise PDC20268 */
1966 case (0x4D69<<16)|0x105A: /* Promise Ultra/133 TX2 */
1967 case (0x3373<<16)|0x105A: /* Promise 20378 RAID */
1968 case (0x3149<<16)|0x1106: /* VIA VT8237 SATA/RAID */
1969 case (0x3112<<16)|0x1095: /* SiL 3112 SATA/RAID */
1973 case (0x3114<<16)|0x1095: /* SiL 3114 SATA/RAID */
1974 case (0x0680<<16)|0x1095: /* SiI 0680/680A PATA133 ATAPI/RAID */
1977 case (0x0004<<16)|0x1103: /* HighPoint HPT366 */
1980 * Turn off fast interrupt prediction.
1982 if((r = pcicfgr8(p, 0x51)) & 0x80)
1983 pcicfgw8(p, 0x51, r & ~0x80);
1984 if((r = pcicfgr8(p, 0x55)) & 0x80)
1985 pcicfgw8(p, 0x55, r & ~0x80);
1987 case (0x0640<<16)|0x1095: /* CMD 640B */
1989 * Bugfix code here...
1992 case (0x7441<<16)|0x1022: /* AMD 768 */
1993 case (0x7800<<16)|0x1022:
1996 * 0x41 prefetch, postwrite;
1997 * 0x43 FIFO configuration 1/2 and 1/2;
1998 * 0x44 status register read retry;
1999 * 0x46 DMA read and end of sector flush.
2001 r = pcicfgr8(p, 0x41);
2002 pcicfgw8(p, 0x41, r|0xF0);
2003 r = pcicfgr8(p, 0x43);
2004 pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
2005 r = pcicfgr8(p, 0x44);
2006 pcicfgw8(p, 0x44, r|0x08);
2007 r = pcicfgr8(p, 0x46);
2008 pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
2010 case (0x01BC<<16)|0x10DE: /* nVidia nForce1 */
2011 case (0x0065<<16)|0x10DE: /* nVidia nForce2 */
2012 case (0x0085<<16)|0x10DE: /* nVidia nForce2 MCP */
2013 case (0x00E3<<16)|0x10DE: /* nVidia nForce2 250 SATA */
2014 case (0x00D5<<16)|0x10DE: /* nVidia nForce3 */
2015 case (0x00E5<<16)|0x10DE: /* nVidia nForce3 Pro */
2016 case (0x00EE<<16)|0x10DE: /* nVidia nForce3 250 SATA */
2017 case (0x0035<<16)|0x10DE: /* nVidia nForce3 MCP */
2018 case (0x0053<<16)|0x10DE: /* nVidia nForce4 */
2019 case (0x0054<<16)|0x10DE: /* nVidia nForce4 SATA */
2020 case (0x0055<<16)|0x10DE: /* nVidia nForce4 SATA */
2021 case (0x0266<<16)|0x10DE: /* nVidia nForce4 430 SATA */
2022 case (0x0265<<16)|0x10DE: /* nVidia nForce 51 MCP */
2023 case (0x0267<<16)|0x10DE: /* nVidia nForce 55 MCP SATA */
2024 case (0x037f<<16)|0x10DE: /* nVidia nForce 55 MCP SATA */
2025 case (0x03ec<<16)|0x10DE: /* nVidia nForce 61 MCP SATA */
2026 case (0x03f6<<16)|0x10DE: /* nVidia nForce 61 MCP PATA */
2027 case (0x0448<<16)|0x10DE: /* nVidia nForce 65 MCP SATA */
2028 case (0x0560<<16)|0x10DE: /* nVidia nForce 69 MCP SATA */
2030 * Ditto, although it may have a different base
2031 * address for the registers (0x50?).
2034 case (0x209A<<16)|0x1022: /* AMD CS5536 */
2035 case (0x7401<<16)|0x1022: /* AMD 755 Cobra */
2036 case (0x7409<<16)|0x1022: /* AMD 756 Viper */
2037 case (0x7410<<16)|0x1022: /* AMD 766 Viper Plus */
2038 case (0x7469<<16)|0x1022: /* AMD 3111 */
2039 case (0x4376<<16)|0x1002: /* SB4xx pata */
2040 case (0x4379<<16)|0x1002: /* SB4xx sata */
2041 case (0x437a<<16)|0x1002: /* SB4xx sata ctlr #2 */
2042 case (0x437c<<16)|0x1002: /* Rx6xx pata */
2043 case (0x438c<<16)|0x1002: /* ATI SB600 PATA */
2044 case (0x439c<<16)|0x1002: /* SB7xx pata */
2047 case (0x6101<<16)|0x11ab: /* Marvell PATA */
2048 case (0x6121<<16)|0x11ab: /* Marvell PATA */
2049 case (0x6123<<16)|0x11ab: /* Marvell PATA */
2050 case (0x6145<<16)|0x11ab: /* Marvell PATA */
2051 case (0x1b4b<<16)|0x91a0: /* Marvell PATA */
2052 case (0x1b4b<<16)|0x91a4: /* Marvell PATA */
2055 case (0x0211<<16)|0x1166: /* ServerWorks IB6566 */
2059 sb = pcimatch(nil, 0x1166, 0x0200);
2062 r = pcicfgr32(sb, 0x64);
2064 pcicfgw32(sb, 0x64, r);
2068 case (0x5229<<16)|0x10B9: /* ALi M1543 */
2069 case (0x5288<<16)|0x10B9: /* ALi M5288 SATA */
2071 case (0x5513<<16)|0x1039: /* SiS 962 */
2072 case (0x0646<<16)|0x1095: /* CMD 646 */
2073 case (0x0571<<16)|0x1106: /* VIA 82C686 */
2074 case (0x9001<<16)|0x1106: /* VIA chipset in VIA PV530 */
2075 case (0x0502<<16)|0x100b: /* National Semiconductor SC1100/SCx200 */
2077 case (0x2360<<16)|0x197b: /* jmicron jmb360 */
2078 case (0x2361<<16)|0x197b: /* jmicron jmb361 */
2079 case (0x2363<<16)|0x197b: /* jmicron jmb363 */
2080 case (0x2365<<16)|0x197b: /* jmicron jmb365 */
2081 case (0x2366<<16)|0x197b: /* jmicron jmb366 */
2082 case (0x2368<<16)|0x197b: /* jmicron jmb368 */
2084 case (0x7010<<16)|0x8086: /* 82371SB (PIIX3) */
2085 case (0x1230<<16)|0x8086: /* 82371FB (PIIX) */
2086 case (0x7111<<16)|0x8086: /* 82371[AE]B (PIIX4[E]) */
2089 case (0x2411<<16)|0x8086: /* 82801AA (ICH) */
2090 case (0x2421<<16)|0x8086: /* 82801AB (ICH0) */
2091 case (0x244A<<16)|0x8086: /* 82801BA (ICH2, Mobile) */
2092 case (0x244B<<16)|0x8086: /* 82801BA (ICH2, High-End) */
2093 case (0x248A<<16)|0x8086: /* 82801CA (ICH3, Mobile) */
2094 case (0x248B<<16)|0x8086: /* 82801CA (ICH3, High-End) */
2095 case (0x24CA<<16)|0x8086: /* 82801DBM (ICH4, Mobile) */
2096 case (0x24CB<<16)|0x8086: /* 82801DB (ICH4, High-End) */
2097 case (0x24D1<<16)|0x8086: /* 82801er (ich5) */
2098 case (0x24DB<<16)|0x8086: /* 82801EB (ICH5) */
2099 case (0x25A2<<16)|0x8086: /* 6300ESB pata */
2100 case (0x25A3<<16)|0x8086: /* 6300ESB (E7210) */
2101 case (0x266F<<16)|0x8086: /* 82801FB (ICH6) */
2102 case (0x2651<<16)|0x8086: /* 82801FB (ICH6) */
2103 case (0x2653<<16)|0x8086: /* 82801FBM (ICH6, Mobile) */
2104 case (0x269e<<16)|0x8086: /* 63xxESB (intel 5000) */
2105 case (0x27DF<<16)|0x8086: /* 82801G PATA (ICH7) */
2106 case (0x27C0<<16)|0x8086: /* 82801GB SATA (ICH7) */
2107 case (0x27C4<<16)|0x8086: /* 82801GBM SATA (ICH7) */
2108 case (0x27C5<<16)|0x8086: /* 82801GBM SATA AHCI (ICH7) */
2109 case (0x2850<<16)|0x8086: /* 82801HBM/HEM PATA */
2110 case (0x2820<<16)|0x8086: /* 82801HB/HR/HH/HO SATA IDE */
2111 case (0x2828<<16)|0x8086: /* 82801HBM SATA (ICH8-M) */
2112 case (0x2829<<16)|0x8086: /* 82801HBM SATA AHCI (ICH8-M) */
2113 case (0x2920<<16)|0x8086: /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-3 */
2114 case (0x2921<<16)|0x8086: /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-1 */
2115 case (0x2926<<16)|0x8086: /* 82801(IB)/IR/IH/IO SATA (ICH9) port 4-5 */
2116 case (0x2928<<16)|0x8086: /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1 */
2117 case (0x2929<<16)|0x8086: /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1, 4-5 */
2118 case (0x292d<<16)|0x8086: /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 4-5*/
2119 case (0x3a20<<16)|0x8086: /* 82801ji (ich10) */
2120 case (0x3a26<<16)|0x8086: /* 82801ji (ich10) */
2121 case (0x3b20<<16)|0x8086: /* 34x0 (pch) port 0-3 */
2122 case (0x3b21<<16)|0x8086: /* 34x0 (pch) port 4-5 */
2123 case (0x3b28<<16)|0x8086: /* 34x0pm (pch) port 0-1, 4-5 */
2124 case (0x3b2e<<16)|0x8086: /* 34x0pm (pch) port 0-3 */
2126 if(pcicfgr16(p, 0x40) & 0x8000)
2128 if(pcicfgr16(p, 0x42) & 0x8000)
2133 for(channel = 0; channel < 2; channel++){
2134 if((map & 1<<channel) == 0)
2136 if(pi & 1<<2*channel){
2137 sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
2138 p->mem[1+2*channel].bar & ~0x01,
2142 else if(lchan[channel].probed == 0){
2143 sdev = ataprobe(lchan[channel].cmdport,
2144 lchan[channel].ctlport, lchan[channel].irq, 3);
2145 lchan[channel].probed = 1;
2154 ctlr->ienable = pc87415ienable;
2155 print("pc87415disable: not yet implemented\n");
2159 ctlr->maxio = maxio;
2160 ctlr->maxdma = maxdma;
2162 ctlr->irqack = irqack;
2163 if((pi & 0x80) && (p->mem[4].bar & 0x01))
2164 ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
2173 if(lchan[0].probed + lchan[1].probed == 0)
2174 for(channel = 0; channel < 2; channel++){
2176 if(lchan[channel].probed == 0){
2177 // print("sdide: blind probe %.3ux\n", lchan[channel].cmdport);
2178 sdev = ataprobe(lchan[channel].cmdport,
2179 lchan[channel].ctlport, lchan[channel].irq, 3);
2180 lchan[channel].probed = 1;
2196 * Hack for PCMCIA drives.
2197 * This will be tidied once we figure out how the whole
2198 * removeable device thing is going to work.
2200 memset(&isa, 0, sizeof(isa));
2201 isa.port = 0x180; /* change this for your machine */
2202 isa.irq = 11; /* change this for your machine */
2204 port = isa.port+0x0C;
2205 channel = pcmspecial("MK2001MPL", &isa);
2207 channel = pcmspecial("SunDisk", &isa);
2210 channel = pcmspecial("CF", &isa);
2214 channel = pcmspecial("OLYMPUS", &isa);
2217 port = isa.port+0x204;
2218 channel = pcmspecial("ATA/ATAPI", &isa);
2220 if(channel >= 0 && (sdev = ataprobe(isa.port, port, isa.irq, 3)) != nil){
2231 atadmaclr(Ctlr *ctlr)
2236 ataabort(ctlr->curdrive, 1);
2237 bmiba = ctlr->bmiba;
2241 outl(bmiba+Bmidtpx, 0);
2242 bmisx = inb(bmiba+Bmisx) & ~Bmidea;
2243 outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
2244 // pciintst(ctlr->pcidev);
2248 ataenable(SDev* sdev)
2256 if(ctlr->pcidev != nil)
2257 pcisetbme(ctlr->pcidev);
2258 ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 4, 0, 64*1024);
2260 snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2261 intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2262 outb(ctlr->ctlport+Dc, 0);
2264 ctlr->ienable(ctlr);
2269 atadisable(SDev *sdev)
2275 outb(ctlr->ctlport+Dc, Nien); /* disable interrupts */
2277 ctlr->idisable(ctlr);
2278 snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2279 intrdisable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2283 pciclrbme(ctlr->pcidev);
2291 ataonline(SDunit *unit)
2297 if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2300 drive = ctlr->drive[unit->subno];
2301 if((drive->flags & Online) == 0){
2302 drive->flags |= Online;
2303 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2306 if(drive->feat & Datapi){
2309 dma = drive->dmactl;
2311 ret = scsionline(unit);
2312 drive->dmactl = dma;
2314 unit->sectors = drive->sectors;
2315 unit->secsize = drive->secsize;
2321 atarctl(SDunit* unit, char* p, int l)
2327 if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2329 drive = ctlr->drive[unit->subno];
2334 p = seprint(p, e, "config %4.4uX capabilities %4.4uX", drive->info[Iconfig], drive->info[Icapabilities]);
2336 p = seprint(p, e, " dma %8.8uX dmactl %8.8uX", drive->dma, drive->dmactl);
2338 p = seprint(p, e, " rwm %ud rwmctl %ud", drive->rwm, drive->rwmctl);
2339 if(drive->feat & Dllba)
2340 p = seprint(p, e, " lba48always %s", (drive->flags&Lba48always) ? "on" : "off");
2341 p = seprint(p, e, "\n");
2342 p = seprint(p, e, "model %s\n", drive->model);
2343 p = seprint(p, e, "serial %s\n", drive->serial);
2344 p = seprint(p, e, "firm %s\n", drive->firmware);
2345 p = seprint(p, e, "feat ");
2346 p = pflag(p, e, drive);
2348 p = seprint(p, e, "geometry %llud %d", drive->sectors, drive->secsize);
2349 if(drive->pkt == 0 && (drive->feat & Dlba) == 0)
2350 p = seprint(p, e, " %d %d %d", drive->c, drive->h, drive->s);
2351 p = seprint(p, e, "\n");
2352 p = seprint(p, e, "alignment %d %d\n",
2353 drive->secsize<<drive->physshift, drive->physalign);
2355 p = seprint(p, e, "missirq %ud\n", drive->missirq);
2356 p = seprint(p, e, "sloop %ud\n", drive->spurloop);
2357 p = seprint(p, e, "irq %ud %ud\n", ctlr->nrq, drive->irq);
2358 p = seprint(p, e, "bsy %ud %ud\n", ctlr->bsy, drive->bsy);
2359 p = seprint(p, e, "nildrive %ud\n", ctlr->nildrive);
2366 atawctl(SDunit* unit, Cmdbuf* cb)
2371 if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2373 drive = ctlr->drive[unit->subno];
2382 * Dma and rwm control is passive at the moment,
2383 * i.e. it is assumed that the hardware is set up
2384 * correctly already either by the BIOS or when
2385 * the drive was initially identified.
2387 if(strcmp(cb->f[0], "dma") == 0){
2388 if(cb->nf != 2 || drive->dma == 0)
2390 if(strcmp(cb->f[1], "on") == 0)
2391 drive->dmactl = drive->dma;
2392 else if(strcmp(cb->f[1], "off") == 0)
2397 else if(strcmp(cb->f[0], "rwm") == 0){
2398 if(cb->nf != 2 || drive->rwm == 0)
2400 if(strcmp(cb->f[1], "on") == 0)
2401 drive->rwmctl = drive->rwm;
2402 else if(strcmp(cb->f[1], "off") == 0)
2407 else if(strcmp(cb->f[0], "lba48always") == 0){
2408 if(cb->nf != 2 || !(drive->feat & Dllba))
2410 if(strcmp(cb->f[1], "on") == 0)
2411 drive->flags |= Lba48always;
2412 else if(strcmp(cb->f[1], "off") == 0)
2413 drive->flags &= ~Lba48always;
2417 else if(strcmp(cb->f[0], "identify") == 0){
2418 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2433 ataenable, /* enable */
2434 atadisable, /* disable */
2436 scsiverify, /* verify */
2437 ataonline, /* online */
2443 ataprobew, /* probe */
2444 ataclear, /* clear */
2445 atastat, /* rtopctl */