sys/src/9/pc/sdide.c

   1 #include "u.h"
   2 #include "../port/lib.h"
   3 #include "mem.h"
   4 #include "dat.h"
   5 #include "fns.h"
   6 #include "io.h"
   7 #include "ureg.h"
   8 #include "../port/error.h"
   9
  10 #include "../port/sd.h"
  11 #include <fis.h>
  12
  13 #define HOWMANY(x, y)   (((x)+((y)-1))/(y))
  14 #define ROUNDUP(x, y)   (HOWMANY((x), (y))*(y))
  15 #define uprint(...)     snprint(up->genbuf, sizeof up->genbuf, __VA_ARGS__);
  16 #pragma varargck        argpos  atadebug                3
  17
  18 extern SDifc sdideifc;
  19
  20 enum {
  21         DbgCONFIG       = 0x0001,       /* detected drive config info */
  22         DbgIDENTIFY     = 0x0002,       /* detected drive identify info */
  23         DbgSTATE        = 0x0004,       /* dump state on panic */
  24         DbgPROBE        = 0x0008,       /* trace device probing */
  25         DbgDEBUG        = 0x0080,       /* the current problem... */
  26         DbgINL          = 0x0100,       /* That Inil20+ message we hate */
  27         Dbg48BIT        = 0x0200,       /* 48-bit LBA */
  28         DbgBsy          = 0x0400,       /* interrupt but Bsy (shared IRQ) */
  29         DbgAtazz        = 0x0800,       /* debug raw ata io */
  30 };
  31 #define DEBUG           (DbgDEBUG|DbgSTATE)
  32
  33 enum {                                  /* I/O ports */
  34         Data            = 0,
  35         Error           = 1,            /* (read) */
  36         Features        = 1,            /* (write) */
  37         Count           = 2,            /* sector count<7-0>, sector count<15-8> */
  38         Ir              = 2,            /* interrupt reason (PACKET) */
  39         Sector          = 3,            /* sector number */
  40         Lbalo           = 3,            /* LBA<7-0>, LBA<31-24> */
  41         Cyllo           = 4,            /* cylinder low */
  42         Bytelo          = 4,            /* byte count low (PACKET) */
  43         Lbamid          = 4,            /* LBA<15-8>, LBA<39-32> */
  44         Cylhi           = 5,            /* cylinder high */
  45         Bytehi          = 5,            /* byte count hi (PACKET) */
  46         Lbahi           = 5,            /* LBA<23-16>, LBA<47-40> */
  47         Dh              = 6,            /* Device/Head, LBA<27-24> */
  48         Status          = 7,            /* (read) */
  49         Command         = 7,            /* (write) */
  50
  51         As              = 2,            /* Alternate Status (read) */
  52         Dc              = 2,            /* Device Control (write) */
  53 };
  54
  55 enum {                                  /* Error */
  56         Med             = 0x01,         /* Media error */
  57         Ili             = 0x01,         /* command set specific (PACKET) */
  58         Nm              = 0x02,         /* No Media */
  59         Eom             = 0x02,         /* command set specific (PACKET) */
  60         Abrt            = 0x04,         /* Aborted command */
  61         Mcr             = 0x08,         /* Media Change Request */
  62         Idnf            = 0x10,         /* no user-accessible address */
  63         Mc              = 0x20,         /* Media Change */
  64         Unc             = 0x40,         /* Uncorrectable data error */
  65         Wp              = 0x40,         /* Write Protect */
  66         Icrc            = 0x80,         /* Interface CRC error */
  67 };
  68
  69 enum {                                  /* Features */
  70         Dma             = 0x01,         /* data transfer via DMA (PACKET) */
  71         Ovl             = 0x02,         /* command overlapped (PACKET) */
  72 };
  73
  74 enum {                                  /* Interrupt Reason */
  75         Cd              = 0x01,         /* Command/Data */
  76         Io              = 0x02,         /* I/O direction */
  77         Rel             = 0x04,         /* Bus Release */
  78 };
  79
  80 enum {                                  /* Device/Head */
  81         Dev0            = 0xA0,         /* Master */
  82         Dev1            = 0xB0,         /* Slave */
  83         Devs            = Dev0 | Dev1,
  84         Lba             = 0x40,         /* LBA mode */
  85 };
  86
  87 enum {                                  /* Status, Alternate Status */
  88         Err             = 0x01,         /* Error */
  89         Chk             = 0x01,         /* Check error (PACKET) */
  90         Drq             = 0x08,         /* Data Request */
  91         Dsc             = 0x10,         /* Device Seek Complete */
  92         Serv            = 0x10,         /* Service */
  93         Df              = 0x20,         /* Device Fault */
  94         Dmrd            = 0x20,         /* DMA ready (PACKET) */
  95         Drdy            = 0x40,         /* Device Ready */
  96         Bsy             = 0x80,         /* Busy */
  97 };
  98
  99 enum {                                  /* Command */
 100         Cnop            = 0x00,         /* NOP */
 101         Crs             = 0x20,         /* Read Sectors */
 102         Crs48           = 0x24,         /* Read Sectors Ext */
 103         Crd48           = 0x25,         /* Read w/ DMA Ext */
 104         Crsm48          = 0x29,         /* Read Multiple Ext */
 105         Cws             = 0x30,         /* Write Sectors */
 106         Cws48           = 0x34,         /* Write Sectors Ext */
 107         Cwd48           = 0x35,         /* Write w/ DMA Ext */
 108         Cwsm48          = 0x39,         /* Write Multiple Ext */
 109         Cedd            = 0x90,         /* Execute Device Diagnostics */
 110         Cpkt            = 0xA0,         /* Packet */
 111         Cidpkt          = 0xA1,         /* Identify Packet Device */
 112         Crsm            = 0xC4,         /* Read Multiple */
 113         Cwsm            = 0xC5,         /* Write Multiple */
 114         Csm             = 0xC6,         /* Set Multiple */
 115         Crd             = 0xC8,         /* Read DMA */
 116         Cwd             = 0xCA,         /* Write DMA */
 117         Cid             = 0xEC,         /* Identify Device */
 118 };
 119
 120 enum {                                  /* Device Control */
 121         Nien            = 0x02,         /* (not) Interrupt Enable */
 122         Srst            = 0x04,         /* Software Reset */
 123         Hob             = 0x80,         /* High Order Bit [sic] */
 124 };
 125
 126 enum {                                  /* PCI Configuration Registers */
 127         Bmiba           = 0x20,         /* Bus Master Interface Base Address */
 128         Idetim          = 0x40,         /* IE Timing */
 129         Sidetim         = 0x44,         /* Slave IE Timing */
 130         Udmactl         = 0x48,         /* Ultra DMA/33 Control */
 131         Udmatim         = 0x4A,         /* Ultra DMA/33 Timing */
 132 };
 133
 134 enum {                                  /* Bus Master IDE I/O Ports */
 135         Bmicx           = 0,            /* Command */
 136         Bmisx           = 2,            /* Status */
 137         Bmidtpx         = 4,            /* Descriptor Table Pointer */
 138 };
 139
 140 enum {                                  /* Bmicx */
 141         Ssbm            = 0x01,         /* Start/Stop Bus Master */
 142         Rwcon           = 0x08,         /* Read/Write Control */
 143 };
 144
 145 enum {                                  /* Bmisx */
 146         Bmidea          = 0x01,         /* Bus Master IDE Active */
 147         Idedmae         = 0x02,         /* IDE DMA Error  (R/WC) */
 148         Ideints         = 0x04,         /* IDE Interrupt Status (R/WC) */
 149         Dma0cap         = 0x20,         /* Drive 0 DMA Capable */
 150         Dma1cap         = 0x40,         /* Drive 0 DMA Capable */
 151 };
 152 enum {                                  /* Physical Region Descriptor */
 153         PrdEOT          = 0x80000000,   /* End of Transfer */
 154 };
 155
 156 enum {                                  /* offsets into the identify info. */
 157         Iconfig         = 0,            /* general configuration */
 158         Ilcyl           = 1,            /* logical cylinders */
 159         Ilhead          = 3,            /* logical heads */
 160         Ilsec           = 6,            /* logical sectors per logical track */
 161         Iserial         = 10,           /* serial number */
 162         Ifirmware       = 23,           /* firmware revision */
 163         Imodel          = 27,           /* model number */
 164         Imaxrwm         = 47,           /* max. read/write multiple sectors */
 165         Icapabilities   = 49,           /* capabilities */
 166         Istandby        = 50,           /* device specific standby timer */
 167         Ipiomode        = 51,           /* PIO data transfer mode number */
 168         Ivalid          = 53,
 169         Iccyl           = 54,           /* cylinders if (valid&0x01) */
 170         Ichead          = 55,           /* heads if (valid&0x01) */
 171         Icsec           = 56,           /* sectors if (valid&0x01) */
 172         Iccap           = 57,           /* capacity if (valid&0x01) */
 173         Irwm            = 59,           /* read/write multiple */
 174         Ilba            = 60,           /* LBA size */
 175         Imwdma          = 63,           /* multiword DMA mode */
 176         Iapiomode       = 64,           /* advanced PIO modes supported */
 177         Iminmwdma       = 65,           /* min. multiword DMA cycle time */
 178         Irecmwdma       = 66,           /* rec. multiword DMA cycle time */
 179         Iminpio         = 67,           /* min. PIO cycle w/o flow control */
 180         Iminiordy       = 68,           /* min. PIO cycle with IORDY */
 181         Ipcktbr         = 71,           /* time from PACKET to bus release */
 182         Iserbsy         = 72,           /* time from SERVICE to !Bsy */
 183         Iqdepth         = 75,           /* max. queue depth */
 184         Imajor          = 80,           /* major version number */
 185         Iminor          = 81,           /* minor version number */
 186         Icsfs           = 82,           /* command set/feature supported */
 187         Icsfe           = 85,           /* command set/feature enabled */
 188         Iudma           = 88,           /* ultra DMA mode */
 189         Ierase          = 89,           /* time for security erase */
 190         Ieerase         = 90,           /* time for enhanced security erase */
 191         Ipower          = 91,           /* current advanced power management */
 192         Ilba48          = 100,          /* 48-bit LBA size (64 bits in 100-103) */
 193         Irmsn           = 127,          /* removable status notification */
 194         Isecstat        = 128,          /* security status */
 195         Icfapwr         = 160,          /* CFA power mode */
 196         Imediaserial    = 176,          /* current media serial number */
 197         Icksum          = 255,          /* checksum */
 198 };
 199
 200 enum {                                  /* bit masks for config identify info */
 201         Mpktsz          = 0x0003,       /* packet command size */
 202         Mincomplete     = 0x0004,       /* incomplete information */
 203         Mdrq            = 0x0060,       /* DRQ type */
 204         Mrmdev          = 0x0080,       /* device is removable */
 205         Mtype           = 0x1F00,       /* device type */
 206         Mproto          = 0x8000,       /* command protocol */
 207 };
 208
 209 enum {                                  /* bit masks for capabilities identify info */
 210         Mdma            = 0x0100,       /* DMA supported */
 211         Mlba            = 0x0200,       /* LBA supported */
 212         Mnoiordy        = 0x0400,       /* IORDY may be disabled */
 213         Miordy          = 0x0800,       /* IORDY supported */
 214         Msoftrst        = 0x1000,       /* needs soft reset when Bsy */
 215         Mqueueing       = 0x4000,       /* queueing overlap supported */
 216         Midma           = 0x8000,       /* interleaved DMA supported */
 217 };
 218
 219 enum {                                  /* bit masks for supported/enabled features */
 220         Msmart          = 0x0001,
 221         Msecurity       = 0x0002,
 222         Mrmmedia        = 0x0004,
 223         Mpwrmgmt        = 0x0008,
 224         Mpkt            = 0x0010,
 225         Mwcache         = 0x0020,
 226         Mlookahead      = 0x0040,
 227         Mrelirq         = 0x0080,
 228         Msvcirq         = 0x0100,
 229         Mreset          = 0x0200,
 230         Mprotected      = 0x0400,
 231         Mwbuf           = 0x1000,
 232         Mrbuf           = 0x2000,
 233         Mnop            = 0x4000,
 234         Mmicrocode      = 0x0001,
 235         Mqueued         = 0x0002,
 236         Mcfa            = 0x0004,
 237         Mapm            = 0x0008,
 238         Mnotify         = 0x0010,
 239         Mspinup         = 0x0040,
 240         Mmaxsec         = 0x0100,
 241         Mautoacoustic   = 0x0200,
 242         Maddr48         = 0x0400,
 243         Mdevconfov      = 0x0800,
 244         Mflush          = 0x1000,
 245         Mflush48        = 0x2000,
 246         Msmarterror     = 0x0001,
 247         Msmartselftest  = 0x0002,
 248         Mmserial        = 0x0004,
 249         Mmpassthru      = 0x0008,
 250         Mlogging        = 0x0020,
 251 };
 252
 253 typedef struct Ctlr Ctlr;
 254 typedef struct Drive Drive;
 255
 256 typedef struct Prd {                    /* Physical Region Descriptor */
 257         ulong   pa;                     /* Physical Base Address */
 258         int     count;
 259 } Prd;
 260
 261 enum {
 262         BMspan          = 64*1024,      /* must be power of 2 <= 64*1024 */
 263
 264         Nprd            = SDmaxio/BMspan+2,
 265 };
 266
 267 typedef struct Ctlr {
 268         int     cmdport;
 269         int     ctlport;
 270         int     irq;
 271         int     tbdf;
 272         int     bmiba;                  /* bus master interface base address */
 273         int     maxio;                  /* sector count transfer maximum */
 274         int     span;                   /* don't span this boundary with dma */
 275
 276         Pcidev* pcidev;
 277         void    (*ienable)(Ctlr*);
 278         void    (*idisable)(Ctlr*);
 279         SDev*   sdev;
 280
 281         Drive*  drive[2];
 282
 283         Prd*    prdt;                   /* physical region descriptor table */
 284         void    (*irqack)(Ctlr*);
 285
 286         QLock;                          /* current command */
 287         Drive*  curdrive;
 288         int     command;                /* last command issued (debugging) */
 289         Rendez;
 290         int     done;
 291         uint    nrq;
 292         uint    nildrive;
 293         uint    bsy;
 294
 295         Lock;                           /* register access */
 296 } Ctlr;
 297
 298 typedef struct Drive {
 299         Ctlr*   ctlr;
 300         SDunit  *unit;
 301
 302         int     dev;
 303         ushort  info[256];
 304         Sfis;
 305
 306         int     dma;                    /* DMA R/W possible */
 307         int     dmactl;
 308         int     rwm;                    /* read/write multiple possible */
 309         int     rwmctl;
 310
 311         int     pkt;                    /* PACKET device, length of pktcmd */
 312         uchar   pktcmd[16];
 313         int     pktdma;                 /* this PACKET command using dma */
 314
 315         uvlong  sectors;
 316         uint    secsize;
 317         char    serial[20+1];
 318         char    firmware[8+1];
 319         char    model[40+1];
 320
 321         QLock;                          /* drive access */
 322         int     command;                /* current command */
 323         int     write;
 324         uchar*  data;
 325         int     dlen;
 326         uchar*  limit;
 327         int     count;                  /* sectors */
 328         int     block;                  /* R/W bytes per block */
 329         int     status;
 330         int     error;
 331         int     flags;                  /* internal flags */
 332         uint    missirq;
 333         uint    spurloop;
 334         uint    irq;
 335         uint    bsy;
 336 } Drive;
 337
 338 enum {                                  /* internal flags */
 339         Lba48always     = 0x2,          /* ... */
 340         Online          = 0x4,          /* drive onlined */
 341 };
 342
 343 static void
 344 pc87415ienable(Ctlr* ctlr)
 345 {
 346         Pcidev *p;
 347         int x;
 348
 349         p = ctlr->pcidev;
 350         if(p == nil)
 351                 return;
 352
 353         x = pcicfgr32(p, 0x40);
 354         if(ctlr->cmdport == p->mem[0].bar)
 355                 x &= ~0x00000100;
 356         else
 357                 x &= ~0x00000200;
 358         pcicfgw32(p, 0x40, x);
 359 }
 360
 361 static void
 362 atadumpstate(Drive* drive, SDreq *r, uvlong lba, int count)
 363 {
 364         Prd *prd;
 365         Pcidev *p;
 366         Ctlr *ctlr;
 367         int i, bmiba, ccnt;
 368         uvlong clba;
 369
 370         if(!(DEBUG & DbgSTATE))
 371                 return;
 372
 373         ctlr = drive->ctlr;
 374         print("command %2.2uX\n", ctlr->command);
 375         print("data %8.8p limit %8.8p dlen %d status %uX error %uX\n",
 376                 drive->data, drive->limit, drive->dlen,
 377                 drive->status, drive->error);
 378         if(r->clen == -16)
 379                 clba = fisrw(nil, r->cmd, &ccnt);
 380         else
 381                 sdfakescsirw(r, &clba, &ccnt, 0);
 382         print("lba %llud -> %llud, count %d -> %d (%d)\n",
 383                 clba, lba, ccnt, count, drive->count);
 384         if(!(inb(ctlr->ctlport+As) & Bsy)){
 385                 for(i = 1; i < 7; i++)
 386                         print(" 0x%2.2uX", inb(ctlr->cmdport+i));
 387                 print(" 0x%2.2uX\n", inb(ctlr->ctlport+As));
 388         }
 389         if(drive->command == Cwd || drive->command == Crd
 390         || drive->command == (Pdma|Pin) || drive->command == (Pdma|Pout)){
 391                 bmiba = ctlr->bmiba;
 392                 prd = ctlr->prdt;
 393                 print("bmicx %2.2uX bmisx %2.2uX prdt %8.8p\n",
 394                         inb(bmiba+Bmicx), inb(bmiba+Bmisx), prd);
 395                 for(;;){
 396                         print("pa 0x%8.8luX count %8.8uX\n",
 397                                 prd->pa, prd->count);
 398                         if(prd->count & PrdEOT)
 399                                 break;
 400                         prd++;
 401                 }
 402         }
 403         if(ctlr->pcidev && ctlr->pcidev->vid == 0x8086){
 404                 p = ctlr->pcidev;
 405                 print("0x40: %4.4uX 0x42: %4.4uX ",
 406                         pcicfgr16(p, 0x40), pcicfgr16(p, 0x42));
 407                 print("0x48: %2.2uX\n", pcicfgr8(p, 0x48));
 408                 print("0x4A: %4.4uX\n", pcicfgr16(p, 0x4A));
 409         }
 410 }
 411
 412 static void
 413 atadebug(int cmdport, int ctlport, char* fmt, ...)
 414 {
 415         char *p, *e, buf[PRINTSIZE];
 416         int i;
 417         va_list arg;
 418
 419         if(!(DEBUG & DbgPROBE))
 420                 return;
 421
 422         p = buf;
 423         e = buf + sizeof buf;
 424         va_start(arg, fmt);
 425         p = vseprint(p, e, fmt, arg);
 426         va_end(arg);
 427
 428         if(cmdport){
 429                 if(p > buf && p[-1] == '\n')
 430                         p--;
 431                 p = seprint(p, e, " ataregs 0x%uX:", cmdport);
 432                 for(i = Features; i < Command; i++)
 433                         p = seprint(p, e, " 0x%2.2uX", inb(cmdport+i));
 434                 if(ctlport)
 435                         p = seprint(p, e, " 0x%2.2uX", inb(ctlport+As));
 436                 p = seprint(p, e, "\n");
 437         }
 438         putstrn(buf, p - buf);
 439 }
 440
 441 static int
 442 ataready(int cmdport, int ctlport, int dev, int reset, int ready, int m)
 443 {
 444         int as, m0;
 445
 446         atadebug(cmdport, ctlport, "ataready: dev %ux:%ux reset %ux ready %ux",
 447                 cmdport, dev, reset, ready);
 448         m0 = m;
 449         do{
 450                 /*
 451                  * Wait for the controller to become not busy and
 452                  * possibly for a status bit to become true (usually
 453                  * Drdy). Must change to the appropriate device
 454                  * register set if necessary before testing for ready.
 455                  * Always run through the loop at least once so it
 456                  * can be used as a test for !Bsy.
 457                  */
 458                 as = inb(ctlport+As);
 459                 if(as & reset){
 460                         /* nothing to do */
 461                 }
 462                 else if(dev){
 463                         outb(cmdport+Dh, dev);
 464                         dev = 0;
 465                 }
 466                 else if(ready == 0 || (as & ready)){
 467                         atadebug(0, 0, "ataready: %d:%d %#.2ux\n", m, m0, as);
 468                         return as;
 469                 }
 470                 microdelay(1);
 471         }while(m-- > 0);
 472         atadebug(0, 0, "ataready: timeout %d %#.2ux\n", m0, as);
 473         return -1;
 474 }
 475
 476 static int
 477 atadone(void* arg)
 478 {
 479         return ((Ctlr*)arg)->done;
 480 }
 481
 482 static int
 483 atarwmmode(Drive* drive, int cmdport, int ctlport, int dev)
 484 {
 485         int as, maxrwm, rwm;
 486
 487         maxrwm = drive->info[Imaxrwm] & 0xFF;
 488         if(maxrwm == 0)
 489                 return 0;
 490
 491         /*
 492          * Sometimes drives come up with the current count set
 493          * to 0; if so, set a suitable value, otherwise believe
 494          * the value in Irwm if the 0x100 bit is set.
 495          */
 496         if(drive->info[Irwm] & 0x100)
 497                 rwm = drive->info[Irwm] & 0xFF;
 498         else
 499                 rwm = 0;
 500         if(rwm == 0)
 501                 rwm = maxrwm;
 502         if(rwm > 16)
 503                 rwm = 16;
 504         if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 102*1000) < 0)
 505                 return 0;
 506         outb(cmdport+Count, rwm);
 507         outb(cmdport+Command, Csm);
 508         microdelay(1);
 509         as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 1000);
 510         inb(cmdport+Status);
 511         if(as < 0 || (as & (Df|Err)))
 512                 return 0;
 513
 514         drive->rwm = rwm;
 515
 516         return rwm;
 517 }
 518
 519 static int
 520 atadmamode(SDunit *unit, Drive* drive)
 521 {
 522         char buf[32], *s;
 523         int dma;
 524
 525         /*
 526          * Check if any DMA mode enabled.
 527          * Assumes the BIOS has picked and enabled the best.
 528          * This is completely passive at the moment, no attempt is
 529          * made to ensure the hardware is correctly set up.
 530          */
 531         dma = drive->info[Imwdma] & 0x0707;
 532         drive->dma = (dma>>8) & dma;
 533         if(drive->dma == 0 && (drive->info[Ivalid] & 0x04)){
 534                 dma = drive->info[Iudma] & 0x7F7F;
 535                 drive->dma = (dma>>8) & dma;
 536                 if(drive->dma)
 537                         drive->dma |= 'U'<<16;
 538         }
 539         if(unit != nil){
 540                 snprint(buf, sizeof buf, "*%sdma", unit->name);
 541                 s = getconf(buf);
 542                 if((s && !strcmp(s, "on")) || (!s && !getconf("*nodma")))
 543                         drive->dmactl = drive->dma;
 544         }
 545         return dma;
 546 }
 547
 548 static int
 549 ataidentify(Ctlr*, int cmdport, int ctlport, int dev, int pkt, void* info)
 550 {
 551         int as, command, drdy;
 552
 553         if(pkt){
 554                 command = Cidpkt;
 555                 drdy = 0;
 556         }
 557         else{
 558                 command = Cid;
 559                 drdy = Drdy;
 560         }
 561         dev &= ~Lba;
 562         as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
 563         if(as < 0)
 564                 return as;
 565         outb(cmdport+Command, command);
 566         microdelay(1);
 567
 568         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
 569         if(as < 0)
 570                 return -1;
 571         if(as & Err)
 572                 return as;
 573
 574         memset(info, 0, 512);
 575         inss(cmdport+Data, info, 256);
 576         ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 3*1000);
 577         inb(cmdport+Status);
 578
 579         return 0;
 580 }
 581
 582 static Drive*
 583 atadrive(SDunit *unit, Drive *drive, int cmdport, int ctlport, int dev)
 584 {
 585         int as, pkt;
 586         uchar buf[512], oserial[21];
 587         uvlong osectors;
 588         Ctlr *ctlr;
 589
 590         if(DEBUG & DbgIDENTIFY)
 591                 print("identify: port %ux dev %.2ux\n", cmdport, dev & ~Lba);
 592         atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
 593         pkt = 1;
 594         if(drive != nil){
 595                 osectors = drive->sectors;
 596                 memmove(oserial, drive->serial, sizeof drive->serial);
 597                 ctlr = drive->ctlr;
 598         }else{
 599                 osectors = 0;
 600                 memset(oserial, 0, sizeof drive->serial);
 601                 ctlr = nil;
 602         }
 603 retry:
 604         as = ataidentify(ctlr, cmdport, ctlport, dev, pkt, buf);
 605         if(as < 0)
 606                 return nil;
 607         if(as & Err){
 608                 if(pkt == 0)
 609                         return nil;
 610                 pkt = 0;
 611                 goto retry;
 612         }
 613
 614         if(drive == 0){
 615                 if((drive = malloc(sizeof(Drive))) == nil)
 616                         return nil;
 617                 drive->serial[0] = ' ';
 618                 drive->dev = dev;
 619         }
 620
 621         memmove(drive->info, buf, sizeof(drive->info));
 622
 623         setfissig(drive, pkt? 0xeb140000: 0x0101);
 624         drive->sectors = idfeat(drive, drive->info);
 625         drive->secsize = idss(drive, drive->info);
 626
 627         idmove(drive->serial, drive->info+10, 20);
 628         idmove(drive->firmware, drive->info+23, 8);
 629         idmove(drive->model, drive->info+27, 40);
 630         if(unit != nil){
 631                 memset(unit->inquiry, 0, sizeof unit->inquiry);
 632                 unit->inquiry[2] = 2;
 633                 unit->inquiry[3] = 2;
 634                 unit->inquiry[4] = sizeof unit->inquiry - 4;
 635                 memmove(unit->inquiry+8, drive->model, 40);
 636         }
 637
 638         if(pkt){
 639                 drive->pkt = 12;
 640                 if(drive->feat & Datapi16)
 641                         drive->pkt = 16;
 642         }else{
 643                 drive->pkt = 0;
 644                 if(drive->feat & Dlba)
 645                         drive->dev |= Lba;
 646                 atarwmmode(drive, cmdport, ctlport, dev);
 647         }
 648         atadmamode(unit, drive);
 649
 650         if(osectors != 0 && memcmp(oserial, drive->serial, sizeof oserial) != 0)
 651                 if(unit)
 652                         unit->sectors = 0;
 653         drive->unit = unit;
 654         if(DEBUG & DbgCONFIG){
 655                 print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
 656                         dev, cmdport, drive->info[Iconfig], drive->info[Icapabilities]);
 657                 print(" mwdma %4.4uX", drive->info[Imwdma]);
 658                 if(drive->info[Ivalid] & 0x04)
 659                         print(" udma %4.4uX", drive->info[Iudma]);
 660                 print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
 661                 if(drive->feat&Dllba)
 662                         print("\tLLBA sectors %llud", drive->sectors);
 663                 print("\n");
 664         }
 665
 666         return drive;
 667 }
 668
 669 static void
 670 atasrst(int ctlport)
 671 {
 672         int dc0;
 673
 674         /*
 675          * Srst is a big stick and may cause problems if further
 676          * commands are tried before the drives become ready again.
 677          * Also, there will be problems here if overlapped commands
 678          * are ever supported.
 679          */
 680         dc0 = inb(ctlport+Dc);
 681         microdelay(5);
 682         outb(ctlport+Dc, Srst|dc0);
 683         microdelay(5);
 684         outb(ctlport+Dc, dc0);
 685         microdelay(2*1000);
 686 }
 687
 688 static int
 689 seldev(int dev, int map)
 690 {
 691         if((dev & Devs) == Dev0 && map&1)
 692                 return dev;
 693         if((dev & Devs) == Dev1 && map&2)
 694                 return dev;
 695         return -1;
 696 }
 697
 698 static SDev*
 699 ataprobe(int cmdport, int ctlport, int irq, int map)
 700 {
 701         Ctlr* ctlr;
 702         SDev *sdev;
 703         Drive *drive;
 704         int dev, error, rhi, rlo;
 705         static int nonlegacy = 'C';
 706
 707         if(ioalloc(cmdport, 8, 0, "atacmd") < 0) {
 708                 print("ataprobe: Cannot allocate %X\n", cmdport);
 709                 return nil;
 710         }
 711         if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
 712                 print("ataprobe: Cannot allocate %X\n", ctlport + As);
 713                 iofree(cmdport);
 714                 return nil;
 715         }
 716
 717         /*
 718          * Try to detect a floating bus.
 719          * Bsy should be cleared. If not, see if the cylinder registers
 720          * are read/write capable.
 721          * If the master fails, try the slave to catch slave-only
 722          * configurations.
 723          * There's no need to restore the tested registers as they will
 724          * be reset on any detected drives by the Cedd command.
 725          * All this indicates is that there is at least one drive on the
 726          * controller; when the non-existent drive is selected in a
 727          * single-drive configuration the registers of the existing drive
 728          * are often seen, only command execution fails.
 729          */
 730         if((dev = seldev(Dev0, map)) == -1)
 731         if((dev = seldev(Dev1, map)) == -1)
 732                 goto release;
 733         if(inb(ctlport+As) & Bsy){
 734                 outb(cmdport+Dh, dev);
 735                 microdelay(1);
 736 trydev1:
 737                 atadebug(cmdport, ctlport, "ataprobe bsy");
 738                 outb(cmdport+Cyllo, 0xAA);
 739                 outb(cmdport+Cylhi, 0x55);
 740                 outb(cmdport+Sector, 0xFF);
 741                 rlo = inb(cmdport+Cyllo);
 742                 rhi = inb(cmdport+Cylhi);
 743                 if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55)){
 744                         if(dev == Dev1 || (dev = seldev(Dev1, map)) == -1){
 745 release:
 746                                 outb(cmdport+Dc, Nien);
 747                                 inb(cmdport+Status);
 748                                 /* further measures to prevent irqs? */
 749                                 iofree(cmdport);
 750                                 iofree(ctlport+As);
 751                                 return nil;
 752                         }
 753                         if(ataready(cmdport, ctlport, dev, Bsy, 0, 20*1000) < 0)
 754                                 goto trydev1;
 755                 }
 756         }
 757
 758         /*
 759          * Disable interrupts on any detected controllers.
 760          */
 761         outb(ctlport+Dc, Nien);
 762 tryedd1:
 763         if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 105*1000) < 0){
 764                 /*
 765                  * There's something there, but it didn't come up clean,
 766                  * so try hitting it with a big stick. The timing here is
 767                  * wrong but this is a last-ditch effort and it sometimes
 768                  * gets some marginal hardware back online.
 769                  */
 770                 atasrst(ctlport);
 771                 if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 106*1000) < 0)
 772                         goto release;
 773         }
 774
 775         /*
 776          * Can only get here if controller is not busy.
 777          * If there are drives Bsy will be set within 400nS,
 778          * must wait 2mS before testing Status.
 779          * Wait for the command to complete (6 seconds max).
 780          */
 781         outb(cmdport+Command, Cedd);
 782         delay(2);
 783         if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 6*1000*1000) < 0)
 784                 goto release;
 785
 786         /*
 787          * If bit 0 of the error register is set then the selected drive
 788          * exists. This is enough to detect single-drive configurations.
 789          * However, if the master exists there is no way short of executing
 790          * a command to determine if a slave is present.
 791          * It appears possible to get here testing Dev0 although it doesn't
 792          * exist and the EDD won't take, so try again with Dev1.
 793          */
 794         error = inb(cmdport+Error);
 795         atadebug(cmdport, ctlport, "ataprobe: dev %uX", dev);
 796         if((error & ~0x80) != 0x01){
 797                 if(dev == Dev1)
 798                         goto release;
 799                 if((dev = seldev(Dev1, map)) == -1)
 800                         goto release;
 801                 goto tryedd1;
 802         }
 803
 804         /*
 805          * At least one drive is known to exist, try to
 806          * identify it. If that fails, don't bother checking
 807          * any further.
 808          * If the one drive found is Dev0 and the EDD command
 809          * didn't indicate Dev1 doesn't exist, check for it.
 810          */
 811         if((drive = atadrive(0, 0, cmdport, ctlport, dev)) == nil)
 812                 goto release;
 813         if((ctlr = malloc(sizeof(Ctlr))) == nil){
 814                 free(drive);
 815                 goto release;
 816         }
 817         if((sdev = malloc(sizeof(SDev))) == nil){
 818                 free(ctlr);
 819                 free(drive);
 820                 goto release;
 821         }
 822         drive->ctlr = ctlr;
 823         if(dev == Dev0){
 824                 ctlr->drive[0] = drive;
 825                 if(!(error & 0x80)){
 826                         /*
 827                          * Always leave Dh pointing to a valid drive,
 828                          * otherwise a subsequent call to ataready on
 829                          * this controller may try to test a bogus Status.
 830                          * Ataprobe is the only place possibly invalid
 831                          * drives should be selected.
 832                          */
 833                         drive = atadrive(0, 0, cmdport, ctlport, Dev1);
 834                         if(drive != nil){
 835                                 drive->ctlr = ctlr;
 836                                 ctlr->drive[1] = drive;
 837                         }
 838                         else{
 839                                 outb(cmdport+Dh, Dev0);
 840                                 microdelay(1);
 841                         }
 842                 }
 843         }
 844         else
 845                 ctlr->drive[1] = drive;
 846
 847         ctlr->cmdport = cmdport;
 848         ctlr->ctlport = ctlport;
 849         ctlr->irq = irq;
 850         ctlr->tbdf = BUSUNKNOWN;
 851         ctlr->command = Cedd;           /* debugging */
 852
 853         switch(cmdport){
 854         default:
 855                 sdev->idno = nonlegacy;
 856                 break;
 857         case 0x1F0:
 858                 sdev->idno = 'C';
 859                 nonlegacy = 'E';
 860                 break;
 861         case 0x170:
 862                 sdev->idno = 'D';
 863                 nonlegacy = 'E';
 864                 break;
 865         }
 866         sdev->ifc = &sdideifc;
 867         sdev->ctlr = ctlr;
 868         sdev->nunit = 2;
 869         ctlr->sdev = sdev;
 870
 871         return sdev;
 872 }
 873
 874 static void
 875 ataclear(SDev *sdev)
 876 {
 877         Ctlr* ctlr;
 878
 879         ctlr = sdev->ctlr;
 880         iofree(ctlr->cmdport);
 881         iofree(ctlr->ctlport + As);
 882
 883         if (ctlr->drive[0])
 884                 free(ctlr->drive[0]);
 885         if (ctlr->drive[1])
 886                 free(ctlr->drive[1]);
 887         if (sdev->name)
 888                 free(sdev->name);
 889         if (sdev->unitflg)
 890                 free(sdev->unitflg);
 891         if (sdev->unit)
 892                 free(sdev->unit);
 893         free(ctlr);
 894         free(sdev);
 895 }
 896
 897 static char *
 898 atastat(SDev *sdev, char *p, char *e)
 899 {
 900         Ctlr *ctlr;
 901
 902         ctlr = sdev->ctlr;
 903 //      return seprint(p, e, "%s ata port %X ctl %X irq %d %T\n",
 904 //                  sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq, ctlr->tbdf);
 905         return seprint(p, e, "%s ata port %X ctl %X irq %d\n",
 906                     sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq);
 907 }
 908
 909 static SDev*
 910 ataprobew(DevConf *cf)
 911 {
 912         char *p;
 913         ISAConf isa;
 914
 915         if (cf->nports != 2)
 916                 error(Ebadarg);
 917
 918         memset(&isa, 0, sizeof isa);
 919         isa.port = cf->ports[0].port;
 920         isa.irq = cf->intnum;
 921         if((p=strchr(cf->type, '/')) == nil || pcmspecial(p+1, &isa) < 0)
 922                 error("cannot find controller");
 923
 924         return ataprobe(cf->ports[0].port, cf->ports[1].port, cf->intnum, 3);
 925 }
 926
 927 static void atainterrupt(Ureg*, void*);
 928
 929 static int
 930 iowait(Drive *drive, int ms, int interrupt)
 931 {
 932         int msec, step;
 933         Ctlr *ctlr;
 934
 935         step = 1000;
 936         if(drive->missirq > 10)
 937                 step = 50;
 938         ctlr = drive->ctlr;
 939         for(msec = 0; msec < ms; msec += step){
 940                 while(waserror())
 941                         if(interrupt)
 942                                 return -1;
 943                 tsleep(ctlr, atadone, ctlr, step);
 944                 poperror();
 945                 if(ctlr->done)
 946                         break;
 947                 atainterrupt(nil, ctlr);
 948                 if(ctlr->done){
 949                         if(drive->missirq++ < 3)
 950                                 print("ide: caught missed irq\n");
 951                         break;
 952                 }else
 953                         drive->spurloop++;
 954         }
 955         return ctlr->done;
 956 }
 957
 958 static void
 959 atanop(Drive* drive, int subcommand)
 960 {
 961         Ctlr* ctlr;
 962         int as, cmdport, ctlport, timeo;
 963
 964         /*
 965          * Attempt to abort a command by using NOP.
 966          * In response, the drive is supposed to set Abrt
 967          * in the Error register, set (Drdy|Err) in Status
 968          * and clear Bsy when done. However, some drives
 969          * (e.g. ATAPI Zip) just go Bsy then clear Status
 970          * when done, hence the timeout loop only on Bsy
 971          * and the forced setting of drive->error.
 972          */
 973         ctlr = drive->ctlr;
 974         cmdport = ctlr->cmdport;
 975         outb(cmdport+Features, subcommand);
 976         outb(cmdport+Dh, drive->dev);
 977         ctlr->command = Cnop;           /* debugging */
 978         outb(cmdport+Command, Cnop);
 979
 980         microdelay(1);
 981         ctlport = ctlr->ctlport;
 982         for(timeo = 0; timeo < 1000; timeo++){
 983                 as = inb(ctlport+As);
 984                 if(!(as & Bsy))
 985                         break;
 986                 microdelay(1);
 987         }
 988         drive->error |= Abrt;
 989 }
 990
 991 static void
 992 ataabort(Drive* drive, int dolock)
 993 {
 994         /*
 995          * If NOP is available use it otherwise
 996          * must try a software reset.
 997          */
 998         if(dolock)
 999                 ilock(drive->ctlr);
1000         if(drive->feat & Dnop)
1001                 atanop(drive, 0);
1002         else{
1003                 atasrst(drive->ctlr->ctlport);
1004                 drive->error |= Abrt;
1005         }
1006         if(dolock)
1007                 iunlock(drive->ctlr);
1008 }
1009
1010 static int
1011 atadmasetup(Drive* drive, int len)
1012 {
1013         Prd *prd;
1014         ulong pa;
1015         Ctlr *ctlr;
1016         int bmiba, bmisx, count, i, span;
1017
1018         ctlr = drive->ctlr;
1019         pa = PCIWADDR(drive->data);
1020         if(pa & 0x03)
1021                 return -1;
1022
1023         /*
1024          * Sometimes drives identify themselves as being DMA capable
1025          * although they are not on a busmastering controller.
1026          */
1027         prd = ctlr->prdt;
1028         if(prd == nil){
1029                 drive->dmactl = 0;
1030                 print("disabling dma: not on a busmastering controller\n");
1031                 return -1;
1032         }
1033
1034         for(i = 0; len && i < Nprd; i++){
1035                 prd->pa = pa;
1036                 span = ROUNDUP(pa, ctlr->span);
1037                 if(span == pa)
1038                         span += ctlr->span;
1039                 count = span - pa;
1040                 if(count >= len){
1041                         prd->count = PrdEOT|len;
1042                         break;
1043                 }
1044                 prd->count = count;
1045                 len -= count;
1046                 pa += count;
1047                 prd++;
1048         }
1049         if(i == Nprd)
1050                 (prd-1)->count |= PrdEOT;
1051
1052         bmiba = ctlr->bmiba;
1053         outl(bmiba+Bmidtpx, PCIWADDR(ctlr->prdt));
1054         if(drive->write)
1055                 outb(bmiba+Bmicx, 0);
1056         else
1057                 outb(bmiba+Bmicx, Rwcon);
1058         bmisx = inb(bmiba+Bmisx);
1059         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
1060
1061         return 0;
1062 }
1063
1064 static void
1065 atadmastart(Ctlr* ctlr, int write)
1066 {
1067         if(write)
1068                 outb(ctlr->bmiba+Bmicx, Ssbm);
1069         else
1070                 outb(ctlr->bmiba+Bmicx, Rwcon|Ssbm);
1071 }
1072
1073 static int
1074 atadmastop(Ctlr* ctlr)
1075 {
1076         int bmiba;
1077
1078         bmiba = ctlr->bmiba;
1079         outb(bmiba+Bmicx, inb(bmiba+Bmicx) & ~Ssbm);
1080
1081         return inb(bmiba+Bmisx);
1082 }
1083
1084 static void
1085 atadmainterrupt(Drive* drive, int count)
1086 {
1087         Ctlr* ctlr;
1088         int bmiba, bmisx;
1089
1090         ctlr = drive->ctlr;
1091         bmiba = ctlr->bmiba;
1092         bmisx = inb(bmiba+Bmisx);
1093         switch(bmisx & (Ideints|Idedmae|Bmidea)){
1094         case Bmidea:
1095                 /*
1096                  * Data transfer still in progress, nothing to do
1097                  * (this should never happen).
1098                  */
1099                 return;
1100
1101         case Ideints:
1102         case Ideints|Bmidea:
1103                 /*
1104                  * Normal termination, tidy up.
1105                  */
1106                 drive->data += count;
1107                 break;
1108
1109         default:
1110                 /*
1111                  * What's left are error conditions (memory transfer
1112                  * problem) and the device is not done but the PRD is
1113                  * exhausted. For both cases must somehow tell the
1114                  * drive to abort.
1115                  */
1116                 ataabort(drive, 0);
1117                 break;
1118         }
1119         atadmastop(ctlr);
1120         ctlr->done = 1;
1121 }
1122
1123 static void
1124 atapktinterrupt(Drive* drive)
1125 {
1126         Ctlr* ctlr;
1127         int cmdport, len;
1128
1129         ctlr = drive->ctlr;
1130         cmdport = ctlr->cmdport;
1131         switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
1132         case Cd:
1133                 outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
1134                 break;
1135
1136         case 0:
1137                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1138                 if(drive->data+len > drive->limit){
1139                         atanop(drive, 0);
1140                         break;
1141                 }
1142                 outss(cmdport+Data, drive->data, len/2);
1143                 drive->data += len;
1144                 break;
1145
1146         case Io:
1147                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1148                 if(drive->data+len > drive->limit){
1149                         atanop(drive, 0);
1150                         break;
1151                 }
1152                 inss(cmdport+Data, drive->data, len/2);
1153                 drive->data += len;
1154                 break;
1155
1156         case Io|Cd:
1157                 if(drive->pktdma)
1158                         atadmainterrupt(drive, drive->dlen);
1159                 else
1160                         ctlr->done = 1;
1161                 break;
1162         }
1163 }
1164
1165 static int
1166 atapktio0(Drive *drive, SDreq *r)
1167 {
1168         uchar *cmd;
1169         int as, cmdport, ctlport, len, rv;
1170         Ctlr *ctlr;
1171
1172         rv = SDok;
1173         cmd = r->cmd;
1174         drive->command = Cpkt;
1175         memmove(drive->pktcmd, cmd, r->clen);
1176         memset(drive->pktcmd+r->clen, 0, drive->pkt-r->clen);
1177         drive->limit = drive->data+drive->dlen;
1178
1179         ctlr = drive->ctlr;
1180         cmdport = ctlr->cmdport;
1181         ctlport = ctlr->ctlport;
1182
1183         as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 107*1000);
1184         /* used to test as&Chk as failure too, but some CD readers use that for media change */
1185         if(as < 0)
1186                 return SDnostatus;
1187
1188         ilock(ctlr);
1189         if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen))
1190                 drive->pktdma = Dma;
1191         else
1192                 drive->pktdma = 0;
1193
1194         outb(cmdport+Features, drive->pktdma);
1195         outb(cmdport+Count, 0);
1196         outb(cmdport+Sector, 0);
1197         if(drive->secsize)
1198                 len = 16*drive->secsize;
1199         else
1200                 len = 0x8000;
1201         outb(cmdport+Bytelo, len);
1202         outb(cmdport+Bytehi, len>>8);
1203         outb(cmdport+Dh, drive->dev);
1204         ctlr->done = 0;
1205         ctlr->curdrive = drive;
1206         ctlr->command = Cpkt;           /* debugging */
1207         if(drive->pktdma)
1208                 atadmastart(ctlr, drive->write);
1209         outb(cmdport+Command, Cpkt);
1210
1211         if((drive->info[Iconfig] & Mdrq) != 0x0020){
1212                 microdelay(1);
1213                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 4*1000);
1214                 if(as < 0 || (as & (Bsy|Chk))){
1215                         drive->status = as<0 ? 0 : as;
1216                         ctlr->curdrive = nil;
1217                         ctlr->done = 1;
1218                         rv = SDtimeout;
1219                 }else
1220                         atapktinterrupt(drive);
1221         }
1222         iunlock(ctlr);
1223
1224         if(iowait(drive, 20*1000, 1) <= 0){
1225                 ilock(ctlr);
1226                 if(!drive->error){
1227                         ataabort(drive, 0);
1228                         if(drive->pktdma){
1229                                 atadmastop(ctlr);
1230                                 drive->dmactl = 0;
1231                         }
1232                 }
1233                 if(drive->error){
1234                         drive->status |= Chk;
1235                         ctlr->curdrive = nil;
1236                 }
1237                 iunlock(ctlr);
1238         }
1239
1240         if(drive->status & Chk)
1241                 rv = SDcheck;
1242         return rv;
1243 }
1244
1245 static int
1246 atapktio(Drive* drive, SDreq *r)
1247 {
1248         int n;
1249         Ctlr *ctlr;
1250
1251         ctlr = drive->ctlr;
1252         qlock(ctlr);
1253         n = atapktio0(drive, r);
1254         qunlock(ctlr);
1255         return n;
1256 }
1257
1258 static uchar cmd48[256] = {
1259         [Crs]   Crs48,
1260         [Crd]   Crd48,
1261         [Crsm]  Crsm48,
1262         [Cws]   Cws48,
1263         [Cwd]   Cwd48,
1264         [Cwsm]  Cwsm48,
1265 };
1266
1267 enum{
1268         Last28  = (1<<28) - 1 - 1,
1269 };
1270
1271 static int
1272 atageniostart(Drive* drive, uvlong lba)
1273 {
1274         Ctlr *ctlr;
1275         uchar cmd;
1276         int as, c, cmdport, ctlport, h, len, s, use48;
1277
1278         use48 = 0;
1279         if((drive->flags&Lba48always) || lba > Last28 || drive->count > 256){
1280                 if((drive->feat & Dllba) == 0)
1281                         return -1;
1282                 use48 = 1;
1283                 c = h = s = 0;
1284         }else if(drive->dev & Lba){
1285                 c = (lba>>8) & 0xFFFF;
1286                 h = (lba>>24) & 0x0F;
1287                 s = lba & 0xFF;
1288         }else{
1289                 if (drive->s == 0 || drive->h == 0){
1290                         print("sdide: chs address botch");
1291                         return -1;
1292                 }
1293                 c = lba/(drive->s*drive->h);
1294                 h = (lba/drive->s) % drive->h;
1295                 s = (lba % drive->s) + 1;
1296         }
1297
1298         ctlr = drive->ctlr;
1299         cmdport = ctlr->cmdport;
1300         ctlport = ctlr->ctlport;
1301         if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 101*1000) < 0)
1302                 return -1;
1303
1304         ilock(ctlr);
1305         if(drive->dmactl && !atadmasetup(drive, drive->count*drive->secsize)){
1306                 if(drive->write)
1307                         drive->command = Cwd;
1308                 else
1309                         drive->command = Crd;
1310         }
1311         else if(drive->rwmctl){
1312                 drive->block = drive->rwm*drive->secsize;
1313                 if(drive->write)
1314                         drive->command = Cwsm;
1315                 else
1316                         drive->command = Crsm;
1317         }
1318         else{
1319                 drive->block = drive->secsize;
1320                 if(drive->write)
1321                         drive->command = Cws;
1322                 else
1323                         drive->command = Crs;
1324         }
1325         drive->limit = drive->data + drive->count*drive->secsize;
1326         cmd = drive->command;
1327         if(use48){
1328                 outb(cmdport+Count, drive->count>>8);
1329                 outb(cmdport+Count, drive->count);
1330                 outb(cmdport+Lbalo, lba>>24);
1331                 outb(cmdport+Lbalo, lba);
1332                 outb(cmdport+Lbamid, lba>>32);
1333                 outb(cmdport+Lbamid, lba>>8);
1334                 outb(cmdport+Lbahi, lba>>40);
1335                 outb(cmdport+Lbahi, lba>>16);
1336                 outb(cmdport+Dh, drive->dev|Lba);
1337                 cmd = cmd48[cmd];
1338
1339                 if(DEBUG & Dbg48BIT)
1340                         print("using 48-bit commands\n");
1341         }else{
1342                 outb(cmdport+Count, drive->count);
1343                 outb(cmdport+Sector, s);
1344                 outb(cmdport+Cyllo, c);
1345                 outb(cmdport+Cylhi, c>>8);
1346                 outb(cmdport+Dh, drive->dev|h);
1347         }
1348         ctlr->done = 0;
1349         ctlr->curdrive = drive;
1350         ctlr->command = drive->command; /* debugging */
1351         outb(cmdport+Command, cmd);
1352
1353         switch(drive->command){
1354         case Cws:
1355         case Cwsm:
1356                 microdelay(1);
1357                 /* 10*1000 for flash ide drives - maybe detect them? */
1358                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 10*1000);
1359                 if(as < 0 || (as & Err)){
1360                         iunlock(ctlr);
1361                         return -1;
1362                 }
1363                 len = drive->block;
1364                 if(drive->data+len > drive->limit)
1365                         len = drive->limit-drive->data;
1366                 outss(cmdport+Data, drive->data, len/2);
1367                 break;
1368
1369         case Crd:
1370         case Cwd:
1371                 atadmastart(ctlr, drive->write);
1372                 break;
1373         }
1374         iunlock(ctlr);
1375
1376         return 0;
1377 }
1378
1379 static int
1380 atagenioretry(Drive* drive, SDreq *r, uvlong lba, int count)
1381 {
1382         char *s;
1383         int rv, count0, rw;
1384         uvlong lba0;
1385
1386         if(drive->dmactl){
1387                 drive->dmactl = 0;
1388                 s = "disabling dma";
1389                 rv = SDretry;
1390         }else if(drive->rwmctl){
1391                 drive->rwmctl = 0;
1392                 s = "disabling rwm";
1393                 rv = SDretry;
1394         }else{
1395                 s = "nondma";
1396                 rv = sdsetsense(r, SDcheck, 4, 8, drive->error);
1397         }
1398         sdfakescsirw(r, &lba0, &count0, &rw);
1399         print("atagenioretry: %s %c:%llud:%d @%llud:%d\n",
1400                 s, "rw"[rw], lba0, count0, lba, count);
1401         return rv;
1402 }
1403
1404 static int
1405 atagenio(Drive* drive, SDreq *r)
1406 {
1407         Ctlr *ctlr;
1408         uvlong lba;
1409         int i, rw, count, maxio;
1410
1411         if((i = sdfakescsi(r)) != SDnostatus)
1412                 return i;
1413         if((i = sdfakescsirw(r, &lba, &count, &rw)) != SDnostatus)
1414                 return i;
1415         ctlr = drive->ctlr;
1416         if(drive->data == nil)
1417                 return SDok;
1418         if(drive->dlen < count*drive->secsize)
1419                 count = drive->dlen/drive->secsize;
1420         qlock(ctlr);
1421         if(ctlr->maxio)
1422                 maxio = ctlr->maxio;
1423         else if(drive->feat & Dllba)
1424                 maxio = 65536;
1425         else
1426                 maxio = 256;
1427         while(count){
1428                 if(count > maxio)
1429                         drive->count = maxio;
1430                 else
1431                         drive->count = count;
1432                 if(atageniostart(drive, lba)){
1433                         ilock(ctlr);
1434                         atanop(drive, 0);
1435                         iunlock(ctlr);
1436                         qunlock(ctlr);
1437                         return atagenioretry(drive, r, lba, count);
1438                 }
1439                 iowait(drive, 60*1000, 0);
1440                 if(!ctlr->done){
1441                         /*
1442                          * What should the above timeout be? In
1443                          * standby and sleep modes it could take as
1444                          * long as 30 seconds for a drive to respond.
1445                          * Very hard to get out of this cleanly.
1446                          */
1447                         atadumpstate(drive, r, lba, count);
1448                         ataabort(drive, 1);
1449                         qunlock(ctlr);
1450                         return atagenioretry(drive, r, lba, count);
1451                 }
1452
1453                 if(drive->status & Err){
1454                         qunlock(ctlr);
1455                         print("atagenio: %llud:%d\n", lba, drive->count);
1456                         return sdsetsense(r, SDcheck, 4, 8, drive->error);
1457                 }
1458                 count -= drive->count;
1459                 lba += drive->count;
1460         }
1461         qunlock(ctlr);
1462
1463         return SDok;
1464 }
1465
1466 static int
1467 atario(SDreq* r)
1468 {
1469         uchar *p;
1470         int status;
1471         Ctlr *ctlr;
1472         Drive *drive;
1473         SDunit *unit;
1474
1475         unit = r->unit;
1476         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil){
1477                 r->status = SDtimeout;
1478                 return SDtimeout;
1479         }
1480         drive = ctlr->drive[unit->subno];
1481         qlock(drive);
1482         for(;;){
1483                 drive->write = r->write;
1484                 drive->data = r->data;
1485                 drive->dlen = r->dlen;
1486                 drive->status = 0;
1487                 drive->error = 0;
1488                 if(drive->pkt)
1489                         status = atapktio(drive, r);
1490                 else
1491                         status = atagenio(drive, r);
1492                 if(status != SDretry)
1493                         break;
1494                 if(DbgDEBUG)
1495                         print("%s: retry: dma %8.8uX rwm %4.4uX\n",
1496                                 unit->name, drive->dmactl, drive->rwmctl);
1497         }
1498         if(status == SDok && r->rlen == 0 && (r->flags & SDvalidsense) == 0){
1499                 sdsetsense(r, SDok, 0, 0, 0);
1500                 if(drive->data){
1501                         p = r->data;
1502                         r->rlen = drive->data - p;
1503                 }
1504                 else
1505                         r->rlen = 0;
1506         }
1507         qunlock(drive);
1508         return status;
1509 }
1510
1511 /**/
1512 static int
1513 isdmacmd(Drive *d, SDreq *r)
1514 {
1515         switch(r->ataproto & Pprotom){
1516         default:
1517                 return 0;
1518         case Pdmq:
1519                 error("no queued support");
1520         case Pdma:
1521                 if(!(d->dmactl || d->rwmctl))
1522                         error("dma in non dma mode\n");
1523                 return 1;
1524         }
1525 }
1526
1527 static int
1528 atagenatastart(Drive* d, SDreq *r)
1529 {
1530         uchar u;
1531         int as, cmdport, ctlport, len, pr, isdma;
1532         Ctlr *ctlr;
1533
1534         isdma = isdmacmd(d, r);
1535         ctlr = d->ctlr;
1536         cmdport = ctlr->cmdport;
1537         ctlport = ctlr->ctlport;
1538         if(ataready(cmdport, ctlport, d->dev, Bsy|Drq, d->pkt? 0: Drdy, 101*1000) < 0)
1539                 return -1;
1540
1541         ilock(ctlr);
1542         if(isdma && atadmasetup(d, d->block)){
1543                 iunlock(ctlr);
1544                 return -1;
1545
1546         }
1547         if(d->feat & Dllba && (r->ataproto & P28) == 0){
1548                 outb(cmdport+Features, r->cmd[Ffeat8]);
1549                 outb(cmdport+Features, r->cmd[Ffeat]);
1550                 outb(cmdport+Count, r->cmd[Fsc8]);
1551                 outb(cmdport+Count, r->cmd[Fsc]);
1552                 outb(cmdport+Lbalo, r->cmd[Flba24]);
1553                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1554                 outb(cmdport+Lbamid, r->cmd[Flba32]);
1555                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1556                 outb(cmdport+Lbahi, r->cmd[Flba40]);
1557                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1558                 u = r->cmd[Fdev] & ~0xb0;
1559                 outb(cmdport+Dh, d->dev|u);
1560         }else{
1561                 outb(cmdport+Features, r->cmd[Ffeat]);
1562                 outb(cmdport+Count, r->cmd[Fsc]);
1563                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1564                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1565                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1566                 u = r->cmd[Fdev] & ~0xb0;
1567                 outb(cmdport+Dh, d->dev|u);
1568         }
1569         ctlr->done = 0;
1570         ctlr->curdrive = d;
1571         d->command = r->ataproto & (Pprotom|Pdatam);
1572         ctlr->command = r->cmd[Fcmd];
1573         outb(cmdport+Command, r->cmd[Fcmd]);
1574
1575         pr = r->ataproto & Pprotom;
1576         if(pr == Pnd || pr == Preset)
1577                 USED(d);
1578         else if(!isdma){
1579                 microdelay(1);
1580                 /* 10*1000 for flash ide drives - maybe detect them? */
1581                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 10*1000);
1582                 if(as < 0 || (as & Err)){
1583                         iunlock(ctlr);
1584                         return -1;
1585                 }
1586                 len = d->block;
1587                 if(r->write && len > 0)
1588                         outss(cmdport+Data, d->data, len/2);
1589         }else
1590                 atadmastart(ctlr, d->write);
1591         iunlock(ctlr);
1592         return 0;
1593 }
1594
1595 static void
1596 mkrfis(Drive *d, SDreq *r)
1597 {
1598         uchar *u;
1599         int cmdport;
1600         Ctlr *ctlr;
1601
1602         ctlr = d->ctlr;
1603         cmdport = ctlr->cmdport;
1604         u = r->cmd;
1605
1606         ilock(ctlr);
1607         u[Ftype] = 0x34;
1608         u[Fioport] = 0;
1609         if((d->feat & Dllba) && (r->ataproto & P28) == 0){
1610                 u[Frerror] = inb(cmdport+Error);
1611                 u[Fsc8] = inb(cmdport+Count);
1612                 u[Fsc] = inb(cmdport+Count);
1613                 u[Flba24] = inb(cmdport+Lbalo);
1614                 u[Flba0] = inb(cmdport+Lbalo);
1615                 u[Flba32] = inb(cmdport+Lbamid);
1616                 u[Flba8] = inb(cmdport+Lbamid);
1617                 u[Flba40] = inb(cmdport+Lbahi);
1618                 u[Flba16] = inb(cmdport+Lbahi);
1619                 u[Fdev] = inb(cmdport+Dh);
1620                 u[Fstatus] = inb(cmdport+Status);
1621         }else{
1622                 u[Frerror] = inb(cmdport+Error);
1623                 u[Fsc] = inb(cmdport+Count);
1624                 u[Flba0] = inb(cmdport+Lbalo);
1625                 u[Flba8] = inb(cmdport+Lbamid);
1626                 u[Flba16] = inb(cmdport+Lbahi);
1627                 u[Fdev] = inb(cmdport+Dh);
1628                 u[Fstatus] = inb(cmdport+Status);
1629         }
1630         iunlock(ctlr);
1631 }
1632
1633 static int
1634 atarstdone(Drive *d)
1635 {
1636         int as;
1637         Ctlr *c;
1638
1639         c = d->ctlr;
1640         as = ataready(c->cmdport, c->ctlport, 0, Bsy|Drq, 0, 5*1000);
1641         c->done = as >= 0;
1642         return c->done;
1643 }
1644
1645 static uint
1646 cmdss(Drive *d, SDreq *r)
1647 {
1648         switch(r->cmd[Fcmd]){
1649         case Cid:
1650         case Cidpkt:
1651                 return 512;
1652         default:
1653                 return d->secsize;
1654         }
1655 }
1656
1657 /*
1658  * various checks.  we should be craftier and
1659  * avoid figuring out how big stuff is supposed to be.
1660  */
1661 static uint
1662 patasizeck(Drive *d, SDreq *r)
1663 {
1664         uint count, maxio, secsize;
1665         Ctlr *ctlr;
1666
1667         secsize = cmdss(d, r);          /* BOTCH */
1668         if(secsize == 0)
1669                 error(Eio);
1670         count = r->dlen / secsize;
1671         ctlr = d->ctlr;
1672         if(ctlr->maxio)
1673                 maxio = ctlr->maxio;
1674         else if((d->feat & Dllba) && (r->ataproto & P28) == 0)
1675                 maxio = 65536;
1676         else
1677                 maxio = 256;
1678         if(count > maxio){
1679                 uprint("i/o too large, lim %d", maxio);
1680                 error(up->genbuf);
1681         }
1682         if(r->ataproto&Ppio && count > 1)
1683                 error("invalid # of sectors");
1684         return count;
1685 }
1686
1687 static int
1688 atapataio(Drive *d, SDreq *r)
1689 {
1690         int rv;
1691         Ctlr *ctlr;
1692
1693         d->count = 0;
1694         if(r->ataproto & Pdatam)
1695                 d->count = patasizeck(d, r);
1696         d->block = r->dlen;
1697         d->limit = d->data + r->dlen;
1698
1699         ctlr = d->ctlr;
1700         qlock(ctlr);
1701         if(waserror()){
1702                 qunlock(ctlr);
1703                 nexterror();
1704         }
1705         rv = atagenatastart(d, r);
1706         poperror();
1707         if(rv){
1708                 if(DEBUG & DbgAtazz)
1709                         print("sdide: !atageatastart\n");
1710                 ilock(ctlr);
1711                 atanop(d, 0);
1712                 iunlock(ctlr);
1713                 qunlock(ctlr);
1714                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1715         }
1716
1717         if((r->ataproto & Pprotom) == Preset)
1718                 atarstdone(d);
1719         else
1720                 while(iowait(d, 30*1000, 1) == 0)
1721                         ;
1722         if(!ctlr->done){
1723                 if(DEBUG & DbgAtazz){
1724                         print("sdide: !done\n");
1725                         atadumpstate(d, r, 0, d->count);
1726                 }
1727                 ataabort(d, 1);
1728                 qunlock(ctlr);
1729                 return sdsetsense(r, SDcheck, 11, 0, 6);        /* aborted; i/o process terminated */
1730         }
1731         mkrfis(d, r);
1732         if(d->status & Err){
1733                 if(DEBUG & DbgAtazz)
1734                         print("sdide: status&Err\n");
1735                 qunlock(ctlr);
1736                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1737         }
1738         qunlock(ctlr);
1739         return SDok;
1740 }
1741
1742 static int
1743 ataataio0(Drive *d, SDreq *r)
1744 {
1745         int i;
1746
1747         if((r->ataproto & Pprotom) == Ppkt){
1748                 if(r->clen > d->pkt)
1749                         error(Eio);
1750                 qlock(d->ctlr);
1751                 i = atapktio0(d, r);
1752                 d->block = d->data - (uchar*)r->data;
1753                 mkrfis(d, r);
1754                 qunlock(d->ctlr);
1755                 return i;
1756         }else
1757                 return atapataio(d, r);
1758 }
1759
1760 /*
1761  * hack to allow udma mode to be set or unset
1762  * via direct ata command.  it would be better
1763  * to move the assumptions about dma mode out
1764  * of some of the helper functions.
1765  */
1766 static int
1767 isudm(SDreq *r)
1768 {
1769         uchar *c;
1770
1771         c = r->cmd;
1772         if(c[Fcmd] == 0xef && c[Ffeat] == 0x03){
1773                 if(c[Fsc]&0x40)
1774                         return 1;
1775                 return -1;
1776         }
1777         return 0;
1778 }
1779
1780 static int
1781 fisreqchk(Sfis *f, SDreq *r)
1782 {
1783         if((r->ataproto & Pprotom) == Ppkt)
1784                 return SDnostatus;
1785         /*
1786          * handle oob requests;
1787          *    restrict & sanitize commands
1788          */
1789         if(r->clen != 16)
1790                 error(Eio);
1791         if(r->cmd[0] == 0xf0){
1792                 sigtofis(f, r->cmd);
1793                 r->status = SDok;
1794                 return SDok;
1795         }
1796         r->cmd[0] = 0x27;
1797         r->cmd[1] = 0x80;
1798         r->cmd[7] |= 0xa0;
1799         return SDnostatus;
1800 }
1801
1802 static int
1803 ataataio(SDreq *r)
1804 {
1805         int status, udm;
1806         Ctlr *c;
1807         Drive *d;
1808         SDunit *u;
1809
1810         u = r->unit;
1811         if((c = u->dev->ctlr) == nil || (d = c->drive[u->subno]) == nil){
1812                 r->status = SDtimeout;
1813                 return SDtimeout;
1814         }
1815         if((status = fisreqchk(d, r)) != SDnostatus)
1816                 return status;
1817         udm = isudm(r);
1818
1819         qlock(d);
1820         if(waserror()){
1821                 qunlock(d);
1822                 nexterror();
1823         }
1824 retry:
1825         d->write = r->write;
1826         d->data = r->data;
1827         d->dlen = r->dlen;
1828         d->status = 0;
1829         d->error = 0;
1830
1831         switch(status = ataataio0(d, r)){
1832         case SDretry:
1833                 if(DbgDEBUG)
1834                         print("%s: retry: dma %.8ux rwm %.4ux\n",
1835                                 u->name, d->dmactl, d->rwmctl);
1836                 goto retry;
1837         case SDok:
1838                 if(udm == 1)
1839                         d->dmactl = d->dma;
1840                 else if(udm == -1)
1841                         d->dmactl = 0;
1842                 sdsetsense(r, SDok, 0, 0, 0);
1843                 r->rlen = d->block;
1844                 break;
1845         }
1846         poperror();
1847         qunlock(d);
1848         r->status = status;
1849         return status;
1850 }
1851 /**/
1852
1853 static void
1854 ichirqack(Ctlr *ctlr)
1855 {
1856         int bmiba;
1857
1858         if(bmiba = ctlr->bmiba)
1859                 outb(bmiba+Bmisx, inb(bmiba+Bmisx));
1860 }
1861
1862 static void
1863 atainterrupt(Ureg*, void* arg)
1864 {
1865         Ctlr *ctlr;
1866         Drive *drive;
1867         int cmdport, len, status;
1868
1869         ctlr = arg;
1870
1871         ilock(ctlr);
1872         ctlr->nrq++;
1873         if(ctlr->curdrive)
1874                 ctlr->curdrive->irq++;
1875         if(inb(ctlr->ctlport+As) & Bsy){
1876                 ctlr->bsy++;
1877                 if(ctlr->curdrive)
1878                         ctlr->curdrive->bsy++;
1879                 iunlock(ctlr);
1880                 if(DEBUG & DbgBsy)
1881                         print("IBsy+");
1882                 return;
1883         }
1884         cmdport = ctlr->cmdport;
1885         status = inb(cmdport+Status);
1886         if((drive = ctlr->curdrive) == nil){
1887                 ctlr->nildrive++;
1888                 if(ctlr->irqack != nil)
1889                         ctlr->irqack(ctlr);
1890                 iunlock(ctlr);
1891                 if((DEBUG & DbgINL) && ctlr->command != Cedd)
1892                         print("Inil%2.2uX+", ctlr->command);
1893                 return;
1894         }
1895
1896         if(status & Err)
1897                 drive->error = inb(cmdport+Error);
1898         else switch(drive->command){
1899         default:
1900                 drive->error = Abrt;
1901                 break;
1902
1903         case Crs:
1904         case Crsm:
1905         case Ppio|Pin:
1906                 if(!(status & Drq)){
1907                         drive->error = Abrt;
1908                         break;
1909                 }
1910                 len = drive->block;
1911                 if(drive->data+len > drive->limit)
1912                         len = drive->limit-drive->data;
1913                 inss(cmdport+Data, drive->data, len/2);
1914                 drive->data += len;
1915                 if(drive->data >= drive->limit)
1916                         ctlr->done = 1;
1917                 break;
1918
1919         case Cws:
1920         case Cwsm:
1921         case Ppio|Pout:
1922                 len = drive->block;
1923                 if(drive->data+len > drive->limit)
1924                         len = drive->limit-drive->data;
1925                 drive->data += len;
1926                 if(drive->data >= drive->limit){
1927                         ctlr->done = 1;
1928                         break;
1929                 }
1930                 if(!(status & Drq)){
1931                         drive->error = Abrt;
1932                         break;
1933                 }
1934                 len = drive->block;
1935                 if(drive->data+len > drive->limit)
1936                         len = drive->limit-drive->data;
1937                 outss(cmdport+Data, drive->data, len/2);
1938                 break;
1939
1940         case Cpkt:
1941         case Ppkt|Pin:
1942         case Ppkt|Pout:
1943                 atapktinterrupt(drive);
1944                 break;
1945
1946         case Crd:
1947         case Cwd:
1948         case Pdma|Pin:
1949         case Pdma|Pout:
1950                 atadmainterrupt(drive, drive->count*drive->secsize);
1951                 break;
1952
1953         case Pnd:
1954         case Preset:
1955                 ctlr->done = 1;
1956                 break;
1957         }
1958         if(ctlr->irqack != nil)
1959                 ctlr->irqack(ctlr);
1960         iunlock(ctlr);
1961
1962         if(drive->error){
1963                 status |= Err;
1964                 ctlr->done = 1;
1965         }
1966
1967         if(ctlr->done){
1968                 ctlr->curdrive = nil;
1969                 drive->status = status;
1970                 wakeup(ctlr);
1971         }
1972 }
1973
1974 typedef struct Lchan Lchan;
1975 struct Lchan {
1976         int     cmdport;
1977         int     ctlport;
1978         int     irq;
1979         int     probed;
1980 };
1981 static Lchan lchan[2] = {
1982         0x1f0,  0x3f4,  IrqATA0,        0,
1983         0x170,  0x374,  IrqATA1,        0,
1984 };
1985
1986 static int
1987 badccru(Pcidev *p)
1988 {
1989         switch(p->did<<16 | p->did){
1990         case 0x439c<<16 | 0x1002:
1991         case 0x438c<<16 | 0x1002:
1992 print("hi, anothy\n");
1993 print("%T: allowing bad ccru %.2ux for suspected ide controller\n", p->tbdf, p->ccru);
1994                 return 1;
1995         default:
1996                 return 0;
1997         }
1998 }
1999
2000 static SDev*
2001 atapnp(void)
2002 {
2003         char *s;
2004         int channel, map, ispc87415, maxio, pi, r, span, tbdf;
2005         Ctlr *ctlr;
2006         Pcidev *p;
2007         SDev *sdev, *head, *tail;
2008         void (*irqack)(Ctlr*);
2009
2010         head = tail = nil;
2011         for(p = nil; p = pcimatch(p, 0, 0); ){
2012                 /*
2013                  * Look for devices with the correct class and sub-class
2014                  * code and known device and vendor ID; add native-mode
2015                  * channels to the list to be probed, save info for the
2016                  * compatibility mode channels.
2017                  * Note that the legacy devices should not be considered
2018                  * PCI devices by the interrupt controller.
2019                  * For both native and legacy, save info for busmastering
2020                  * if capable.
2021                  * Promise Ultra ATA/66 (PDC20262) appears to
2022                  * 1) give a sub-class of 'other mass storage controller'
2023                  *    instead of 'IDE controller', regardless of whether it's
2024                  *    the only controller or not;
2025                  * 2) put 0 in the programming interface byte (probably
2026                  *    as a consequence of 1) above).
2027                  * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
2028                  */
2029                 if(p->ccrb != 0x01)
2030                         continue;
2031                 if(!badccru(p))
2032                 if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
2033                         continue;
2034                 pi = p->ccrp;
2035                 map = 3;
2036                 ispc87415 = 0;
2037                 maxio = 0;
2038                 if(s = getconf("*idemaxio"))
2039                         maxio = atoi(s);
2040                 span = BMspan;
2041                 irqack = nil;
2042
2043                 switch((p->did<<16)|p->vid){
2044                 default:
2045                         continue;
2046
2047                 case (0x0002<<16)|0x100B:       /* NS PC87415 */
2048                         /*
2049                          * Disable interrupts on both channels until
2050                          * after they are probed for drives.
2051                          * This must be called before interrupts are
2052                          * enabled because the IRQ may be shared.
2053                          */
2054                         ispc87415 = 1;
2055                         pcicfgw32(p, 0x40, 0x00000300);
2056                         break;
2057                 case (0x1000<<16)|0x1042:       /* PC-Tech RZ1000 */
2058                         /*
2059                          * Turn off prefetch. Overkill, but cheap.
2060                          */
2061                         r = pcicfgr32(p, 0x40);
2062                         r &= ~0x2000;
2063                         pcicfgw32(p, 0x40, r);
2064                         break;
2065                 case (0x4D38<<16)|0x105A:       /* Promise PDC20262 */
2066                 case (0x4D30<<16)|0x105A:       /* Promise PDC202xx */
2067                 case (0x4D68<<16)|0x105A:       /* Promise PDC20268 */
2068                 case (0x4D69<<16)|0x105A:       /* Promise Ultra/133 TX2 */
2069                 case (0x3373<<16)|0x105A:       /* Promise 20378 RAID */
2070                 case (0x3149<<16)|0x1106:       /* VIA VT8237 SATA/RAID */
2071                 case (0x3112<<16)|0x1095:       /* SiL 3112 SATA/RAID */
2072                         maxio = 15;
2073                         span = 8*1024;
2074                         /*FALLTHROUGH*/
2075                 case (0x3114<<16)|0x1095:       /* SiL 3114 SATA/RAID */
2076                 case (0x0680<<16)|0x1095:       /* SiI 0680/680A PATA133 ATAPI/RAID */
2077                         pi = 0x85;
2078                         break;
2079                 case (0x0004<<16)|0x1103:       /* HighPoint HPT366 */
2080                         pi = 0x85;
2081                         /*
2082                          * Turn off fast interrupt prediction.
2083                          */
2084                         if((r = pcicfgr8(p, 0x51)) & 0x80)
2085                                 pcicfgw8(p, 0x51, r & ~0x80);
2086                         if((r = pcicfgr8(p, 0x55)) & 0x80)
2087                                 pcicfgw8(p, 0x55, r & ~0x80);
2088                         break;
2089                 case (0x0640<<16)|0x1095:       /* CMD 640B */
2090                         /*
2091                          * Bugfix code here...
2092                          */
2093                         break;
2094                 case (0x7441<<16)|0x1022:       /* AMD 768 */
2095                         /*
2096                          * Set:
2097                          *      0x41    prefetch, postwrite;
2098                          *      0x43    FIFO configuration 1/2 and 1/2;
2099                          *      0x44    status register read retry;
2100                          *      0x46    DMA read and end of sector flush.
2101                          */
2102                         r = pcicfgr8(p, 0x41);
2103                         pcicfgw8(p, 0x41, r|0xF0);
2104                         r = pcicfgr8(p, 0x43);
2105                         pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
2106                         r = pcicfgr8(p, 0x44);
2107                         pcicfgw8(p, 0x44, r|0x08);
2108                         r = pcicfgr8(p, 0x46);
2109                         pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
2110                         /*FALLTHROUGH*/
2111                 case (0x01BC<<16)|0x10DE:       /* nVidia nForce1 */
2112                 case (0x0065<<16)|0x10DE:       /* nVidia nForce2 */
2113                 case (0x0085<<16)|0x10DE:       /* nVidia nForce2 MCP */
2114                 case (0x00E3<<16)|0x10DE:       /* nVidia nForce2 250 SATA */
2115                 case (0x00D5<<16)|0x10DE:       /* nVidia nForce3 */
2116                 case (0x00E5<<16)|0x10DE:       /* nVidia nForce3 Pro */
2117                 case (0x00EE<<16)|0x10DE:       /* nVidia nForce3 250 SATA */
2118                 case (0x0035<<16)|0x10DE:       /* nVidia nForce3 MCP */
2119                 case (0x0053<<16)|0x10DE:       /* nVidia nForce4 */
2120                 case (0x0054<<16)|0x10DE:       /* nVidia nForce4 SATA */
2121                 case (0x0055<<16)|0x10DE:       /* nVidia nForce4 SATA */
2122                 case (0x0266<<16)|0x10DE:       /* nVidia nForce4 430 SATA */
2123                 case (0x0265<<16)|0x10DE:       /* nVidia nForce 51 MCP */
2124                 case (0x0267<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2125                 case (0x03ec<<16)|0x10DE:       /* nVidia nForce 61 MCP SATA */
2126                 case (0x03f6<<16)|0x10DE:       /* nVidia nForce 61 MCP PATA */
2127                 case (0x0448<<16)|0x10DE:       /* nVidia nForce 65 MCP SATA */
2128                 case (0x0560<<16)|0x10DE:       /* nVidia nForce 69 MCP SATA */
2129                         /*
2130                          * Ditto, although it may have a different base
2131                          * address for the registers (0x50?).
2132                          */
2133                         /*FALLTHROUGH*/
2134                 case (0x209A<<16)|0x1022:       /* AMD CS5536 */
2135                 case (0x7401<<16)|0x1022:       /* AMD 755 Cobra */
2136                 case (0x7409<<16)|0x1022:       /* AMD 756 Viper */
2137                 case (0x7410<<16)|0x1022:       /* AMD 766 Viper Plus */
2138                 case (0x7469<<16)|0x1022:       /* AMD 3111 */
2139                 case (0x4376<<16)|0x1002:       /* SB4xx pata */
2140                 case (0x4379<<16)|0x1002:       /* SB4xx sata */
2141                 case (0x437a<<16)|0x1002:       /* SB4xx sata ctlr #2 */
2142                 case (0x437c<<16)|0x1002:       /* Rx6xx pata */
2143                 case (0x438c<<16)|0x1002:       /* ATI SB600 PATA */
2144                 case (0x439c<<16)|0x1002:       /* SB7xx pata */
2145                         break;
2146                 case (0x0211<<16)|0x1166:       /* ServerWorks IB6566 */
2147                         {
2148                                 Pcidev *sb;
2149
2150                                 sb = pcimatch(nil, 0x1166, 0x0200);
2151                                 if(sb == nil)
2152                                         break;
2153                                 r = pcicfgr32(sb, 0x64);
2154                                 r &= ~0x2000;
2155                                 pcicfgw32(sb, 0x64, r);
2156                         }
2157                         span = 32*1024;
2158                         break;
2159                 case (0x5229<<16)|0x10B9:       /* ALi M1543 */
2160                 case (0x5288<<16)|0x10B9:       /* ALi M5288 SATA */
2161                         /*FALLTHROUGH*/
2162                 case (0x5513<<16)|0x1039:       /* SiS 962 */
2163                 case (0x0646<<16)|0x1095:       /* CMD 646 */
2164                 case (0x0571<<16)|0x1106:       /* VIA 82C686 */
2165                 case (0x9001<<16)|0x1106:       /* VIA chipset in VIA PV530 */
2166                 case (0x0502<<16)|0x100b:       /* National Semiconductor SC1100/SCx200 */
2167                         break;
2168                 case (0x2360<<16)|0x197b:       /* jmicron jmb360 */
2169                 case (0x2361<<16)|0x197b:       /* jmicron jmb361 */
2170                 case (0x2363<<16)|0x197b:       /* jmicron jmb363 */
2171                 case (0x2365<<16)|0x197b:       /* jmicron jmb365 */
2172                 case (0x2366<<16)|0x197b:       /* jmicron jmb366 */
2173                 case (0x2368<<16)|0x197b:       /* jmicron jmb368 */
2174                         break;
2175                 case (0x1230<<16)|0x8086:       /* 82371FB (PIIX) */
2176                 case (0x7010<<16)|0x8086:       /* 82371SB (PIIX3) */
2177                 case (0x7111<<16)|0x8086:       /* 82371[AE]B (PIIX4[E]) */
2178                         break;
2179                 case (0x2411<<16)|0x8086:       /* 82801AA (ICH) */
2180                 case (0x2421<<16)|0x8086:       /* 82801AB (ICH0) */
2181                 case (0x244A<<16)|0x8086:       /* 82801BA (ICH2, Mobile) */
2182                 case (0x244B<<16)|0x8086:       /* 82801BA (ICH2, High-End) */
2183                 case (0x248A<<16)|0x8086:       /* 82801CA (ICH3, Mobile) */
2184                 case (0x248B<<16)|0x8086:       /* 82801CA (ICH3, High-End) */
2185                 case (0x24CA<<16)|0x8086:       /* 82801DBM (ICH4, Mobile) */
2186                 case (0x24CB<<16)|0x8086:       /* 82801DB (ICH4, High-End) */
2187                 case (0x24D1<<16)|0x8086:       /* 82801er (ich5) */
2188                 case (0x24DB<<16)|0x8086:       /* 82801EB (ICH5) */
2189                 case (0x25A2<<16)|0x8086:       /* 6300ESB pata */
2190                 case (0x25A3<<16)|0x8086:       /* 6300ESB (E7210) */
2191                 case (0x266F<<16)|0x8086:       /* 82801FB (ICH6) */
2192                 case (0x2653<<16)|0x8086:       /* 82801FBM (ICH6, Mobile) */
2193                 case (0x269e<<16)|0x8086:       /* 63xxESB (intel 5000) */
2194                 case (0x27DF<<16)|0x8086:       /* 82801G PATA (ICH7) */
2195                 case (0x27C0<<16)|0x8086:       /* 82801GB SATA (ICH7) */
2196                 case (0x27C4<<16)|0x8086:       /* 82801GBM SATA (ICH7) */
2197                 case (0x27C5<<16)|0x8086:       /* 82801GBM SATA AHCI (ICH7) */
2198                 case (0x2850<<16)|0x8086:       /* 82801HBM/HEM PATA */
2199                 case (0x2820<<16)|0x8086:       /* 82801HB/HR/HH/HO SATA IDE */
2200                 case (0x2828<<16)|0x8086:       /* 82801HBM SATA (ICH8-M) */
2201                 case (0x2829<<16)|0x8086:       /* 82801HBM SATA AHCI (ICH8-M) */
2202                 case (0x2920<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-3 */
2203                 case (0x2921<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-1 */
2204                 case (0x2926<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 4-5 */
2205                 case (0x2928<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1 */
2206                 case (0x2929<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1, 4-5 */
2207                 case (0x292d<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 4-5*/
2208                 case (0x3a20<<16)|0x8086:       /* 82801ji (ich10) */
2209                 case (0x3a26<<16)|0x8086:       /* 82801ji (ich10) */
2210                 case (0x3b20<<16)|0x8086:       /* 34x0 (pch) port 0-3 */
2211                 case (0x3b21<<16)|0x8086:       /* 34x0 (pch) port 4-5 */
2212                 case (0x3b28<<16)|0x8086:       /* 34x0pm (pch) port 0-1, 4-5 */
2213                 case (0x3b2e<<16)|0x8086:       /* 34x0pm (pch) port 0-3 */
2214                         map = 0;
2215                         if(pcicfgr16(p, 0x40) & 0x8000)
2216                                 map |= 1;
2217                         if(pcicfgr16(p, 0x42) & 0x8000)
2218                                 map |= 2;
2219                         irqack = ichirqack;
2220                         break;
2221                 }
2222                 for(channel = 0; channel < 2; channel++){
2223                         if((map & 1<<channel) == 0)
2224                                 continue;
2225                         if(pi & 1<<2*channel){
2226                                 sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
2227                                                 p->mem[1+2*channel].bar & ~0x01,
2228                                                 p->intl, 3);
2229                                 tbdf = p->tbdf;
2230                         }
2231                         else if(lchan[channel].probed == 0){
2232                                 sdev = ataprobe(lchan[channel].cmdport,
2233                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2234                                 lchan[channel].probed = 1;
2235                                 tbdf = BUSUNKNOWN;
2236                         }
2237                         else
2238                                 continue;
2239                         if(sdev == nil)
2240                                 continue;
2241                         ctlr = sdev->ctlr;
2242                         if(ispc87415) {
2243                                 ctlr->ienable = pc87415ienable;
2244                                 print("pc87415disable: not yet implemented\n");
2245                         }
2246                         ctlr->tbdf = tbdf;
2247                         ctlr->pcidev = p;
2248                         ctlr->maxio = maxio;
2249                         ctlr->span = span;
2250                         ctlr->irqack = irqack;
2251                         if(pi & 0x80)
2252                                 ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
2253                         if(head != nil)
2254                                 tail->next = sdev;
2255                         else
2256                                 head = sdev;
2257                         tail = sdev;
2258                 }
2259         }
2260
2261         if(lchan[0].probed + lchan[1].probed == 0)
2262                 for(channel = 0; channel < 2; channel++){
2263                         sdev = nil;
2264                         if(lchan[channel].probed == 0){
2265         //                      print("sdide: blind probe %.3ux\n", lchan[channel].cmdport);
2266                                 sdev = ataprobe(lchan[channel].cmdport,
2267                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2268                                 lchan[channel].probed = 1;
2269                         }
2270                         if(sdev == nil)
2271                                 continue;
2272                         if(head != nil)
2273                                 tail->next = sdev;
2274                         else
2275                                 head = sdev;
2276                         tail = sdev;
2277                 }
2278
2279 if(0){
2280         int port;
2281         ISAConf isa;
2282
2283         /*
2284          * Hack for PCMCIA drives.
2285          * This will be tidied once we figure out how the whole
2286          * removeable device thing is going to work.
2287          */
2288         memset(&isa, 0, sizeof(isa));
2289         isa.port = 0x180;               /* change this for your machine */
2290         isa.irq = 11;                   /* change this for your machine */
2291
2292         port = isa.port+0x0C;
2293         channel = pcmspecial("MK2001MPL", &isa);
2294         if(channel == -1)
2295                 channel = pcmspecial("SunDisk", &isa);
2296         if(channel == -1){
2297                 isa.irq = 10;
2298                 channel = pcmspecial("CF", &isa);
2299         }
2300         if(channel == -1){
2301                 isa.irq = 10;
2302                 channel = pcmspecial("OLYMPUS", &isa);
2303         }
2304         if(channel == -1){
2305                 port = isa.port+0x204;
2306                 channel = pcmspecial("ATA/ATAPI", &isa);
2307         }
2308         if(channel >= 0 && (sdev = ataprobe(isa.port, port, isa.irq, 3)) != nil){
2309                 if(head != nil)
2310                         tail->next = sdev;
2311                 else
2312                         head = sdev;
2313         }
2314 }
2315         return head;
2316 }
2317
2318 static void
2319 atadmaclr(Ctlr *ctlr)
2320 {
2321         int bmiba, bmisx;
2322
2323         if(ctlr->curdrive)
2324                 ataabort(ctlr->curdrive, 1);
2325         bmiba = ctlr->bmiba;
2326         if(bmiba == 0)
2327                 return;
2328         atadmastop(ctlr);
2329         outl(bmiba+Bmidtpx, 0);
2330         bmisx = inb(bmiba+Bmisx) & ~Bmidea;
2331         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
2332 //      pciintst(ctlr->pcidev);
2333 }
2334
2335 static int
2336 ataenable(SDev* sdev)
2337 {
2338         Ctlr *ctlr;
2339         char name[32];
2340
2341         ctlr = sdev->ctlr;
2342         if(ctlr->bmiba){
2343                 atadmaclr(ctlr);
2344                 if(ctlr->pcidev != nil)
2345                         pcisetbme(ctlr->pcidev);
2346                 ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 4, 0, 64*1024);
2347         }
2348         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2349         intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2350         outb(ctlr->ctlport+Dc, 0);
2351         if(ctlr->ienable)
2352                 ctlr->ienable(ctlr);
2353         return 1;
2354 }
2355
2356 static int
2357 atadisable(SDev *sdev)
2358 {
2359         Ctlr *ctlr;
2360         char name[32];
2361
2362         ctlr = sdev->ctlr;
2363         outb(ctlr->ctlport+Dc, Nien);           /* disable interrupts */
2364         if (ctlr->idisable)
2365                 ctlr->idisable(ctlr);
2366         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2367         intrdisable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2368         if(ctlr->bmiba) {
2369 //              atadmaclr(ctlr);
2370                 if (ctlr->pcidev)
2371                         pciclrbme(ctlr->pcidev);
2372                 free(ctlr->prdt);
2373         }
2374         return 0;
2375 }
2376
2377 static int
2378 ataonline(SDunit *unit)
2379 {
2380         Ctlr *ctlr;
2381         Drive *drive;
2382
2383         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2384                 return 0;
2385         drive = ctlr->drive[unit->subno];
2386         if((drive->flags & Online) == 0){
2387                 drive->flags |= Online;
2388                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2389         }
2390         unit->sectors = drive->sectors;
2391         unit->secsize = drive->secsize;
2392         if(drive->feat & Datapi)
2393                 return scsionline(unit);
2394         return 1;
2395 }
2396
2397 static int
2398 atarctl(SDunit* unit, char* p, int l)
2399 {
2400         Ctlr *ctlr;
2401         Drive *drive;
2402         char *e, *op;
2403
2404         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2405                 return 0;
2406         drive = ctlr->drive[unit->subno];
2407
2408         e = p+l;
2409         op = p;
2410         qlock(drive);
2411         p = seprint(p, e, "config %4.4uX capabilities %4.4uX", drive->info[Iconfig], drive->info[Icapabilities]);
2412         if(drive->dma)
2413                 p = seprint(p, e, " dma %8.8uX dmactl %8.8uX", drive->dma, drive->dmactl);
2414         if(drive->rwm)
2415                 p = seprint(p, e, " rwm %ud rwmctl %ud", drive->rwm, drive->rwmctl);
2416         if(drive->feat & Dllba)
2417                 p = seprint(p, e, " lba48always %s", (drive->flags&Lba48always) ? "on" : "off");
2418         p = seprint(p, e, "\n");
2419         p = seprint(p, e, "model        %s\n", drive->model);
2420         p = seprint(p, e, "serial       %s\n", drive->serial);
2421         p = seprint(p, e, "firm %s\n", drive->firmware);
2422         p = seprint(p, e, "feat ");
2423         p = pflag(p, e, drive);
2424         if(drive->sectors){
2425                 p = seprint(p, e, "geometry %llud %d", drive->sectors, drive->secsize);
2426                 if(drive->pkt == 0 && (drive->feat & Dlba) == 0)
2427                         p = seprint(p, e, " %d %d %d", drive->c, drive->h, drive->s);
2428                 p = seprint(p, e, "\n");
2429         }
2430         p = seprint(p, e, "missirq      %ud\n", drive->missirq);
2431         p = seprint(p, e, "sloop        %ud\n", drive->spurloop);
2432         p = seprint(p, e, "irq  %ud %ud\n", ctlr->nrq, drive->irq);
2433         p = seprint(p, e, "bsy  %ud %ud\n", ctlr->bsy, drive->bsy);
2434         p = seprint(p, e, "nildrive     %ud\n", ctlr->nildrive);
2435         qunlock(drive);
2436
2437         return p - op;
2438 }
2439
2440 static int
2441 atawctl(SDunit* unit, Cmdbuf* cb)
2442 {
2443         Ctlr *ctlr;
2444         Drive *drive;
2445
2446         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2447                 return 0;
2448         drive = ctlr->drive[unit->subno];
2449
2450         qlock(drive);
2451         if(waserror()){
2452                 qunlock(drive);
2453                 nexterror();
2454         }
2455
2456         /*
2457          * Dma and rwm control is passive at the moment,
2458          * i.e. it is assumed that the hardware is set up
2459          * correctly already either by the BIOS or when
2460          * the drive was initially identified.
2461          */
2462         if(strcmp(cb->f[0], "dma") == 0){
2463                 if(cb->nf != 2 || drive->dma == 0)
2464                         error(Ebadctl);
2465                 if(strcmp(cb->f[1], "on") == 0)
2466                         drive->dmactl = drive->dma;
2467                 else if(strcmp(cb->f[1], "off") == 0)
2468                         drive->dmactl = 0;
2469                 else
2470                         error(Ebadctl);
2471         }
2472         else if(strcmp(cb->f[0], "rwm") == 0){
2473                 if(cb->nf != 2 || drive->rwm == 0)
2474                         error(Ebadctl);
2475                 if(strcmp(cb->f[1], "on") == 0)
2476                         drive->rwmctl = drive->rwm;
2477                 else if(strcmp(cb->f[1], "off") == 0)
2478                         drive->rwmctl = 0;
2479                 else
2480                         error(Ebadctl);
2481         }
2482         else if(strcmp(cb->f[0], "lba48always") == 0){
2483                 if(cb->nf != 2 || !(drive->feat & Dllba))
2484                         error(Ebadctl);
2485                 if(strcmp(cb->f[1], "on") == 0)
2486                         drive->flags |= Lba48always;
2487                 else if(strcmp(cb->f[1], "off") == 0)
2488                         drive->flags &= ~Lba48always;
2489                 else
2490                         error(Ebadctl);
2491         }
2492         else if(strcmp(cb->f[0], "identify") == 0){
2493                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2494         }
2495         else
2496                 error(Ebadctl);
2497         qunlock(drive);
2498         poperror();
2499
2500         return 0;
2501 }
2502
2503 SDifc sdideifc = {
2504         "ide",                          /* name */
2505
2506         atapnp,                         /* pnp */
2507         nil,                    /* legacy */
2508         ataenable,                      /* enable */
2509         atadisable,                     /* disable */
2510
2511         scsiverify,                     /* verify */
2512         ataonline,                      /* online */
2513         atario,                         /* rio */
2514         atarctl,                        /* rctl */
2515         atawctl,                        /* wctl */
2516
2517         scsibio,                        /* bio */
2518         ataprobew,                      /* probe */
2519         ataclear,                       /* clear */
2520         atastat,                        /* rtopctl */
2521         nil,                            /* wtopctl */
2522         ataataio,
2523 };