sys/src/9/pc/sdide.c

   1 #include "u.h"
   2 #include "../port/lib.h"
   3 #include "mem.h"
   4 #include "dat.h"
   5 #include "fns.h"
   6 #include "io.h"
   7 #include "ureg.h"
   8 #include "../port/error.h"
   9
  10 #include "../port/sd.h"
  11 #include <fis.h>
  12
  13 #define HOWMANY(x, y)   (((x)+((y)-1))/(y))
  14 #define ROUNDUP(x, y)   (HOWMANY((x), (y))*(y))
  15 #define uprint(...)     snprint(up->genbuf, sizeof up->genbuf, __VA_ARGS__);
  16 #pragma varargck        argpos  atadebug                3
  17
  18 extern SDifc sdideifc;
  19
  20 enum {
  21         DbgCONFIG       = 0x0001,       /* detected drive config info */
  22         DbgIDENTIFY     = 0x0002,       /* detected drive identify info */
  23         DbgSTATE        = 0x0004,       /* dump state on panic */
  24         DbgPROBE        = 0x0008,       /* trace device probing */
  25         DbgDEBUG        = 0x0080,       /* the current problem... */
  26         DbgINL          = 0x0100,       /* That Inil20+ message we hate */
  27         Dbg48BIT        = 0x0200,       /* 48-bit LBA */
  28         DbgBsy          = 0x0400,       /* interrupt but Bsy (shared IRQ) */
  29         DbgAtazz        = 0x0800,       /* debug raw ata io */
  30 };
  31 #define DEBUG           (DbgDEBUG|DbgSTATE)
  32
  33 enum {                                  /* I/O ports */
  34         Data            = 0,
  35         Error           = 1,            /* (read) */
  36         Features        = 1,            /* (write) */
  37         Count           = 2,            /* sector count<7-0>, sector count<15-8> */
  38         Ir              = 2,            /* interrupt reason (PACKET) */
  39         Sector          = 3,            /* sector number */
  40         Lbalo           = 3,            /* LBA<7-0>, LBA<31-24> */
  41         Cyllo           = 4,            /* cylinder low */
  42         Bytelo          = 4,            /* byte count low (PACKET) */
  43         Lbamid          = 4,            /* LBA<15-8>, LBA<39-32> */
  44         Cylhi           = 5,            /* cylinder high */
  45         Bytehi          = 5,            /* byte count hi (PACKET) */
  46         Lbahi           = 5,            /* LBA<23-16>, LBA<47-40> */
  47         Dh              = 6,            /* Device/Head, LBA<27-24> */
  48         Status          = 7,            /* (read) */
  49         Command         = 7,            /* (write) */
  50
  51         As              = 2,            /* Alternate Status (read) */
  52         Dc              = 2,            /* Device Control (write) */
  53 };
  54
  55 enum {                                  /* Error */
  56         Med             = 0x01,         /* Media error */
  57         Ili             = 0x01,         /* command set specific (PACKET) */
  58         Nm              = 0x02,         /* No Media */
  59         Eom             = 0x02,         /* command set specific (PACKET) */
  60         Abrt            = 0x04,         /* Aborted command */
  61         Mcr             = 0x08,         /* Media Change Request */
  62         Idnf            = 0x10,         /* no user-accessible address */
  63         Mc              = 0x20,         /* Media Change */
  64         Unc             = 0x40,         /* Uncorrectable data error */
  65         Wp              = 0x40,         /* Write Protect */
  66         Icrc            = 0x80,         /* Interface CRC error */
  67 };
  68
  69 enum {                                  /* Features */
  70         Dma             = 0x01,         /* data transfer via DMA (PACKET) */
  71         Ovl             = 0x02,         /* command overlapped (PACKET) */
  72 };
  73
  74 enum {                                  /* Interrupt Reason */
  75         Cd              = 0x01,         /* Command/Data */
  76         Io              = 0x02,         /* I/O direction */
  77         Rel             = 0x04,         /* Bus Release */
  78 };
  79
  80 enum {                                  /* Device/Head */
  81         Dev0            = 0xA0,         /* Master */
  82         Dev1            = 0xB0,         /* Slave */
  83         Devs            = Dev0 | Dev1,
  84         Lba             = 0x40,         /* LBA mode */
  85 };
  86
  87 enum {                                  /* Status, Alternate Status */
  88         Err             = 0x01,         /* Error */
  89         Chk             = 0x01,         /* Check error (PACKET) */
  90         Drq             = 0x08,         /* Data Request */
  91         Dsc             = 0x10,         /* Device Seek Complete */
  92         Serv            = 0x10,         /* Service */
  93         Df              = 0x20,         /* Device Fault */
  94         Dmrd            = 0x20,         /* DMA ready (PACKET) */
  95         Drdy            = 0x40,         /* Device Ready */
  96         Bsy             = 0x80,         /* Busy */
  97 };
  98
  99 enum {                                  /* Command */
 100         Cnop            = 0x00,         /* NOP */
 101         Crs             = 0x20,         /* Read Sectors */
 102         Crs48           = 0x24,         /* Read Sectors Ext */
 103         Crd48           = 0x25,         /* Read w/ DMA Ext */
 104         Crsm48          = 0x29,         /* Read Multiple Ext */
 105         Cws             = 0x30,         /* Write Sectors */
 106         Cws48           = 0x34,         /* Write Sectors Ext */
 107         Cwd48           = 0x35,         /* Write w/ DMA Ext */
 108         Cwsm48          = 0x39,         /* Write Multiple Ext */
 109         Cedd            = 0x90,         /* Execute Device Diagnostics */
 110         Cpkt            = 0xA0,         /* Packet */
 111         Cidpkt          = 0xA1,         /* Identify Packet Device */
 112         Crsm            = 0xC4,         /* Read Multiple */
 113         Cwsm            = 0xC5,         /* Write Multiple */
 114         Csm             = 0xC6,         /* Set Multiple */
 115         Crd             = 0xC8,         /* Read DMA */
 116         Cwd             = 0xCA,         /* Write DMA */
 117         Cid             = 0xEC,         /* Identify Device */
 118 };
 119
 120 enum {                                  /* Device Control */
 121         Nien            = 0x02,         /* (not) Interrupt Enable */
 122         Srst            = 0x04,         /* Software Reset */
 123         Hob             = 0x80,         /* High Order Bit [sic] */
 124 };
 125
 126 enum {                                  /* PCI Configuration Registers */
 127         Bmiba           = 0x20,         /* Bus Master Interface Base Address */
 128         Idetim          = 0x40,         /* IE Timing */
 129         Sidetim         = 0x44,         /* Slave IE Timing */
 130         Udmactl         = 0x48,         /* Ultra DMA/33 Control */
 131         Udmatim         = 0x4A,         /* Ultra DMA/33 Timing */
 132 };
 133
 134 enum {                                  /* Bus Master IDE I/O Ports */
 135         Bmicx           = 0,            /* Command */
 136         Bmisx           = 2,            /* Status */
 137         Bmidtpx         = 4,            /* Descriptor Table Pointer */
 138 };
 139
 140 enum {                                  /* Bmicx */
 141         Ssbm            = 0x01,         /* Start/Stop Bus Master */
 142         Rwcon           = 0x08,         /* Read/Write Control */
 143 };
 144
 145 enum {                                  /* Bmisx */
 146         Bmidea          = 0x01,         /* Bus Master IDE Active */
 147         Idedmae         = 0x02,         /* IDE DMA Error  (R/WC) */
 148         Ideints         = 0x04,         /* IDE Interrupt Status (R/WC) */
 149         Dma0cap         = 0x20,         /* Drive 0 DMA Capable */
 150         Dma1cap         = 0x40,         /* Drive 0 DMA Capable */
 151 };
 152 enum {                                  /* Physical Region Descriptor */
 153         PrdEOT          = 0x80000000,   /* End of Transfer */
 154 };
 155
 156 enum {                                  /* offsets into the identify info. */
 157         Iconfig         = 0,            /* general configuration */
 158         Ilcyl           = 1,            /* logical cylinders */
 159         Ilhead          = 3,            /* logical heads */
 160         Ilsec           = 6,            /* logical sectors per logical track */
 161         Iserial         = 10,           /* serial number */
 162         Ifirmware       = 23,           /* firmware revision */
 163         Imodel          = 27,           /* model number */
 164         Imaxrwm         = 47,           /* max. read/write multiple sectors */
 165         Icapabilities   = 49,           /* capabilities */
 166         Istandby        = 50,           /* device specific standby timer */
 167         Ipiomode        = 51,           /* PIO data transfer mode number */
 168         Ivalid          = 53,
 169         Iccyl           = 54,           /* cylinders if (valid&0x01) */
 170         Ichead          = 55,           /* heads if (valid&0x01) */
 171         Icsec           = 56,           /* sectors if (valid&0x01) */
 172         Iccap           = 57,           /* capacity if (valid&0x01) */
 173         Irwm            = 59,           /* read/write multiple */
 174         Ilba            = 60,           /* LBA size */
 175         Imwdma          = 63,           /* multiword DMA mode */
 176         Iapiomode       = 64,           /* advanced PIO modes supported */
 177         Iminmwdma       = 65,           /* min. multiword DMA cycle time */
 178         Irecmwdma       = 66,           /* rec. multiword DMA cycle time */
 179         Iminpio         = 67,           /* min. PIO cycle w/o flow control */
 180         Iminiordy       = 68,           /* min. PIO cycle with IORDY */
 181         Ipcktbr         = 71,           /* time from PACKET to bus release */
 182         Iserbsy         = 72,           /* time from SERVICE to !Bsy */
 183         Iqdepth         = 75,           /* max. queue depth */
 184         Imajor          = 80,           /* major version number */
 185         Iminor          = 81,           /* minor version number */
 186         Icsfs           = 82,           /* command set/feature supported */
 187         Icsfe           = 85,           /* command set/feature enabled */
 188         Iudma           = 88,           /* ultra DMA mode */
 189         Ierase          = 89,           /* time for security erase */
 190         Ieerase         = 90,           /* time for enhanced security erase */
 191         Ipower          = 91,           /* current advanced power management */
 192         Ilba48          = 100,          /* 48-bit LBA size (64 bits in 100-103) */
 193         Irmsn           = 127,          /* removable status notification */
 194         Isecstat        = 128,          /* security status */
 195         Icfapwr         = 160,          /* CFA power mode */
 196         Imediaserial    = 176,          /* current media serial number */
 197         Icksum          = 255,          /* checksum */
 198 };
 199
 200 enum {                                  /* bit masks for config identify info */
 201         Mpktsz          = 0x0003,       /* packet command size */
 202         Mincomplete     = 0x0004,       /* incomplete information */
 203         Mdrq            = 0x0060,       /* DRQ type */
 204         Mrmdev          = 0x0080,       /* device is removable */
 205         Mtype           = 0x1F00,       /* device type */
 206         Mproto          = 0x8000,       /* command protocol */
 207 };
 208
 209 enum {                                  /* bit masks for capabilities identify info */
 210         Mdma            = 0x0100,       /* DMA supported */
 211         Mlba            = 0x0200,       /* LBA supported */
 212         Mnoiordy        = 0x0400,       /* IORDY may be disabled */
 213         Miordy          = 0x0800,       /* IORDY supported */
 214         Msoftrst        = 0x1000,       /* needs soft reset when Bsy */
 215         Mqueueing       = 0x4000,       /* queueing overlap supported */
 216         Midma           = 0x8000,       /* interleaved DMA supported */
 217 };
 218
 219 enum {                                  /* bit masks for supported/enabled features */
 220         Msmart          = 0x0001,
 221         Msecurity       = 0x0002,
 222         Mrmmedia        = 0x0004,
 223         Mpwrmgmt        = 0x0008,
 224         Mpkt            = 0x0010,
 225         Mwcache         = 0x0020,
 226         Mlookahead      = 0x0040,
 227         Mrelirq         = 0x0080,
 228         Msvcirq         = 0x0100,
 229         Mreset          = 0x0200,
 230         Mprotected      = 0x0400,
 231         Mwbuf           = 0x1000,
 232         Mrbuf           = 0x2000,
 233         Mnop            = 0x4000,
 234         Mmicrocode      = 0x0001,
 235         Mqueued         = 0x0002,
 236         Mcfa            = 0x0004,
 237         Mapm            = 0x0008,
 238         Mnotify         = 0x0010,
 239         Mspinup         = 0x0040,
 240         Mmaxsec         = 0x0100,
 241         Mautoacoustic   = 0x0200,
 242         Maddr48         = 0x0400,
 243         Mdevconfov      = 0x0800,
 244         Mflush          = 0x1000,
 245         Mflush48        = 0x2000,
 246         Msmarterror     = 0x0001,
 247         Msmartselftest  = 0x0002,
 248         Mmserial        = 0x0004,
 249         Mmpassthru      = 0x0008,
 250         Mlogging        = 0x0020,
 251 };
 252
 253 typedef struct Ctlr Ctlr;
 254 typedef struct Drive Drive;
 255
 256 typedef struct Prd {                    /* Physical Region Descriptor */
 257         ulong   pa;                     /* Physical Base Address */
 258         int     count;
 259 } Prd;
 260
 261 enum {
 262         BMspan          = 32*1024,      /* must be power of 2 <= 64*1024 */
 263
 264         Nprd            = SDmaxio/BMspan+2,
 265 };
 266
 267 typedef struct Ctlr {
 268         int     cmdport;
 269         int     ctlport;
 270         int     irq;
 271         int     tbdf;
 272         int     bmiba;                  /* bus master interface base address */
 273         int     maxio;                  /* sector count transfer maximum */
 274         int     span;                   /* don't span this boundary with dma */
 275         int     maxdma;                 /* don't attempt dma transfers bigger than this */
 276
 277         Pcidev* pcidev;
 278         void    (*ienable)(Ctlr*);
 279         void    (*idisable)(Ctlr*);
 280         SDev*   sdev;
 281
 282         Drive*  drive[2];
 283
 284         Prd*    prdt;                   /* physical region descriptor table */
 285         void    (*irqack)(Ctlr*);
 286
 287         QLock;                          /* current command */
 288         Drive*  curdrive;
 289         int     command;                /* last command issued (debugging) */
 290         Rendez;
 291         int     done;
 292         uint    nrq;
 293         uint    nildrive;
 294         uint    bsy;
 295
 296         Lock;                           /* register access */
 297 } Ctlr;
 298
 299 typedef struct Drive {
 300         Ctlr*   ctlr;
 301         SDunit  *unit;
 302
 303         int     dev;
 304         ushort  info[256];
 305         Sfis;
 306
 307         int     dma;                    /* DMA R/W possible */
 308         int     dmactl;
 309         int     rwm;                    /* read/write multiple possible */
 310         int     rwmctl;
 311
 312         int     pkt;                    /* PACKET device, length of pktcmd */
 313         uchar   pktcmd[16];
 314         int     pktdma;                 /* this PACKET command using dma */
 315
 316         uvlong  sectors;
 317         uint    secsize;
 318         char    serial[20+1];
 319         char    firmware[8+1];
 320         char    model[40+1];
 321
 322         QLock;                          /* drive access */
 323         int     command;                /* current command */
 324         int     write;
 325         uchar*  data;
 326         int     dlen;
 327         uchar*  limit;
 328         int     count;                  /* sectors */
 329         int     block;                  /* R/W bytes per block */
 330         int     status;
 331         int     error;
 332         int     flags;                  /* internal flags */
 333         uint    missirq;
 334         uint    spurloop;
 335         uint    irq;
 336         uint    bsy;
 337 } Drive;
 338
 339 enum {                                  /* internal flags */
 340         Lba48always     = 0x2,          /* ... */
 341         Online          = 0x4,          /* drive onlined */
 342 };
 343
 344 static void
 345 pc87415ienable(Ctlr* ctlr)
 346 {
 347         Pcidev *p;
 348         int x;
 349
 350         p = ctlr->pcidev;
 351         if(p == nil)
 352                 return;
 353
 354         x = pcicfgr32(p, 0x40);
 355         if(ctlr->cmdport == p->mem[0].bar)
 356                 x &= ~0x00000100;
 357         else
 358                 x &= ~0x00000200;
 359         pcicfgw32(p, 0x40, x);
 360 }
 361
 362 static void
 363 atadumpstate(Drive* drive, SDreq *r, uvlong lba, int count)
 364 {
 365         Prd *prd;
 366         Pcidev *p;
 367         Ctlr *ctlr;
 368         int i, bmiba, ccnt;
 369         uvlong clba;
 370
 371         if(!(DEBUG & DbgSTATE))
 372                 return;
 373
 374         ctlr = drive->ctlr;
 375         print("command %2.2uX\n", ctlr->command);
 376         print("data %8.8p limit %8.8p dlen %d status %uX error %uX\n",
 377                 drive->data, drive->limit, drive->dlen,
 378                 drive->status, drive->error);
 379         if(r->clen == -16)
 380                 clba = fisrw(nil, r->cmd, &ccnt);
 381         else
 382                 sdfakescsirw(r, &clba, &ccnt, 0);
 383         print("lba %llud -> %llud, count %d -> %d (%d)\n",
 384                 clba, lba, ccnt, count, drive->count);
 385         if(!(inb(ctlr->ctlport+As) & Bsy)){
 386                 for(i = 1; i < 7; i++)
 387                         print(" 0x%2.2uX", inb(ctlr->cmdport+i));
 388                 print(" 0x%2.2uX\n", inb(ctlr->ctlport+As));
 389         }
 390         if(drive->command == Cwd || drive->command == Crd
 391         || drive->command == (Pdma|Pin) || drive->command == (Pdma|Pout)){
 392                 bmiba = ctlr->bmiba;
 393                 prd = ctlr->prdt;
 394                 print("bmicx %2.2uX bmisx %2.2uX prdt %8.8p\n",
 395                         inb(bmiba+Bmicx), inb(bmiba+Bmisx), prd);
 396                 while(prd){
 397                         print("pa 0x%8.8luX count %8.8uX\n",
 398                                 prd->pa, prd->count);
 399                         if(prd->count & PrdEOT)
 400                                 break;
 401                         prd++;
 402                 }
 403         }
 404         if(ctlr->pcidev && ctlr->pcidev->vid == 0x8086){
 405                 p = ctlr->pcidev;
 406                 print("0x40: %4.4uX 0x42: %4.4uX ",
 407                         pcicfgr16(p, 0x40), pcicfgr16(p, 0x42));
 408                 print("0x48: %2.2uX\n", pcicfgr8(p, 0x48));
 409                 print("0x4A: %4.4uX\n", pcicfgr16(p, 0x4A));
 410         }
 411 }
 412
 413 static void
 414 atadebug(int cmdport, int ctlport, char* fmt, ...)
 415 {
 416         char *p, *e, buf[PRINTSIZE];
 417         int i;
 418         va_list arg;
 419
 420         if(!(DEBUG & DbgPROBE)){
 421                 USED(cmdport);
 422                 USED(ctlport);
 423                 USED(fmt);
 424                 return;
 425         }
 426
 427         p = buf;
 428         e = buf + sizeof buf;
 429         va_start(arg, fmt);
 430         p = vseprint(p, e, fmt, arg);
 431         va_end(arg);
 432
 433         if(cmdport){
 434                 if(p > buf && p[-1] == '\n')
 435                         p--;
 436                 p = seprint(p, e, " ataregs 0x%uX:", cmdport);
 437                 for(i = Features; i < Command; i++)
 438                         p = seprint(p, e, " 0x%2.2uX", inb(cmdport+i));
 439                 if(ctlport)
 440                         p = seprint(p, e, " 0x%2.2uX", inb(ctlport+As));
 441                 p = seprint(p, e, "\n");
 442         }
 443         putstrn(buf, p - buf);
 444 }
 445
 446 static int
 447 ataready(int cmdport, int ctlport, int dev, int reset, int ready, int m)
 448 {
 449         int as, m0;
 450
 451         atadebug(cmdport, ctlport, "ataready: dev %ux:%ux reset %ux ready %ux",
 452                 cmdport, dev, reset, ready);
 453         m0 = m;
 454         do{
 455                 /*
 456                  * Wait for the controller to become not busy and
 457                  * possibly for a status bit to become true (usually
 458                  * Drdy). Must change to the appropriate device
 459                  * register set if necessary before testing for ready.
 460                  * Always run through the loop at least once so it
 461                  * can be used as a test for !Bsy.
 462                  */
 463                 as = inb(ctlport+As);
 464                 if(as & reset){
 465                         /* nothing to do */
 466                 }
 467                 else if(dev){
 468                         outb(cmdport+Dh, dev);
 469                         dev = 0;
 470                 }
 471                 else if(ready == 0 || (as & ready)){
 472                         atadebug(0, 0, "ataready: %d:%d %#.2ux\n", m, m0, as);
 473                         return as;
 474                 }
 475                 microdelay(1);
 476         }while(m-- > 0);
 477         atadebug(0, 0, "ataready: timeout %d %#.2ux\n", m0, as);
 478         return -1;
 479 }
 480
 481 static int
 482 atadone(void* arg)
 483 {
 484         return ((Ctlr*)arg)->done;
 485 }
 486
 487 static int
 488 atarwmmode(Drive* drive, int cmdport, int ctlport, int dev)
 489 {
 490         int as, maxrwm, rwm;
 491
 492         maxrwm = drive->info[Imaxrwm] & 0xFF;
 493         if(maxrwm == 0)
 494                 return 0;
 495
 496         /*
 497          * Sometimes drives come up with the current count set
 498          * to 0; if so, set a suitable value, otherwise believe
 499          * the value in Irwm if the 0x100 bit is set.
 500          */
 501         if(drive->info[Irwm] & 0x100)
 502                 rwm = drive->info[Irwm] & 0xFF;
 503         else
 504                 rwm = 0;
 505         if(rwm == 0)
 506                 rwm = maxrwm;
 507         if(rwm > 16)
 508                 rwm = 16;
 509         if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 102*1000) < 0)
 510                 return 0;
 511         outb(cmdport+Count, rwm);
 512         outb(cmdport+Command, Csm);
 513         microdelay(1);
 514         as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 1000);
 515         inb(cmdport+Status);
 516         if(as < 0 || (as & (Df|Err)))
 517                 return 0;
 518
 519         drive->rwm = rwm;
 520
 521         return rwm;
 522 }
 523
 524 static int
 525 atadmamode(SDunit *unit, Drive* drive)
 526 {
 527         char buf[32], *s;
 528         int dma;
 529
 530         /*
 531          * Check if any DMA mode enabled.
 532          * Assumes the BIOS has picked and enabled the best.
 533          * This is completely passive at the moment, no attempt is
 534          * made to ensure the hardware is correctly set up.
 535          */
 536         dma = drive->info[Imwdma] & 0x0707;
 537         drive->dma = (dma>>8) & dma;
 538         if(drive->dma == 0 && (drive->info[Ivalid] & 0x04)){
 539                 dma = drive->info[Iudma] & 0x7F7F;
 540                 drive->dma = (dma>>8) & dma;
 541                 if(drive->dma)
 542                         drive->dma |= 'U'<<16;
 543         }
 544         if(unit != nil){
 545                 snprint(buf, sizeof buf, "*%sdma", unit->name);
 546                 s = getconf(buf);
 547                 if((s && !strcmp(s, "on")) || (!s && !getconf("*nodma")))
 548                         drive->dmactl = drive->dma;
 549         }
 550         return dma;
 551 }
 552
 553 static int
 554 ataidentify(Ctlr*, int cmdport, int ctlport, int dev, int pkt, void* info)
 555 {
 556         int as, command, drdy;
 557
 558         if(pkt){
 559                 command = Cidpkt;
 560                 drdy = 0;
 561         }
 562         else{
 563                 command = Cid;
 564                 drdy = Drdy;
 565         }
 566         dev &= ~Lba;
 567         as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
 568         if(as < 0)
 569                 return -1;
 570         outb(cmdport+Command, command);
 571         microdelay(1);
 572
 573         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
 574         if(as < 0 || (as & Err))
 575                 return as;
 576         memset(info, 0, 512);
 577         inss(cmdport+Data, info, 256);
 578         inb(cmdport+Status);
 579         return 0;
 580 }
 581
 582 static Drive*
 583 atadrive(SDunit *unit, Drive *drive, int cmdport, int ctlport, int dev)
 584 {
 585         int as, pkt, rlo, rhi;
 586         uchar buf[512], oserial[21];
 587         uvlong osectors;
 588         Ctlr *ctlr;
 589
 590         if(DEBUG & DbgIDENTIFY)
 591                 print("identify: port %ux dev %.2ux\n", cmdport, dev & ~Lba);
 592
 593         atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
 594         if(drive != nil){
 595                 osectors = drive->sectors;
 596                 memmove(oserial, drive->serial, sizeof drive->serial);
 597                 ctlr = drive->ctlr;
 598         }else{
 599                 osectors = 0;
 600                 memset(oserial, 0, sizeof drive->serial);
 601                 ctlr = nil;
 602
 603                 /* detect if theres a drive present */
 604                 outb(cmdport+Dh, dev & ~Lba);
 605                 microdelay(1);
 606                 outb(cmdport+Cyllo, 0xAA);
 607                 outb(cmdport+Cylhi, 0x55);
 608                 outb(cmdport+Sector, 0xFF);
 609                 rlo = inb(cmdport+Cyllo);
 610                 rhi = inb(cmdport+Cylhi);
 611                 if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55))
 612                         return nil;
 613         }
 614
 615         pkt = 1;
 616 retry:
 617         as = ataidentify(ctlr, cmdport, ctlport, dev, pkt, buf);
 618         if(as < 0)
 619                 return nil;
 620         if(as & Err){
 621                 if(pkt == 0)
 622                         return nil;
 623                 pkt = 0;
 624                 goto retry;
 625         }
 626
 627         if(drive == 0){
 628                 if((drive = malloc(sizeof(Drive))) == nil)
 629                         return nil;
 630                 drive->serial[0] = ' ';
 631                 drive->dev = dev;
 632         }
 633
 634         memmove(drive->info, buf, sizeof(drive->info));
 635
 636         setfissig(drive, pkt ? 0xeb140000 : 0x0101);
 637         drive->sectors = idfeat(drive, drive->info);
 638         drive->secsize = idss(drive, drive->info);
 639
 640         idmove(drive->serial, drive->info+10, 20);
 641         idmove(drive->firmware, drive->info+23, 8);
 642         idmove(drive->model, drive->info+27, 40);
 643         if(unit != nil){
 644                 memset(unit->inquiry, 0, sizeof unit->inquiry);
 645                 unit->inquiry[2] = 2;
 646                 unit->inquiry[3] = 2;
 647                 unit->inquiry[4] = sizeof unit->inquiry - 4;
 648                 memmove(unit->inquiry+8, drive->model, 40);
 649         }
 650
 651         if(pkt){
 652                 drive->pkt = 12;
 653                 if(drive->feat & Datapi16)
 654                         drive->pkt = 16;
 655         }else{
 656                 drive->pkt = 0;
 657                 if(drive->feat & Dlba)
 658                         drive->dev |= Lba;
 659                 atarwmmode(drive, cmdport, ctlport, dev);
 660         }
 661         atadmamode(unit, drive);
 662
 663         if(osectors != 0 && memcmp(oserial, drive->serial, sizeof oserial) != 0)
 664                 if(unit)
 665                         unit->sectors = 0;
 666         drive->unit = unit;
 667         if(DEBUG & DbgCONFIG){
 668                 print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
 669                         dev, cmdport, drive->info[Iconfig], drive->info[Icapabilities]);
 670                 print(" mwdma %4.4uX", drive->info[Imwdma]);
 671                 if(drive->info[Ivalid] & 0x04)
 672                         print(" udma %4.4uX", drive->info[Iudma]);
 673                 print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
 674                 if(drive->feat&Dllba)
 675                         print("\tLLBA sectors %llud", drive->sectors);
 676                 print("\n");
 677         }
 678
 679         return drive;
 680 }
 681
 682 static void
 683 atasrst(int ctlport)
 684 {
 685         int dc0;
 686
 687         /*
 688          * Srst is a big stick and may cause problems if further
 689          * commands are tried before the drives become ready again.
 690          * Also, there will be problems here if overlapped commands
 691          * are ever supported.
 692          */
 693         dc0 = inb(ctlport+Dc);
 694         microdelay(5);
 695         outb(ctlport+Dc, Srst|dc0);
 696         microdelay(5);
 697         outb(ctlport+Dc, dc0);
 698         microdelay(2*1000);
 699 }
 700
 701 static SDev*
 702 ataprobe(int cmdport, int ctlport, int irq, int map)
 703 {
 704         static int nonlegacy = 'C';
 705         Ctlr* ctlr;
 706         SDev *sdev;
 707
 708         if(ioalloc(cmdport, 8, 0, "atacmd") < 0) {
 709                 print("ataprobe: Cannot allocate %X\n", cmdport);
 710                 return nil;
 711         }
 712         if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
 713                 print("ataprobe: Cannot allocate %X\n", ctlport + As);
 714                 iofree(cmdport);
 715                 return nil;
 716         }
 717
 718         if((ctlr = malloc(sizeof(Ctlr))) == nil)
 719                 goto release;
 720         if((sdev = malloc(sizeof(SDev))) == nil){
 721                 free(ctlr);
 722                 goto release;
 723         }
 724
 725         if((map & 2) && (ctlr->drive[1] = atadrive(0, 0, cmdport, ctlport, Dev1)))
 726                 ctlr->drive[1]->ctlr = ctlr;
 727         if((map & 1) && (ctlr->drive[0] = atadrive(0, 0, cmdport, ctlport, Dev0)))
 728                 ctlr->drive[0]->ctlr = ctlr;
 729
 730         if(ctlr->drive[0] == nil && ctlr->drive[1] == nil){
 731                 free(ctlr->drive[0]);
 732                 free(ctlr->drive[1]);
 733                 free(ctlr);
 734                 free(sdev);
 735                 goto release;
 736         }
 737
 738         ctlr->cmdport = cmdport;
 739         ctlr->ctlport = ctlport;
 740         ctlr->irq = irq;
 741         ctlr->tbdf = BUSUNKNOWN;
 742         ctlr->command = Cnop;           /* debugging */
 743
 744         switch(cmdport){
 745         default:
 746                 sdev->idno = nonlegacy;
 747                 break;
 748         case 0x1F0:
 749                 sdev->idno = 'C';
 750                 nonlegacy = 'E';
 751                 break;
 752         case 0x170:
 753                 sdev->idno = 'D';
 754                 nonlegacy = 'E';
 755                 break;
 756         }
 757         sdev->ifc = &sdideifc;
 758         sdev->ctlr = ctlr;
 759         sdev->nunit = 2;
 760         ctlr->sdev = sdev;
 761
 762         return sdev;
 763
 764 release:
 765         iofree(cmdport);
 766         iofree(ctlport+As);
 767
 768         return nil;
 769 }
 770
 771 static void
 772 ataclear(SDev *sdev)
 773 {
 774         Ctlr* ctlr;
 775
 776         ctlr = sdev->ctlr;
 777         iofree(ctlr->cmdport);
 778         iofree(ctlr->ctlport + As);
 779
 780         if (ctlr->drive[0])
 781                 free(ctlr->drive[0]);
 782         if (ctlr->drive[1])
 783                 free(ctlr->drive[1]);
 784         if (sdev->name)
 785                 free(sdev->name);
 786         if (sdev->unitflg)
 787                 free(sdev->unitflg);
 788         if (sdev->unit)
 789                 free(sdev->unit);
 790         free(ctlr);
 791         free(sdev);
 792 }
 793
 794 static char *
 795 atastat(SDev *sdev, char *p, char *e)
 796 {
 797         Ctlr *ctlr;
 798
 799         ctlr = sdev->ctlr;
 800 //      return seprint(p, e, "%s ata port %X ctl %X irq %d %T\n",
 801 //                  sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq, ctlr->tbdf);
 802         return seprint(p, e, "%s ata port %X ctl %X irq %d\n",
 803                     sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq);
 804 }
 805
 806 static SDev*
 807 ataprobew(DevConf *cf)
 808 {
 809         char *p;
 810         ISAConf isa;
 811
 812         if (cf->nports != 2)
 813                 error(Ebadarg);
 814
 815         memset(&isa, 0, sizeof isa);
 816         isa.port = cf->ports[0].port;
 817         isa.irq = cf->intnum;
 818         if((p=strchr(cf->type, '/')) == nil || pcmspecial(p+1, &isa) < 0)
 819                 error("cannot find controller");
 820
 821         return ataprobe(cf->ports[0].port, cf->ports[1].port, cf->intnum, 3);
 822 }
 823
 824 static void atainterrupt(Ureg*, void*);
 825
 826 static int
 827 iowait(Drive *drive, int ms, int interrupt)
 828 {
 829         int msec, step;
 830         Ctlr *ctlr;
 831
 832         step = 1000;
 833         if(drive->missirq > 10)
 834                 step = 50;
 835         ctlr = drive->ctlr;
 836         for(msec = 0; msec < ms; msec += step){
 837                 while(waserror())
 838                         if(interrupt)
 839                                 return -1;
 840                 tsleep(ctlr, atadone, ctlr, step);
 841                 poperror();
 842                 if(ctlr->done)
 843                         break;
 844                 atainterrupt(nil, ctlr);
 845                 if(ctlr->done){
 846                         if(drive->missirq++ < 3)
 847                                 print("ide: caught missed irq\n");
 848                         break;
 849                 }else
 850                         drive->spurloop++;
 851         }
 852         return ctlr->done;
 853 }
 854
 855 static void
 856 atanop(Drive* drive, int subcommand)
 857 {
 858         Ctlr* ctlr;
 859         int as, cmdport, ctlport, timeo;
 860
 861         /*
 862          * Attempt to abort a command by using NOP.
 863          * In response, the drive is supposed to set Abrt
 864          * in the Error register, set (Drdy|Err) in Status
 865          * and clear Bsy when done. However, some drives
 866          * (e.g. ATAPI Zip) just go Bsy then clear Status
 867          * when done, hence the timeout loop only on Bsy
 868          * and the forced setting of drive->error.
 869          */
 870         ctlr = drive->ctlr;
 871         cmdport = ctlr->cmdport;
 872         outb(cmdport+Features, subcommand);
 873         outb(cmdport+Dh, drive->dev);
 874         ctlr->command = Cnop;           /* debugging */
 875         outb(cmdport+Command, Cnop);
 876
 877         microdelay(1);
 878         ctlport = ctlr->ctlport;
 879         for(timeo = 0; timeo < 1000; timeo++){
 880                 as = inb(ctlport+As);
 881                 if(!(as & Bsy))
 882                         break;
 883                 microdelay(1);
 884         }
 885         drive->error |= Abrt;
 886 }
 887
 888 static void
 889 ataabort(Drive* drive, int dolock)
 890 {
 891         /*
 892          * If NOP is available use it otherwise
 893          * must try a software reset.
 894          */
 895         if(dolock)
 896                 ilock(drive->ctlr);
 897         if(drive->feat & Dnop)
 898                 atanop(drive, 0);
 899         else{
 900                 atasrst(drive->ctlr->ctlport);
 901                 drive->error |= Abrt;
 902         }
 903         if(dolock)
 904                 iunlock(drive->ctlr);
 905 }
 906
 907 static int
 908 atadmasetup(Drive* drive, int len)
 909 {
 910         Prd *prd;
 911         ulong pa;
 912         Ctlr *ctlr;
 913         int bmiba, bmisx, count, i, span;
 914
 915         ctlr = drive->ctlr;
 916         pa = PCIWADDR(drive->data);
 917         if(pa & 0x03)
 918                 return -1;
 919         if(ctlr->maxdma && len > ctlr->maxdma)
 920                 return -1;
 921
 922         /*
 923          * Sometimes drives identify themselves as being DMA capable
 924          * although they are not on a busmastering controller.
 925          */
 926         prd = ctlr->prdt;
 927         if(prd == nil){
 928                 drive->dmactl = 0;
 929                 print("disabling dma: not on a busmastering controller\n");
 930                 return -1;
 931         }
 932
 933         for(i = 0; len && i < Nprd; i++){
 934                 prd->pa = pa;
 935                 span = ROUNDUP(pa, ctlr->span);
 936                 if(span == pa)
 937                         span += ctlr->span;
 938                 count = span - pa;
 939                 if(count >= len){
 940                         prd->count = PrdEOT|len;
 941                         break;
 942                 }
 943                 prd->count = count;
 944                 len -= count;
 945                 pa += count;
 946                 prd++;
 947         }
 948         if(i == Nprd)
 949                 return -1;
 950
 951         bmiba = ctlr->bmiba;
 952         outl(bmiba+Bmidtpx, PCIWADDR(ctlr->prdt));
 953         if(drive->write)
 954                 outb(bmiba+Bmicx, 0);
 955         else
 956                 outb(bmiba+Bmicx, Rwcon);
 957         bmisx = inb(bmiba+Bmisx);
 958         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
 959
 960         return 0;
 961 }
 962
 963 static void
 964 atadmastart(Ctlr* ctlr, int write)
 965 {
 966         if(write)
 967                 outb(ctlr->bmiba+Bmicx, Ssbm);
 968         else
 969                 outb(ctlr->bmiba+Bmicx, Rwcon|Ssbm);
 970 }
 971
 972 static int
 973 atadmastop(Ctlr* ctlr)
 974 {
 975         int bmiba;
 976
 977         bmiba = ctlr->bmiba;
 978         outb(bmiba+Bmicx, inb(bmiba+Bmicx) & ~Ssbm);
 979
 980         return inb(bmiba+Bmisx);
 981 }
 982
 983 static void
 984 atadmainterrupt(Drive* drive, int count)
 985 {
 986         Ctlr* ctlr;
 987         int bmiba, bmisx;
 988
 989         ctlr = drive->ctlr;
 990         bmiba = ctlr->bmiba;
 991         bmisx = inb(bmiba+Bmisx);
 992         switch(bmisx & (Ideints|Idedmae|Bmidea)){
 993         case Bmidea:
 994                 /*
 995                  * Data transfer still in progress, nothing to do
 996                  * (this should never happen).
 997                  */
 998                 return;
 999
1000         case Ideints:
1001         case Ideints|Bmidea:
1002                 /*
1003                  * Normal termination, tidy up.
1004                  */
1005                 drive->data += count;
1006                 break;
1007
1008         default:
1009                 /*
1010                  * What's left are error conditions (memory transfer
1011                  * problem) and the device is not done but the PRD is
1012                  * exhausted. For both cases must somehow tell the
1013                  * drive to abort.
1014                  */
1015                 ataabort(drive, 0);
1016                 break;
1017         }
1018         atadmastop(ctlr);
1019         ctlr->done = 1;
1020 }
1021
1022 static void
1023 atapktinterrupt(Drive* drive)
1024 {
1025         Ctlr* ctlr;
1026         int cmdport, len;
1027
1028         ctlr = drive->ctlr;
1029         cmdport = ctlr->cmdport;
1030         switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
1031         case Cd:
1032                 outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
1033                 break;
1034
1035         case 0:
1036                 if(drive->pktdma)
1037                         goto Pktdma;
1038                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1039                 if(drive->data+len > drive->limit){
1040                         atanop(drive, 0);
1041                         break;
1042                 }
1043                 outss(cmdport+Data, drive->data, len/2);
1044                 drive->data += len;
1045                 break;
1046
1047         case Io:
1048                 if(drive->pktdma)
1049                         goto Pktdma;
1050                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1051                 if(drive->data+len > drive->limit){
1052                         atanop(drive, 0);
1053                         break;
1054                 }
1055                 inss(cmdport+Data, drive->data, len/2);
1056                 drive->data += len;
1057                 break;
1058
1059         case Io|Cd:
1060                 if(drive->pktdma){
1061         Pktdma:
1062                         atadmainterrupt(drive, drive->dlen);
1063                 } else
1064                         ctlr->done = 1;
1065                 break;
1066         }
1067 }
1068
1069 static int
1070 atapktio0(Drive *drive, SDreq *r)
1071 {
1072         uchar *cmd;
1073         int as, len, cmdport, ctlport, rv;
1074         Ctlr *ctlr;
1075
1076         rv = SDok;
1077         cmd = r->cmd;
1078         drive->command = Cpkt;
1079         memmove(drive->pktcmd, cmd, r->clen);
1080         memset(drive->pktcmd+r->clen, 0, drive->pkt-r->clen);
1081         drive->limit = drive->data+drive->dlen;
1082
1083         ctlr = drive->ctlr;
1084         cmdport = ctlr->cmdport;
1085         ctlport = ctlr->ctlport;
1086
1087         as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 107*1000);
1088         /* used to test as&Chk as failure too, but some CD readers use that for media change */
1089         if(as < 0)
1090                 return SDnostatus;
1091
1092         ilock(ctlr);
1093         if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen))
1094                 drive->pktdma = Dma;
1095         else
1096                 drive->pktdma = 0;
1097         len = drive->secsize > 0 ? 16*drive->secsize : 0x8000;
1098         outb(cmdport+Features, drive->pktdma);
1099         outb(cmdport+Count, 0);
1100         outb(cmdport+Sector, 0);
1101         outb(cmdport+Bytelo, len);
1102         outb(cmdport+Bytehi, len>>8);
1103         outb(cmdport+Dh, drive->dev);
1104         ctlr->done = 0;
1105         ctlr->curdrive = drive;
1106         ctlr->command = Cpkt;           /* debugging */
1107         outb(cmdport+Command, Cpkt);
1108
1109         microdelay(1);
1110         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 400*1000);
1111         if(as < 0 || (as & (Bsy|Chk))){
1112                 drive->status = as<0 ? 0 : as;
1113                 ctlr->curdrive = nil;
1114                 ctlr->done = 1;
1115                 rv = SDtimeout;
1116         }else
1117                 atapktinterrupt(drive);
1118         if(drive->pktdma)
1119                 atadmastart(ctlr, drive->write);
1120         iunlock(ctlr);
1121
1122         while(iowait(drive, 30*1000, 1) == 0)
1123                 ;
1124
1125         ilock(ctlr);
1126         if(!ctlr->done){
1127                 rv = SDcheck;
1128                 ataabort(drive, 0);
1129         }
1130         if(drive->error){
1131                 if(drive->pktdma)
1132                         atadmastop(ctlr);
1133                 drive->status |= Chk;
1134                 ctlr->curdrive = nil;
1135         }
1136         iunlock(ctlr);
1137
1138         if(rv != SDcheck && drive->status & Chk){
1139                 rv = SDcheck;
1140                 if(drive->pktdma){
1141                         print("atapktio: disabling dma\n");
1142                         drive->dmactl = 0;
1143                 }
1144         }
1145         return rv;
1146 }
1147
1148 static int
1149 atapktio(Drive* drive, SDreq *r)
1150 {
1151         int n;
1152         Ctlr *ctlr;
1153
1154         ctlr = drive->ctlr;
1155         qlock(ctlr);
1156         n = atapktio0(drive, r);
1157         qunlock(ctlr);
1158         return n;
1159 }
1160
1161 static uchar cmd48[256] = {
1162         [Crs]   Crs48,
1163         [Crd]   Crd48,
1164         [Crsm]  Crsm48,
1165         [Cws]   Cws48,
1166         [Cwd]   Cwd48,
1167         [Cwsm]  Cwsm48,
1168 };
1169
1170 enum{
1171         Last28  = (1<<28) - 1,
1172 };
1173
1174 static int
1175 atageniostart(Drive* drive, uvlong lba)
1176 {
1177         Ctlr *ctlr;
1178         uchar cmd;
1179         int as, c, cmdport, ctlport, h, len, s, use48;
1180
1181         use48 = 0;
1182         if((drive->flags&Lba48always) || (lba+drive->count) > Last28 || drive->count > 256){
1183                 if((drive->feat & Dllba) == 0)
1184                         return -1;
1185                 use48 = 1;
1186                 c = h = s = 0;
1187         }else if(drive->dev & Lba){
1188                 c = (lba>>8) & 0xFFFF;
1189                 h = (lba>>24) & 0x0F;
1190                 s = lba & 0xFF;
1191         }else{
1192                 if (drive->s == 0 || drive->h == 0){
1193                         print("sdide: chs address botch");
1194                         return -1;
1195                 }
1196                 c = lba/(drive->s*drive->h);
1197                 h = (lba/drive->s) % drive->h;
1198                 s = (lba % drive->s) + 1;
1199         }
1200
1201         ctlr = drive->ctlr;
1202         cmdport = ctlr->cmdport;
1203         ctlport = ctlr->ctlport;
1204         if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 101*1000) < 0)
1205                 return -1;
1206
1207         ilock(ctlr);
1208         if(drive->dmactl && !atadmasetup(drive, drive->count*drive->secsize)){
1209                 if(drive->write)
1210                         drive->command = Cwd;
1211                 else
1212                         drive->command = Crd;
1213         }
1214         else if(drive->rwmctl){
1215                 drive->block = drive->rwm*drive->secsize;
1216                 if(drive->write)
1217                         drive->command = Cwsm;
1218                 else
1219                         drive->command = Crsm;
1220         }
1221         else{
1222                 drive->block = drive->secsize;
1223                 if(drive->write)
1224                         drive->command = Cws;
1225                 else
1226                         drive->command = Crs;
1227         }
1228         drive->limit = drive->data + drive->count*drive->secsize;
1229         cmd = drive->command;
1230         if(use48){
1231                 outb(cmdport+Count, drive->count>>8);
1232                 outb(cmdport+Count, drive->count);
1233                 outb(cmdport+Lbalo, lba>>24);
1234                 outb(cmdport+Lbalo, lba);
1235                 outb(cmdport+Lbamid, lba>>32);
1236                 outb(cmdport+Lbamid, lba>>8);
1237                 outb(cmdport+Lbahi, lba>>40);
1238                 outb(cmdport+Lbahi, lba>>16);
1239                 outb(cmdport+Dh, drive->dev|Lba);
1240                 cmd = cmd48[cmd];
1241
1242                 if(DEBUG & Dbg48BIT)
1243                         print("using 48-bit commands\n");
1244         }else{
1245                 outb(cmdport+Count, drive->count);
1246                 outb(cmdport+Sector, s);
1247                 outb(cmdport+Cyllo, c);
1248                 outb(cmdport+Cylhi, c>>8);
1249                 outb(cmdport+Dh, drive->dev|h);
1250         }
1251         ctlr->done = 0;
1252         ctlr->curdrive = drive;
1253         ctlr->command = drive->command; /* debugging */
1254         outb(cmdport+Command, cmd);
1255
1256         switch(drive->command){
1257         case Cws:
1258         case Cwsm:
1259                 microdelay(1);
1260                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1261                 if(as < 0 || (as & Err)){
1262                         iunlock(ctlr);
1263                         return -1;
1264                 }
1265                 len = drive->block;
1266                 if(drive->data+len > drive->limit)
1267                         len = drive->limit-drive->data;
1268                 outss(cmdport+Data, drive->data, len/2);
1269                 break;
1270
1271         case Crd:
1272         case Cwd:
1273                 atadmastart(ctlr, drive->write);
1274                 break;
1275         }
1276         iunlock(ctlr);
1277
1278         return 0;
1279 }
1280
1281 static int
1282 atagenioretry(Drive* drive, SDreq *r, uvlong lba, int count)
1283 {
1284         char *s;
1285         int rv, count0, rw;
1286         uvlong lba0;
1287
1288         if(drive->dmactl){
1289                 drive->dmactl = 0;
1290                 s = "disabling dma";
1291                 rv = SDretry;
1292         }else if(drive->rwmctl){
1293                 drive->rwmctl = 0;
1294                 s = "disabling rwm";
1295                 rv = SDretry;
1296         }else{
1297                 s = "nondma";
1298                 rv = sdsetsense(r, SDcheck, 4, 8, drive->error);
1299         }
1300         sdfakescsirw(r, &lba0, &count0, &rw);
1301         print("atagenioretry: %s %c:%llud:%d @%llud:%d\n",
1302                 s, "rw"[rw], lba0, count0, lba, count);
1303         return rv;
1304 }
1305
1306 static int
1307 atagenio(Drive* drive, SDreq *r)
1308 {
1309         Ctlr *ctlr;
1310         uvlong lba;
1311         int i, rw, count, maxio;
1312
1313         if((i = sdfakescsi(r)) != SDnostatus)
1314                 return i;
1315         if((i = sdfakescsirw(r, &lba, &count, &rw)) != SDnostatus)
1316                 return i;
1317         ctlr = drive->ctlr;
1318         if(drive->data == nil)
1319                 return SDok;
1320         if(drive->dlen < count*drive->secsize)
1321                 count = drive->dlen/drive->secsize;
1322         qlock(ctlr);
1323         if(ctlr->maxio)
1324                 maxio = ctlr->maxio;
1325         else if(drive->feat & Dllba)
1326                 maxio = 65536;
1327         else
1328                 maxio = 256;
1329         while(count){
1330                 if(count > maxio)
1331                         drive->count = maxio;
1332                 else
1333                         drive->count = count;
1334                 if(atageniostart(drive, lba)){
1335                         ilock(ctlr);
1336                         atanop(drive, 0);
1337                         iunlock(ctlr);
1338                         qunlock(ctlr);
1339                         return atagenioretry(drive, r, lba, count);
1340                 }
1341                 iowait(drive, 30*1000, 0);
1342                 if(!ctlr->done){
1343                         /*
1344                          * What should the above timeout be? In
1345                          * standby and sleep modes it could take as
1346                          * long as 30 seconds for a drive to respond.
1347                          * Very hard to get out of this cleanly.
1348                          */
1349                         atadumpstate(drive, r, lba, count);
1350                         ataabort(drive, 1);
1351                         qunlock(ctlr);
1352                         return atagenioretry(drive, r, lba, count);
1353                 }
1354
1355                 if(drive->status & Err){
1356                         qunlock(ctlr);
1357                         print("atagenio: %llud:%d\n", lba, drive->count);
1358                         return sdsetsense(r, SDcheck, 4, 8, drive->error);
1359                 }
1360                 count -= drive->count;
1361                 lba += drive->count;
1362         }
1363         qunlock(ctlr);
1364
1365         return SDok;
1366 }
1367
1368 static int
1369 atario(SDreq* r)
1370 {
1371         uchar *p;
1372         int status;
1373         Ctlr *ctlr;
1374         Drive *drive;
1375         SDunit *unit;
1376
1377         unit = r->unit;
1378         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
1379                 return r->status = SDtimeout;
1380         drive = ctlr->drive[unit->subno];
1381         qlock(drive);
1382         for(;;){
1383                 drive->write = r->write;
1384                 drive->data = r->data;
1385                 drive->dlen = r->dlen;
1386                 drive->status = 0;
1387                 drive->error = 0;
1388                 if(drive->pkt)
1389                         status = atapktio(drive, r);
1390                 else
1391                         status = atagenio(drive, r);
1392                 if(status != SDretry)
1393                         break;
1394                 if(DbgDEBUG)
1395                         print("%s: retry: dma %8.8uX rwm %4.4uX\n",
1396                                 unit->name, drive->dmactl, drive->rwmctl);
1397         }
1398         if(status == SDok && r->rlen == 0 && (r->flags & SDvalidsense) == 0){
1399                 sdsetsense(r, SDok, 0, 0, 0);
1400                 if(drive->data){
1401                         p = r->data;
1402                         r->rlen = drive->data - p;
1403                 }
1404                 else
1405                         r->rlen = 0;
1406         }
1407         qunlock(drive);
1408         return status;
1409 }
1410
1411 /**/
1412 static int
1413 isdmacmd(Drive *d, SDreq *r)
1414 {
1415         switch(r->ataproto & Pprotom){
1416         default:
1417                 return 0;
1418         case Pdmq:
1419                 error("no queued support");
1420         case Pdma:
1421                 if(!(d->dmactl || d->rwmctl))
1422                         error("dma in non dma mode\n");
1423                 return 1;
1424         }
1425 }
1426
1427 static int
1428 atagenatastart(Drive* d, SDreq *r)
1429 {
1430         uchar u;
1431         int as, cmdport, ctlport, len, pr, isdma;
1432         Ctlr *ctlr;
1433
1434         isdma = isdmacmd(d, r);
1435         ctlr = d->ctlr;
1436         cmdport = ctlr->cmdport;
1437         ctlport = ctlr->ctlport;
1438         if(ataready(cmdport, ctlport, d->dev, Bsy|Drq, d->pkt ? 0 : Drdy, 101*1000) < 0)
1439                 return -1;
1440
1441         ilock(ctlr);
1442         if(isdma && atadmasetup(d, d->block)){
1443                 iunlock(ctlr);
1444                 return -1;
1445
1446         }
1447         if(d->feat & Dllba && (r->ataproto & P28) == 0){
1448                 outb(cmdport+Features, r->cmd[Ffeat8]);
1449                 outb(cmdport+Features, r->cmd[Ffeat]);
1450                 outb(cmdport+Count, r->cmd[Fsc8]);
1451                 outb(cmdport+Count, r->cmd[Fsc]);
1452                 outb(cmdport+Lbalo, r->cmd[Flba24]);
1453                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1454                 outb(cmdport+Lbamid, r->cmd[Flba32]);
1455                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1456                 outb(cmdport+Lbahi, r->cmd[Flba40]);
1457                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1458                 u = r->cmd[Fdev] & ~0xb0;
1459                 outb(cmdport+Dh, d->dev|u);
1460         }else{
1461                 outb(cmdport+Features, r->cmd[Ffeat]);
1462                 outb(cmdport+Count, r->cmd[Fsc]);
1463                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1464                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1465                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1466                 u = r->cmd[Fdev] & ~0xb0;
1467                 outb(cmdport+Dh, d->dev|u);
1468         }
1469         ctlr->done = 0;
1470         ctlr->curdrive = d;
1471         d->command = r->ataproto & (Pprotom|Pdatam);
1472         ctlr->command = r->cmd[Fcmd];
1473         outb(cmdport+Command, r->cmd[Fcmd]);
1474
1475         pr = r->ataproto & Pprotom;
1476         if(pr == Pnd || pr == Preset)
1477                 USED(d);
1478         else if(!isdma){
1479                 microdelay(1);
1480                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
1481                 if(as < 0 || (as & Err)){
1482                         iunlock(ctlr);
1483                         return -1;
1484                 }
1485                 len = d->block;
1486                 if(r->write && len > 0)
1487                         outss(cmdport+Data, d->data, len/2);
1488         }else
1489                 atadmastart(ctlr, d->write);
1490         iunlock(ctlr);
1491         return 0;
1492 }
1493
1494 static void
1495 mkrfis(Drive *d, SDreq *r)
1496 {
1497         uchar *u;
1498         int cmdport;
1499         Ctlr *ctlr;
1500
1501         ctlr = d->ctlr;
1502         cmdport = ctlr->cmdport;
1503         u = r->cmd;
1504
1505         ilock(ctlr);
1506         u[Ftype] = 0x34;
1507         u[Fioport] = 0;
1508         if((d->feat & Dllba) && (r->ataproto & P28) == 0){
1509                 u[Frerror] = inb(cmdport+Error);
1510                 u[Fsc8] = inb(cmdport+Count);
1511                 u[Fsc] = inb(cmdport+Count);
1512                 u[Flba24] = inb(cmdport+Lbalo);
1513                 u[Flba0] = inb(cmdport+Lbalo);
1514                 u[Flba32] = inb(cmdport+Lbamid);
1515                 u[Flba8] = inb(cmdport+Lbamid);
1516                 u[Flba40] = inb(cmdport+Lbahi);
1517                 u[Flba16] = inb(cmdport+Lbahi);
1518                 u[Fdev] = inb(cmdport+Dh);
1519                 u[Fstatus] = inb(cmdport+Status);
1520         }else{
1521                 u[Frerror] = inb(cmdport+Error);
1522                 u[Fsc] = inb(cmdport+Count);
1523                 u[Flba0] = inb(cmdport+Lbalo);
1524                 u[Flba8] = inb(cmdport+Lbamid);
1525                 u[Flba16] = inb(cmdport+Lbahi);
1526                 u[Fdev] = inb(cmdport+Dh);
1527                 u[Fstatus] = inb(cmdport+Status);
1528         }
1529         iunlock(ctlr);
1530 }
1531
1532 static int
1533 atarstdone(Drive *d)
1534 {
1535         int as;
1536         Ctlr *c;
1537
1538         c = d->ctlr;
1539         as = ataready(c->cmdport, c->ctlport, 0, Bsy|Drq, 0, 5*1000);
1540         c->done = as >= 0;
1541         return c->done;
1542 }
1543
1544 static uint
1545 cmdss(Drive *d, SDreq *r)
1546 {
1547         switch(r->cmd[Fcmd]){
1548         case Cid:
1549         case Cidpkt:
1550                 return 512;
1551         default:
1552                 return d->secsize;
1553         }
1554 }
1555
1556 /*
1557  * various checks.  we should be craftier and
1558  * avoid figuring out how big stuff is supposed to be.
1559  */
1560 static uint
1561 patasizeck(Drive *d, SDreq *r)
1562 {
1563         uint count, maxio, secsize;
1564         Ctlr *ctlr;
1565
1566         secsize = cmdss(d, r);          /* BOTCH */
1567         if(secsize == 0)
1568                 error(Eio);
1569         count = r->dlen / secsize;
1570         ctlr = d->ctlr;
1571         if(ctlr->maxio)
1572                 maxio = ctlr->maxio;
1573         else if((d->feat & Dllba) && (r->ataproto & P28) == 0)
1574                 maxio = 65536;
1575         else
1576                 maxio = 256;
1577         if(count > maxio){
1578                 uprint("i/o too large, lim %d", maxio);
1579                 error(up->genbuf);
1580         }
1581         if(r->ataproto&Ppio && count > 1)
1582                 error("invalid # of sectors");
1583         return count;
1584 }
1585
1586 static int
1587 atapataio(Drive *d, SDreq *r)
1588 {
1589         int rv;
1590         Ctlr *ctlr;
1591
1592         d->count = 0;
1593         if(r->ataproto & Pdatam)
1594                 d->count = patasizeck(d, r);
1595         d->block = r->dlen;
1596         d->limit = d->data + r->dlen;
1597
1598         ctlr = d->ctlr;
1599         qlock(ctlr);
1600         if(waserror()){
1601                 qunlock(ctlr);
1602                 nexterror();
1603         }
1604         rv = atagenatastart(d, r);
1605         poperror();
1606         if(rv){
1607                 if(DEBUG & DbgAtazz)
1608                         print("sdide: !atageatastart\n");
1609                 ilock(ctlr);
1610                 atanop(d, 0);
1611                 iunlock(ctlr);
1612                 qunlock(ctlr);
1613                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1614         }
1615
1616         if((r->ataproto & Pprotom) == Preset)
1617                 atarstdone(d);
1618         else
1619                 while(iowait(d, 30*1000, 1) == 0)
1620                         ;
1621         if(!ctlr->done){
1622                 if(DEBUG & DbgAtazz){
1623                         print("sdide: !done\n");
1624                         atadumpstate(d, r, 0, d->count);
1625                 }
1626                 ataabort(d, 1);
1627                 qunlock(ctlr);
1628                 return sdsetsense(r, SDcheck, 11, 0, 6);        /* aborted; i/o process terminated */
1629         }
1630         mkrfis(d, r);
1631         if(d->status & Err){
1632                 if(DEBUG & DbgAtazz)
1633                         print("sdide: status&Err\n");
1634                 qunlock(ctlr);
1635                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1636         }
1637         qunlock(ctlr);
1638         return SDok;
1639 }
1640
1641 static int
1642 ataataio0(Drive *d, SDreq *r)
1643 {
1644         int i;
1645
1646         if((r->ataproto & Pprotom) == Ppkt){
1647                 if(r->clen > d->pkt)
1648                         error(Eio);
1649                 qlock(d->ctlr);
1650                 i = atapktio0(d, r);
1651                 d->block = d->data - (uchar*)r->data;
1652                 mkrfis(d, r);
1653                 qunlock(d->ctlr);
1654                 return i;
1655         }else
1656                 return atapataio(d, r);
1657 }
1658
1659 /*
1660  * hack to allow udma mode to be set or unset
1661  * via direct ata command.  it would be better
1662  * to move the assumptions about dma mode out
1663  * of some of the helper functions.
1664  */
1665 static int
1666 isudm(SDreq *r)
1667 {
1668         uchar *c;
1669
1670         c = r->cmd;
1671         if(c[Fcmd] == 0xef && c[Ffeat] == 0x03){
1672                 if(c[Fsc]&0x40)
1673                         return 1;
1674                 return -1;
1675         }
1676         return 0;
1677 }
1678
1679 static int
1680 fisreqchk(Sfis *f, SDreq *r)
1681 {
1682         if((r->ataproto & Pprotom) == Ppkt)
1683                 return SDnostatus;
1684         /*
1685          * handle oob requests;
1686          *    restrict & sanitize commands
1687          */
1688         if(r->clen != 16)
1689                 error(Eio);
1690         if(r->cmd[0] == 0xf0){
1691                 sigtofis(f, r->cmd);
1692                 r->status = SDok;
1693                 return SDok;
1694         }
1695         r->cmd[0] = 0x27;
1696         r->cmd[1] = 0x80;
1697         r->cmd[7] |= 0xa0;
1698         return SDnostatus;
1699 }
1700
1701 static int
1702 ataataio(SDreq *r)
1703 {
1704         int status, udm;
1705         Ctlr *c;
1706         Drive *d;
1707         SDunit *u;
1708
1709         u = r->unit;
1710         if((c = u->dev->ctlr) == nil || (d = c->drive[u->subno]) == nil){
1711                 r->status = SDtimeout;
1712                 return SDtimeout;
1713         }
1714         if((status = fisreqchk(d, r)) != SDnostatus)
1715                 return status;
1716         udm = isudm(r);
1717
1718         qlock(d);
1719         if(waserror()){
1720                 qunlock(d);
1721                 nexterror();
1722         }
1723 retry:
1724         d->write = r->write;
1725         d->data = r->data;
1726         d->dlen = r->dlen;
1727         d->status = 0;
1728         d->error = 0;
1729
1730         switch(status = ataataio0(d, r)){
1731         case SDretry:
1732                 if(DbgDEBUG)
1733                         print("%s: retry: dma %.8ux rwm %.4ux\n",
1734                                 u->name, d->dmactl, d->rwmctl);
1735                 goto retry;
1736         case SDok:
1737                 if(udm == 1)
1738                         d->dmactl = d->dma;
1739                 else if(udm == -1)
1740                         d->dmactl = 0;
1741                 sdsetsense(r, SDok, 0, 0, 0);
1742                 r->rlen = d->block;
1743                 break;
1744         }
1745         poperror();
1746         qunlock(d);
1747         r->status = status;
1748         return status;
1749 }
1750 /**/
1751
1752 static void
1753 ichirqack(Ctlr *ctlr)
1754 {
1755         int bmiba;
1756
1757         if(bmiba = ctlr->bmiba)
1758                 outb(bmiba+Bmisx, inb(bmiba+Bmisx));
1759 }
1760
1761 static void
1762 atainterrupt(Ureg*, void* arg)
1763 {
1764         Ctlr *ctlr;
1765         Drive *drive;
1766         int cmdport, len, status;
1767
1768         ctlr = arg;
1769
1770         ilock(ctlr);
1771         ctlr->nrq++;
1772         if(ctlr->curdrive)
1773                 ctlr->curdrive->irq++;
1774         if(inb(ctlr->ctlport+As) & Bsy){
1775                 ctlr->bsy++;
1776                 if(ctlr->curdrive)
1777                         ctlr->curdrive->bsy++;
1778                 iunlock(ctlr);
1779                 if(DEBUG & DbgBsy)
1780                         print("IBsy+");
1781                 return;
1782         }
1783         cmdport = ctlr->cmdport;
1784         status = inb(cmdport+Status);
1785         if((drive = ctlr->curdrive) == nil){
1786                 ctlr->nildrive++;
1787                 if(ctlr->irqack != nil)
1788                         ctlr->irqack(ctlr);
1789                 iunlock(ctlr);
1790                 return;
1791         }
1792         if(status & Err)
1793                 drive->error = inb(cmdport+Error);
1794         else switch(drive->command){
1795         default:
1796                 drive->error = Abrt;
1797                 break;
1798
1799         case Crs:
1800         case Crsm:
1801         case Ppio|Pin:
1802                 if(!(status & Drq)){
1803                         drive->error = Abrt;
1804                         break;
1805                 }
1806                 len = drive->block;
1807                 if(drive->data+len > drive->limit)
1808                         len = drive->limit-drive->data;
1809                 inss(cmdport+Data, drive->data, len/2);
1810                 drive->data += len;
1811                 if(drive->data >= drive->limit)
1812                         ctlr->done = 1;
1813                 break;
1814
1815         case Cws:
1816         case Cwsm:
1817         case Ppio|Pout:
1818                 len = drive->block;
1819                 if(drive->data+len > drive->limit)
1820                         len = drive->limit-drive->data;
1821                 drive->data += len;
1822                 if(drive->data >= drive->limit){
1823                         ctlr->done = 1;
1824                         break;
1825                 }
1826                 if(!(status & Drq)){
1827                         drive->error = Abrt;
1828                         break;
1829                 }
1830                 len = drive->block;
1831                 if(drive->data+len > drive->limit)
1832                         len = drive->limit-drive->data;
1833                 outss(cmdport+Data, drive->data, len/2);
1834                 break;
1835
1836         case Cpkt:
1837         case Ppkt|Pin:
1838         case Ppkt|Pout:
1839                 atapktinterrupt(drive);
1840                 break;
1841
1842         case Crd:
1843         case Cwd:
1844         case Pdma|Pin:
1845         case Pdma|Pout:
1846                 atadmainterrupt(drive, drive->count*drive->secsize);
1847                 break;
1848
1849         case Pnd:
1850         case Preset:
1851                 ctlr->done = 1;
1852                 break;
1853         }
1854         if(ctlr->irqack != nil)
1855                 ctlr->irqack(ctlr);
1856         iunlock(ctlr);
1857
1858         if(drive->error){
1859                 status |= Err;
1860                 ctlr->done = 1;
1861         }
1862
1863         if(ctlr->done){
1864                 ctlr->curdrive = nil;
1865                 drive->status = status;
1866                 wakeup(ctlr);
1867         }
1868 }
1869
1870 typedef struct Lchan Lchan;
1871 struct Lchan {
1872         int     cmdport;
1873         int     ctlport;
1874         int     irq;
1875         int     probed;
1876 };
1877 static Lchan lchan[2] = {
1878         0x1f0,  0x3f4,  IrqATA0,        0,
1879         0x170,  0x374,  IrqATA1,        0,
1880 };
1881
1882 static int
1883 badccru(Pcidev *p)
1884 {
1885         switch(p->did<<16 | p->did){
1886         case 0x439c<<16 | 0x1002:
1887         case 0x438c<<16 | 0x1002:
1888                 print("%T: allowing bad ccru %.2ux for suspected ide controller\n",
1889                         p->tbdf, p->ccru);
1890                 return 1;
1891         default:
1892                 return 0;
1893         }
1894 }
1895
1896 static SDev*
1897 atapnp(void)
1898 {
1899         char *s;
1900         int channel, map, ispc87415, maxio, pi, r, span, maxdma, tbdf;
1901         Ctlr *ctlr;
1902         Pcidev *p;
1903         SDev *sdev, *head, *tail;
1904         void (*irqack)(Ctlr*);
1905
1906         head = tail = nil;
1907         for(p = nil; p = pcimatch(p, 0, 0); ){
1908                 /*
1909                  * Look for devices with the correct class and sub-class
1910                  * code and known device and vendor ID; add native-mode
1911                  * channels to the list to be probed, save info for the
1912                  * compatibility mode channels.
1913                  * Note that the legacy devices should not be considered
1914                  * PCI devices by the interrupt controller.
1915                  * For both native and legacy, save info for busmastering
1916                  * if capable.
1917                  * Promise Ultra ATA/66 (PDC20262) appears to
1918                  * 1) give a sub-class of 'other mass storage controller'
1919                  *    instead of 'IDE controller', regardless of whether it's
1920                  *    the only controller or not;
1921                  * 2) put 0 in the programming interface byte (probably
1922                  *    as a consequence of 1) above).
1923                  * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
1924                  */
1925                 if(p->ccrb != 0x01)
1926                         continue;
1927                 if(!badccru(p))
1928                 if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
1929                         continue;
1930                 pi = p->ccrp;
1931                 map = 3;
1932                 ispc87415 = 0;
1933                 maxdma = 0;
1934                 maxio = 0;
1935                 if(s = getconf("*idemaxio"))
1936                         maxio = atoi(s);
1937                 span = BMspan;
1938                 irqack = nil;
1939
1940                 switch((p->did<<16)|p->vid){
1941                 default:
1942                         continue;
1943
1944                 case (0x0002<<16)|0x100B:       /* NS PC87415 */
1945                         /*
1946                          * Disable interrupts on both channels until
1947                          * after they are probed for drives.
1948                          * This must be called before interrupts are
1949                          * enabled because the IRQ may be shared.
1950                          */
1951                         ispc87415 = 1;
1952                         pcicfgw32(p, 0x40, 0x00000300);
1953                         break;
1954                 case (0x1000<<16)|0x1042:       /* PC-Tech RZ1000 */
1955                         /*
1956                          * Turn off prefetch. Overkill, but cheap.
1957                          */
1958                         r = pcicfgr32(p, 0x40);
1959                         r &= ~0x2000;
1960                         pcicfgw32(p, 0x40, r);
1961                         break;
1962                 case (0x4D38<<16)|0x105A:       /* Promise PDC20262 */
1963                 case (0x4D30<<16)|0x105A:       /* Promise PDC202xx */
1964                 case (0x4D68<<16)|0x105A:       /* Promise PDC20268 */
1965                 case (0x4D69<<16)|0x105A:       /* Promise Ultra/133 TX2 */
1966                 case (0x3373<<16)|0x105A:       /* Promise 20378 RAID */
1967                 case (0x3149<<16)|0x1106:       /* VIA VT8237 SATA/RAID */
1968                 case (0x0415<<16)|0x1106:       /* VIA VT6415 PATA IDE */
1969                 case (0x3112<<16)|0x1095:       /* SiL 3112 SATA/RAID */
1970                         maxio = 15;
1971                         span = 8*1024;
1972                         /*FALLTHROUGH*/
1973                 case (0x3114<<16)|0x1095:       /* SiL 3114 SATA/RAID */
1974                 case (0x0680<<16)|0x1095:       /* SiI 0680/680A PATA133 ATAPI/RAID */
1975                         pi = 0x85;
1976                         break;
1977                 case (0x0004<<16)|0x1103:       /* HighPoint HPT366 */
1978                         pi = 0x85;
1979                         /*
1980                          * Turn off fast interrupt prediction.
1981                          */
1982                         if((r = pcicfgr8(p, 0x51)) & 0x80)
1983                                 pcicfgw8(p, 0x51, r & ~0x80);
1984                         if((r = pcicfgr8(p, 0x55)) & 0x80)
1985                                 pcicfgw8(p, 0x55, r & ~0x80);
1986                         break;
1987                 case (0x0640<<16)|0x1095:       /* CMD 640B */
1988                         /*
1989                          * Bugfix code here...
1990                          */
1991                         break;
1992                 case (0x7441<<16)|0x1022:       /* AMD 768 */
1993                         /*
1994                          * Set:
1995                          *      0x41    prefetch, postwrite;
1996                          *      0x43    FIFO configuration 1/2 and 1/2;
1997                          *      0x44    status register read retry;
1998                          *      0x46    DMA read and end of sector flush.
1999                          */
2000                         r = pcicfgr8(p, 0x41);
2001                         pcicfgw8(p, 0x41, r|0xF0);
2002                         r = pcicfgr8(p, 0x43);
2003                         pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
2004                         r = pcicfgr8(p, 0x44);
2005                         pcicfgw8(p, 0x44, r|0x08);
2006                         r = pcicfgr8(p, 0x46);
2007                         pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
2008                         /*FALLTHROUGH*/
2009                 case (0x01BC<<16)|0x10DE:       /* nVidia nForce1 */
2010                 case (0x0065<<16)|0x10DE:       /* nVidia nForce2 */
2011                 case (0x0085<<16)|0x10DE:       /* nVidia nForce2 MCP */
2012                 case (0x00E3<<16)|0x10DE:       /* nVidia nForce2 250 SATA */
2013                 case (0x00D5<<16)|0x10DE:       /* nVidia nForce3 */
2014                 case (0x00E5<<16)|0x10DE:       /* nVidia nForce3 Pro */
2015                 case (0x00EE<<16)|0x10DE:       /* nVidia nForce3 250 SATA */
2016                 case (0x0035<<16)|0x10DE:       /* nVidia nForce3 MCP */
2017                 case (0x0053<<16)|0x10DE:       /* nVidia nForce4 */
2018                 case (0x0054<<16)|0x10DE:       /* nVidia nForce4 SATA */
2019                 case (0x0055<<16)|0x10DE:       /* nVidia nForce4 SATA */
2020                 case (0x0266<<16)|0x10DE:       /* nVidia nForce4 430 SATA */
2021                 case (0x0265<<16)|0x10DE:       /* nVidia nForce 51 MCP */
2022                 case (0x0267<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2023                 case (0x037f<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2024                 case (0x03ec<<16)|0x10DE:       /* nVidia nForce 61 MCP SATA */
2025                 case (0x03f6<<16)|0x10DE:       /* nVidia nForce 61 MCP PATA */
2026                 case (0x0448<<16)|0x10DE:       /* nVidia nForce 65 MCP SATA */
2027                 case (0x0560<<16)|0x10DE:       /* nVidia nForce 69 MCP SATA */
2028                         /*
2029                          * Ditto, although it may have a different base
2030                          * address for the registers (0x50?).
2031                          */
2032                         /*FALLTHROUGH*/
2033                 case (0x209A<<16)|0x1022:       /* AMD CS5536 */
2034                 case (0x7401<<16)|0x1022:       /* AMD 755 Cobra */
2035                 case (0x7409<<16)|0x1022:       /* AMD 756 Viper */
2036                 case (0x7410<<16)|0x1022:       /* AMD 766 Viper Plus */
2037                 case (0x7469<<16)|0x1022:       /* AMD 3111 */
2038                 case (0x4376<<16)|0x1002:       /* SB4xx pata */
2039                 case (0x4379<<16)|0x1002:       /* SB4xx sata */
2040                 case (0x437a<<16)|0x1002:       /* SB4xx sata ctlr #2 */
2041                 case (0x437c<<16)|0x1002:       /* Rx6xx pata */
2042                 case (0x438c<<16)|0x1002:       /* ATI SB600 PATA */
2043                 case (0x439c<<16)|0x1002:       /* SB7xx pata */
2044                         break;
2045
2046                 case (0x6101<<16)|0x11ab:       /* Marvell PATA */
2047                 case (0x6121<<16)|0x11ab:       /* Marvell PATA */
2048                 case (0x6123<<16)|0x11ab:       /* Marvell PATA */
2049                 case (0x6145<<16)|0x11ab:       /* Marvell PATA */
2050                 case (0x1b4b<<16)|0x91a0:       /* Marvell PATA */
2051                 case (0x1b4b<<16)|0x91a4:       /* Marvell PATA */
2052                         break;
2053
2054                 case (0x0211<<16)|0x1166:       /* ServerWorks IB6566 */
2055                         {
2056                                 Pcidev *sb;
2057
2058                                 sb = pcimatch(nil, 0x1166, 0x0200);
2059                                 if(sb == nil)
2060                                         break;
2061                                 r = pcicfgr32(sb, 0x64);
2062                                 r &= ~0x2000;
2063                                 pcicfgw32(sb, 0x64, r);
2064                         }
2065                         span = 32*1024;
2066                         break;
2067                 case (0x5229<<16)|0x10B9:       /* ALi M1543 */
2068                 case (0x5288<<16)|0x10B9:       /* ALi M5288 SATA */
2069                         /*FALLTHROUGH*/
2070                 case (0x5513<<16)|0x1039:       /* SiS 962 */
2071                 case (0x0646<<16)|0x1095:       /* CMD 646 */
2072                 case (0x0571<<16)|0x1106:       /* VIA 82C686 */
2073                 case (0x9001<<16)|0x1106:       /* VIA chipset in VIA PV530 */
2074                 case (0x0502<<16)|0x100b:       /* National Semiconductor SC1100/SCx200 */
2075                         break;
2076                 case (0x2360<<16)|0x197b:       /* jmicron jmb360 */
2077                 case (0x2361<<16)|0x197b:       /* jmicron jmb361 */
2078                 case (0x2363<<16)|0x197b:       /* jmicron jmb363 */
2079                 case (0x2365<<16)|0x197b:       /* jmicron jmb365 */
2080                 case (0x2366<<16)|0x197b:       /* jmicron jmb366 */
2081                 case (0x2368<<16)|0x197b:       /* jmicron jmb368 */
2082                         break;
2083                 case (0x7010<<16)|0x8086:       /* 82371SB (PIIX3) */
2084                 case (0x1230<<16)|0x8086:       /* 82371FB (PIIX) */
2085                 case (0x7111<<16)|0x8086:       /* 82371[AE]B (PIIX4[E]) */
2086                         maxdma = 0x20000;
2087                         break;
2088                 case (0x1c00<<16)|0x8086:       /* SERIES6 SATA */
2089                 case (0x1c01<<16)|0x8086:       /* SERIES6 SATA */
2090                 case (0x1c08<<16)|0x8086:       /* SERIES6 SATA */
2091                 case (0x1c09<<16)|0x8086:       /* SERIES6 SATA */
2092                 case (0x2411<<16)|0x8086:       /* 82801AA (ICH) */
2093                 case (0x2421<<16)|0x8086:       /* 82801AB (ICH0) */
2094                 case (0x244A<<16)|0x8086:       /* 82801BA (ICH2, Mobile) */
2095                 case (0x244B<<16)|0x8086:       /* 82801BA (ICH2, High-End) */
2096                 case (0x248A<<16)|0x8086:       /* 82801CA (ICH3, Mobile) */
2097                 case (0x248B<<16)|0x8086:       /* 82801CA (ICH3, High-End) */
2098                 case (0x24CA<<16)|0x8086:       /* 82801DBM (ICH4, Mobile) */
2099                 case (0x24CB<<16)|0x8086:       /* 82801DB (ICH4, High-End) */
2100                 case (0x24D1<<16)|0x8086:       /* 82801er (ich5) */
2101                 case (0x24DB<<16)|0x8086:       /* 82801EB (ICH5) */
2102                 case (0x25A2<<16)|0x8086:       /* 6300ESB pata */
2103                 case (0x25A3<<16)|0x8086:       /* 6300ESB (E7210) */
2104                 case (0x266F<<16)|0x8086:       /* 82801FB (ICH6) */
2105                 case (0x2651<<16)|0x8086:       /* 82801FB (ICH6) */
2106                 case (0x2653<<16)|0x8086:       /* 82801FBM (ICH6, Mobile) */
2107                 case (0x269e<<16)|0x8086:       /* 63xxESB (intel 5000) */
2108                 case (0x27DF<<16)|0x8086:       /* 82801G PATA (ICH7) */
2109                 case (0x27C0<<16)|0x8086:       /* 82801GB SATA (ICH7) */
2110                 case (0x27C4<<16)|0x8086:       /* 82801GBM SATA (ICH7) */
2111                 case (0x27C5<<16)|0x8086:       /* 82801GBM SATA AHCI (ICH7) */
2112                 case (0x2850<<16)|0x8086:       /* 82801HBM/HEM PATA */
2113                 case (0x2820<<16)|0x8086:       /* 82801HB/HR/HH/HO SATA IDE */
2114                 case (0x2825<<16)|0x8086:       /* 82801IIH Intel Q35 IDE */
2115                 case (0x2828<<16)|0x8086:       /* 82801HBM SATA (ICH8-M) */
2116                 case (0x2829<<16)|0x8086:       /* 82801HBM SATA AHCI (ICH8-M) */
2117                 case (0x2920<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-3 */
2118                 case (0x2921<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-1 */
2119                 case (0x2926<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 4-5 */
2120                 case (0x2928<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1 */
2121                 case (0x2929<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1, 4-5 */
2122                 case (0x292d<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 4-5*/
2123                 case (0x3a20<<16)|0x8086:       /* 82801ji (ich10) */
2124                 case (0x3a26<<16)|0x8086:       /* 82801ji (ich10) */
2125                 case (0x3b20<<16)|0x8086:       /* 34x0 (pch) port 0-3 */
2126                 case (0x3b21<<16)|0x8086:       /* 34x0 (pch) port 4-5 */
2127                 case (0x3b28<<16)|0x8086:       /* 34x0pm (pch) port 0-1, 4-5 */
2128                 case (0x3b2e<<16)|0x8086:       /* 34x0pm (pch) port 0-3 */
2129                         map = 0;
2130                         if(pcicfgr16(p, 0x40) & 0x8000)
2131                                 map |= 1;
2132                         if(pcicfgr16(p, 0x42) & 0x8000)
2133                                 map |= 2;
2134                         irqack = ichirqack;
2135                         break;
2136                 case (0x811a<<16)|0x8086:       /* Intel SCH (Poulsbo) */
2137                         map = 1;
2138                         irqack = ichirqack;
2139                         break;
2140                 }
2141                 for(channel = 0; channel < 2; channel++){
2142                         if((map & 1<<channel) == 0)
2143                                 continue;
2144                         if(pi & 1<<2*channel){
2145                                 sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
2146                                                 p->mem[1+2*channel].bar & ~0x01,
2147                                                 p->intl, 3);
2148                                 tbdf = p->tbdf;
2149                         }
2150                         else if(lchan[channel].probed == 0){
2151                                 sdev = ataprobe(lchan[channel].cmdport,
2152                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2153                                 lchan[channel].probed = 1;
2154                                 tbdf = BUSUNKNOWN;
2155                         }
2156                         else
2157                                 continue;
2158                         if(sdev == nil)
2159                                 continue;
2160                         ctlr = sdev->ctlr;
2161                         if(ispc87415) {
2162                                 ctlr->ienable = pc87415ienable;
2163                                 print("pc87415disable: not yet implemented\n");
2164                         }
2165                         ctlr->tbdf = tbdf;
2166                         ctlr->pcidev = p;
2167                         ctlr->maxio = maxio;
2168                         ctlr->maxdma = maxdma;
2169                         ctlr->span = span;
2170                         ctlr->irqack = irqack;
2171                         if((pi & 0x80) && (p->mem[4].bar & 0x01))
2172                                 ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
2173                         if(head != nil)
2174                                 tail->next = sdev;
2175                         else
2176                                 head = sdev;
2177                         tail = sdev;
2178                 }
2179         }
2180
2181         if(lchan[0].probed + lchan[1].probed == 0)
2182                 for(channel = 0; channel < 2; channel++){
2183                         sdev = nil;
2184                         if(lchan[channel].probed == 0){
2185         //                      print("sdide: blind probe %.3ux\n", lchan[channel].cmdport);
2186                                 sdev = ataprobe(lchan[channel].cmdport,
2187                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2188                                 lchan[channel].probed = 1;
2189                         }
2190                         if(sdev == nil)
2191                                 continue;
2192                         if(head != nil)
2193                                 tail->next = sdev;
2194                         else
2195                                 head = sdev;
2196                         tail = sdev;
2197                 }
2198
2199 if(0){
2200         int port;
2201         ISAConf isa;
2202
2203         /*
2204          * Hack for PCMCIA drives.
2205          * This will be tidied once we figure out how the whole
2206          * removeable device thing is going to work.
2207          */
2208         memset(&isa, 0, sizeof(isa));
2209         isa.port = 0x180;               /* change this for your machine */
2210         isa.irq = 11;                   /* change this for your machine */
2211
2212         port = isa.port+0x0C;
2213         channel = pcmspecial("MK2001MPL", &isa);
2214         if(channel == -1)
2215                 channel = pcmspecial("SunDisk", &isa);
2216         if(channel == -1){
2217                 isa.irq = 10;
2218                 channel = pcmspecial("CF", &isa);
2219         }
2220         if(channel == -1){
2221                 isa.irq = 10;
2222                 channel = pcmspecial("OLYMPUS", &isa);
2223         }
2224         if(channel == -1){
2225                 port = isa.port+0x204;
2226                 channel = pcmspecial("ATA/ATAPI", &isa);
2227         }
2228         if(channel >= 0 && (sdev = ataprobe(isa.port, port, isa.irq, 3)) != nil){
2229                 if(head != nil)
2230                         tail->next = sdev;
2231                 else
2232                         head = sdev;
2233         }
2234 }
2235         return head;
2236 }
2237
2238 static void
2239 atadmaclr(Ctlr *ctlr)
2240 {
2241         int bmiba, bmisx;
2242
2243         if(ctlr->curdrive)
2244                 ataabort(ctlr->curdrive, 1);
2245         bmiba = ctlr->bmiba;
2246         if(bmiba == 0)
2247                 return;
2248         atadmastop(ctlr);
2249         outl(bmiba+Bmidtpx, 0);
2250         bmisx = inb(bmiba+Bmisx) & ~Bmidea;
2251         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
2252 //      pciintst(ctlr->pcidev);
2253 }
2254
2255 static int
2256 ataenable(SDev* sdev)
2257 {
2258         Ctlr *ctlr;
2259         char name[32];
2260
2261         ctlr = sdev->ctlr;
2262         if(ctlr->bmiba){
2263                 atadmaclr(ctlr);
2264                 if(ctlr->pcidev != nil)
2265                         pcisetbme(ctlr->pcidev);
2266                 /* Intel SCH requires 8 byte alignment, though datasheet says 4 m( */
2267                 ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 8, 0, 64*1024);
2268         }
2269         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2270         intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2271         outb(ctlr->ctlport+Dc, 0);
2272         if(ctlr->ienable)
2273                 ctlr->ienable(ctlr);
2274         return 1;
2275 }
2276
2277 static int
2278 atadisable(SDev *sdev)
2279 {
2280         Ctlr *ctlr;
2281         char name[32];
2282
2283         ctlr = sdev->ctlr;
2284         outb(ctlr->ctlport+Dc, Nien);           /* disable interrupts */
2285         if (ctlr->idisable)
2286                 ctlr->idisable(ctlr);
2287         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2288         intrdisable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2289         if(ctlr->bmiba) {
2290 //              atadmaclr(ctlr);
2291                 if (ctlr->pcidev)
2292                         pciclrbme(ctlr->pcidev);
2293                 free(ctlr->prdt);
2294                 ctlr->prdt = nil;
2295         }
2296         return 0;
2297 }
2298
2299 static int
2300 ataonline(SDunit *unit)
2301 {
2302         Drive *drive;
2303         Ctlr *ctlr;
2304         int ret;
2305
2306         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2307                 return 0;
2308         ret = 1;
2309         drive = ctlr->drive[unit->subno];
2310         if((drive->flags & Online) == 0){
2311                 drive->flags |= Online;
2312                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2313                 ret = 2;
2314         }
2315         if(drive->feat & Datapi){
2316                 ulong dma;
2317
2318                 dma = drive->dmactl;
2319                 drive->dmactl = 0;
2320                 ret = scsionline(unit);
2321                 drive->dmactl = dma;
2322         } else {
2323                 unit->sectors = drive->sectors;
2324                 unit->secsize = drive->secsize;
2325         }
2326         return ret;
2327 }
2328
2329 static int
2330 atarctl(SDunit* unit, char* p, int l)
2331 {
2332         Ctlr *ctlr;
2333         Drive *drive;
2334         char *e, *op;
2335
2336         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2337                 return 0;
2338         drive = ctlr->drive[unit->subno];
2339
2340         e = p+l;
2341         op = p;
2342         qlock(drive);
2343         p = seprint(p, e, "config %4.4uX capabilities %4.4uX", drive->info[Iconfig], drive->info[Icapabilities]);
2344         if(drive->dma)
2345                 p = seprint(p, e, " dma %8.8uX dmactl %8.8uX", drive->dma, drive->dmactl);
2346         if(drive->rwm)
2347                 p = seprint(p, e, " rwm %ud rwmctl %ud", drive->rwm, drive->rwmctl);
2348         if(drive->feat & Dllba)
2349                 p = seprint(p, e, " lba48always %s", (drive->flags&Lba48always) ? "on" : "off");
2350         p = seprint(p, e, "\n");
2351         p = seprint(p, e, "model        %s\n", drive->model);
2352         p = seprint(p, e, "serial       %s\n", drive->serial);
2353         p = seprint(p, e, "firm %s\n", drive->firmware);
2354         p = seprint(p, e, "feat ");
2355         p = pflag(p, e, drive);
2356         if(drive->sectors){
2357                 p = seprint(p, e, "geometry %llud %d", drive->sectors, drive->secsize);
2358                 if(drive->pkt == 0 && (drive->feat & Dlba) == 0)
2359                         p = seprint(p, e, " %d %d %d", drive->c, drive->h, drive->s);
2360                 p = seprint(p, e, "\n");
2361                 p = seprint(p, e, "alignment %d %d\n",
2362                         drive->secsize<<drive->physshift, drive->physalign);
2363         }
2364         p = seprint(p, e, "missirq      %ud\n", drive->missirq);
2365         p = seprint(p, e, "sloop        %ud\n", drive->spurloop);
2366         p = seprint(p, e, "irq  %ud %ud\n", ctlr->nrq, drive->irq);
2367         p = seprint(p, e, "bsy  %ud %ud\n", ctlr->bsy, drive->bsy);
2368         p = seprint(p, e, "nildrive     %ud\n", ctlr->nildrive);
2369         qunlock(drive);
2370
2371         return p - op;
2372 }
2373
2374 static int
2375 atawctl(SDunit* unit, Cmdbuf* cb)
2376 {
2377         Ctlr *ctlr;
2378         Drive *drive;
2379
2380         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2381                 return 0;
2382         drive = ctlr->drive[unit->subno];
2383
2384         qlock(drive);
2385         if(waserror()){
2386                 qunlock(drive);
2387                 nexterror();
2388         }
2389
2390         /*
2391          * Dma and rwm control is passive at the moment,
2392          * i.e. it is assumed that the hardware is set up
2393          * correctly already either by the BIOS or when
2394          * the drive was initially identified.
2395          */
2396         if(strcmp(cb->f[0], "dma") == 0){
2397                 if(cb->nf != 2 || drive->dma == 0)
2398                         error(Ebadctl);
2399                 if(strcmp(cb->f[1], "on") == 0)
2400                         drive->dmactl = drive->dma;
2401                 else if(strcmp(cb->f[1], "off") == 0)
2402                         drive->dmactl = 0;
2403                 else
2404                         error(Ebadctl);
2405         }
2406         else if(strcmp(cb->f[0], "rwm") == 0){
2407                 if(cb->nf != 2 || drive->rwm == 0)
2408                         error(Ebadctl);
2409                 if(strcmp(cb->f[1], "on") == 0)
2410                         drive->rwmctl = drive->rwm;
2411                 else if(strcmp(cb->f[1], "off") == 0)
2412                         drive->rwmctl = 0;
2413                 else
2414                         error(Ebadctl);
2415         }
2416         else if(strcmp(cb->f[0], "lba48always") == 0){
2417                 if(cb->nf != 2 || !(drive->feat & Dllba))
2418                         error(Ebadctl);
2419                 if(strcmp(cb->f[1], "on") == 0)
2420                         drive->flags |= Lba48always;
2421                 else if(strcmp(cb->f[1], "off") == 0)
2422                         drive->flags &= ~Lba48always;
2423                 else
2424                         error(Ebadctl);
2425         }
2426         else if(strcmp(cb->f[0], "identify") == 0){
2427                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2428         }
2429         else
2430                 error(Ebadctl);
2431         qunlock(drive);
2432         poperror();
2433
2434         return 0;
2435 }
2436
2437 SDifc sdideifc = {
2438         "ide",                          /* name */
2439
2440         atapnp,                         /* pnp */
2441         nil,                            /* legacy */
2442         ataenable,                      /* enable */
2443         atadisable,                     /* disable */
2444
2445         scsiverify,                     /* verify */
2446         ataonline,                      /* online */
2447         atario,                         /* rio */
2448         atarctl,                        /* rctl */
2449         atawctl,                        /* wctl */
2450
2451         scsibio,                        /* bio */
2452         ataprobew,                      /* probe */
2453         ataclear,                       /* clear */
2454         atastat,                        /* rtopctl */
2455         nil,                            /* wtopctl */
2456         ataataio,
2457 };