sys/src/9/pc/sdide.c

   1 #include "u.h"
   2 #include "../port/lib.h"
   3 #include "mem.h"
   4 #include "dat.h"
   5 #include "fns.h"
   6 #include "io.h"
   7 #include "ureg.h"
   8 #include "../port/error.h"
   9
  10 #include "../port/sd.h"
  11 #include <fis.h>
  12
  13 #define HOWMANY(x, y)   (((x)+((y)-1))/(y))
  14 #define ROUNDUP(x, y)   (HOWMANY((x), (y))*(y))
  15 #define uprint(...)     snprint(up->genbuf, sizeof up->genbuf, __VA_ARGS__);
  16 #pragma varargck        argpos  atadebug                3
  17
  18 extern SDifc sdideifc;
  19
  20 enum {
  21         DbgCONFIG       = 0x0001,       /* detected drive config info */
  22         DbgIDENTIFY     = 0x0002,       /* detected drive identify info */
  23         DbgSTATE        = 0x0004,       /* dump state on panic */
  24         DbgPROBE        = 0x0008,       /* trace device probing */
  25         DbgDEBUG        = 0x0080,       /* the current problem... */
  26         DbgINL          = 0x0100,       /* That Inil20+ message we hate */
  27         Dbg48BIT        = 0x0200,       /* 48-bit LBA */
  28         DbgBsy          = 0x0400,       /* interrupt but Bsy (shared IRQ) */
  29         DbgAtazz        = 0x0800,       /* debug raw ata io */
  30 };
  31 #define DEBUG           (DbgDEBUG|DbgSTATE)
  32
  33 enum {                                  /* I/O ports */
  34         Data            = 0,
  35         Error           = 1,            /* (read) */
  36         Features        = 1,            /* (write) */
  37         Count           = 2,            /* sector count<7-0>, sector count<15-8> */
  38         Ir              = 2,            /* interrupt reason (PACKET) */
  39         Sector          = 3,            /* sector number */
  40         Lbalo           = 3,            /* LBA<7-0>, LBA<31-24> */
  41         Cyllo           = 4,            /* cylinder low */
  42         Bytelo          = 4,            /* byte count low (PACKET) */
  43         Lbamid          = 4,            /* LBA<15-8>, LBA<39-32> */
  44         Cylhi           = 5,            /* cylinder high */
  45         Bytehi          = 5,            /* byte count hi (PACKET) */
  46         Lbahi           = 5,            /* LBA<23-16>, LBA<47-40> */
  47         Dh              = 6,            /* Device/Head, LBA<27-24> */
  48         Status          = 7,            /* (read) */
  49         Command         = 7,            /* (write) */
  50
  51         As              = 2,            /* Alternate Status (read) */
  52         Dc              = 2,            /* Device Control (write) */
  53 };
  54
  55 enum {                                  /* Error */
  56         Med             = 0x01,         /* Media error */
  57         Ili             = 0x01,         /* command set specific (PACKET) */
  58         Nm              = 0x02,         /* No Media */
  59         Eom             = 0x02,         /* command set specific (PACKET) */
  60         Abrt            = 0x04,         /* Aborted command */
  61         Mcr             = 0x08,         /* Media Change Request */
  62         Idnf            = 0x10,         /* no user-accessible address */
  63         Mc              = 0x20,         /* Media Change */
  64         Unc             = 0x40,         /* Uncorrectable data error */
  65         Wp              = 0x40,         /* Write Protect */
  66         Icrc            = 0x80,         /* Interface CRC error */
  67 };
  68
  69 enum {                                  /* Features */
  70         Dma             = 0x01,         /* data transfer via DMA (PACKET) */
  71         Ovl             = 0x02,         /* command overlapped (PACKET) */
  72 };
  73
  74 enum {                                  /* Interrupt Reason */
  75         Cd              = 0x01,         /* Command/Data */
  76         Io              = 0x02,         /* I/O direction */
  77         Rel             = 0x04,         /* Bus Release */
  78 };
  79
  80 enum {                                  /* Device/Head */
  81         Dev0            = 0xA0,         /* Master */
  82         Dev1            = 0xB0,         /* Slave */
  83         Devs            = Dev0 | Dev1,
  84         Lba             = 0x40,         /* LBA mode */
  85 };
  86
  87 enum {                                  /* Status, Alternate Status */
  88         Err             = 0x01,         /* Error */
  89         Chk             = 0x01,         /* Check error (PACKET) */
  90         Drq             = 0x08,         /* Data Request */
  91         Dsc             = 0x10,         /* Device Seek Complete */
  92         Serv            = 0x10,         /* Service */
  93         Df              = 0x20,         /* Device Fault */
  94         Dmrd            = 0x20,         /* DMA ready (PACKET) */
  95         Drdy            = 0x40,         /* Device Ready */
  96         Bsy             = 0x80,         /* Busy */
  97 };
  98
  99 enum {                                  /* Command */
 100         Cnop            = 0x00,         /* NOP */
 101         Crs             = 0x20,         /* Read Sectors */
 102         Crs48           = 0x24,         /* Read Sectors Ext */
 103         Crd48           = 0x25,         /* Read w/ DMA Ext */
 104         Crsm48          = 0x29,         /* Read Multiple Ext */
 105         Cws             = 0x30,         /* Write Sectors */
 106         Cws48           = 0x34,         /* Write Sectors Ext */
 107         Cwd48           = 0x35,         /* Write w/ DMA Ext */
 108         Cwsm48          = 0x39,         /* Write Multiple Ext */
 109         Cedd            = 0x90,         /* Execute Device Diagnostics */
 110         Cpkt            = 0xA0,         /* Packet */
 111         Cidpkt          = 0xA1,         /* Identify Packet Device */
 112         Crsm            = 0xC4,         /* Read Multiple */
 113         Cwsm            = 0xC5,         /* Write Multiple */
 114         Csm             = 0xC6,         /* Set Multiple */
 115         Crd             = 0xC8,         /* Read DMA */
 116         Cwd             = 0xCA,         /* Write DMA */
 117         Cid             = 0xEC,         /* Identify Device */
 118 };
 119
 120 enum {                                  /* Device Control */
 121         Nien            = 0x02,         /* (not) Interrupt Enable */
 122         Srst            = 0x04,         /* Software Reset */
 123         Hob             = 0x80,         /* High Order Bit [sic] */
 124 };
 125
 126 enum {                                  /* PCI Configuration Registers */
 127         Bmiba           = 0x20,         /* Bus Master Interface Base Address */
 128         Idetim          = 0x40,         /* IE Timing */
 129         Sidetim         = 0x44,         /* Slave IE Timing */
 130         Udmactl         = 0x48,         /* Ultra DMA/33 Control */
 131         Udmatim         = 0x4A,         /* Ultra DMA/33 Timing */
 132 };
 133
 134 enum {                                  /* Bus Master IDE I/O Ports */
 135         Bmicx           = 0,            /* Command */
 136         Bmisx           = 2,            /* Status */
 137         Bmidtpx         = 4,            /* Descriptor Table Pointer */
 138 };
 139
 140 enum {                                  /* Bmicx */
 141         Ssbm            = 0x01,         /* Start/Stop Bus Master */
 142         Rwcon           = 0x08,         /* Read/Write Control */
 143 };
 144
 145 enum {                                  /* Bmisx */
 146         Bmidea          = 0x01,         /* Bus Master IDE Active */
 147         Idedmae         = 0x02,         /* IDE DMA Error  (R/WC) */
 148         Ideints         = 0x04,         /* IDE Interrupt Status (R/WC) */
 149         Dma0cap         = 0x20,         /* Drive 0 DMA Capable */
 150         Dma1cap         = 0x40,         /* Drive 0 DMA Capable */
 151 };
 152 enum {                                  /* Physical Region Descriptor */
 153         PrdEOT          = 0x80000000,   /* End of Transfer */
 154 };
 155
 156 enum {                                  /* offsets into the identify info. */
 157         Iconfig         = 0,            /* general configuration */
 158         Ilcyl           = 1,            /* logical cylinders */
 159         Ilhead          = 3,            /* logical heads */
 160         Ilsec           = 6,            /* logical sectors per logical track */
 161         Iserial         = 10,           /* serial number */
 162         Ifirmware       = 23,           /* firmware revision */
 163         Imodel          = 27,           /* model number */
 164         Imaxrwm         = 47,           /* max. read/write multiple sectors */
 165         Icapabilities   = 49,           /* capabilities */
 166         Istandby        = 50,           /* device specific standby timer */
 167         Ipiomode        = 51,           /* PIO data transfer mode number */
 168         Ivalid          = 53,
 169         Iccyl           = 54,           /* cylinders if (valid&0x01) */
 170         Ichead          = 55,           /* heads if (valid&0x01) */
 171         Icsec           = 56,           /* sectors if (valid&0x01) */
 172         Iccap           = 57,           /* capacity if (valid&0x01) */
 173         Irwm            = 59,           /* read/write multiple */
 174         Ilba            = 60,           /* LBA size */
 175         Imwdma          = 63,           /* multiword DMA mode */
 176         Iapiomode       = 64,           /* advanced PIO modes supported */
 177         Iminmwdma       = 65,           /* min. multiword DMA cycle time */
 178         Irecmwdma       = 66,           /* rec. multiword DMA cycle time */
 179         Iminpio         = 67,           /* min. PIO cycle w/o flow control */
 180         Iminiordy       = 68,           /* min. PIO cycle with IORDY */
 181         Ipcktbr         = 71,           /* time from PACKET to bus release */
 182         Iserbsy         = 72,           /* time from SERVICE to !Bsy */
 183         Iqdepth         = 75,           /* max. queue depth */
 184         Imajor          = 80,           /* major version number */
 185         Iminor          = 81,           /* minor version number */
 186         Icsfs           = 82,           /* command set/feature supported */
 187         Icsfe           = 85,           /* command set/feature enabled */
 188         Iudma           = 88,           /* ultra DMA mode */
 189         Ierase          = 89,           /* time for security erase */
 190         Ieerase         = 90,           /* time for enhanced security erase */
 191         Ipower          = 91,           /* current advanced power management */
 192         Ilba48          = 100,          /* 48-bit LBA size (64 bits in 100-103) */
 193         Irmsn           = 127,          /* removable status notification */
 194         Isecstat        = 128,          /* security status */
 195         Icfapwr         = 160,          /* CFA power mode */
 196         Imediaserial    = 176,          /* current media serial number */
 197         Icksum          = 255,          /* checksum */
 198 };
 199
 200 enum {                                  /* bit masks for config identify info */
 201         Mpktsz          = 0x0003,       /* packet command size */
 202         Mincomplete     = 0x0004,       /* incomplete information */
 203         Mdrq            = 0x0060,       /* DRQ type */
 204         Mrmdev          = 0x0080,       /* device is removable */
 205         Mtype           = 0x1F00,       /* device type */
 206         Mproto          = 0x8000,       /* command protocol */
 207 };
 208
 209 enum {                                  /* bit masks for capabilities identify info */
 210         Mdma            = 0x0100,       /* DMA supported */
 211         Mlba            = 0x0200,       /* LBA supported */
 212         Mnoiordy        = 0x0400,       /* IORDY may be disabled */
 213         Miordy          = 0x0800,       /* IORDY supported */
 214         Msoftrst        = 0x1000,       /* needs soft reset when Bsy */
 215         Mqueueing       = 0x4000,       /* queueing overlap supported */
 216         Midma           = 0x8000,       /* interleaved DMA supported */
 217 };
 218
 219 enum {                                  /* bit masks for supported/enabled features */
 220         Msmart          = 0x0001,
 221         Msecurity       = 0x0002,
 222         Mrmmedia        = 0x0004,
 223         Mpwrmgmt        = 0x0008,
 224         Mpkt            = 0x0010,
 225         Mwcache         = 0x0020,
 226         Mlookahead      = 0x0040,
 227         Mrelirq         = 0x0080,
 228         Msvcirq         = 0x0100,
 229         Mreset          = 0x0200,
 230         Mprotected      = 0x0400,
 231         Mwbuf           = 0x1000,
 232         Mrbuf           = 0x2000,
 233         Mnop            = 0x4000,
 234         Mmicrocode      = 0x0001,
 235         Mqueued         = 0x0002,
 236         Mcfa            = 0x0004,
 237         Mapm            = 0x0008,
 238         Mnotify         = 0x0010,
 239         Mspinup         = 0x0040,
 240         Mmaxsec         = 0x0100,
 241         Mautoacoustic   = 0x0200,
 242         Maddr48         = 0x0400,
 243         Mdevconfov      = 0x0800,
 244         Mflush          = 0x1000,
 245         Mflush48        = 0x2000,
 246         Msmarterror     = 0x0001,
 247         Msmartselftest  = 0x0002,
 248         Mmserial        = 0x0004,
 249         Mmpassthru      = 0x0008,
 250         Mlogging        = 0x0020,
 251 };
 252
 253 typedef struct Ctlr Ctlr;
 254 typedef struct Drive Drive;
 255
 256 typedef struct Prd {                    /* Physical Region Descriptor */
 257         ulong   pa;                     /* Physical Base Address */
 258         int     count;
 259 } Prd;
 260
 261 enum {
 262         BMspan          = 32*1024,      /* must be power of 2 <= 64*1024 */
 263
 264         Nprd            = SDmaxio/BMspan+2,
 265 };
 266
 267 typedef struct Ctlr {
 268         int     cmdport;
 269         int     ctlport;
 270         int     irq;
 271         int     tbdf;
 272         int     bmiba;                  /* bus master interface base address */
 273         int     maxio;                  /* sector count transfer maximum */
 274         int     span;                   /* don't span this boundary with dma */
 275         int     maxdma;                 /* don't attempt dma transfers bigger than this */
 276
 277         Pcidev* pcidev;
 278         void    (*ienable)(Ctlr*);
 279         void    (*idisable)(Ctlr*);
 280         SDev*   sdev;
 281
 282         Drive*  drive[2];
 283
 284         Prd*    prdt;                   /* physical region descriptor table */
 285         void    (*irqack)(Ctlr*);
 286
 287         QLock;                          /* current command */
 288         Drive*  curdrive;
 289         int     command;                /* last command issued (debugging) */
 290         Rendez;
 291         int     done;
 292         uint    nrq;
 293         uint    nildrive;
 294         uint    bsy;
 295
 296         Lock;                           /* register access */
 297 } Ctlr;
 298
 299 typedef struct Drive {
 300         Ctlr*   ctlr;
 301         SDunit  *unit;
 302
 303         int     dev;
 304         ushort  info[256];
 305         Sfis;
 306
 307         int     dma;                    /* DMA R/W possible */
 308         int     dmactl;
 309         int     rwm;                    /* read/write multiple possible */
 310         int     rwmctl;
 311
 312         int     pkt;                    /* PACKET device, length of pktcmd */
 313         uchar   pktcmd[16];
 314         int     pktdma;                 /* this PACKET command using dma */
 315
 316         uvlong  sectors;
 317         uint    secsize;
 318         char    serial[20+1];
 319         char    firmware[8+1];
 320         char    model[40+1];
 321
 322         QLock;                          /* drive access */
 323         int     command;                /* current command */
 324         int     write;
 325         uchar*  data;
 326         int     dlen;
 327         uchar*  limit;
 328         int     count;                  /* sectors */
 329         int     block;                  /* R/W bytes per block */
 330         int     status;
 331         int     error;
 332         int     flags;                  /* internal flags */
 333         uint    missirq;
 334         uint    spurloop;
 335         uint    irq;
 336         uint    bsy;
 337 } Drive;
 338
 339 enum {                                  /* internal flags */
 340         Lba48always     = 0x2,          /* ... */
 341         Online          = 0x4,          /* drive onlined */
 342 };
 343
 344 static void
 345 pc87415ienable(Ctlr* ctlr)
 346 {
 347         Pcidev *p;
 348         int x;
 349
 350         p = ctlr->pcidev;
 351         if(p == nil)
 352                 return;
 353
 354         x = pcicfgr32(p, 0x40);
 355         if(ctlr->cmdport == p->mem[0].bar)
 356                 x &= ~0x00000100;
 357         else
 358                 x &= ~0x00000200;
 359         pcicfgw32(p, 0x40, x);
 360 }
 361
 362 static void
 363 atadumpstate(Drive* drive, SDreq *r, uvlong lba, int count)
 364 {
 365         Prd *prd;
 366         Pcidev *p;
 367         Ctlr *ctlr;
 368         int i, bmiba, ccnt;
 369         uvlong clba;
 370
 371         if(!(DEBUG & DbgSTATE))
 372                 return;
 373
 374         ctlr = drive->ctlr;
 375         print("command %2.2uX\n", ctlr->command);
 376         print("data %8.8p limit %8.8p dlen %d status %uX error %uX\n",
 377                 drive->data, drive->limit, drive->dlen,
 378                 drive->status, drive->error);
 379         if(r->clen == -16)
 380                 clba = fisrw(nil, r->cmd, &ccnt);
 381         else
 382                 sdfakescsirw(r, &clba, &ccnt, 0);
 383         print("lba %llud -> %llud, count %d -> %d (%d)\n",
 384                 clba, lba, ccnt, count, drive->count);
 385         if(!(inb(ctlr->ctlport+As) & Bsy)){
 386                 for(i = 1; i < 7; i++)
 387                         print(" 0x%2.2uX", inb(ctlr->cmdport+i));
 388                 print(" 0x%2.2uX\n", inb(ctlr->ctlport+As));
 389         }
 390         if(drive->command == Cwd || drive->command == Crd
 391         || drive->command == (Pdma|Pin) || drive->command == (Pdma|Pout)){
 392                 bmiba = ctlr->bmiba;
 393                 prd = ctlr->prdt;
 394                 print("bmicx %2.2uX bmisx %2.2uX prdt %8.8p\n",
 395                         inb(bmiba+Bmicx), inb(bmiba+Bmisx), prd);
 396                 for(;;){
 397                         print("pa 0x%8.8luX count %8.8uX\n",
 398                                 prd->pa, prd->count);
 399                         if(prd->count & PrdEOT)
 400                                 break;
 401                         prd++;
 402                 }
 403         }
 404         if(ctlr->pcidev && ctlr->pcidev->vid == 0x8086){
 405                 p = ctlr->pcidev;
 406                 print("0x40: %4.4uX 0x42: %4.4uX ",
 407                         pcicfgr16(p, 0x40), pcicfgr16(p, 0x42));
 408                 print("0x48: %2.2uX\n", pcicfgr8(p, 0x48));
 409                 print("0x4A: %4.4uX\n", pcicfgr16(p, 0x4A));
 410         }
 411 }
 412
 413 static void
 414 atadebug(int cmdport, int ctlport, char* fmt, ...)
 415 {
 416         char *p, *e, buf[PRINTSIZE];
 417         int i;
 418         va_list arg;
 419
 420         if(!(DEBUG & DbgPROBE))
 421                 return;
 422
 423         p = buf;
 424         e = buf + sizeof buf;
 425         va_start(arg, fmt);
 426         p = vseprint(p, e, fmt, arg);
 427         va_end(arg);
 428
 429         if(cmdport){
 430                 if(p > buf && p[-1] == '\n')
 431                         p--;
 432                 p = seprint(p, e, " ataregs 0x%uX:", cmdport);
 433                 for(i = Features; i < Command; i++)
 434                         p = seprint(p, e, " 0x%2.2uX", inb(cmdport+i));
 435                 if(ctlport)
 436                         p = seprint(p, e, " 0x%2.2uX", inb(ctlport+As));
 437                 p = seprint(p, e, "\n");
 438         }
 439         putstrn(buf, p - buf);
 440 }
 441
 442 static int
 443 ataready(int cmdport, int ctlport, int dev, int reset, int ready, int m)
 444 {
 445         int as, m0;
 446
 447         atadebug(cmdport, ctlport, "ataready: dev %ux:%ux reset %ux ready %ux",
 448                 cmdport, dev, reset, ready);
 449         m0 = m;
 450         do{
 451                 /*
 452                  * Wait for the controller to become not busy and
 453                  * possibly for a status bit to become true (usually
 454                  * Drdy). Must change to the appropriate device
 455                  * register set if necessary before testing for ready.
 456                  * Always run through the loop at least once so it
 457                  * can be used as a test for !Bsy.
 458                  */
 459                 as = inb(ctlport+As);
 460                 if(as & reset){
 461                         /* nothing to do */
 462                 }
 463                 else if(dev){
 464                         outb(cmdport+Dh, dev);
 465                         dev = 0;
 466                 }
 467                 else if(ready == 0 || (as & ready)){
 468                         atadebug(0, 0, "ataready: %d:%d %#.2ux\n", m, m0, as);
 469                         return as;
 470                 }
 471                 microdelay(1);
 472         }while(m-- > 0);
 473         atadebug(0, 0, "ataready: timeout %d %#.2ux\n", m0, as);
 474         return -1;
 475 }
 476
 477 static int
 478 atadone(void* arg)
 479 {
 480         return ((Ctlr*)arg)->done;
 481 }
 482
 483 static int
 484 atarwmmode(Drive* drive, int cmdport, int ctlport, int dev)
 485 {
 486         int as, maxrwm, rwm;
 487
 488         maxrwm = drive->info[Imaxrwm] & 0xFF;
 489         if(maxrwm == 0)
 490                 return 0;
 491
 492         /*
 493          * Sometimes drives come up with the current count set
 494          * to 0; if so, set a suitable value, otherwise believe
 495          * the value in Irwm if the 0x100 bit is set.
 496          */
 497         if(drive->info[Irwm] & 0x100)
 498                 rwm = drive->info[Irwm] & 0xFF;
 499         else
 500                 rwm = 0;
 501         if(rwm == 0)
 502                 rwm = maxrwm;
 503         if(rwm > 16)
 504                 rwm = 16;
 505         if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 102*1000) < 0)
 506                 return 0;
 507         outb(cmdport+Count, rwm);
 508         outb(cmdport+Command, Csm);
 509         microdelay(1);
 510         as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 1000);
 511         inb(cmdport+Status);
 512         if(as < 0 || (as & (Df|Err)))
 513                 return 0;
 514
 515         drive->rwm = rwm;
 516
 517         return rwm;
 518 }
 519
 520 static int
 521 atadmamode(SDunit *unit, Drive* drive)
 522 {
 523         char buf[32], *s;
 524         int dma;
 525
 526         /*
 527          * Check if any DMA mode enabled.
 528          * Assumes the BIOS has picked and enabled the best.
 529          * This is completely passive at the moment, no attempt is
 530          * made to ensure the hardware is correctly set up.
 531          */
 532         dma = drive->info[Imwdma] & 0x0707;
 533         drive->dma = (dma>>8) & dma;
 534         if(drive->dma == 0 && (drive->info[Ivalid] & 0x04)){
 535                 dma = drive->info[Iudma] & 0x7F7F;
 536                 drive->dma = (dma>>8) & dma;
 537                 if(drive->dma)
 538                         drive->dma |= 'U'<<16;
 539         }
 540         if(unit != nil){
 541                 snprint(buf, sizeof buf, "*%sdma", unit->name);
 542                 s = getconf(buf);
 543                 if((s && !strcmp(s, "on")) || (!s && !getconf("*nodma")))
 544                         drive->dmactl = drive->dma;
 545         }
 546         return dma;
 547 }
 548
 549 static int
 550 ataidentify(Ctlr*, int cmdport, int ctlport, int dev, int pkt, void* info)
 551 {
 552         int as, command, drdy;
 553
 554         if(pkt){
 555                 command = Cidpkt;
 556                 drdy = 0;
 557         }
 558         else{
 559                 command = Cid;
 560                 drdy = Drdy;
 561         }
 562         dev &= ~Lba;
 563         as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
 564         if(as < 0)
 565                 return as;
 566         outb(cmdport+Command, command);
 567         microdelay(1);
 568
 569         as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
 570         if(as < 0)
 571                 return -1;
 572         if(as & Err)
 573                 return as;
 574
 575         memset(info, 0, 512);
 576         inss(cmdport+Data, info, 256);
 577         ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 3*1000);
 578         inb(cmdport+Status);
 579
 580         return 0;
 581 }
 582
 583 static Drive*
 584 atadrive(SDunit *unit, Drive *drive, int cmdport, int ctlport, int dev)
 585 {
 586         int as, pkt;
 587         uchar buf[512], oserial[21];
 588         uvlong osectors;
 589         Ctlr *ctlr;
 590
 591         if(DEBUG & DbgIDENTIFY)
 592                 print("identify: port %ux dev %.2ux\n", cmdport, dev & ~Lba);
 593         atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
 594         pkt = 1;
 595         if(drive != nil){
 596                 osectors = drive->sectors;
 597                 memmove(oserial, drive->serial, sizeof drive->serial);
 598                 ctlr = drive->ctlr;
 599         }else{
 600                 osectors = 0;
 601                 memset(oserial, 0, sizeof drive->serial);
 602                 ctlr = nil;
 603         }
 604 retry:
 605         as = ataidentify(ctlr, cmdport, ctlport, dev, pkt, buf);
 606         if(as < 0)
 607                 return nil;
 608         if(as & Err){
 609                 if(pkt == 0)
 610                         return nil;
 611                 pkt = 0;
 612                 goto retry;
 613         }
 614
 615         if(drive == 0){
 616                 if((drive = malloc(sizeof(Drive))) == nil)
 617                         return nil;
 618                 drive->serial[0] = ' ';
 619                 drive->dev = dev;
 620         }
 621
 622         memmove(drive->info, buf, sizeof(drive->info));
 623
 624         setfissig(drive, pkt? 0xeb140000: 0x0101);
 625         drive->sectors = idfeat(drive, drive->info);
 626         drive->secsize = idss(drive, drive->info);
 627
 628         idmove(drive->serial, drive->info+10, 20);
 629         idmove(drive->firmware, drive->info+23, 8);
 630         idmove(drive->model, drive->info+27, 40);
 631         if(unit != nil){
 632                 memset(unit->inquiry, 0, sizeof unit->inquiry);
 633                 unit->inquiry[2] = 2;
 634                 unit->inquiry[3] = 2;
 635                 unit->inquiry[4] = sizeof unit->inquiry - 4;
 636                 memmove(unit->inquiry+8, drive->model, 40);
 637         }
 638
 639         if(pkt){
 640                 drive->pkt = 12;
 641                 if(drive->feat & Datapi16)
 642                         drive->pkt = 16;
 643         }else{
 644                 drive->pkt = 0;
 645                 if(drive->feat & Dlba)
 646                         drive->dev |= Lba;
 647                 atarwmmode(drive, cmdport, ctlport, dev);
 648         }
 649         atadmamode(unit, drive);
 650
 651         if(osectors != 0 && memcmp(oserial, drive->serial, sizeof oserial) != 0)
 652                 if(unit)
 653                         unit->sectors = 0;
 654         drive->unit = unit;
 655         if(DEBUG & DbgCONFIG){
 656                 print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
 657                         dev, cmdport, drive->info[Iconfig], drive->info[Icapabilities]);
 658                 print(" mwdma %4.4uX", drive->info[Imwdma]);
 659                 if(drive->info[Ivalid] & 0x04)
 660                         print(" udma %4.4uX", drive->info[Iudma]);
 661                 print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
 662                 if(drive->feat&Dllba)
 663                         print("\tLLBA sectors %llud", drive->sectors);
 664                 print("\n");
 665         }
 666
 667         return drive;
 668 }
 669
 670 static void
 671 atasrst(int ctlport)
 672 {
 673         int dc0;
 674
 675         /*
 676          * Srst is a big stick and may cause problems if further
 677          * commands are tried before the drives become ready again.
 678          * Also, there will be problems here if overlapped commands
 679          * are ever supported.
 680          */
 681         dc0 = inb(ctlport+Dc);
 682         microdelay(5);
 683         outb(ctlport+Dc, Srst|dc0);
 684         microdelay(5);
 685         outb(ctlport+Dc, dc0);
 686         microdelay(2*1000);
 687 }
 688
 689 static int
 690 seldev(int dev, int map)
 691 {
 692         if((dev & Devs) == Dev0 && map&1)
 693                 return dev;
 694         if((dev & Devs) == Dev1 && map&2)
 695                 return dev;
 696         return -1;
 697 }
 698
 699 static SDev*
 700 ataprobe(int cmdport, int ctlport, int irq, int map)
 701 {
 702         Ctlr* ctlr;
 703         SDev *sdev;
 704         Drive *drive;
 705         int dev, error, rhi, rlo;
 706         static int nonlegacy = 'C';
 707
 708         if(ioalloc(cmdport, 8, 0, "atacmd") < 0) {
 709                 print("ataprobe: Cannot allocate %X\n", cmdport);
 710                 return nil;
 711         }
 712         if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
 713                 print("ataprobe: Cannot allocate %X\n", ctlport + As);
 714                 iofree(cmdport);
 715                 return nil;
 716         }
 717
 718         /*
 719          * Try to detect a floating bus.
 720          * Bsy should be cleared. If not, see if the cylinder registers
 721          * are read/write capable.
 722          * If the master fails, try the slave to catch slave-only
 723          * configurations.
 724          * There's no need to restore the tested registers as they will
 725          * be reset on any detected drives by the Cedd command.
 726          * All this indicates is that there is at least one drive on the
 727          * controller; when the non-existent drive is selected in a
 728          * single-drive configuration the registers of the existing drive
 729          * are often seen, only command execution fails.
 730          */
 731         if((dev = seldev(Dev0, map)) == -1)
 732         if((dev = seldev(Dev1, map)) == -1)
 733                 goto release;
 734         if(inb(ctlport+As) & Bsy){
 735                 outb(cmdport+Dh, dev);
 736                 microdelay(1);
 737 trydev1:
 738                 atadebug(cmdport, ctlport, "ataprobe bsy");
 739                 outb(cmdport+Cyllo, 0xAA);
 740                 outb(cmdport+Cylhi, 0x55);
 741                 outb(cmdport+Sector, 0xFF);
 742                 rlo = inb(cmdport+Cyllo);
 743                 rhi = inb(cmdport+Cylhi);
 744                 if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55)){
 745                         if(dev == Dev1 || (dev = seldev(Dev1, map)) == -1){
 746 release:
 747                                 outb(cmdport+Dc, Nien);
 748                                 inb(cmdport+Status);
 749                                 /* further measures to prevent irqs? */
 750                                 iofree(cmdport);
 751                                 iofree(ctlport+As);
 752                                 return nil;
 753                         }
 754                         if(ataready(cmdport, ctlport, dev, Bsy, 0, 20*1000) < 0)
 755                                 goto trydev1;
 756                 }
 757         }
 758
 759         /*
 760          * Disable interrupts on any detected controllers.
 761          */
 762         outb(ctlport+Dc, Nien);
 763 tryedd1:
 764         if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 105*1000) < 0){
 765                 /*
 766                  * There's something there, but it didn't come up clean,
 767                  * so try hitting it with a big stick. The timing here is
 768                  * wrong but this is a last-ditch effort and it sometimes
 769                  * gets some marginal hardware back online.
 770                  */
 771                 atasrst(ctlport);
 772                 if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 106*1000) < 0)
 773                         goto release;
 774         }
 775
 776         /*
 777          * Can only get here if controller is not busy.
 778          * If there are drives Bsy will be set within 400nS,
 779          * must wait 2mS before testing Status.
 780          * Wait for the command to complete (6 seconds max).
 781          */
 782         outb(cmdport+Command, Cedd);
 783         delay(2);
 784         if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 6*1000*1000) < 0)
 785                 goto release;
 786
 787         /*
 788          * If bit 0 of the error register is set then the selected drive
 789          * exists. This is enough to detect single-drive configurations.
 790          * However, if the master exists there is no way short of executing
 791          * a command to determine if a slave is present.
 792          * It appears possible to get here testing Dev0 although it doesn't
 793          * exist and the EDD won't take, so try again with Dev1.
 794          */
 795         error = inb(cmdport+Error);
 796         atadebug(cmdport, ctlport, "ataprobe: dev %uX", dev);
 797         if((error & ~0x80) != 0x01){
 798                 if(dev == Dev1)
 799                         goto release;
 800                 if((dev = seldev(Dev1, map)) == -1)
 801                         goto release;
 802                 goto tryedd1;
 803         }
 804
 805         /*
 806          * At least one drive is known to exist, try to
 807          * identify it. If that fails, don't bother checking
 808          * any further.
 809          * If the one drive found is Dev0 and the EDD command
 810          * didn't indicate Dev1 doesn't exist, check for it.
 811          */
 812         if((drive = atadrive(0, 0, cmdport, ctlport, dev)) == nil)
 813                 goto release;
 814         if((ctlr = malloc(sizeof(Ctlr))) == nil){
 815                 free(drive);
 816                 goto release;
 817         }
 818         if((sdev = malloc(sizeof(SDev))) == nil){
 819                 free(ctlr);
 820                 free(drive);
 821                 goto release;
 822         }
 823         drive->ctlr = ctlr;
 824         if(dev == Dev0){
 825                 ctlr->drive[0] = drive;
 826                 if(!(error & 0x80)){
 827                         /*
 828                          * Always leave Dh pointing to a valid drive,
 829                          * otherwise a subsequent call to ataready on
 830                          * this controller may try to test a bogus Status.
 831                          * Ataprobe is the only place possibly invalid
 832                          * drives should be selected.
 833                          */
 834                         drive = atadrive(0, 0, cmdport, ctlport, Dev1);
 835                         if(drive != nil){
 836                                 drive->ctlr = ctlr;
 837                                 ctlr->drive[1] = drive;
 838                         }
 839                         else{
 840                                 outb(cmdport+Dh, Dev0);
 841                                 microdelay(1);
 842                         }
 843                 }
 844         }
 845         else
 846                 ctlr->drive[1] = drive;
 847
 848         ctlr->cmdport = cmdport;
 849         ctlr->ctlport = ctlport;
 850         ctlr->irq = irq;
 851         ctlr->tbdf = BUSUNKNOWN;
 852         ctlr->command = Cedd;           /* debugging */
 853
 854         switch(cmdport){
 855         default:
 856                 sdev->idno = nonlegacy;
 857                 break;
 858         case 0x1F0:
 859                 sdev->idno = 'C';
 860                 nonlegacy = 'E';
 861                 break;
 862         case 0x170:
 863                 sdev->idno = 'D';
 864                 nonlegacy = 'E';
 865                 break;
 866         }
 867         sdev->ifc = &sdideifc;
 868         sdev->ctlr = ctlr;
 869         sdev->nunit = 2;
 870         ctlr->sdev = sdev;
 871
 872         return sdev;
 873 }
 874
 875 static void
 876 ataclear(SDev *sdev)
 877 {
 878         Ctlr* ctlr;
 879
 880         ctlr = sdev->ctlr;
 881         iofree(ctlr->cmdport);
 882         iofree(ctlr->ctlport + As);
 883
 884         if (ctlr->drive[0])
 885                 free(ctlr->drive[0]);
 886         if (ctlr->drive[1])
 887                 free(ctlr->drive[1]);
 888         if (sdev->name)
 889                 free(sdev->name);
 890         if (sdev->unitflg)
 891                 free(sdev->unitflg);
 892         if (sdev->unit)
 893                 free(sdev->unit);
 894         free(ctlr);
 895         free(sdev);
 896 }
 897
 898 static char *
 899 atastat(SDev *sdev, char *p, char *e)
 900 {
 901         Ctlr *ctlr;
 902
 903         ctlr = sdev->ctlr;
 904 //      return seprint(p, e, "%s ata port %X ctl %X irq %d %T\n",
 905 //                  sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq, ctlr->tbdf);
 906         return seprint(p, e, "%s ata port %X ctl %X irq %d\n",
 907                     sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq);
 908 }
 909
 910 static SDev*
 911 ataprobew(DevConf *cf)
 912 {
 913         char *p;
 914         ISAConf isa;
 915
 916         if (cf->nports != 2)
 917                 error(Ebadarg);
 918
 919         memset(&isa, 0, sizeof isa);
 920         isa.port = cf->ports[0].port;
 921         isa.irq = cf->intnum;
 922         if((p=strchr(cf->type, '/')) == nil || pcmspecial(p+1, &isa) < 0)
 923                 error("cannot find controller");
 924
 925         return ataprobe(cf->ports[0].port, cf->ports[1].port, cf->intnum, 3);
 926 }
 927
 928 static void atainterrupt(Ureg*, void*);
 929
 930 static int
 931 iowait(Drive *drive, int ms, int interrupt)
 932 {
 933         int msec, step;
 934         Ctlr *ctlr;
 935
 936         step = 1000;
 937         if(drive->missirq > 10)
 938                 step = 50;
 939         ctlr = drive->ctlr;
 940         for(msec = 0; msec < ms; msec += step){
 941                 while(waserror())
 942                         if(interrupt)
 943                                 return -1;
 944                 tsleep(ctlr, atadone, ctlr, step);
 945                 poperror();
 946                 if(ctlr->done)
 947                         break;
 948                 atainterrupt(nil, ctlr);
 949                 if(ctlr->done){
 950                         if(drive->missirq++ < 3)
 951                                 print("ide: caught missed irq\n");
 952                         break;
 953                 }else
 954                         drive->spurloop++;
 955         }
 956         return ctlr->done;
 957 }
 958
 959 static void
 960 atanop(Drive* drive, int subcommand)
 961 {
 962         Ctlr* ctlr;
 963         int as, cmdport, ctlport, timeo;
 964
 965         /*
 966          * Attempt to abort a command by using NOP.
 967          * In response, the drive is supposed to set Abrt
 968          * in the Error register, set (Drdy|Err) in Status
 969          * and clear Bsy when done. However, some drives
 970          * (e.g. ATAPI Zip) just go Bsy then clear Status
 971          * when done, hence the timeout loop only on Bsy
 972          * and the forced setting of drive->error.
 973          */
 974         ctlr = drive->ctlr;
 975         cmdport = ctlr->cmdport;
 976         outb(cmdport+Features, subcommand);
 977         outb(cmdport+Dh, drive->dev);
 978         ctlr->command = Cnop;           /* debugging */
 979         outb(cmdport+Command, Cnop);
 980
 981         microdelay(1);
 982         ctlport = ctlr->ctlport;
 983         for(timeo = 0; timeo < 1000; timeo++){
 984                 as = inb(ctlport+As);
 985                 if(!(as & Bsy))
 986                         break;
 987                 microdelay(1);
 988         }
 989         drive->error |= Abrt;
 990 }
 991
 992 static void
 993 ataabort(Drive* drive, int dolock)
 994 {
 995         /*
 996          * If NOP is available use it otherwise
 997          * must try a software reset.
 998          */
 999         if(dolock)
1000                 ilock(drive->ctlr);
1001         if(drive->feat & Dnop)
1002                 atanop(drive, 0);
1003         else{
1004                 atasrst(drive->ctlr->ctlport);
1005                 drive->error |= Abrt;
1006         }
1007         if(dolock)
1008                 iunlock(drive->ctlr);
1009 }
1010
1011 static int
1012 atadmasetup(Drive* drive, int len)
1013 {
1014         Prd *prd;
1015         ulong pa;
1016         Ctlr *ctlr;
1017         int bmiba, bmisx, count, i, span;
1018
1019         ctlr = drive->ctlr;
1020         pa = PCIWADDR(drive->data);
1021         if(pa & 0x03)
1022                 return -1;
1023         if(ctlr->maxdma && len > ctlr->maxdma)
1024                 return -1;
1025
1026         /*
1027          * Sometimes drives identify themselves as being DMA capable
1028          * although they are not on a busmastering controller.
1029          */
1030         prd = ctlr->prdt;
1031         if(prd == nil){
1032                 drive->dmactl = 0;
1033                 print("disabling dma: not on a busmastering controller\n");
1034                 return -1;
1035         }
1036
1037         for(i = 0; len && i < Nprd; i++){
1038                 prd->pa = pa;
1039                 span = ROUNDUP(pa, ctlr->span);
1040                 if(span == pa)
1041                         span += ctlr->span;
1042                 count = span - pa;
1043                 if(count >= len){
1044                         prd->count = PrdEOT|len;
1045                         break;
1046                 }
1047                 prd->count = count;
1048                 len -= count;
1049                 pa += count;
1050                 prd++;
1051         }
1052         if(i == Nprd)
1053                 return -1;
1054
1055         bmiba = ctlr->bmiba;
1056         outl(bmiba+Bmidtpx, PCIWADDR(ctlr->prdt));
1057         if(drive->write)
1058                 outb(bmiba+Bmicx, 0);
1059         else
1060                 outb(bmiba+Bmicx, Rwcon);
1061         bmisx = inb(bmiba+Bmisx);
1062         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
1063
1064         return 0;
1065 }
1066
1067 static void
1068 atadmastart(Ctlr* ctlr, int write)
1069 {
1070         if(write)
1071                 outb(ctlr->bmiba+Bmicx, Ssbm);
1072         else
1073                 outb(ctlr->bmiba+Bmicx, Rwcon|Ssbm);
1074 }
1075
1076 static int
1077 atadmastop(Ctlr* ctlr)
1078 {
1079         int bmiba;
1080
1081         bmiba = ctlr->bmiba;
1082         outb(bmiba+Bmicx, inb(bmiba+Bmicx) & ~Ssbm);
1083
1084         return inb(bmiba+Bmisx);
1085 }
1086
1087 static void
1088 atadmainterrupt(Drive* drive, int count)
1089 {
1090         Ctlr* ctlr;
1091         int bmiba, bmisx;
1092
1093         ctlr = drive->ctlr;
1094         bmiba = ctlr->bmiba;
1095         bmisx = inb(bmiba+Bmisx);
1096         switch(bmisx & (Ideints|Idedmae|Bmidea)){
1097         case Bmidea:
1098                 /*
1099                  * Data transfer still in progress, nothing to do
1100                  * (this should never happen).
1101                  */
1102                 return;
1103
1104         case Ideints:
1105         case Ideints|Bmidea:
1106                 /*
1107                  * Normal termination, tidy up.
1108                  */
1109                 drive->data += count;
1110                 break;
1111
1112         default:
1113                 /*
1114                  * What's left are error conditions (memory transfer
1115                  * problem) and the device is not done but the PRD is
1116                  * exhausted. For both cases must somehow tell the
1117                  * drive to abort.
1118                  */
1119                 ataabort(drive, 0);
1120                 break;
1121         }
1122         atadmastop(ctlr);
1123         ctlr->done = 1;
1124 }
1125
1126 static void
1127 atapktinterrupt(Drive* drive)
1128 {
1129         Ctlr* ctlr;
1130         int cmdport, len;
1131
1132         ctlr = drive->ctlr;
1133         cmdport = ctlr->cmdport;
1134         switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
1135         case Cd:
1136                 outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
1137                 break;
1138
1139         case 0:
1140                 if(drive->pktdma)
1141                         goto Pktdma;
1142                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1143                 if(drive->data+len > drive->limit){
1144                         atanop(drive, 0);
1145                         break;
1146                 }
1147                 outss(cmdport+Data, drive->data, len/2);
1148                 drive->data += len;
1149                 break;
1150
1151         case Io:
1152                 if(drive->pktdma)
1153                         goto Pktdma;
1154                 len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
1155                 if(drive->data+len > drive->limit){
1156                         atanop(drive, 0);
1157                         break;
1158                 }
1159                 inss(cmdport+Data, drive->data, len/2);
1160                 drive->data += len;
1161                 break;
1162
1163         case Io|Cd:
1164                 if(drive->pktdma){
1165         Pktdma:
1166                         atadmainterrupt(drive, drive->dlen);
1167                 } else
1168                         ctlr->done = 1;
1169                 break;
1170         }
1171 }
1172
1173 static int
1174 atapktio0(Drive *drive, SDreq *r)
1175 {
1176         uchar *cmd;
1177         int as, cmdport, ctlport, len, rv;
1178         Ctlr *ctlr;
1179
1180         rv = SDok;
1181         cmd = r->cmd;
1182         drive->command = Cpkt;
1183         memmove(drive->pktcmd, cmd, r->clen);
1184         memset(drive->pktcmd+r->clen, 0, drive->pkt-r->clen);
1185         drive->limit = drive->data+drive->dlen;
1186
1187         ctlr = drive->ctlr;
1188         cmdport = ctlr->cmdport;
1189         ctlport = ctlr->ctlport;
1190
1191         as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 107*1000);
1192         /* used to test as&Chk as failure too, but some CD readers use that for media change */
1193         if(as < 0)
1194                 return SDnostatus;
1195
1196         ilock(ctlr);
1197         if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen)){
1198                 drive->pktdma = Dma;
1199                 len = 0;                /* bytecount should be 0 for dma */
1200         }else{
1201                 drive->pktdma = 0;
1202                 if(drive->secsize)
1203                         len = 16*drive->secsize;
1204                 else
1205                         len = 0x8000;
1206         }
1207         outb(cmdport+Features, drive->pktdma);
1208         outb(cmdport+Count, 0);
1209         outb(cmdport+Sector, 0);
1210         outb(cmdport+Bytelo, len);
1211         outb(cmdport+Bytehi, len>>8);
1212         outb(cmdport+Dh, drive->dev);
1213         ctlr->done = 0;
1214         ctlr->curdrive = drive;
1215         ctlr->command = Cpkt;           /* debugging */
1216         outb(cmdport+Command, Cpkt);
1217
1218         if((drive->info[Iconfig] & Mdrq) != 0x0020){
1219                 microdelay(1);
1220                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 4*1000);
1221                 if(as < 0 || (as & (Bsy|Chk))){
1222                         drive->status = as<0 ? 0 : as;
1223                         ctlr->curdrive = nil;
1224                         ctlr->done = 1;
1225                         rv = SDtimeout;
1226                 }else
1227                         atapktinterrupt(drive);
1228         }
1229         if(drive->pktdma)
1230                 atadmastart(ctlr, drive->write);
1231         iunlock(ctlr);
1232
1233         if(iowait(drive, 20*1000, 1) <= 0){
1234                 ilock(ctlr);
1235                 ataabort(drive, 0);
1236         } else
1237                 ilock(ctlr);
1238         if(drive->error){
1239                 if(drive->pktdma)
1240                         atadmastop(ctlr);
1241                 drive->status |= Chk;
1242                 ctlr->curdrive = nil;
1243         }
1244         iunlock(ctlr);
1245
1246         if(drive->status & Chk)
1247                 rv = SDcheck;
1248         return rv;
1249 }
1250
1251 static int
1252 atapktio(Drive* drive, SDreq *r)
1253 {
1254         int n;
1255         Ctlr *ctlr;
1256
1257         ctlr = drive->ctlr;
1258         qlock(ctlr);
1259         n = atapktio0(drive, r);
1260         qunlock(ctlr);
1261         return n;
1262 }
1263
1264 static uchar cmd48[256] = {
1265         [Crs]   Crs48,
1266         [Crd]   Crd48,
1267         [Crsm]  Crsm48,
1268         [Cws]   Cws48,
1269         [Cwd]   Cwd48,
1270         [Cwsm]  Cwsm48,
1271 };
1272
1273 enum{
1274         Last28  = (1<<28) - 1 - 1,
1275 };
1276
1277 static int
1278 atageniostart(Drive* drive, uvlong lba)
1279 {
1280         Ctlr *ctlr;
1281         uchar cmd;
1282         int as, c, cmdport, ctlport, h, len, s, use48;
1283
1284         use48 = 0;
1285         if((drive->flags&Lba48always) || lba > Last28 || drive->count > 256){
1286                 if((drive->feat & Dllba) == 0)
1287                         return -1;
1288                 use48 = 1;
1289                 c = h = s = 0;
1290         }else if(drive->dev & Lba){
1291                 c = (lba>>8) & 0xFFFF;
1292                 h = (lba>>24) & 0x0F;
1293                 s = lba & 0xFF;
1294         }else{
1295                 if (drive->s == 0 || drive->h == 0){
1296                         print("sdide: chs address botch");
1297                         return -1;
1298                 }
1299                 c = lba/(drive->s*drive->h);
1300                 h = (lba/drive->s) % drive->h;
1301                 s = (lba % drive->s) + 1;
1302         }
1303
1304         ctlr = drive->ctlr;
1305         cmdport = ctlr->cmdport;
1306         ctlport = ctlr->ctlport;
1307         if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, Drdy, 101*1000) < 0)
1308                 return -1;
1309
1310         ilock(ctlr);
1311         if(drive->dmactl && !atadmasetup(drive, drive->count*drive->secsize)){
1312                 if(drive->write)
1313                         drive->command = Cwd;
1314                 else
1315                         drive->command = Crd;
1316         }
1317         else if(drive->rwmctl){
1318                 drive->block = drive->rwm*drive->secsize;
1319                 if(drive->write)
1320                         drive->command = Cwsm;
1321                 else
1322                         drive->command = Crsm;
1323         }
1324         else{
1325                 drive->block = drive->secsize;
1326                 if(drive->write)
1327                         drive->command = Cws;
1328                 else
1329                         drive->command = Crs;
1330         }
1331         drive->limit = drive->data + drive->count*drive->secsize;
1332         cmd = drive->command;
1333         if(use48){
1334                 outb(cmdport+Count, drive->count>>8);
1335                 outb(cmdport+Count, drive->count);
1336                 outb(cmdport+Lbalo, lba>>24);
1337                 outb(cmdport+Lbalo, lba);
1338                 outb(cmdport+Lbamid, lba>>32);
1339                 outb(cmdport+Lbamid, lba>>8);
1340                 outb(cmdport+Lbahi, lba>>40);
1341                 outb(cmdport+Lbahi, lba>>16);
1342                 outb(cmdport+Dh, drive->dev|Lba);
1343                 cmd = cmd48[cmd];
1344
1345                 if(DEBUG & Dbg48BIT)
1346                         print("using 48-bit commands\n");
1347         }else{
1348                 outb(cmdport+Count, drive->count);
1349                 outb(cmdport+Sector, s);
1350                 outb(cmdport+Cyllo, c);
1351                 outb(cmdport+Cylhi, c>>8);
1352                 outb(cmdport+Dh, drive->dev|h);
1353         }
1354         ctlr->done = 0;
1355         ctlr->curdrive = drive;
1356         ctlr->command = drive->command; /* debugging */
1357         outb(cmdport+Command, cmd);
1358
1359         switch(drive->command){
1360         case Cws:
1361         case Cwsm:
1362                 microdelay(1);
1363                 /* 10*1000 for flash ide drives - maybe detect them? */
1364                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 10*1000);
1365                 if(as < 0 || (as & Err)){
1366                         iunlock(ctlr);
1367                         return -1;
1368                 }
1369                 len = drive->block;
1370                 if(drive->data+len > drive->limit)
1371                         len = drive->limit-drive->data;
1372                 outss(cmdport+Data, drive->data, len/2);
1373                 break;
1374
1375         case Crd:
1376         case Cwd:
1377                 atadmastart(ctlr, drive->write);
1378                 break;
1379         }
1380         iunlock(ctlr);
1381
1382         return 0;
1383 }
1384
1385 static int
1386 atagenioretry(Drive* drive, SDreq *r, uvlong lba, int count)
1387 {
1388         char *s;
1389         int rv, count0, rw;
1390         uvlong lba0;
1391
1392         if(drive->dmactl){
1393                 drive->dmactl = 0;
1394                 s = "disabling dma";
1395                 rv = SDretry;
1396         }else if(drive->rwmctl){
1397                 drive->rwmctl = 0;
1398                 s = "disabling rwm";
1399                 rv = SDretry;
1400         }else{
1401                 s = "nondma";
1402                 rv = sdsetsense(r, SDcheck, 4, 8, drive->error);
1403         }
1404         sdfakescsirw(r, &lba0, &count0, &rw);
1405         print("atagenioretry: %s %c:%llud:%d @%llud:%d\n",
1406                 s, "rw"[rw], lba0, count0, lba, count);
1407         return rv;
1408 }
1409
1410 static int
1411 atagenio(Drive* drive, SDreq *r)
1412 {
1413         Ctlr *ctlr;
1414         uvlong lba;
1415         int i, rw, count, maxio;
1416
1417         if((i = sdfakescsi(r)) != SDnostatus)
1418                 return i;
1419         if((i = sdfakescsirw(r, &lba, &count, &rw)) != SDnostatus)
1420                 return i;
1421         ctlr = drive->ctlr;
1422         if(drive->data == nil)
1423                 return SDok;
1424         if(drive->dlen < count*drive->secsize)
1425                 count = drive->dlen/drive->secsize;
1426         qlock(ctlr);
1427         if(ctlr->maxio)
1428                 maxio = ctlr->maxio;
1429         else if(drive->feat & Dllba)
1430                 maxio = 65536;
1431         else
1432                 maxio = 256;
1433         while(count){
1434                 if(count > maxio)
1435                         drive->count = maxio;
1436                 else
1437                         drive->count = count;
1438                 if(atageniostart(drive, lba)){
1439                         ilock(ctlr);
1440                         atanop(drive, 0);
1441                         iunlock(ctlr);
1442                         qunlock(ctlr);
1443                         return atagenioretry(drive, r, lba, count);
1444                 }
1445                 iowait(drive, 60*1000, 0);
1446                 if(!ctlr->done){
1447                         /*
1448                          * What should the above timeout be? In
1449                          * standby and sleep modes it could take as
1450                          * long as 30 seconds for a drive to respond.
1451                          * Very hard to get out of this cleanly.
1452                          */
1453                         atadumpstate(drive, r, lba, count);
1454                         ataabort(drive, 1);
1455                         qunlock(ctlr);
1456                         return atagenioretry(drive, r, lba, count);
1457                 }
1458
1459                 if(drive->status & Err){
1460                         qunlock(ctlr);
1461                         print("atagenio: %llud:%d\n", lba, drive->count);
1462                         return sdsetsense(r, SDcheck, 4, 8, drive->error);
1463                 }
1464                 count -= drive->count;
1465                 lba += drive->count;
1466         }
1467         qunlock(ctlr);
1468
1469         return SDok;
1470 }
1471
1472 static int
1473 atario(SDreq* r)
1474 {
1475         uchar *p;
1476         int status;
1477         Ctlr *ctlr;
1478         Drive *drive;
1479         SDunit *unit;
1480
1481         unit = r->unit;
1482         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil){
1483                 r->status = SDtimeout;
1484                 return SDtimeout;
1485         }
1486         drive = ctlr->drive[unit->subno];
1487         qlock(drive);
1488         for(;;){
1489                 drive->write = r->write;
1490                 drive->data = r->data;
1491                 drive->dlen = r->dlen;
1492                 drive->status = 0;
1493                 drive->error = 0;
1494                 if(drive->pkt)
1495                         status = atapktio(drive, r);
1496                 else
1497                         status = atagenio(drive, r);
1498                 if(status != SDretry)
1499                         break;
1500                 if(DbgDEBUG)
1501                         print("%s: retry: dma %8.8uX rwm %4.4uX\n",
1502                                 unit->name, drive->dmactl, drive->rwmctl);
1503         }
1504         if(status == SDok && r->rlen == 0 && (r->flags & SDvalidsense) == 0){
1505                 sdsetsense(r, SDok, 0, 0, 0);
1506                 if(drive->data){
1507                         p = r->data;
1508                         r->rlen = drive->data - p;
1509                 }
1510                 else
1511                         r->rlen = 0;
1512         }
1513         qunlock(drive);
1514         return status;
1515 }
1516
1517 /**/
1518 static int
1519 isdmacmd(Drive *d, SDreq *r)
1520 {
1521         switch(r->ataproto & Pprotom){
1522         default:
1523                 return 0;
1524         case Pdmq:
1525                 error("no queued support");
1526         case Pdma:
1527                 if(!(d->dmactl || d->rwmctl))
1528                         error("dma in non dma mode\n");
1529                 return 1;
1530         }
1531 }
1532
1533 static int
1534 atagenatastart(Drive* d, SDreq *r)
1535 {
1536         uchar u;
1537         int as, cmdport, ctlport, len, pr, isdma;
1538         Ctlr *ctlr;
1539
1540         isdma = isdmacmd(d, r);
1541         ctlr = d->ctlr;
1542         cmdport = ctlr->cmdport;
1543         ctlport = ctlr->ctlport;
1544         if(ataready(cmdport, ctlport, d->dev, Bsy|Drq, d->pkt? 0: Drdy, 101*1000) < 0)
1545                 return -1;
1546
1547         ilock(ctlr);
1548         if(isdma && atadmasetup(d, d->block)){
1549                 iunlock(ctlr);
1550                 return -1;
1551
1552         }
1553         if(d->feat & Dllba && (r->ataproto & P28) == 0){
1554                 outb(cmdport+Features, r->cmd[Ffeat8]);
1555                 outb(cmdport+Features, r->cmd[Ffeat]);
1556                 outb(cmdport+Count, r->cmd[Fsc8]);
1557                 outb(cmdport+Count, r->cmd[Fsc]);
1558                 outb(cmdport+Lbalo, r->cmd[Flba24]);
1559                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1560                 outb(cmdport+Lbamid, r->cmd[Flba32]);
1561                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1562                 outb(cmdport+Lbahi, r->cmd[Flba40]);
1563                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1564                 u = r->cmd[Fdev] & ~0xb0;
1565                 outb(cmdport+Dh, d->dev|u);
1566         }else{
1567                 outb(cmdport+Features, r->cmd[Ffeat]);
1568                 outb(cmdport+Count, r->cmd[Fsc]);
1569                 outb(cmdport+Lbalo, r->cmd[Flba0]);
1570                 outb(cmdport+Lbamid, r->cmd[Flba8]);
1571                 outb(cmdport+Lbahi, r->cmd[Flba16]);
1572                 u = r->cmd[Fdev] & ~0xb0;
1573                 outb(cmdport+Dh, d->dev|u);
1574         }
1575         ctlr->done = 0;
1576         ctlr->curdrive = d;
1577         d->command = r->ataproto & (Pprotom|Pdatam);
1578         ctlr->command = r->cmd[Fcmd];
1579         outb(cmdport+Command, r->cmd[Fcmd]);
1580
1581         pr = r->ataproto & Pprotom;
1582         if(pr == Pnd || pr == Preset)
1583                 USED(d);
1584         else if(!isdma){
1585                 microdelay(1);
1586                 /* 10*1000 for flash ide drives - maybe detect them? */
1587                 as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 10*1000);
1588                 if(as < 0 || (as & Err)){
1589                         iunlock(ctlr);
1590                         return -1;
1591                 }
1592                 len = d->block;
1593                 if(r->write && len > 0)
1594                         outss(cmdport+Data, d->data, len/2);
1595         }else
1596                 atadmastart(ctlr, d->write);
1597         iunlock(ctlr);
1598         return 0;
1599 }
1600
1601 static void
1602 mkrfis(Drive *d, SDreq *r)
1603 {
1604         uchar *u;
1605         int cmdport;
1606         Ctlr *ctlr;
1607
1608         ctlr = d->ctlr;
1609         cmdport = ctlr->cmdport;
1610         u = r->cmd;
1611
1612         ilock(ctlr);
1613         u[Ftype] = 0x34;
1614         u[Fioport] = 0;
1615         if((d->feat & Dllba) && (r->ataproto & P28) == 0){
1616                 u[Frerror] = inb(cmdport+Error);
1617                 u[Fsc8] = inb(cmdport+Count);
1618                 u[Fsc] = inb(cmdport+Count);
1619                 u[Flba24] = inb(cmdport+Lbalo);
1620                 u[Flba0] = inb(cmdport+Lbalo);
1621                 u[Flba32] = inb(cmdport+Lbamid);
1622                 u[Flba8] = inb(cmdport+Lbamid);
1623                 u[Flba40] = inb(cmdport+Lbahi);
1624                 u[Flba16] = inb(cmdport+Lbahi);
1625                 u[Fdev] = inb(cmdport+Dh);
1626                 u[Fstatus] = inb(cmdport+Status);
1627         }else{
1628                 u[Frerror] = inb(cmdport+Error);
1629                 u[Fsc] = inb(cmdport+Count);
1630                 u[Flba0] = inb(cmdport+Lbalo);
1631                 u[Flba8] = inb(cmdport+Lbamid);
1632                 u[Flba16] = inb(cmdport+Lbahi);
1633                 u[Fdev] = inb(cmdport+Dh);
1634                 u[Fstatus] = inb(cmdport+Status);
1635         }
1636         iunlock(ctlr);
1637 }
1638
1639 static int
1640 atarstdone(Drive *d)
1641 {
1642         int as;
1643         Ctlr *c;
1644
1645         c = d->ctlr;
1646         as = ataready(c->cmdport, c->ctlport, 0, Bsy|Drq, 0, 5*1000);
1647         c->done = as >= 0;
1648         return c->done;
1649 }
1650
1651 static uint
1652 cmdss(Drive *d, SDreq *r)
1653 {
1654         switch(r->cmd[Fcmd]){
1655         case Cid:
1656         case Cidpkt:
1657                 return 512;
1658         default:
1659                 return d->secsize;
1660         }
1661 }
1662
1663 /*
1664  * various checks.  we should be craftier and
1665  * avoid figuring out how big stuff is supposed to be.
1666  */
1667 static uint
1668 patasizeck(Drive *d, SDreq *r)
1669 {
1670         uint count, maxio, secsize;
1671         Ctlr *ctlr;
1672
1673         secsize = cmdss(d, r);          /* BOTCH */
1674         if(secsize == 0)
1675                 error(Eio);
1676         count = r->dlen / secsize;
1677         ctlr = d->ctlr;
1678         if(ctlr->maxio)
1679                 maxio = ctlr->maxio;
1680         else if((d->feat & Dllba) && (r->ataproto & P28) == 0)
1681                 maxio = 65536;
1682         else
1683                 maxio = 256;
1684         if(count > maxio){
1685                 uprint("i/o too large, lim %d", maxio);
1686                 error(up->genbuf);
1687         }
1688         if(r->ataproto&Ppio && count > 1)
1689                 error("invalid # of sectors");
1690         return count;
1691 }
1692
1693 static int
1694 atapataio(Drive *d, SDreq *r)
1695 {
1696         int rv;
1697         Ctlr *ctlr;
1698
1699         d->count = 0;
1700         if(r->ataproto & Pdatam)
1701                 d->count = patasizeck(d, r);
1702         d->block = r->dlen;
1703         d->limit = d->data + r->dlen;
1704
1705         ctlr = d->ctlr;
1706         qlock(ctlr);
1707         if(waserror()){
1708                 qunlock(ctlr);
1709                 nexterror();
1710         }
1711         rv = atagenatastart(d, r);
1712         poperror();
1713         if(rv){
1714                 if(DEBUG & DbgAtazz)
1715                         print("sdide: !atageatastart\n");
1716                 ilock(ctlr);
1717                 atanop(d, 0);
1718                 iunlock(ctlr);
1719                 qunlock(ctlr);
1720                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1721         }
1722
1723         if((r->ataproto & Pprotom) == Preset)
1724                 atarstdone(d);
1725         else
1726                 while(iowait(d, 30*1000, 1) == 0)
1727                         ;
1728         if(!ctlr->done){
1729                 if(DEBUG & DbgAtazz){
1730                         print("sdide: !done\n");
1731                         atadumpstate(d, r, 0, d->count);
1732                 }
1733                 ataabort(d, 1);
1734                 qunlock(ctlr);
1735                 return sdsetsense(r, SDcheck, 11, 0, 6);        /* aborted; i/o process terminated */
1736         }
1737         mkrfis(d, r);
1738         if(d->status & Err){
1739                 if(DEBUG & DbgAtazz)
1740                         print("sdide: status&Err\n");
1741                 qunlock(ctlr);
1742                 return sdsetsense(r, SDcheck, 4, 8, d->error);
1743         }
1744         qunlock(ctlr);
1745         return SDok;
1746 }
1747
1748 static int
1749 ataataio0(Drive *d, SDreq *r)
1750 {
1751         int i;
1752
1753         if((r->ataproto & Pprotom) == Ppkt){
1754                 if(r->clen > d->pkt)
1755                         error(Eio);
1756                 qlock(d->ctlr);
1757                 i = atapktio0(d, r);
1758                 d->block = d->data - (uchar*)r->data;
1759                 mkrfis(d, r);
1760                 qunlock(d->ctlr);
1761                 return i;
1762         }else
1763                 return atapataio(d, r);
1764 }
1765
1766 /*
1767  * hack to allow udma mode to be set or unset
1768  * via direct ata command.  it would be better
1769  * to move the assumptions about dma mode out
1770  * of some of the helper functions.
1771  */
1772 static int
1773 isudm(SDreq *r)
1774 {
1775         uchar *c;
1776
1777         c = r->cmd;
1778         if(c[Fcmd] == 0xef && c[Ffeat] == 0x03){
1779                 if(c[Fsc]&0x40)
1780                         return 1;
1781                 return -1;
1782         }
1783         return 0;
1784 }
1785
1786 static int
1787 fisreqchk(Sfis *f, SDreq *r)
1788 {
1789         if((r->ataproto & Pprotom) == Ppkt)
1790                 return SDnostatus;
1791         /*
1792          * handle oob requests;
1793          *    restrict & sanitize commands
1794          */
1795         if(r->clen != 16)
1796                 error(Eio);
1797         if(r->cmd[0] == 0xf0){
1798                 sigtofis(f, r->cmd);
1799                 r->status = SDok;
1800                 return SDok;
1801         }
1802         r->cmd[0] = 0x27;
1803         r->cmd[1] = 0x80;
1804         r->cmd[7] |= 0xa0;
1805         return SDnostatus;
1806 }
1807
1808 static int
1809 ataataio(SDreq *r)
1810 {
1811         int status, udm;
1812         Ctlr *c;
1813         Drive *d;
1814         SDunit *u;
1815
1816         u = r->unit;
1817         if((c = u->dev->ctlr) == nil || (d = c->drive[u->subno]) == nil){
1818                 r->status = SDtimeout;
1819                 return SDtimeout;
1820         }
1821         if((status = fisreqchk(d, r)) != SDnostatus)
1822                 return status;
1823         udm = isudm(r);
1824
1825         qlock(d);
1826         if(waserror()){
1827                 qunlock(d);
1828                 nexterror();
1829         }
1830 retry:
1831         d->write = r->write;
1832         d->data = r->data;
1833         d->dlen = r->dlen;
1834         d->status = 0;
1835         d->error = 0;
1836
1837         switch(status = ataataio0(d, r)){
1838         case SDretry:
1839                 if(DbgDEBUG)
1840                         print("%s: retry: dma %.8ux rwm %.4ux\n",
1841                                 u->name, d->dmactl, d->rwmctl);
1842                 goto retry;
1843         case SDok:
1844                 if(udm == 1)
1845                         d->dmactl = d->dma;
1846                 else if(udm == -1)
1847                         d->dmactl = 0;
1848                 sdsetsense(r, SDok, 0, 0, 0);
1849                 r->rlen = d->block;
1850                 break;
1851         }
1852         poperror();
1853         qunlock(d);
1854         r->status = status;
1855         return status;
1856 }
1857 /**/
1858
1859 static void
1860 ichirqack(Ctlr *ctlr)
1861 {
1862         int bmiba;
1863
1864         if(bmiba = ctlr->bmiba)
1865                 outb(bmiba+Bmisx, inb(bmiba+Bmisx));
1866 }
1867
1868 static void
1869 atainterrupt(Ureg*, void* arg)
1870 {
1871         Ctlr *ctlr;
1872         Drive *drive;
1873         int cmdport, len, status;
1874
1875         ctlr = arg;
1876
1877         ilock(ctlr);
1878         ctlr->nrq++;
1879         if(ctlr->curdrive)
1880                 ctlr->curdrive->irq++;
1881         if(inb(ctlr->ctlport+As) & Bsy){
1882                 ctlr->bsy++;
1883                 if(ctlr->curdrive)
1884                         ctlr->curdrive->bsy++;
1885                 iunlock(ctlr);
1886                 if(DEBUG & DbgBsy)
1887                         print("IBsy+");
1888                 return;
1889         }
1890         cmdport = ctlr->cmdport;
1891         status = inb(cmdport+Status);
1892         if((drive = ctlr->curdrive) == nil){
1893                 ctlr->nildrive++;
1894                 if(ctlr->irqack != nil)
1895                         ctlr->irqack(ctlr);
1896                 iunlock(ctlr);
1897                 if((DEBUG & DbgINL) && ctlr->command != Cedd)
1898                         print("Inil%2.2uX+", ctlr->command);
1899                 return;
1900         }
1901
1902         if(status & Err)
1903                 drive->error = inb(cmdport+Error);
1904         else switch(drive->command){
1905         default:
1906                 drive->error = Abrt;
1907                 break;
1908
1909         case Crs:
1910         case Crsm:
1911         case Ppio|Pin:
1912                 if(!(status & Drq)){
1913                         drive->error = Abrt;
1914                         break;
1915                 }
1916                 len = drive->block;
1917                 if(drive->data+len > drive->limit)
1918                         len = drive->limit-drive->data;
1919                 inss(cmdport+Data, drive->data, len/2);
1920                 drive->data += len;
1921                 if(drive->data >= drive->limit)
1922                         ctlr->done = 1;
1923                 break;
1924
1925         case Cws:
1926         case Cwsm:
1927         case Ppio|Pout:
1928                 len = drive->block;
1929                 if(drive->data+len > drive->limit)
1930                         len = drive->limit-drive->data;
1931                 drive->data += len;
1932                 if(drive->data >= drive->limit){
1933                         ctlr->done = 1;
1934                         break;
1935                 }
1936                 if(!(status & Drq)){
1937                         drive->error = Abrt;
1938                         break;
1939                 }
1940                 len = drive->block;
1941                 if(drive->data+len > drive->limit)
1942                         len = drive->limit-drive->data;
1943                 outss(cmdport+Data, drive->data, len/2);
1944                 break;
1945
1946         case Cpkt:
1947         case Ppkt|Pin:
1948         case Ppkt|Pout:
1949                 atapktinterrupt(drive);
1950                 break;
1951
1952         case Crd:
1953         case Cwd:
1954         case Pdma|Pin:
1955         case Pdma|Pout:
1956                 atadmainterrupt(drive, drive->count*drive->secsize);
1957                 break;
1958
1959         case Pnd:
1960         case Preset:
1961                 ctlr->done = 1;
1962                 break;
1963         }
1964         if(ctlr->irqack != nil)
1965                 ctlr->irqack(ctlr);
1966         iunlock(ctlr);
1967
1968         if(drive->error){
1969                 status |= Err;
1970                 ctlr->done = 1;
1971         }
1972
1973         if(ctlr->done){
1974                 ctlr->curdrive = nil;
1975                 drive->status = status;
1976                 wakeup(ctlr);
1977         }
1978 }
1979
1980 typedef struct Lchan Lchan;
1981 struct Lchan {
1982         int     cmdport;
1983         int     ctlport;
1984         int     irq;
1985         int     probed;
1986 };
1987 static Lchan lchan[2] = {
1988         0x1f0,  0x3f4,  IrqATA0,        0,
1989         0x170,  0x374,  IrqATA1,        0,
1990 };
1991
1992 static int
1993 badccru(Pcidev *p)
1994 {
1995         switch(p->did<<16 | p->did){
1996         case 0x439c<<16 | 0x1002:
1997         case 0x438c<<16 | 0x1002:
1998 print("hi, anothy\n");
1999 print("%T: allowing bad ccru %.2ux for suspected ide controller\n", p->tbdf, p->ccru);
2000                 return 1;
2001         default:
2002                 return 0;
2003         }
2004 }
2005
2006 static SDev*
2007 atapnp(void)
2008 {
2009         char *s;
2010         int channel, map, ispc87415, maxio, pi, r, span, maxdma, tbdf;
2011         Ctlr *ctlr;
2012         Pcidev *p;
2013         SDev *sdev, *head, *tail;
2014         void (*irqack)(Ctlr*);
2015
2016         head = tail = nil;
2017         for(p = nil; p = pcimatch(p, 0, 0); ){
2018                 /*
2019                  * Look for devices with the correct class and sub-class
2020                  * code and known device and vendor ID; add native-mode
2021                  * channels to the list to be probed, save info for the
2022                  * compatibility mode channels.
2023                  * Note that the legacy devices should not be considered
2024                  * PCI devices by the interrupt controller.
2025                  * For both native and legacy, save info for busmastering
2026                  * if capable.
2027                  * Promise Ultra ATA/66 (PDC20262) appears to
2028                  * 1) give a sub-class of 'other mass storage controller'
2029                  *    instead of 'IDE controller', regardless of whether it's
2030                  *    the only controller or not;
2031                  * 2) put 0 in the programming interface byte (probably
2032                  *    as a consequence of 1) above).
2033                  * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
2034                  */
2035                 if(p->ccrb != 0x01)
2036                         continue;
2037                 if(!badccru(p))
2038                 if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
2039                         continue;
2040                 pi = p->ccrp;
2041                 map = 3;
2042                 ispc87415 = 0;
2043                 maxdma = 0;
2044                 maxio = 0;
2045                 if(s = getconf("*idemaxio"))
2046                         maxio = atoi(s);
2047                 span = BMspan;
2048                 irqack = nil;
2049
2050                 switch((p->did<<16)|p->vid){
2051                 default:
2052                         continue;
2053
2054                 case (0x0002<<16)|0x100B:       /* NS PC87415 */
2055                         /*
2056                          * Disable interrupts on both channels until
2057                          * after they are probed for drives.
2058                          * This must be called before interrupts are
2059                          * enabled because the IRQ may be shared.
2060                          */
2061                         ispc87415 = 1;
2062                         pcicfgw32(p, 0x40, 0x00000300);
2063                         break;
2064                 case (0x1000<<16)|0x1042:       /* PC-Tech RZ1000 */
2065                         /*
2066                          * Turn off prefetch. Overkill, but cheap.
2067                          */
2068                         r = pcicfgr32(p, 0x40);
2069                         r &= ~0x2000;
2070                         pcicfgw32(p, 0x40, r);
2071                         break;
2072                 case (0x4D38<<16)|0x105A:       /* Promise PDC20262 */
2073                 case (0x4D30<<16)|0x105A:       /* Promise PDC202xx */
2074                 case (0x4D68<<16)|0x105A:       /* Promise PDC20268 */
2075                 case (0x4D69<<16)|0x105A:       /* Promise Ultra/133 TX2 */
2076                 case (0x3373<<16)|0x105A:       /* Promise 20378 RAID */
2077                 case (0x3149<<16)|0x1106:       /* VIA VT8237 SATA/RAID */
2078                 case (0x3112<<16)|0x1095:       /* SiL 3112 SATA/RAID */
2079                         maxio = 15;
2080                         span = 8*1024;
2081                         /*FALLTHROUGH*/
2082                 case (0x3114<<16)|0x1095:       /* SiL 3114 SATA/RAID */
2083                 case (0x0680<<16)|0x1095:       /* SiI 0680/680A PATA133 ATAPI/RAID */
2084                         pi = 0x85;
2085                         break;
2086                 case (0x0004<<16)|0x1103:       /* HighPoint HPT366 */
2087                         pi = 0x85;
2088                         /*
2089                          * Turn off fast interrupt prediction.
2090                          */
2091                         if((r = pcicfgr8(p, 0x51)) & 0x80)
2092                                 pcicfgw8(p, 0x51, r & ~0x80);
2093                         if((r = pcicfgr8(p, 0x55)) & 0x80)
2094                                 pcicfgw8(p, 0x55, r & ~0x80);
2095                         break;
2096                 case (0x0640<<16)|0x1095:       /* CMD 640B */
2097                         /*
2098                          * Bugfix code here...
2099                          */
2100                         break;
2101                 case (0x7441<<16)|0x1022:       /* AMD 768 */
2102                         /*
2103                          * Set:
2104                          *      0x41    prefetch, postwrite;
2105                          *      0x43    FIFO configuration 1/2 and 1/2;
2106                          *      0x44    status register read retry;
2107                          *      0x46    DMA read and end of sector flush.
2108                          */
2109                         r = pcicfgr8(p, 0x41);
2110                         pcicfgw8(p, 0x41, r|0xF0);
2111                         r = pcicfgr8(p, 0x43);
2112                         pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
2113                         r = pcicfgr8(p, 0x44);
2114                         pcicfgw8(p, 0x44, r|0x08);
2115                         r = pcicfgr8(p, 0x46);
2116                         pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
2117                         /*FALLTHROUGH*/
2118                 case (0x01BC<<16)|0x10DE:       /* nVidia nForce1 */
2119                 case (0x0065<<16)|0x10DE:       /* nVidia nForce2 */
2120                 case (0x0085<<16)|0x10DE:       /* nVidia nForce2 MCP */
2121                 case (0x00E3<<16)|0x10DE:       /* nVidia nForce2 250 SATA */
2122                 case (0x00D5<<16)|0x10DE:       /* nVidia nForce3 */
2123                 case (0x00E5<<16)|0x10DE:       /* nVidia nForce3 Pro */
2124                 case (0x00EE<<16)|0x10DE:       /* nVidia nForce3 250 SATA */
2125                 case (0x0035<<16)|0x10DE:       /* nVidia nForce3 MCP */
2126                 case (0x0053<<16)|0x10DE:       /* nVidia nForce4 */
2127                 case (0x0054<<16)|0x10DE:       /* nVidia nForce4 SATA */
2128                 case (0x0055<<16)|0x10DE:       /* nVidia nForce4 SATA */
2129                 case (0x0266<<16)|0x10DE:       /* nVidia nForce4 430 SATA */
2130                 case (0x0265<<16)|0x10DE:       /* nVidia nForce 51 MCP */
2131                 case (0x0267<<16)|0x10DE:       /* nVidia nForce 55 MCP SATA */
2132                 case (0x03ec<<16)|0x10DE:       /* nVidia nForce 61 MCP SATA */
2133                 case (0x03f6<<16)|0x10DE:       /* nVidia nForce 61 MCP PATA */
2134                 case (0x0448<<16)|0x10DE:       /* nVidia nForce 65 MCP SATA */
2135                 case (0x0560<<16)|0x10DE:       /* nVidia nForce 69 MCP SATA */
2136                         /*
2137                          * Ditto, although it may have a different base
2138                          * address for the registers (0x50?).
2139                          */
2140                         /*FALLTHROUGH*/
2141                 case (0x209A<<16)|0x1022:       /* AMD CS5536 */
2142                 case (0x7401<<16)|0x1022:       /* AMD 755 Cobra */
2143                 case (0x7409<<16)|0x1022:       /* AMD 756 Viper */
2144                 case (0x7410<<16)|0x1022:       /* AMD 766 Viper Plus */
2145                 case (0x7469<<16)|0x1022:       /* AMD 3111 */
2146                 case (0x4376<<16)|0x1002:       /* SB4xx pata */
2147                 case (0x4379<<16)|0x1002:       /* SB4xx sata */
2148                 case (0x437a<<16)|0x1002:       /* SB4xx sata ctlr #2 */
2149                 case (0x437c<<16)|0x1002:       /* Rx6xx pata */
2150                 case (0x438c<<16)|0x1002:       /* ATI SB600 PATA */
2151                 case (0x439c<<16)|0x1002:       /* SB7xx pata */
2152                         break;
2153                 case (0x0211<<16)|0x1166:       /* ServerWorks IB6566 */
2154                         {
2155                                 Pcidev *sb;
2156
2157                                 sb = pcimatch(nil, 0x1166, 0x0200);
2158                                 if(sb == nil)
2159                                         break;
2160                                 r = pcicfgr32(sb, 0x64);
2161                                 r &= ~0x2000;
2162                                 pcicfgw32(sb, 0x64, r);
2163                         }
2164                         span = 32*1024;
2165                         break;
2166                 case (0x5229<<16)|0x10B9:       /* ALi M1543 */
2167                 case (0x5288<<16)|0x10B9:       /* ALi M5288 SATA */
2168                         /*FALLTHROUGH*/
2169                 case (0x5513<<16)|0x1039:       /* SiS 962 */
2170                 case (0x0646<<16)|0x1095:       /* CMD 646 */
2171                 case (0x0571<<16)|0x1106:       /* VIA 82C686 */
2172                 case (0x9001<<16)|0x1106:       /* VIA chipset in VIA PV530 */
2173                 case (0x0502<<16)|0x100b:       /* National Semiconductor SC1100/SCx200 */
2174                         break;
2175                 case (0x2360<<16)|0x197b:       /* jmicron jmb360 */
2176                 case (0x2361<<16)|0x197b:       /* jmicron jmb361 */
2177                 case (0x2363<<16)|0x197b:       /* jmicron jmb363 */
2178                 case (0x2365<<16)|0x197b:       /* jmicron jmb365 */
2179                 case (0x2366<<16)|0x197b:       /* jmicron jmb366 */
2180                 case (0x2368<<16)|0x197b:       /* jmicron jmb368 */
2181                         break;
2182                 case (0x7010<<16)|0x8086:       /* 82371SB (PIIX3) */
2183                 case (0x1230<<16)|0x8086:       /* 82371FB (PIIX) */
2184                 case (0x7111<<16)|0x8086:       /* 82371[AE]B (PIIX4[E]) */
2185                         maxdma = 0x20000;
2186                         break;
2187                 case (0x2411<<16)|0x8086:       /* 82801AA (ICH) */
2188                 case (0x2421<<16)|0x8086:       /* 82801AB (ICH0) */
2189                 case (0x244A<<16)|0x8086:       /* 82801BA (ICH2, Mobile) */
2190                 case (0x244B<<16)|0x8086:       /* 82801BA (ICH2, High-End) */
2191                 case (0x248A<<16)|0x8086:       /* 82801CA (ICH3, Mobile) */
2192                 case (0x248B<<16)|0x8086:       /* 82801CA (ICH3, High-End) */
2193                 case (0x24CA<<16)|0x8086:       /* 82801DBM (ICH4, Mobile) */
2194                 case (0x24CB<<16)|0x8086:       /* 82801DB (ICH4, High-End) */
2195                 case (0x24D1<<16)|0x8086:       /* 82801er (ich5) */
2196                 case (0x24DB<<16)|0x8086:       /* 82801EB (ICH5) */
2197                 case (0x25A2<<16)|0x8086:       /* 6300ESB pata */
2198                 case (0x25A3<<16)|0x8086:       /* 6300ESB (E7210) */
2199                 case (0x266F<<16)|0x8086:       /* 82801FB (ICH6) */
2200                 case (0x2653<<16)|0x8086:       /* 82801FBM (ICH6, Mobile) */
2201                 case (0x269e<<16)|0x8086:       /* 63xxESB (intel 5000) */
2202                 case (0x27DF<<16)|0x8086:       /* 82801G PATA (ICH7) */
2203                 case (0x27C0<<16)|0x8086:       /* 82801GB SATA (ICH7) */
2204                 case (0x27C4<<16)|0x8086:       /* 82801GBM SATA (ICH7) */
2205                 case (0x27C5<<16)|0x8086:       /* 82801GBM SATA AHCI (ICH7) */
2206                 case (0x2850<<16)|0x8086:       /* 82801HBM/HEM PATA */
2207                 case (0x2820<<16)|0x8086:       /* 82801HB/HR/HH/HO SATA IDE */
2208                 case (0x2828<<16)|0x8086:       /* 82801HBM SATA (ICH8-M) */
2209                 case (0x2829<<16)|0x8086:       /* 82801HBM SATA AHCI (ICH8-M) */
2210                 case (0x2920<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-3 */
2211                 case (0x2921<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-1 */
2212                 case (0x2926<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9) port 4-5 */
2213                 case (0x2928<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1 */
2214                 case (0x2929<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 0-1, 4-5 */
2215                 case (0x292d<<16)|0x8086:       /* 82801(IB)/IR/IH/IO SATA (ICH9m) port 4-5*/
2216                 case (0x3a20<<16)|0x8086:       /* 82801ji (ich10) */
2217                 case (0x3a26<<16)|0x8086:       /* 82801ji (ich10) */
2218                 case (0x3b20<<16)|0x8086:       /* 34x0 (pch) port 0-3 */
2219                 case (0x3b21<<16)|0x8086:       /* 34x0 (pch) port 4-5 */
2220                 case (0x3b28<<16)|0x8086:       /* 34x0pm (pch) port 0-1, 4-5 */
2221                 case (0x3b2e<<16)|0x8086:       /* 34x0pm (pch) port 0-3 */
2222                         map = 0;
2223                         if(pcicfgr16(p, 0x40) & 0x8000)
2224                                 map |= 1;
2225                         if(pcicfgr16(p, 0x42) & 0x8000)
2226                                 map |= 2;
2227                         irqack = ichirqack;
2228                         break;
2229                 }
2230                 for(channel = 0; channel < 2; channel++){
2231                         if((map & 1<<channel) == 0)
2232                                 continue;
2233                         if(pi & 1<<2*channel){
2234                                 sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
2235                                                 p->mem[1+2*channel].bar & ~0x01,
2236                                                 p->intl, 3);
2237                                 tbdf = p->tbdf;
2238                         }
2239                         else if(lchan[channel].probed == 0){
2240                                 sdev = ataprobe(lchan[channel].cmdport,
2241                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2242                                 lchan[channel].probed = 1;
2243                                 tbdf = BUSUNKNOWN;
2244                         }
2245                         else
2246                                 continue;
2247                         if(sdev == nil)
2248                                 continue;
2249                         ctlr = sdev->ctlr;
2250                         if(ispc87415) {
2251                                 ctlr->ienable = pc87415ienable;
2252                                 print("pc87415disable: not yet implemented\n");
2253                         }
2254                         ctlr->tbdf = tbdf;
2255                         ctlr->pcidev = p;
2256                         ctlr->maxio = maxio;
2257                         ctlr->maxdma = maxdma;
2258                         ctlr->span = span;
2259                         ctlr->irqack = irqack;
2260                         if(pi & 0x80)
2261                                 ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
2262                         if(head != nil)
2263                                 tail->next = sdev;
2264                         else
2265                                 head = sdev;
2266                         tail = sdev;
2267                 }
2268         }
2269
2270         if(lchan[0].probed + lchan[1].probed == 0)
2271                 for(channel = 0; channel < 2; channel++){
2272                         sdev = nil;
2273                         if(lchan[channel].probed == 0){
2274         //                      print("sdide: blind probe %.3ux\n", lchan[channel].cmdport);
2275                                 sdev = ataprobe(lchan[channel].cmdport,
2276                                         lchan[channel].ctlport, lchan[channel].irq, 3);
2277                                 lchan[channel].probed = 1;
2278                         }
2279                         if(sdev == nil)
2280                                 continue;
2281                         if(head != nil)
2282                                 tail->next = sdev;
2283                         else
2284                                 head = sdev;
2285                         tail = sdev;
2286                 }
2287
2288 if(0){
2289         int port;
2290         ISAConf isa;
2291
2292         /*
2293          * Hack for PCMCIA drives.
2294          * This will be tidied once we figure out how the whole
2295          * removeable device thing is going to work.
2296          */
2297         memset(&isa, 0, sizeof(isa));
2298         isa.port = 0x180;               /* change this for your machine */
2299         isa.irq = 11;                   /* change this for your machine */
2300
2301         port = isa.port+0x0C;
2302         channel = pcmspecial("MK2001MPL", &isa);
2303         if(channel == -1)
2304                 channel = pcmspecial("SunDisk", &isa);
2305         if(channel == -1){
2306                 isa.irq = 10;
2307                 channel = pcmspecial("CF", &isa);
2308         }
2309         if(channel == -1){
2310                 isa.irq = 10;
2311                 channel = pcmspecial("OLYMPUS", &isa);
2312         }
2313         if(channel == -1){
2314                 port = isa.port+0x204;
2315                 channel = pcmspecial("ATA/ATAPI", &isa);
2316         }
2317         if(channel >= 0 && (sdev = ataprobe(isa.port, port, isa.irq, 3)) != nil){
2318                 if(head != nil)
2319                         tail->next = sdev;
2320                 else
2321                         head = sdev;
2322         }
2323 }
2324         return head;
2325 }
2326
2327 static void
2328 atadmaclr(Ctlr *ctlr)
2329 {
2330         int bmiba, bmisx;
2331
2332         if(ctlr->curdrive)
2333                 ataabort(ctlr->curdrive, 1);
2334         bmiba = ctlr->bmiba;
2335         if(bmiba == 0)
2336                 return;
2337         atadmastop(ctlr);
2338         outl(bmiba+Bmidtpx, 0);
2339         bmisx = inb(bmiba+Bmisx) & ~Bmidea;
2340         outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
2341 //      pciintst(ctlr->pcidev);
2342 }
2343
2344 static int
2345 ataenable(SDev* sdev)
2346 {
2347         Ctlr *ctlr;
2348         char name[32];
2349
2350         ctlr = sdev->ctlr;
2351         if(ctlr->bmiba){
2352                 atadmaclr(ctlr);
2353                 if(ctlr->pcidev != nil)
2354                         pcisetbme(ctlr->pcidev);
2355                 ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 4, 0, 64*1024);
2356         }
2357         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2358         intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2359         outb(ctlr->ctlport+Dc, 0);
2360         if(ctlr->ienable)
2361                 ctlr->ienable(ctlr);
2362         return 1;
2363 }
2364
2365 static int
2366 atadisable(SDev *sdev)
2367 {
2368         Ctlr *ctlr;
2369         char name[32];
2370
2371         ctlr = sdev->ctlr;
2372         outb(ctlr->ctlport+Dc, Nien);           /* disable interrupts */
2373         if (ctlr->idisable)
2374                 ctlr->idisable(ctlr);
2375         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2376         intrdisable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
2377         if(ctlr->bmiba) {
2378 //              atadmaclr(ctlr);
2379                 if (ctlr->pcidev)
2380                         pciclrbme(ctlr->pcidev);
2381                 free(ctlr->prdt);
2382         }
2383         return 0;
2384 }
2385
2386 static int
2387 ataonline(SDunit *unit)
2388 {
2389         Ctlr *ctlr;
2390         Drive *drive;
2391
2392         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2393                 return 0;
2394         drive = ctlr->drive[unit->subno];
2395         if((drive->flags & Online) == 0){
2396                 drive->flags |= Online;
2397                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2398         }
2399         unit->sectors = drive->sectors;
2400         unit->secsize = drive->secsize;
2401         if(drive->feat & Datapi)
2402                 return scsionline(unit);
2403         return 1;
2404 }
2405
2406 static int
2407 atarctl(SDunit* unit, char* p, int l)
2408 {
2409         Ctlr *ctlr;
2410         Drive *drive;
2411         char *e, *op;
2412
2413         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2414                 return 0;
2415         drive = ctlr->drive[unit->subno];
2416
2417         e = p+l;
2418         op = p;
2419         qlock(drive);
2420         p = seprint(p, e, "config %4.4uX capabilities %4.4uX", drive->info[Iconfig], drive->info[Icapabilities]);
2421         if(drive->dma)
2422                 p = seprint(p, e, " dma %8.8uX dmactl %8.8uX", drive->dma, drive->dmactl);
2423         if(drive->rwm)
2424                 p = seprint(p, e, " rwm %ud rwmctl %ud", drive->rwm, drive->rwmctl);
2425         if(drive->feat & Dllba)
2426                 p = seprint(p, e, " lba48always %s", (drive->flags&Lba48always) ? "on" : "off");
2427         p = seprint(p, e, "\n");
2428         p = seprint(p, e, "model        %s\n", drive->model);
2429         p = seprint(p, e, "serial       %s\n", drive->serial);
2430         p = seprint(p, e, "firm %s\n", drive->firmware);
2431         p = seprint(p, e, "feat ");
2432         p = pflag(p, e, drive);
2433         if(drive->sectors){
2434                 p = seprint(p, e, "geometry %llud %d", drive->sectors, drive->secsize);
2435                 if(drive->pkt == 0 && (drive->feat & Dlba) == 0)
2436                         p = seprint(p, e, " %d %d %d", drive->c, drive->h, drive->s);
2437                 p = seprint(p, e, "\n");
2438         }
2439         p = seprint(p, e, "missirq      %ud\n", drive->missirq);
2440         p = seprint(p, e, "sloop        %ud\n", drive->spurloop);
2441         p = seprint(p, e, "irq  %ud %ud\n", ctlr->nrq, drive->irq);
2442         p = seprint(p, e, "bsy  %ud %ud\n", ctlr->bsy, drive->bsy);
2443         p = seprint(p, e, "nildrive     %ud\n", ctlr->nildrive);
2444         qunlock(drive);
2445
2446         return p - op;
2447 }
2448
2449 static int
2450 atawctl(SDunit* unit, Cmdbuf* cb)
2451 {
2452         Ctlr *ctlr;
2453         Drive *drive;
2454
2455         if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
2456                 return 0;
2457         drive = ctlr->drive[unit->subno];
2458
2459         qlock(drive);
2460         if(waserror()){
2461                 qunlock(drive);
2462                 nexterror();
2463         }
2464
2465         /*
2466          * Dma and rwm control is passive at the moment,
2467          * i.e. it is assumed that the hardware is set up
2468          * correctly already either by the BIOS or when
2469          * the drive was initially identified.
2470          */
2471         if(strcmp(cb->f[0], "dma") == 0){
2472                 if(cb->nf != 2 || drive->dma == 0)
2473                         error(Ebadctl);
2474                 if(strcmp(cb->f[1], "on") == 0)
2475                         drive->dmactl = drive->dma;
2476                 else if(strcmp(cb->f[1], "off") == 0)
2477                         drive->dmactl = 0;
2478                 else
2479                         error(Ebadctl);
2480         }
2481         else if(strcmp(cb->f[0], "rwm") == 0){
2482                 if(cb->nf != 2 || drive->rwm == 0)
2483                         error(Ebadctl);
2484                 if(strcmp(cb->f[1], "on") == 0)
2485                         drive->rwmctl = drive->rwm;
2486                 else if(strcmp(cb->f[1], "off") == 0)
2487                         drive->rwmctl = 0;
2488                 else
2489                         error(Ebadctl);
2490         }
2491         else if(strcmp(cb->f[0], "lba48always") == 0){
2492                 if(cb->nf != 2 || !(drive->feat & Dllba))
2493                         error(Ebadctl);
2494                 if(strcmp(cb->f[1], "on") == 0)
2495                         drive->flags |= Lba48always;
2496                 else if(strcmp(cb->f[1], "off") == 0)
2497                         drive->flags &= ~Lba48always;
2498                 else
2499                         error(Ebadctl);
2500         }
2501         else if(strcmp(cb->f[0], "identify") == 0){
2502                 atadrive(unit, drive, ctlr->cmdport, ctlr->ctlport, drive->dev);
2503         }
2504         else
2505                 error(Ebadctl);
2506         qunlock(drive);
2507         poperror();
2508
2509         return 0;
2510 }
2511
2512 SDifc sdideifc = {
2513         "ide",                          /* name */
2514
2515         atapnp,                         /* pnp */
2516         nil,                    /* legacy */
2517         ataenable,                      /* enable */
2518         atadisable,                     /* disable */
2519
2520         scsiverify,                     /* verify */
2521         ataonline,                      /* online */
2522         atario,                         /* rio */
2523         atarctl,                        /* rctl */
2524         atawctl,                        /* wctl */
2525
2526         scsibio,                        /* bio */
2527         ataprobew,                      /* probe */
2528         ataclear,                       /* clear */
2529         atastat,                        /* rtopctl */
2530         nil,                            /* wtopctl */
2531         ataataio,
2532 };