sys/src/9/pc/sd53c8xx.c

   1 /*
   2  * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
   3  * Nigel Roles (nigel@9fs.org)
   4  *
   5  * 27/5/02      Fixed problems with transfers >= 256 * 512
   6  *
   7  * 13/3/01      Fixed microcode to support targets > 7
   8  *
   9  * 01/12/00     Removed previous comments. Fixed a small problem in
  10  *                      mismatch recovery for targets with synchronous offsets of >=16
  11  *                      connected to >=875s. Thanks, Jean.
  12  *
  13  * Known problems
  14  *
  15  * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
  16  */
  17
  18 #define MAXTARGET       16              /* can be 8 or 16 */
  19
  20 #include "u.h"
  21 #include "../port/lib.h"
  22 #include "mem.h"
  23 #include "dat.h"
  24 #include "fns.h"
  25 #include "io.h"
  26 #include "../port/pci.h"
  27
  28 #include "../port/sd.h"
  29 extern SDifc sd53c8xxifc;
  30
  31 /**********************************/
  32 /* Portable configuration macros  */
  33 /**********************************/
  34
  35 #define WMR_DEBUG
  36
  37 /**********************************/
  38 /* CPU specific macros            */
  39 /**********************************/
  40
  41 #define PRINTPREFIX "sd53c8xx: "
  42
  43 static int idebug = 0;
  44 #define KPRINT  if(0) iprint
  45 #define IPRINT  if(idebug) iprint
  46 #define DEBUG(n) (0)
  47 #define IFLUSH()
  48
  49 /*******************************/
  50 /* General                     */
  51 /*******************************/
  52
  53 #define DMASEG(x) PCIWADDR(x)
  54 #define legetl(x) (*(ulong*)(x))
  55 #define lesetl(x,v) (*(ulong*)(x) = (v))
  56 #define swabl(a,b,c)
  57 #define DMASEG_TO_PADDR(x) ((uintptr)(x)-PCIWINDOW)
  58 #define DMASEG_TO_KADDR(x) KADDR(DMASEG_TO_PADDR(x))
  59 #define KPTR(x) (((x) == 0) ? nil : DMASEG_TO_KADDR(x))
  60
  61 #define MEGA 1000000L
  62 #ifdef INTERNAL_SCLK
  63 #define SCLK (33 * MEGA)
  64 #else
  65 #define SCLK (40 * MEGA)
  66 #endif /* INTERNAL_SCLK */
  67 #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
  68
  69 #define MAXSYNCSCSIRATE (5 * MEGA)
  70 #define MAXFASTSYNCSCSIRATE (10 * MEGA)
  71 #define MAXULTRASYNCSCSIRATE (20 * MEGA)
  72 #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
  73 #define MAXASYNCCORERATE (25 * MEGA)
  74 #define MAXSYNCCORERATE (25 * MEGA)
  75 #define MAXFASTSYNCCORERATE (50 * MEGA)
  76 #define MAXULTRASYNCCORERATE (80 * MEGA)
  77 #define MAXULTRA2SYNCCORERATE (160 * MEGA)
  78
  79
  80 #define X_MSG   1
  81 #define X_MSG_SDTR 1
  82 #define X_MSG_WDTR 3
  83
  84 struct na_patch {
  85         unsigned lwoff;
  86         unsigned char type;
  87 };
  88
  89 typedef struct Ncr {
  90         uchar scntl0;   /* 00 */
  91         uchar scntl1;
  92         uchar scntl2;
  93         uchar scntl3;
  94
  95         uchar scid;     /* 04 */
  96         uchar sxfer;
  97         uchar sdid;
  98         uchar gpreg;
  99
 100         uchar sfbr;     /* 08 */
 101         uchar socl;
 102         uchar ssid;
 103         uchar sbcl;
 104
 105         uchar dstat;    /* 0c */
 106         uchar sstat0;
 107         uchar sstat1;
 108         uchar sstat2;
 109
 110         uchar dsa[4];   /* 10 */
 111
 112         uchar istat;    /* 14 */
 113         uchar istatpad[3];
 114
 115         uchar ctest0;   /* 18 */
 116         uchar ctest1;
 117         uchar ctest2;
 118         uchar ctest3;
 119
 120         uchar temp[4];  /* 1c */
 121
 122         uchar dfifo;    /* 20 */
 123         uchar ctest4;
 124         uchar ctest5;
 125         uchar ctest6;
 126
 127         uchar dbc[3];   /* 24 */
 128         uchar dcmd;     /* 27 */
 129
 130         uchar dnad[4];  /* 28 */
 131         uchar dsp[4];   /* 2c */
 132         uchar dsps[4];  /* 30 */
 133
 134         uchar scratcha[4];      /* 34 */
 135
 136         uchar dmode;    /* 38 */
 137         uchar dien;
 138         uchar dwt;
 139         uchar dcntl;
 140
 141         uchar adder[4]; /* 3c */
 142
 143         uchar sien0;    /* 40 */
 144         uchar sien1;
 145         uchar sist0;
 146         uchar sist1;
 147
 148         uchar slpar;    /* 44 */
 149         uchar slparpad0;
 150         uchar macntl;
 151         uchar gpcntl;
 152
 153         uchar stime0;   /* 48 */
 154         uchar stime1;
 155         uchar respid;
 156         uchar respidpad0;
 157
 158         uchar stest0;   /* 4c */
 159         uchar stest1;
 160         uchar stest2;
 161         uchar stest3;
 162
 163         uchar sidl;     /* 50 */
 164         uchar sidlpad[3];
 165
 166         uchar sodl;     /* 54 */
 167         uchar sodlpad[3];
 168
 169         uchar sbdl;     /* 58 */
 170         uchar sbdlpad[3];
 171
 172         uchar scratchb[4];      /* 5c */
 173 } Ncr;
 174
 175 typedef struct Movedata {
 176         uchar dbc[4];
 177         uchar pa[4];
 178 } Movedata;
 179
 180 typedef enum NegoState {
 181         NeitherDone, WideInit, WideResponse, WideDone,
 182         SyncInit, SyncResponse, BothDone
 183 } NegoState;
 184
 185 typedef enum State {
 186         Allocated, Queued, Active, Done
 187 } State;
 188
 189 typedef struct Dsa Dsa;
 190 struct Dsa {
 191         uchar stateb;
 192         uchar result;
 193         uchar dmablks;
 194         uchar flag;     /* setbyte(state,3,...) */
 195
 196         uchar dmaaddr[4];       /* For block transfer: NCR order (little-endian) */
 197
 198         uchar target;                   /* Target */
 199         uchar pad0[3];
 200
 201         uchar lun;                      /* Logical Unit Number */
 202         uchar pad1[3];
 203
 204         uchar scntl3;                   /* Sync */
 205         uchar sxfer;
 206         uchar pad2[2];
 207
 208         uchar next[4];                  /* chaining for SCRIPT (NCR byte order) */
 209
 210         Dsa     *freechain;             /* chaining for freelist */
 211         Rendez;
 212
 213         uchar scsi_id_buf[4];
 214         Movedata msg_out_buf;
 215         Movedata cmd_buf;
 216         Movedata data_buf;
 217         Movedata status_buf;
 218
 219         uchar msg_out[10];              /* enough to include SDTR */
 220         uchar status;
 221         int p9status;
 222         uchar parityerror;
 223 };
 224
 225 typedef enum Feature {
 226         BigFifo = 1,                    /* 536 byte fifo */
 227         BurstOpCodeFetch = 2,           /* burst fetch opcodes */
 228         Prefetch = 4,                   /* prefetch 8 longwords */
 229         LocalRAM = 8,                   /* 4K longwords of local RAM */
 230         Differential = 16,              /* Differential support */
 231         Wide = 32,                      /* Wide capable */
 232         Ultra = 64,                     /* Ultra capable */
 233         ClockDouble = 128,              /* Has clock doubler */
 234         ClockQuad = 256,                /* Has clock quadrupler (same as Ultra2) */
 235         Ultra2 = 256,
 236 } Feature;
 237
 238 typedef enum Burst {
 239         Burst2 = 0,
 240         Burst4 = 1,
 241         Burst8 = 2,
 242         Burst16 = 3,
 243         Burst32 = 4,
 244         Burst64 = 5,
 245         Burst128 = 6
 246 } Burst;
 247
 248 typedef struct Variant {
 249         ushort did;
 250         uchar maxrid;                   /* maximum allowed revision ID */
 251         char *name;
 252         Burst burst;                    /* codings for max burst */
 253         uchar maxsyncoff;               /* max synchronous offset */
 254         uchar registers;                /* number of 32 bit registers */
 255         unsigned feature;
 256 } Variant;
 257
 258 static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
 259 #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
 260 #define NULTRASCF (NULTRA2SCF - 2)
 261 #define NSCF (NULTRASCF - 1)
 262
 263 typedef struct Controller {
 264         Lock;
 265         struct {
 266                 uchar scntl3;
 267                 uchar stest2;
 268         } bios;
 269         uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
 270         NegoState s[MAXTARGET];
 271         uchar scntl3[MAXTARGET];
 272         uchar sxfer[MAXTARGET];
 273         uchar cap[MAXTARGET];           /* capabilities byte from Identify */
 274         ushort capvalid;                /* bit per target for validity of cap[] */
 275         ushort wide;                    /* bit per target set if wide negotiated */
 276         ulong sclk;                     /* clock speed of controller */
 277         uchar clockmult;                /* set by synctabinit */
 278         uchar ccf;                      /* CCF bits */
 279         uchar tpf;                      /* best tpf value for this controller */
 280         uchar feature;                  /* requested features */
 281         int running;                    /* is the script processor running? */
 282         int ssm;                        /* single step mode */
 283         Ncr *n;                         /* pointer to registers */
 284         Variant *v;                     /* pointer to variant type */
 285         ulong *script;                  /* where the real script is */
 286         ulong scriptpa;                 /* where the real script is */
 287         Pcidev* pcidev;
 288         SDev*   sdev;
 289
 290         struct {
 291                 Lock;
 292                 uchar head[4];          /* head of free list (NCR byte order) */
 293                 Dsa     *freechain;
 294         } dsalist;
 295
 296         QLock q[MAXTARGET];             /* queues for each target */
 297 } Controller;
 298
 299 #define SYNCOFFMASK(c)          (((c)->v->maxsyncoff * 2) - 1)
 300 #define SSIDMASK(c)             (((c)->v->feature & Wide) ? 15 : 7)
 301
 302 /* ISTAT */
 303 enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
 304
 305 /* DSTAT */
 306 enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
 307
 308 /* SSTAT */
 309 enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
 310
 311 static void setmovedata(Movedata*, ulong, ulong);
 312 static void advancedata(Movedata*, long);
 313 static int bios_set_differential(Controller *c);
 314
 315 static char *phase[] = {
 316         "data out", "data in", "command", "status",
 317         "reserved out", "reserved in", "message out", "message in"
 318 };
 319
 320 #ifdef BOOTDEBUG
 321 #define DEBUGSIZE 10240
 322 char debugbuf[DEBUGSIZE];
 323 char *debuglast;
 324
 325 static void
 326 intrprint(char *format, ...)
 327 {
 328         if (debuglast == 0)
 329                 debuglast = debugbuf;
 330         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
 331 }
 332
 333 static void
 334 iflush()
 335 {
 336         int s;
 337         char *endp;
 338         s = splhi();
 339         if (debuglast == 0)
 340                 debuglast = debugbuf;
 341         if (debuglast == debugbuf) {
 342                 splx(s);
 343                 return;
 344         }
 345         endp = debuglast;
 346         splx(s);
 347         screenputs(debugbuf, endp - debugbuf);
 348         s = splhi();
 349         memmove(debugbuf, endp, debuglast - endp);
 350         debuglast -= endp - debugbuf;
 351         splx(s);
 352 }
 353
 354 static void
 355 oprint(char *format, ...)
 356 {
 357         int s;
 358
 359         iflush();
 360         s = splhi();
 361         if (debuglast == 0)
 362                 debuglast = debugbuf;
 363         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
 364         splx(s);
 365         iflush();
 366 }
 367 #endif
 368
 369 #include "../pc/sd53c8xx.i"
 370
 371 /*
 372  * We used to use a linked list of Dsas with nil as the terminator,
 373  * but occasionally the 896 card seems not to notice that the 0
 374  * is really a 0, and then it tries to reference the Dsa at address 0.
 375  * To address this, we use a sentinel dsa that links back to itself
 376  * and has state A_STATE_END.  If the card takes an iteration or
 377  * two to notice that the state says A_STATE_END, that's no big
 378  * deal.  Clearly this isn't the right approach, but I'm just
 379  * stumped.  Even with this, we occasionally get prints about
 380  * "WSR set", usually with about the same frequency that the
 381  * card used to walk past 0.
 382  */
 383 static Dsa *dsaend;
 384
 385 static Dsa *
 386 dsaalloc(Controller *c, int target, int lun)
 387 {
 388         Dsa *d;
 389
 390         ilock(&c->dsalist);
 391         if ((d = c->dsalist.freechain) != nil) {
 392                 c->dsalist.freechain = d->freechain;
 393                 d->freechain = nil;
 394                 if (DEBUG(1))
 395                         IPRINT(PRINTPREFIX "%d/%d: reused dsa %#p\n", target, lun, d);
 396         } else {
 397                 /* c->dsalist must be ilocked */
 398                 d = xalloc(sizeof *d);
 399                 if (d == nil)
 400                         panic("sd53c8xx dsaallocnew: no memory");
 401                 d->freechain = nil;
 402                 lesetl(d->next, legetl(c->dsalist.head));
 403                 lesetl(&d->stateb, A_STATE_FREE);
 404                 coherence();
 405                 lesetl(c->dsalist.head, DMASEG(d));
 406                 coherence();
 407                 if (DEBUG(1))
 408                         IPRINT(PRINTPREFIX "%d/%d: allocated dsa %#p\n", target, lun, d);
 409         }
 410         lesetl(&d->stateb, A_STATE_ALLOCATED);
 411         iunlock(&c->dsalist);
 412         d->target = target;
 413         d->lun = lun;
 414         return d;
 415 }
 416
 417 static void
 418 dsafree(Controller *c, Dsa *d)
 419 {
 420         ilock(&c->dsalist);
 421         d->freechain = c->dsalist.freechain;
 422         c->dsalist.freechain = d;
 423         lesetl(&d->stateb, A_STATE_FREE);
 424         iunlock(&c->dsalist);
 425 }
 426
 427 static void
 428 dsadump(Controller *c)
 429 {
 430         Dsa *d;
 431         u32int *a;
 432
 433         iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
 434         for(d=KPTR(legetl(c->dsalist.head)); d != nil && d != dsaend; d=KPTR(legetl(d->next))){
 435                 a = (u32int*)d;
 436                 iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
 437         }
 438
 439 /*
 440         a = KPTR(c->scriptpa+E_dsa_addr);
 441         iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
 442                 a[0], a[1], a[2], a[3], a[4]);
 443         a = KPTR(c->scriptpa+E_issue_addr);
 444         iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
 445                 a[0], a[1], a[2], a[3], a[4]);
 446
 447         a = KPTR(c->scriptpa+E_issue_test_begin);
 448         e = KPTR(c->scriptpa+E_issue_test_end);
 449         iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
 450
 451         i = 0;
 452         for(; a<e; a++){
 453                 iprint(" %.8ux", *a);
 454                 if(++i%8 == 0)
 455                         iprint("\n");
 456         }
 457         if(i%8)
 458                 iprint("\n");
 459 */
 460 }
 461
 462 static Dsa *
 463 dsafind(Controller *c, uchar target, uchar lun, uchar state)
 464 {
 465         Dsa *d;
 466
 467         for (d = KPTR(legetl(c->dsalist.head)); d != nil && d != dsaend; d = KPTR(legetl(d->next))) {
 468                 if (d->target != 0xff && d->target != target)
 469                         continue;
 470                 if (lun != 0xff && d->lun != lun)
 471                         continue;
 472                 if (state != 0xff && d->stateb != state)
 473                         continue;
 474                 break;
 475         }
 476         return d;
 477 }
 478
 479 static void
 480 dumpncrregs(Controller *c, int intr)
 481 {
 482         int i;
 483         Ncr *n = c->n;
 484         int depth = c->v->registers / 4;
 485
 486         if (intr) {
 487                 IPRINT("sa = %.8lux\n", c->scriptpa);
 488         }
 489         else {
 490                 KPRINT("sa = %.8lux\n", c->scriptpa);
 491         }
 492         for (i = 0; i < depth; i++) {
 493                 int j;
 494                 for (j = 0; j < 4; j++) {
 495                         int k = j * depth + i;
 496                         uchar *p;
 497
 498                         /* display little-endian to make 32-bit values readable */
 499                         p = (uchar*)n+k*4;
 500                         if (intr) {
 501                                 IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
 502                         }
 503                         else {
 504                                 KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
 505                         }
 506                         USED(p);
 507                 }
 508                 if (intr) {
 509                         IPRINT("\n");
 510                 }
 511                 else {
 512                         KPRINT("\n");
 513                 }
 514         }
 515 }
 516
 517 static int
 518 chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
 519 {
 520         /* find lowest entry >= tpf */
 521         int besttpf = 1000;
 522         int bestscfi = 0;
 523         int bestxferp = 0;
 524         int scf, xferp;
 525         int maxscf;
 526
 527         if (c->v->feature & Ultra2)
 528                 maxscf = NULTRA2SCF;
 529         else if (c->v->feature & Ultra)
 530                 maxscf = NULTRASCF;
 531         else
 532                 maxscf = NSCF;
 533
 534         /*
 535          * search large clock factors first since this should
 536          * result in more reliable transfers
 537          */
 538         for (scf = maxscf; scf >= 1; scf--) {
 539                 for (xferp = 0; xferp < 8; xferp++) {
 540                         unsigned char v = c->synctab[scf - 1][xferp];
 541                         if (v == 0)
 542                                 continue;
 543                         if (v >= tpf && v < besttpf) {
 544                                 besttpf = v;
 545                                 bestscfi = scf;
 546                                 bestxferp = xferp;
 547                         }
 548                 }
 549         }
 550         if (besttpf == 1000)
 551                 return 0;
 552         if (scfp)
 553                 *scfp = bestscfi;
 554         if (xferpp)
 555                 *xferpp = bestxferp;
 556         return besttpf;
 557 }
 558
 559 static void
 560 synctabinit(Controller *c)
 561 {
 562         int scf;
 563         unsigned long scsilimit;
 564         int xferp;
 565         unsigned long cr, sr;
 566         int tpf;
 567         int fast;
 568         int maxscf;
 569
 570         if (c->v->feature & Ultra2)
 571                 maxscf = NULTRA2SCF;
 572         else if (c->v->feature & Ultra)
 573                 maxscf = NULTRASCF;
 574         else
 575                 maxscf = NSCF;
 576
 577         /*
 578          * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
 579          * first spin of the 875), assume 80MHz
 580          * otherwise use the internal (33 Mhz) or external (40MHz) default
 581          */
 582
 583         if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
 584                 c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
 585         else
 586                 c->sclk = SCLK;
 587
 588         /*
 589          * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
 590          * invoke the doubler
 591          */
 592
 593         if (SCLK <= 40000000) {
 594                 if (c->v->feature & ClockDouble) {
 595                         c->sclk *= 2;
 596                         c->clockmult = 1;
 597                 }
 598                 else if (c->v->feature & ClockQuad) {
 599                         c->sclk *= 4;
 600                         c->clockmult = 1;
 601                 }
 602                 else
 603                         c->clockmult = 0;
 604         }
 605         else
 606                 c->clockmult = 0;
 607
 608         /* derive CCF from sclk */
 609         /* woebetide anyone with SCLK < 16.7 or > 80MHz */
 610         if (c->sclk <= 25 * MEGA)
 611                 c->ccf = 1;
 612         else if (c->sclk <= 3750000)
 613                 c->ccf = 2;
 614         else if (c->sclk <= 50 * MEGA)
 615                 c->ccf = 3;
 616         else if (c->sclk <= 75 * MEGA)
 617                 c->ccf = 4;
 618         else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
 619                 c->ccf = 5;
 620         else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
 621                 c->ccf = 6;
 622         else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
 623                 c->ccf = 7;
 624
 625         for (scf = 1; scf < maxscf; scf++) {
 626                 /* check for legal core rate */
 627                 /* round up so we run slower for safety */
 628                 cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
 629                 if (cr <= MAXSYNCCORERATE) {
 630                         scsilimit = MAXSYNCSCSIRATE;
 631                         fast = 0;
 632                 }
 633                 else if (cr <= MAXFASTSYNCCORERATE) {
 634                         scsilimit = MAXFASTSYNCSCSIRATE;
 635                         fast = 1;
 636                 }
 637                 else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
 638                         scsilimit = MAXULTRASYNCSCSIRATE;
 639                         fast = 2;
 640                 }
 641                 else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
 642                         scsilimit = MAXULTRA2SYNCSCSIRATE;
 643                         fast = 3;
 644                 }
 645                 else
 646                         continue;
 647                 for (xferp = 11; xferp >= 4; xferp--) {
 648                         int ok;
 649                         int tp;
 650                         /* calculate scsi rate - round up again */
 651                         /* start from sclk for accuracy */
 652                         int totaldivide = xferp * cf2[scf];
 653                         sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
 654                         if (sr > scsilimit)
 655                                 break;
 656                         /*
 657                          * now work out transfer period
 658                          * round down now so that period is pessimistic
 659                          */
 660                         tp = (MEGA * 1000) / sr;
 661                         /*
 662                          * bounds check it
 663                          */
 664                         if (tp < 25 || tp > 255 * 4)
 665                                 continue;
 666                         /*
 667                          * spot stupid special case for Ultra or Ultra2
 668                          * while working out factor
 669                          */
 670                         if (tp == 25)
 671                                 tpf = 10;
 672                         else if (tp == 50)
 673                                 tpf = 12;
 674                         else if (tp < 52)
 675                                 continue;
 676                         else
 677                                 tpf = tp / 4;
 678                         /*
 679                          * now check tpf looks sensible
 680                          * given core rate
 681                          */
 682                         switch (fast) {
 683                         case 0:
 684                                 /* scf must be ccf for SCSI 1 */
 685                                 ok = tpf >= 50 && scf == c->ccf;
 686                                 break;
 687                         case 1:
 688                                 ok = tpf >= 25 && tpf < 50;
 689                                 break;
 690                         case 2:
 691                                 /*
 692                                  * must use xferp of 4, or 5 at a pinch
 693                                  * for an Ultra transfer
 694                                  */
 695                                 ok = xferp <= 5 && tpf >= 12 && tpf < 25;
 696                                 break;
 697                         case 3:
 698                                 ok = xferp == 4 && (tpf == 10 || tpf == 11);
 699                                 break;
 700                         default:
 701                                 ok = 0;
 702                         }
 703                         if (!ok)
 704                                 continue;
 705                         c->synctab[scf - 1][xferp - 4] = tpf;
 706                 }
 707         }
 708
 709 #ifndef NO_ULTRA2
 710         if (c->v->feature & Ultra2)
 711                 tpf = 10;
 712         else
 713 #endif
 714         if (c->v->feature & Ultra)
 715                 tpf = 12;
 716         else
 717                 tpf = 25;
 718         for (; tpf < 256; tpf++) {
 719                 if (chooserate(c, tpf, &scf, &xferp) == tpf) {
 720                         unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
 721                         unsigned long khz = (MEGA + tp - 1) / (tp);
 722                         KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
 723                             tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
 724                             xferp + 4, khz / 1000, khz % 1000);
 725                         USED(khz);
 726                         if (c->tpf == 0)
 727                                 c->tpf = tpf;   /* note lowest value for controller */
 728                 }
 729         }
 730 }
 731
 732 static void
 733 synctodsa(Dsa *dsa, Controller *c)
 734 {
 735 /*
 736         KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
 737             dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
 738 */
 739         dsa->scntl3 = c->scntl3[dsa->target];
 740         dsa->sxfer = c->sxfer[dsa->target];
 741 }
 742
 743 static void
 744 setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
 745 {
 746         c->scntl3[target] =
 747             (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
 748         c->sxfer[target] = (xferp << 5) | reqack;
 749         c->s[target] = BothDone;
 750         if (dsa) {
 751                 synctodsa(dsa, c);
 752                 c->n->scntl3 = c->scntl3[target];
 753                 c->n->sxfer = c->sxfer[target];
 754         }
 755 }
 756
 757 static void
 758 setasync(Dsa *dsa, Controller *c, int target)
 759 {
 760         setsync(dsa, c, target, 0, c->ccf, 0, 0);
 761 }
 762
 763 static void
 764 setwide(Dsa *dsa, Controller *c, int target, uchar wide)
 765 {
 766         c->scntl3[target] = wide ? (1 << 3) : 0;
 767         setasync(dsa, c, target);
 768         c->s[target] = WideDone;
 769 }
 770
 771 static int
 772 buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
 773 {
 774         *buf++ = X_MSG;
 775         *buf++ = 3;
 776         *buf++ = X_MSG_SDTR;
 777         *buf++ = tpf;
 778         *buf = offset;
 779         return 5;
 780 }
 781
 782 static int
 783 buildwdtrmsg(uchar *buf, uchar expo)
 784 {
 785         *buf++ = X_MSG;
 786         *buf++ = 2;
 787         *buf++ = X_MSG_WDTR;
 788         *buf = expo;
 789         return 4;
 790 }
 791
 792 static void
 793 start(Controller *c, long entry)
 794 {
 795         ulong p;
 796
 797         if (c->running)
 798                 panic(PRINTPREFIX "start called while running");
 799         c->running = 1;
 800         p = c->scriptpa + entry;
 801         lesetl(c->n->dsp, p);
 802         coherence();
 803         if (c->ssm)
 804                 c->n->dcntl |= 0x4;             /* start DMA in SSI mode */
 805 }
 806
 807 static void
 808 ncrcontinue(Controller *c)
 809 {
 810         if (c->running)
 811                 panic(PRINTPREFIX "ncrcontinue called while running");
 812         /* set the start DMA bit to continue execution */
 813         c->running = 1;
 814         coherence();
 815         c->n->dcntl |= 0x4;
 816 }
 817
 818 static void
 819 softreset(Controller *c)
 820 {
 821         Ncr *n = c->n;
 822
 823         n->istat = Srst;                /* software reset */
 824         n->istat = 0;
 825         /* general initialisation */
 826         n->scid = (1 << 6) | 7;         /* respond to reselect, ID 7 */
 827         n->respid = 1 << 7;             /* response ID = 7 */
 828
 829 #ifdef INTERNAL_SCLK
 830         n->stest1 = 0x80;               /* disable external scsi clock */
 831 #else
 832         n->stest1 = 0x00;
 833 #endif
 834
 835         n->stime0 = 0xdd;               /* about 0.5 second timeout on each device */
 836         n->scntl0 |= 0x8;               /* Enable parity checking */
 837
 838         /* continued setup */
 839         n->sien0 = 0x8f;
 840         n->sien1 = 0x04;
 841         n->dien = 0x7d;
 842         n->stest3 = 0x80;               /* TolerANT enable */
 843         c->running = 0;
 844
 845         if (c->v->feature & BigFifo)
 846                 n->ctest5 = (1 << 5);
 847         n->dmode = c->v->burst << 6;    /* set burst length bits */
 848         if (c->v->burst & 4)
 849                 n->ctest5 |= (1 << 2);  /* including overflow into ctest5 bit 2 */
 850         if (c->v->feature & Prefetch)
 851                 n->dcntl |= (1 << 5);   /* prefetch enable */
 852         else if (c->v->feature & BurstOpCodeFetch)
 853                 n->dmode |= (1 << 1);   /* burst opcode fetch */
 854         if (c->v->feature & Differential) {
 855                 /* chip capable */
 856                 if ((c->feature & Differential) || bios_set_differential(c)) {
 857                         /* user enabled, or some evidence bios set differential */
 858                         if (n->sstat2 & (1 << 2))
 859                                 print(PRINTPREFIX "can't go differential; wrong cable\n");
 860                         else {
 861                                 n->stest2 = (1 << 5);
 862                                 print(PRINTPREFIX "differential mode set\n");
 863                         }
 864                 }
 865         }
 866         if (c->clockmult) {
 867                 n->stest1 |= (1 << 3);  /* power up doubler */
 868                 delay(2);
 869                 n->stest3 |= (1 << 5);  /* stop clock */
 870                 n->stest1 |= (1 << 2);  /* enable doubler */
 871                 n->stest3 &= ~(1 << 5); /* start clock */
 872                 /* pray */
 873         }
 874 }
 875
 876 static void
 877 msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
 878 {
 879         uchar histpf, hisreqack;
 880         int tpf;
 881         int scf, xferp;
 882         int len;
 883
 884         Ncr *n = c->n;
 885
 886         switch (c->s[dsa->target]) {
 887         case SyncInit:
 888                 switch (msg) {
 889                 case A_SIR_MSG_SDTR:
 890                         /* reply to my SDTR */
 891                         histpf = n->scratcha[2];
 892                         hisreqack = n->scratcha[3];
 893                         KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
 894                             dsa->target, histpf, hisreqack);
 895
 896                         if (hisreqack == 0)
 897                                 setasync(dsa, c, dsa->target);
 898                         else {
 899                                 /* hisreqack should be <= c->v->maxsyncoff */
 900                                 tpf = chooserate(c, histpf, &scf, &xferp);
 901                                 KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
 902                                     dsa->target, tpf, hisreqack);
 903                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
 904                         }
 905                         *cont = -2;
 906                         return;
 907                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
 908                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
 909                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
 910                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
 911                         setasync(dsa, c, dsa->target);
 912                         *cont = E_to_decisions;
 913                         return;
 914                 case A_SIR_MSG_REJECT:
 915                         /* rejection of my SDTR */
 916                         KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
 917                 //async:
 918                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
 919                         setasync(dsa, c, dsa->target);
 920                         *cont = -2;
 921                         return;
 922                 }
 923                 break;
 924         case WideInit:
 925                 switch (msg) {
 926                 case A_SIR_MSG_WDTR:
 927                         /* reply to my WDTR */
 928                         KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
 929                             dsa->target, n->scratcha[2]);
 930                         setwide(dsa, c, dsa->target, n->scratcha[2]);
 931                         *cont = -2;
 932                         return;
 933                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
 934                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
 935                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
 936                         setwide(dsa, c, dsa->target, 0);
 937                         *cont = E_to_decisions;
 938                         return;
 939                 case A_SIR_MSG_REJECT:
 940                         /* rejection of my SDTR */
 941                         KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
 942                         setwide(dsa, c, dsa->target, 0);
 943                         *cont = -2;
 944                         return;
 945                 }
 946                 break;
 947
 948         case NeitherDone:
 949         case WideDone:
 950         case BothDone:
 951                 switch (msg) {
 952                 case A_SIR_MSG_WDTR: {
 953                         uchar hiswide, mywide;
 954                         hiswide = n->scratcha[2];
 955                         mywide = (c->v->feature & Wide) != 0;
 956                         KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
 957                             dsa->target, hiswide);
 958                         if (hiswide < mywide)
 959                                 mywide = hiswide;
 960                         KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
 961                             dsa->target, mywide);
 962                         setwide(dsa, c, dsa->target, mywide);
 963                         len = buildwdtrmsg(dsa->msg_out, mywide);
 964                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
 965                         *cont = E_response;
 966                         c->s[dsa->target] = WideResponse;
 967                         return;
 968                 }
 969                 case A_SIR_MSG_SDTR:
 970 #ifdef ASYNC_ONLY
 971                         *cont = E_reject;
 972                         return;
 973 #else
 974                         /* target decides to renegotiate */
 975                         histpf = n->scratcha[2];
 976                         hisreqack = n->scratcha[3];
 977                         KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
 978                             dsa->target, histpf, hisreqack);
 979                         if (hisreqack == 0) {
 980                                 /* he wants asynchronous */
 981                                 setasync(dsa, c, dsa->target);
 982                                 tpf = 0;
 983                         }
 984                         else {
 985                                 /* he wants synchronous */
 986                                 tpf = chooserate(c, histpf, &scf, &xferp);
 987                                 if (hisreqack > c->v->maxsyncoff)
 988                                         hisreqack = c->v->maxsyncoff;
 989                                 KPRINT(PRINTPREFIX "%d: using %d %d\n",
 990                                     dsa->target, tpf, hisreqack);
 991                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
 992                         }
 993                         /* build my SDTR message */
 994                         len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
 995                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
 996                         *cont = E_response;
 997                         c->s[dsa->target] = SyncResponse;
 998                         return;
 999 #endif
1000                 }
1001                 break;
1002         case WideResponse:
1003                 switch (msg) {
1004                 case A_SIR_EV_RESPONSE_OK:
1005                         c->s[dsa->target] = WideDone;
1006                         KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
1007                         *cont = -2;
1008                         return;
1009                 case A_SIR_MSG_REJECT:
1010                         setwide(dsa, c, dsa->target, 0);
1011                         KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
1012                         *cont = -2;
1013                         return;
1014                 }
1015                 break;
1016         case SyncResponse:
1017                 switch (msg) {
1018                 case A_SIR_EV_RESPONSE_OK:
1019                         c->s[dsa->target] = BothDone;
1020                         KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
1021                             dsa->target, phase[n->sstat1 & 7]);
1022                         *cont = -2;
1023                         return; /* chf */
1024                 case A_SIR_MSG_REJECT:
1025                         setasync(dsa, c, dsa->target);
1026                         KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
1027                         *cont = -2;
1028                         return;
1029                 }
1030                 break;
1031         }
1032         KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
1033             dsa->target, c->s[dsa->target], msg);
1034         *wakeme = 1;
1035         return;
1036 }
1037
1038 static void
1039 calcblockdma(Dsa *d, ulong base, ulong count)
1040 {
1041         ulong blocks;
1042         if (DEBUG(3))
1043                 blocks = 0;
1044         else {
1045                 blocks = count / A_BSIZE;
1046                 if (blocks > 255)
1047                         blocks = 255;
1048         }
1049         d->dmablks = blocks;
1050         d->dmaaddr[0] = base;
1051         d->dmaaddr[1] = base >> 8;
1052         d->dmaaddr[2] = base >> 16;
1053         d->dmaaddr[3] = base >> 24;
1054         setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
1055         d->flag = legetl(d->data_buf.dbc) == 0;
1056 }
1057
1058 static ulong
1059 read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
1060 {
1061         ulong dbc;
1062         uchar dfifo = n->dfifo;
1063         int inchip;
1064
1065         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1066         if (n->ctest5 & (1 << 5))
1067                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
1068         else
1069                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
1070         if (inchip) {
1071                 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
1072                     dsa->target, dsa->lun, inchip);
1073         }
1074         if (n->sxfer & SYNCOFFMASK(c)) {
1075                 /* SCSI FIFO */
1076                 uchar fifo = n->sstat1 >> 4;
1077                 if (c->v->maxsyncoff > 8)
1078                         fifo |= (n->sstat2 & (1 << 4));
1079                 if (fifo) {
1080                         inchip += fifo;
1081                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
1082                             dsa->target, dsa->lun, fifo);
1083                 }
1084         }
1085         else {
1086                 if (n->sstat0 & (1 << 7)) {
1087                         inchip++;
1088                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
1089                             dsa->target, dsa->lun);
1090                 }
1091                 if (n->sstat2 & (1 << 7)) {
1092                         inchip++;
1093                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
1094                             dsa->target, dsa->lun);
1095                 }
1096         }
1097         USED(inchip);
1098         return dbc;
1099 }
1100
1101 static ulong
1102 write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
1103 {
1104         ulong dbc;
1105         uchar dfifo = n->dfifo;
1106         int inchip;
1107
1108         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1109         USED(dsa);
1110         if (n->ctest5 & (1 << 5))
1111                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
1112         else
1113                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
1114 #ifdef WMR_DEBUG
1115         if (inchip) {
1116                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
1117                     dsa->target, dsa->lun, inchip);
1118         }
1119 #endif
1120         if (n->sstat0 & (1 << 5)) {
1121                 inchip++;
1122 #ifdef WMR_DEBUG
1123                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
1124 #endif
1125         }
1126         if (n->sstat2 & (1 << 5)) {
1127                 inchip++;
1128 #ifdef WMR_DEBUG
1129                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
1130 #endif
1131         }
1132         if (n->sxfer & SYNCOFFMASK(c)) {
1133                 /* synchronous SODR */
1134                 if (n->sstat0 & (1 << 6)) {
1135                         inchip++;
1136 #ifdef WMR_DEBUG
1137                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
1138                             dsa->target, dsa->lun);
1139 #endif
1140                 }
1141                 if (n->sstat2 & (1 << 6)) {
1142                         inchip++;
1143 #ifdef WMR_DEBUG
1144                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
1145                             dsa->target, dsa->lun);
1146 #endif
1147                 }
1148         }
1149         /* clear the dma fifo */
1150         n->ctest3 |= (1 << 2);
1151         /* wait till done */
1152         while ((n->dstat & Dfe) == 0)
1153                 ;
1154         return dbc + inchip;
1155 }
1156
1157 static void
1158 sd53c8xxinterrupt(Ureg *ur, void *a)
1159 {
1160         uchar istat, dstat;
1161         ushort sist;
1162         int wakeme = 0;
1163         int cont = -1;
1164         Dsa *dsa;
1165         ulong dsapa;
1166         Controller *c = a;
1167         Ncr *n = c->n;
1168
1169         USED(ur);
1170         if (DEBUG(1)) {
1171                 IPRINT(PRINTPREFIX "int\n");
1172         }
1173         ilock(c);
1174         istat = n->istat;
1175         if (istat & Intf) {
1176                 Dsa *d;
1177                 int wokesomething = 0;
1178                 if (DEBUG(1)) {
1179                         IPRINT(PRINTPREFIX "Intfly\n");
1180                 }
1181                 n->istat = Intf;
1182                 /* search for structures in A_STATE_DONE */
1183                 for (d = KPTR(legetl(c->dsalist.head)); d != nil && d != dsaend; d = KPTR(legetl(d->next))) {
1184                         if (d->stateb == A_STATE_DONE) {
1185                                 d->p9status = d->status;
1186                                 if (DEBUG(1)) {
1187                                         IPRINT(PRINTPREFIX "waking up dsa %#p\n", d);
1188                                 }
1189                                 wakeup(d);
1190                                 wokesomething = 1;
1191                         }
1192                 }
1193                 if (!wokesomething) {
1194                         IPRINT(PRINTPREFIX "nothing to wake up\n");
1195                 }
1196         }
1197
1198         if ((istat & (Sip | Dip)) == 0) {
1199                 if (DEBUG(1)) {
1200                         IPRINT(PRINTPREFIX "int end %x\n", istat);
1201                 }
1202                 iunlock(c);
1203                 return;
1204         }
1205
1206         sist = (n->sist1<<8)|n->sist0;  /* BUG? can two-byte read be inconsistent? */
1207         dstat = n->dstat;
1208         dsapa = legetl(n->dsa);
1209
1210         /*
1211          * Can't compute dsa until we know that dsapa is valid.
1212          */
1213         if(DMASEG_TO_PADDR(dsapa) < -KZERO)
1214                 dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
1215         else{
1216                 dsa = nil;
1217                 /*
1218                  * happens at startup on some cards but we
1219                  * don't actually deref dsa because none of the
1220                  * flags we are about are set.
1221                  * still, print in case that changes and we're
1222                  * about to dereference nil.
1223                  */
1224                 iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
1225         }
1226
1227         c->running = 0;
1228         if (istat & Sip) {
1229                 if (DEBUG(1)) {
1230                         IPRINT("sist = %.4x\n", sist);
1231                 }
1232                 if (sist & 0x80) {
1233                         ulong addr;
1234                         ulong sa;
1235                         ulong dbc;
1236                         ulong tbc;
1237                         int dmablks;
1238                         ulong dmaaddr;
1239
1240                         addr = legetl(n->dsp);
1241                         sa = addr - c->scriptpa;
1242                         if (DEBUG(1) || DEBUG(2)) {
1243                                 IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
1244                                     dsa->target, dsa->lun, sa);
1245                         }
1246                         /*
1247                          * now recover
1248                          */
1249                         if (sa == E_data_in_mismatch) {
1250                                 /*
1251                                  * though this is a failure in the residue, there may have been blocks
1252                                  * as well. if so, dmablks will not have been zeroed, since the state
1253                                  * was not saved by the microcode.
1254                                  */
1255                                 dbc = read_mismatch_recover(c, n, dsa);
1256                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
1257                                 dsa->dmablks = 0;
1258                                 n->scratcha[2] = 0;
1259                                 advancedata(&dsa->data_buf, tbc);
1260                                 if (DEBUG(1) || DEBUG(2)) {
1261                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
1262                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
1263                                 }
1264                                 cont = E_data_mismatch_recover;
1265                         }
1266                         else if (sa == E_data_in_block_mismatch) {
1267                                 dbc = read_mismatch_recover(c, n, dsa);
1268                                 tbc = A_BSIZE - dbc;
1269                                 /* recover current state from registers */
1270                                 dmablks = n->scratcha[2];
1271                                 dmaaddr = legetl(n->scratchb);
1272                                 /* we have got to dmaaddr + tbc */
1273                                 /* we have dmablks * A_BSIZE - tbc + residue left to do */
1274                                 /* so remaining transfer is */
1275                                 IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
1276                                     dmaaddr, tbc, dmablks);
1277                                 calcblockdma(dsa, dmaaddr + tbc,
1278                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
1279                                 /* copy changes into scratch registers */
1280                                 IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
1281                                     dsa->dmablks, legetl(dsa->dmaaddr),
1282                                     legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
1283                                 n->scratcha[2] = dsa->dmablks;
1284                                 lesetl(n->scratchb, *((ulong*)dsa->dmaaddr));
1285                                 cont = E_data_block_mismatch_recover;
1286                         }
1287                         else if (sa == E_data_out_mismatch) {
1288                                 dbc = write_mismatch_recover(c, n, dsa);
1289                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
1290                                 dsa->dmablks = 0;
1291                                 n->scratcha[2] = 0;
1292                                 advancedata(&dsa->data_buf, tbc);
1293                                 if (DEBUG(1) || DEBUG(2)) {
1294                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
1295                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
1296                                 }
1297                                 cont = E_data_mismatch_recover;
1298                         }
1299                         else if (sa == E_data_out_block_mismatch) {
1300                                 dbc = write_mismatch_recover(c, n, dsa);
1301                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
1302                                 /* recover current state from registers */
1303                                 dmablks = n->scratcha[2];
1304                                 dmaaddr = legetl(n->scratchb);
1305                                 /* we have got to dmaaddr + tbc */
1306                                 /* we have dmablks blocks - tbc + residue left to do */
1307                                 /* so remaining transfer is */
1308                                 IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
1309                                     dmaaddr, tbc, dmablks);
1310                                 calcblockdma(dsa, dmaaddr + tbc,
1311                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
1312                                 /* copy changes into scratch registers */
1313                                 n->scratcha[2] = dsa->dmablks;
1314                                 lesetl(n->scratchb, *((ulong*)dsa->dmaaddr));
1315                                 cont = E_data_block_mismatch_recover;
1316                         }
1317                         else if (sa == E_id_out_mismatch) {
1318                                 /*
1319                                  * target switched phases while attention held during
1320                                  * message out. The possibilities are:
1321                                  * 1. It didn't like the last message. This is indicated
1322                                  *    by the new phase being message_in. Use script to recover
1323                                  *
1324                                  * 2. It's not SCSI-II compliant. The new phase will be other
1325                                  *    than message_in. We should also indicate that the device
1326                                  *    is asynchronous, if it's the SDTR that got ignored
1327                                  *
1328                                  * For now, if the phase switch is not to message_in, and
1329                                  * and it happens after IDENTIFY and before SDTR, we
1330                                  * notify the negotiation state machine.
1331                                  */
1332                                 ulong lim = legetl(dsa->msg_out_buf.dbc);
1333                                 uchar p = n->sstat1 & 7;
1334                                 dbc = write_mismatch_recover(c, n, dsa);
1335                                 tbc = lim - dbc;
1336                                 IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
1337                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
1338                                 if (p != MessageIn && tbc == 1) {
1339                                         msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
1340                                 }
1341                                 else
1342                                         cont = E_id_out_mismatch_recover;
1343                         }
1344                         else if (sa == E_cmd_out_mismatch) {
1345                                 /*
1346                                  * probably the command count is longer than the device wants ...
1347                                  */
1348                                 ulong lim = legetl(dsa->cmd_buf.dbc);
1349                                 uchar p = n->sstat1 & 7;
1350                                 dbc = write_mismatch_recover(c, n, dsa);
1351                                 tbc = lim - dbc;
1352                                 IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
1353                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
1354                                 USED(p, tbc);
1355                                 cont = E_to_decisions;
1356                         }
1357                         else {
1358                                 IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
1359                                     dsa->target, dsa->lun, sa,
1360                                     phase[n->dcmd & 7],
1361                                     phase[n->sstat1 & 7]);
1362                                 dumpncrregs(c, 1);
1363                                 dsa->p9status = SDeio;  /* chf */
1364                                 wakeme = 1;
1365                         }
1366                 }
1367                 /*else*/ if (sist & 0x400) {
1368                         if (DEBUG(0)) {
1369                                 IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
1370                         }
1371                         dsa->p9status = SDtimeout;
1372                         dsa->stateb = A_STATE_DONE;
1373                         coherence();
1374                         softreset(c);
1375                         cont = E_issue_check;
1376                         wakeme = 1;
1377                 }
1378                 if (sist & 0x1) {
1379                         IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
1380                         dsa->parityerror = 1;
1381                 }
1382                 if (sist & 0x4) {
1383                         IPRINT(PRINTPREFIX "%s%d lun %d: unexpected disconnect\n",
1384                                 c->sdev->name, dsa->target, dsa->lun);
1385                         dumpncrregs(c, 1);
1386                         //wakeme = 1;
1387                         dsa->p9status = SDeio;
1388                 }
1389         }
1390         if (istat & Dip) {
1391                 if (DEBUG(1)) {
1392                         IPRINT("dstat = %.2x\n", dstat);
1393                 }
1394                 /*else*/ if (dstat & Ssi) {
1395                         ulong w = legetl(n->dsp) - c->scriptpa;
1396                         IPRINT("[%lux]", w);
1397                         USED(w);
1398                         cont = -2;      /* restart */
1399                 }
1400                 if (dstat & Sir) {
1401                         switch (legetl(n->dsps)) {
1402                         case A_SIR_MSG_IO_COMPLETE:
1403                                 dsa->p9status = dsa->status;
1404                                 wakeme = 1;
1405                                 break;
1406                         case A_SIR_MSG_SDTR:
1407                         case A_SIR_MSG_WDTR:
1408                         case A_SIR_MSG_REJECT:
1409                         case A_SIR_EV_RESPONSE_OK:
1410                                 msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
1411                                 break;
1412                         case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
1413                                 /* back up one in the data transfer */
1414                                 IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
1415                                     dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
1416                                 if (dsa->flag == 2) {
1417                                         IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
1418                                             dsa->target, dsa->lun);
1419                                 }
1420                                 else {
1421                                         calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
1422                                             dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
1423                                 }
1424                                 cont = -2;
1425                                 break;
1426                         case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
1427                                 IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
1428                                     n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
1429                                 dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
1430                                 dumpncrregs(c, 1);
1431                                 wakeme = 1;
1432                                 break;
1433                         case A_SIR_NOTIFY_LOAD_STATE:
1434                                 IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
1435                                 if (dsa == nil) {
1436                                         dsadump(c);
1437                                         dumpncrregs(c, 1);
1438                                         panic("bad dsa in load_state");
1439                                 }
1440                                 cont = -2;
1441                                 break;
1442                         case A_SIR_NOTIFY_MSG_IN:
1443                                 IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
1444                                     dsa->target, dsa->lun, n->sfbr);
1445                                 cont = -2;
1446                                 break;
1447                         case A_SIR_NOTIFY_DISC:
1448                                 IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
1449                                 goto dsadump;
1450                         case A_SIR_NOTIFY_STATUS:
1451                                 IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
1452                                 cont = -2;
1453                                 break;
1454                         case A_SIR_NOTIFY_COMMAND:
1455                                 IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
1456                                 cont = -2;
1457                                 break;
1458                         case A_SIR_NOTIFY_DATA_IN:
1459                                 IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
1460                                     dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
1461                                 cont = -2;
1462                                 break;
1463                         case A_SIR_NOTIFY_BLOCK_DATA_IN:
1464                                 IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
1465                                     dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
1466                                 cont = -2;
1467                                 break;
1468                         case A_SIR_NOTIFY_DATA_OUT:
1469                                 IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
1470                                 cont = -2;
1471                                 break;
1472                         case A_SIR_NOTIFY_DUMP:
1473                                 IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
1474                                 dumpncrregs(c, 1);
1475                                 cont = -2;
1476                                 break;
1477                         case A_SIR_NOTIFY_DUMP2:
1478                                 IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
1479                                 IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
1480                                 IPRINT(" dsa %lux", legetl(n->dsa));
1481                                 IPRINT(" sfbr %ux", n->sfbr);
1482                                 IPRINT(" a %lux", legetl(n->scratcha));
1483                                 IPRINT(" b %lux", legetl(n->scratchb));
1484                                 IPRINT(" ssid %ux", n->ssid);
1485                                 IPRINT("\n");
1486                                 cont = -2;
1487                                 break;
1488                         case A_SIR_NOTIFY_WAIT_RESELECT:
1489                                 IPRINT(PRINTPREFIX "wait reselect\n");
1490                                 cont = -2;
1491                                 break;
1492                         case A_SIR_NOTIFY_RESELECT:
1493                                 IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
1494                                     n->ssid, n->sfbr, TK2MS(m->ticks));
1495                                 cont = -2;
1496                                 break;
1497                         case A_SIR_NOTIFY_ISSUE:
1498                                 IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
1499                         dsadump:
1500                                 IPRINT(" tgt=%d", dsa->target);
1501                                 IPRINT(" time=%ld", TK2MS(m->ticks));
1502                                 IPRINT("\n");
1503                                 cont = -2;
1504                                 break;
1505                         case A_SIR_NOTIFY_ISSUE_CHECK:
1506                                 IPRINT(PRINTPREFIX "issue check\n");
1507                                 cont = -2;
1508                                 break;
1509                         case A_SIR_NOTIFY_SIGP:
1510                                 IPRINT(PRINTPREFIX "responded to SIGP\n");
1511                                 cont = -2;
1512                                 break;
1513                         case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
1514                                 ulong *dsp = &c->script[(legetl(n->dsp)-c->scriptpa)/4];
1515                                 int x;
1516                                 IPRINT(PRINTPREFIX "code at %lux", (ulong)(dsp - c->script));
1517                                 for (x = 0; x < 6; x++) {
1518                                         IPRINT(" %.8lux", dsp[x]);
1519                                 }
1520                                 IPRINT("\n");
1521                                 USED(dsp);
1522                                 cont = -2;
1523                                 break;
1524                         }
1525                         case A_SIR_NOTIFY_WSR:
1526                                 IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
1527                                 cont = -2;
1528                                 break;
1529                         case A_SIR_NOTIFY_LOAD_SYNC:
1530                                 IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
1531                                     dsa->target, dsa->lun, n->scntl3, n->sxfer);
1532                                 cont = -2;
1533                                 break;
1534                         case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
1535                                 if (DEBUG(2)) {
1536                                         IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
1537                                             dsa->target, dsa->lun);
1538                                 }
1539                                 cont = -2;
1540                                 break;
1541                         case A_error_reselected:                /* dsa isn't valid here */
1542                                 iprint(PRINTPREFIX "reselection error\n");
1543                                 dumpncrregs(c, 1);
1544                                 for (dsa = KPTR(legetl(c->dsalist.head)); dsa != nil && dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
1545                                         IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
1546                                 }
1547                                 break;
1548                         default:
1549                                 IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
1550                                         dsa->target, dsa->lun, legetl(n->dsps));
1551                                 dumpncrregs(c, 1);
1552                                 wakeme = 1;
1553                         }
1554                 }
1555                 /*else*/ if (dstat & Iid) {
1556                         int i, target, lun;
1557                         ulong addr, dbc, *v;
1558
1559                         addr = legetl(n->dsp);
1560                         if(dsa){
1561                                 target = dsa->target;
1562                                 lun = dsa->lun;
1563                         }else{
1564                                 target = -1;
1565                                 lun = -1;
1566                         }
1567                         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1568
1569                 //      if(dsa == nil)
1570                                 idebug++;
1571                         IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
1572                             target, lun,
1573                             addr, addr - c->scriptpa, dbc);
1574                         addr -= c->scriptpa;
1575                         addr -= 64;
1576                         addr &= ~63;
1577                         v = &c->script[addr/4];
1578                         for(i=0; i<8; i++){
1579                                 IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n",
1580                                         addr, v[0], v[1], v[2], v[3]);
1581                                 addr += 4*4;
1582                                 v += 4;
1583                         }
1584                         USED(addr, dbc);
1585                         if(dsa == nil){
1586                                 dsadump(c);
1587                                 dumpncrregs(c, 1);
1588                                 panic("bad dsa");
1589                         }
1590                         dsa->p9status = SDeio;
1591                         wakeme = 1;
1592                 }
1593                 /*else*/ if (dstat & Bf) {
1594                         IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
1595                         dumpncrregs(c, 1);
1596                         dsa->p9status = SDeio;
1597                         wakeme = 1;
1598                 }
1599         }
1600         if (cont == -2)
1601                 ncrcontinue(c);
1602         else if (cont >= 0)
1603                 start(c, cont);
1604         if (wakeme){
1605                 if(dsa->p9status == SDnostatus)
1606                         dsa->p9status = SDeio;
1607                 wakeup(dsa);
1608         }
1609         iunlock(c);
1610         if (DEBUG(1)) {
1611                 IPRINT(PRINTPREFIX "int end 1\n");
1612         }
1613 }
1614
1615 static int
1616 done(void *arg)
1617 {
1618         return ((Dsa *)arg)->p9status != SDnostatus;
1619 }
1620
1621 static void
1622 setmovedata(Movedata *d, ulong pa, ulong bc)
1623 {
1624         d->pa[0] = pa;
1625         d->pa[1] = pa>>8;
1626         d->pa[2] = pa>>16;
1627         d->pa[3] = pa>>24;
1628         d->dbc[0] = bc;
1629         d->dbc[1] = bc>>8;
1630         d->dbc[2] = bc>>16;
1631         d->dbc[3] = bc>>24;
1632 }
1633
1634 static void
1635 advancedata(Movedata *d, long v)
1636 {
1637         lesetl(d->pa, legetl(d->pa) + v);
1638         lesetl(d->dbc, legetl(d->dbc) - v);
1639 }
1640
1641 static void
1642 dumpwritedata(uchar *data, int datalen)
1643 {
1644         int i;
1645         uchar *bp;
1646         if (!DEBUG(0)){
1647                 USED(data, datalen);
1648                 return;
1649         }
1650
1651         if (datalen) {
1652                 KPRINT(PRINTPREFIX "write:");
1653                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
1654                         KPRINT("%.2ux", *bp);
1655                 }
1656                 if (i < datalen) {
1657                         KPRINT("...");
1658                 }
1659                 KPRINT("\n");
1660         }
1661 }
1662
1663 static void
1664 dumpreaddata(uchar *data, int datalen)
1665 {
1666         int i;
1667         uchar *bp;
1668         if (!DEBUG(0)){
1669                 USED(data, datalen);
1670                 return;
1671         }
1672
1673         if (datalen) {
1674                 KPRINT(PRINTPREFIX "read:");
1675                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
1676                         KPRINT("%.2ux", *bp);
1677                 }
1678                 if (i < datalen) {
1679                         KPRINT("...");
1680                 }
1681                 KPRINT("\n");
1682         }
1683 }
1684
1685 static void
1686 busreset(Controller *c)
1687 {
1688         int x, ntarget;
1689
1690         /* bus reset */
1691         c->n->scntl1 |= (1 << 3);
1692         delay(500);
1693         c->n->scntl1 &= ~(1 << 3);
1694         if(!(c->v->feature & Wide))
1695                 ntarget = 8;
1696         else
1697                 ntarget = MAXTARGET;
1698         for (x = 0; x < ntarget; x++) {
1699                 setwide(0, c, x, 0);
1700 #ifndef ASYNC_ONLY
1701                 c->s[x] = NeitherDone;
1702 #endif
1703         }
1704         c->capvalid = 0;
1705 }
1706
1707 static void
1708 reset(Controller *c)
1709 {
1710         /* should wakeup all pending tasks */
1711         softreset(c);
1712         busreset(c);
1713 }
1714
1715 static int
1716 sd53c8xxrio(SDreq* r)
1717 {
1718         Dsa *d;
1719         uchar *bp;
1720         Controller *c;
1721         uchar target_expo, my_expo;
1722         int bc, check, i, status, target;
1723
1724         if((target = r->unit->subno) == 0x07)
1725                 return r->status = SDtimeout;   /* assign */
1726
1727         c = r->unit->dev->ctlr;
1728
1729         check = 0;
1730         d = dsaalloc(c, target, r->lun);
1731
1732         qlock(&c->q[target]);                   /* obtain access to target */
1733 docheck:
1734         /* load the transfer control stuff */
1735         d->scsi_id_buf[0] = 0;
1736         d->scsi_id_buf[1] = c->sxfer[target];
1737         d->scsi_id_buf[2] = target;
1738         d->scsi_id_buf[3] = c->scntl3[target];
1739         synctodsa(d, c);
1740
1741         bc = 0;
1742
1743         d->msg_out[bc] = 0x80 | r->lun;
1744
1745 #ifndef NO_DISCONNECT
1746         d->msg_out[bc] |= (1 << 6);
1747 #endif
1748         bc++;
1749
1750         /* work out what to do about negotiation */
1751         switch (c->s[target]) {
1752         default:
1753                 KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
1754                 c->s[target] = NeitherDone;
1755                 /* fall through */
1756         case NeitherDone:
1757                 if ((c->capvalid & (1 << target)) == 0)
1758                         break;
1759                 target_expo = (c->cap[target] >> 5) & 3;
1760                 my_expo = (c->v->feature & Wide) != 0;
1761                 if (target_expo < my_expo)
1762                         my_expo = target_expo;
1763 #ifdef ALWAYS_DO_WDTR
1764                 bc += buildwdtrmsg(d->msg_out + bc, my_expo);
1765                 KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
1766                 c->s[target] = WideInit;
1767                 break;
1768 #else
1769                 if (my_expo) {
1770                         bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
1771                         KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
1772                         c->s[target] = WideInit;
1773                         break;
1774                 }
1775                 KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
1776                 /* fall through */
1777 #endif
1778         case WideDone:
1779                 if (c->cap[target] & (1 << 4)) {
1780                         KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
1781                         bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
1782                         c->s[target] = SyncInit;
1783                         break;
1784                 }
1785                 KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
1786                 c->s[target] = BothDone;
1787                 break;
1788
1789         case BothDone:
1790                 break;
1791         }
1792
1793         setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
1794         setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
1795         calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
1796
1797         if (DEBUG(0)) {
1798                 KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
1799                 for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
1800                         KPRINT("%.2ux", *bp);
1801                 }
1802                 KPRINT("\n");
1803                 if (!r->write) {
1804                         KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
1805                           target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
1806                 }
1807                 else
1808                         dumpwritedata(r->data, r->dlen);
1809         }
1810
1811         setmovedata(&d->status_buf, DMASEG(&d->status), 1);
1812
1813         d->p9status = SDnostatus;
1814         d->parityerror = 0;
1815         coherence();
1816         d->stateb = A_STATE_ISSUE;              /* start operation */
1817         coherence();
1818
1819         ilock(c);
1820         if (c->ssm)
1821                 c->n->dcntl |= 0x10;            /* single step */
1822         if (c->running) {
1823                 c->n->istat = Sigp;
1824         }
1825         else {
1826                 start(c, E_issue_check);
1827         }
1828         iunlock(c);
1829
1830         while(waserror())
1831                 ;
1832         tsleep(d, done, d, 600 * 1000);
1833         poperror();
1834
1835         if (!done(d)) {
1836                 KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
1837                 dumpncrregs(c, 0);
1838                 dsafree(c, d);
1839                 reset(c);
1840                 qunlock(&c->q[target]);
1841                 r->status = SDtimeout;
1842                 return r->status = SDtimeout;   /* assign */
1843         }
1844
1845         if((status = d->p9status) == SDeio)
1846                 c->s[target] = NeitherDone;
1847         if (d->parityerror) {
1848                 status = SDeio;
1849         }
1850
1851         /*
1852          * adjust datalen
1853          */
1854         r->rlen = r->dlen;
1855         if (DEBUG(0)) {
1856                 KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
1857                     target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
1858         }
1859         r->rlen = r->dlen;
1860         if (d->flag != 2) {
1861                 r->rlen -= d->dmablks * A_BSIZE;
1862                 r->rlen -= legetl(d->data_buf.dbc);
1863         }
1864         if(!r->write)
1865                 dumpreaddata(r->data, r->rlen);
1866         if (DEBUG(0)) {
1867                 KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
1868                     target, r->lun, d->p9status, status, r->rlen);
1869         }
1870         /*
1871          * spot the identify
1872          */
1873         if ((c->capvalid & (1 << target)) == 0
1874          && (status == SDok || status == SDcheck)
1875          && r->cmd[0] == 0x12 && r->dlen >= 8) {
1876                 c->capvalid |= 1 << target;
1877                 bp = r->data;
1878                 c->cap[target] = bp[7];
1879                 KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
1880         }
1881         if(!check && status == SDcheck && !(r->flags & SDnosense)){
1882                 check = 1;
1883                 r->write = 0;
1884                 memset(r->cmd, 0, sizeof(r->cmd));
1885                 r->cmd[0] = 0x03;
1886                 r->cmd[1] = r->lun<<5;
1887                 r->cmd[4] = sizeof(r->sense)-1;
1888                 r->clen = 6;
1889                 r->data = r->sense;
1890                 r->dlen = sizeof(r->sense)-1;
1891                 /*
1892                  * Clear out the microcode state
1893                  * so the Dsa can be re-used.
1894                  */
1895                 lesetl(&d->stateb, A_STATE_ALLOCATED);
1896                 coherence();
1897                 goto docheck;
1898         }
1899         qunlock(&c->q[target]);
1900         dsafree(c, d);
1901
1902         if(status == SDok && check){
1903                 status = SDcheck;
1904                 r->flags |= SDvalidsense;
1905         }
1906         if(DEBUG(0))
1907                 KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
1908                         target, r->flags, status, r->rlen);
1909         if(r->flags & SDvalidsense){
1910                 if(!DEBUG(0))
1911                         KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
1912                                 target, r->flags, status, r->rlen);
1913                 for(i = 0; i < r->rlen; i++)
1914                         KPRINT(" %2.2uX", r->sense[i]);
1915                 KPRINT("\n");
1916         }
1917         return r->status = status;
1918 }
1919
1920 static void
1921 cribbios(Controller *c)
1922 {
1923         c->bios.scntl3 = c->n->scntl3;
1924         c->bios.stest2 = c->n->stest2;
1925         print(PRINTPREFIX "%s: bios scntl3(%.2x) stest2(%.2x)\n",
1926                 c->sdev->name, c->bios.scntl3, c->bios.stest2);
1927 }
1928
1929 static int
1930 bios_set_differential(Controller *c)
1931 {
1932         /* Concept lifted from FreeBSD - thanks Gerard */
1933         /* basically, if clock conversion factors are set, then there is
1934          * evidence the bios had a go at the chip, and if so, it would
1935          * have set the differential enable bit in stest2
1936          */
1937         return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
1938 }
1939
1940 #define NCR_VID         0x1000
1941 #define NCR_810_DID     0x0001
1942 #define NCR_820_DID     0x0002  /* don't know enough about this one to support it */
1943 #define NCR_825_DID     0x0003
1944 #define NCR_815_DID     0x0004
1945 #define SYM_810AP_DID   0x0005
1946 #define SYM_860_DID     0x0006
1947 #define SYM_896_DID     0x000b
1948 #define SYM_895_DID     0x000c
1949 #define SYM_885_DID     0x000d  /* ditto */
1950 #define SYM_875_DID     0x000f  /* ditto */
1951 #define SYM_1010_DID    0x0020
1952 #define SYM_1011_DID    0x0021
1953 #define SYM_875J_DID    0x008f
1954
1955 static Variant variant[] = {
1956 { NCR_810_DID,   0x0f, "NCR53C810",     Burst16,   8, 24, 0 },
1957 { NCR_810_DID,   0x1f, "SYM53C810ALV",  Burst16,   8, 24, Prefetch },
1958 { NCR_810_DID,   0xff, "SYM53C810A",    Burst16,   8, 24, Prefetch },
1959 { SYM_810AP_DID, 0xff, "SYM53C810AP",   Burst16,   8, 24, Prefetch },
1960 { NCR_815_DID,   0xff, "NCR53C815",     Burst16,   8, 24, BurstOpCodeFetch },
1961 { NCR_825_DID,   0x0f, "NCR53C825",     Burst16,   8, 24, Wide|BurstOpCodeFetch|Differential },
1962 { NCR_825_DID,   0xff, "SYM53C825A",    Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
1963 { SYM_860_DID,   0x0f, "SYM53C860",     Burst16,   8, 24, Prefetch|Ultra },
1964 { SYM_860_DID,   0xff, "SYM53C860LV",   Burst16,   8, 24, Prefetch|Ultra },
1965 { SYM_875_DID,   0x01, "SYM53C875r1",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
1966 { SYM_875_DID,   0xff, "SYM53C875",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
1967 { SYM_875J_DID,   0xff, "SYM53C875j",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
1968 { SYM_885_DID,   0xff, "SYM53C885",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
1969 { SYM_895_DID,   0xff, "SYM53C895",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1970 { SYM_896_DID,   0xff, "SYM53C896",     Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1971 { SYM_1010_DID,  0xff, "SYM53C1010",    Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1972 { SYM_1011_DID,   0xff, "SYM53C1010",   Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1973 };
1974
1975 static int
1976 xfunc(Controller *c, enum na_external x, unsigned long *v)
1977 {
1978         switch (x) {
1979         default:
1980                 print("xfunc: can't find external %d\n", x);
1981                 return 0;
1982         case X_scsi_id_buf:
1983                 *v = offsetof(Dsa, scsi_id_buf[0]);
1984                 break;
1985         case X_msg_out_buf:
1986                 *v = offsetof(Dsa, msg_out_buf);
1987                 break;
1988         case X_cmd_buf:
1989                 *v = offsetof(Dsa, cmd_buf);
1990                 break;
1991         case X_data_buf:
1992                 *v = offsetof(Dsa, data_buf);
1993                 break;
1994         case X_status_buf:
1995                 *v = offsetof(Dsa, status_buf);
1996                 break;
1997         case X_dsa_head:
1998                 *v = DMASEG(&c->dsalist.head[0]);
1999                 break;
2000         case X_ssid_mask:
2001                 *v = SSIDMASK(c);
2002                 break;
2003         }
2004         return 1;
2005 }
2006
2007 static int
2008 na_fixup(Controller *c, ulong pa_reg,
2009     struct na_patch *patch, int patches,
2010     int (*externval)(Controller*, int, ulong*))
2011 {
2012         int p;
2013         int v;
2014         ulong *script, pa_script;
2015         unsigned long lw, lv;
2016
2017         script = c->script;
2018         pa_script = c->scriptpa;
2019         for (p = 0; p < patches; p++) {
2020                 switch (patch[p].type) {
2021                 case 1:
2022                         /* script relative */
2023                         script[patch[p].lwoff] += pa_script;
2024                         break;
2025                 case 2:
2026                         /* register i/o relative */
2027                         script[patch[p].lwoff] += pa_reg;
2028                         break;
2029                 case 3:
2030                         /* data external */
2031                         lw = script[patch[p].lwoff];
2032                         v = (lw >> 8) & 0xff;
2033                         if (!(*externval)(c, v, &lv))
2034                                 return 0;
2035                         v = lv & 0xff;
2036                         script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
2037                         break;
2038                 case 4:
2039                         /* 32 bit external */
2040                         lw = script[patch[p].lwoff];
2041                         if (!(*externval)(c, lw, &lv))
2042                                 return 0;
2043                         script[patch[p].lwoff] = lv;
2044                         break;
2045                 case 5:
2046                         /* 24 bit external */
2047                         lw = script[patch[p].lwoff];
2048                         if (!(*externval)(c, lw & 0xffffff, &lv))
2049                                 return 0;
2050                         script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
2051                         break;
2052                 }
2053         }
2054         return 1;
2055 }
2056
2057 static SDev*
2058 sd53c8xxpnp(void)
2059 {
2060         char *cp;
2061         Pcidev *p;
2062         Variant *v;
2063         int ba, nctlr;
2064         void *scriptma;
2065         Controller *ctlr;
2066         SDev *sdev, *head, *tail;
2067         uvlong regpa, scriptpa;
2068         ulong *script;
2069         void *regva, *scriptva;
2070
2071         if(cp = getconf("*maxsd53c8xx"))
2072                 nctlr = strtoul(cp, 0, 0);
2073         else
2074                 nctlr = 32;
2075
2076         p = nil;
2077         head = tail = nil;
2078         while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
2079                 for(v = variant; v < &variant[nelem(variant)]; v++){
2080                         if(p->did == v->did && p->rid <= v->maxrid)
2081                                 break;
2082                 }
2083                 if(v >= &variant[nelem(variant)]) {
2084                         print("no match\n");
2085                         continue;
2086                 }
2087                 print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
2088                         v->name, p->rid, p->intl, p->pcr);
2089
2090                 regpa = p->mem[1].bar;
2091                 ba = 2;
2092                 if(regpa & 0x04){
2093                         if(p->mem[2].bar)
2094                                 continue;
2095                         ba++;
2096                 }
2097                 regpa &= ~0xF;
2098                 if(regpa == 0)
2099                         print("regpa 0\n");
2100                 regva = vmap(regpa, p->mem[1].size);
2101                 if(regva == nil){
2102                         print("sd53c8xx: can't map %llux\n", regpa);
2103                         continue;
2104                 }
2105
2106                 script = nil;
2107                 scriptpa = 0;
2108                 scriptva = nil;
2109                 scriptma = nil;
2110                 if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
2111                         scriptpa = p->mem[ba].bar;
2112                         if((scriptpa & 0x04) && p->mem[ba+1].bar){
2113                                 vunmap(regva, p->mem[1].size);
2114                                 continue;
2115                         }
2116                         scriptpa &= ~0x0F;
2117                         scriptva = vmap(scriptpa, p->mem[ba].size);
2118                         if(scriptva != nil)
2119                                 script = scriptva;
2120                 }
2121                 if(scriptpa == 0){
2122                         /*
2123                          * Either the map failed, or this chip does not have
2124                          * local RAM. It will need a copy of the microcode.
2125                          */
2126                         scriptma = malloc(sizeof(na_script));
2127                         if(scriptma == nil){
2128                                 vunmap(regva, p->mem[1].size);
2129                                 continue;
2130                         }
2131                         scriptpa = DMASEG(scriptma);
2132                         script = scriptma;
2133                 }
2134
2135                 ctlr = malloc(sizeof(Controller));
2136                 sdev = malloc(sizeof(SDev));
2137                 if(ctlr == nil || sdev == nil){
2138 buggery:
2139                         if(ctlr)
2140                                 free(ctlr);
2141                         if(sdev)
2142                                 free(sdev);
2143                         if(scriptma)
2144                                 free(scriptma);
2145                         else if(scriptva)
2146                                 vunmap(scriptva, p->mem[ba].size);
2147                         if(regva)
2148                                 vunmap(regva, p->mem[1].size);
2149                         continue;
2150                 }
2151
2152                 lock(&ctlr->dsalist);
2153                 ctlr->dsalist.freechain = nil;
2154                 if(dsaend == nil)
2155                         dsaend = xalloc(sizeof *dsaend);
2156                 if(dsaend == nil)
2157                         panic("sd53c8xxpnp: no memory");
2158                 lesetl(&dsaend->stateb, A_STATE_END);
2159                 lesetl(dsaend->next, DMASEG(dsaend));
2160                 coherence();
2161                 lesetl(ctlr->dsalist.head, DMASEG(dsaend));
2162                 coherence();
2163                 unlock(&ctlr->dsalist);
2164
2165                 ctlr->n = regva;
2166                 ctlr->v = v;
2167                 ctlr->script = script;
2168                 memmove(ctlr->script, na_script, sizeof(na_script));
2169
2170                 /*
2171                  * Because we don't yet have an abstraction for the
2172                  * addresses as seen from the controller side (and on
2173                  * the 386 it doesn't matter), the following two lines
2174                  * are different between the 386 and alpha copies of
2175                  * this driver.
2176                  */
2177                 ctlr->scriptpa = scriptpa;
2178                 if(!na_fixup(ctlr, regpa, na_patches, NA_PATCHES, xfunc)){
2179                         print("script fixup failed\n");
2180                         goto buggery;
2181                 }
2182                 swabl(ctlr->script, ctlr->script, sizeof(na_script));
2183
2184                 ctlr->pcidev = p;
2185
2186                 sdev->ifc = &sd53c8xxifc;
2187                 sdev->ctlr = ctlr;
2188                 sdev->idno = '0';
2189                 if(!(v->feature & Wide))
2190                         sdev->nunit = 8;
2191                 else
2192                         sdev->nunit = MAXTARGET;
2193                 ctlr->sdev = sdev;
2194
2195                 if(head != nil)
2196                         tail->next = sdev;
2197                 else
2198                         head = sdev;
2199                 tail = sdev;
2200
2201                 nctlr--;
2202         }
2203
2204         return head;
2205 }
2206
2207 static int
2208 sd53c8xxenable(SDev* sdev)
2209 {
2210         Pcidev *pcidev;
2211         Controller *ctlr;
2212         char name[32];
2213
2214         ctlr = sdev->ctlr;
2215         pcidev = ctlr->pcidev;
2216
2217         pcisetbme(pcidev);
2218
2219         ilock(ctlr);
2220         synctabinit(ctlr);
2221         cribbios(ctlr);
2222         reset(ctlr);
2223         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2224         intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
2225         iunlock(ctlr);
2226
2227         return 1;
2228 }
2229
2230 SDifc sd53c8xxifc = {
2231         "53c8xx",                       /* name */
2232
2233         sd53c8xxpnp,                    /* pnp */
2234         nil,                            /* legacy */
2235         sd53c8xxenable,                 /* enable */
2236         nil,                            /* disable */
2237
2238         scsiverify,                     /* verify */
2239         scsionline,                     /* online */
2240         sd53c8xxrio,                    /* rio */
2241         nil,                            /* rctl */
2242         nil,                            /* wctl */
2243
2244         scsibio,                        /* bio */
2245         nil,                            /* probe */
2246         nil,                            /* clear */
2247         nil,                            /* rtopctl */
2248         nil,                            /* wtopctl */
2249 };