sys/src/9/pc/sd53c8xx.c

   1 /*
   2  * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
   3  * Nigel Roles (nigel@9fs.org)
   4  *
   5  * 27/5/02      Fixed problems with transfers >= 256 * 512
   6  *
   7  * 13/3/01      Fixed microcode to support targets > 7
   8  *
   9  * 01/12/00     Removed previous comments. Fixed a small problem in
  10  *                      mismatch recovery for targets with synchronous offsets of >=16
  11  *                      connected to >=875s. Thanks, Jean.
  12  *
  13  * Known problems
  14  *
  15  * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
  16  */
  17
  18 #define MAXTARGET       16              /* can be 8 or 16 */
  19
  20 #include "u.h"
  21 #include "../port/lib.h"
  22 #include "mem.h"
  23 #include "dat.h"
  24 #include "fns.h"
  25 #include "io.h"
  26
  27 #include "../port/sd.h"
  28 extern SDifc sd53c8xxifc;
  29
  30 /**********************************/
  31 /* Portable configuration macros  */
  32 /**********************************/
  33
  34 #define WMR_DEBUG
  35
  36 /**********************************/
  37 /* CPU specific macros            */
  38 /**********************************/
  39
  40 #define PRINTPREFIX "sd53c8xx: "
  41
  42 static int idebug = 0;
  43 #define KPRINT  if(0) iprint
  44 #define IPRINT  if(idebug) iprint
  45 #define DEBUG(n) (0)
  46 #define IFLUSH()
  47
  48 /*******************************/
  49 /* General                     */
  50 /*******************************/
  51
  52 #define DMASEG(x) PCIWADDR(x)
  53 #define legetl(x) (*(ulong*)(x))
  54 #define lesetl(x,v) (*(ulong*)(x) = (v))
  55 #define swabl(a,b,c)
  56 #define DMASEG_TO_PADDR(x) ((uintptr)(x)-PCIWINDOW)
  57 #define DMASEG_TO_KADDR(x) KADDR(DMASEG_TO_PADDR(x))
  58 #define KPTR(x) (((x) == 0) ? nil : DMASEG_TO_KADDR(x))
  59
  60 #define MEGA 1000000L
  61 #ifdef INTERNAL_SCLK
  62 #define SCLK (33 * MEGA)
  63 #else
  64 #define SCLK (40 * MEGA)
  65 #endif /* INTERNAL_SCLK */
  66 #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
  67
  68 #define MAXSYNCSCSIRATE (5 * MEGA)
  69 #define MAXFASTSYNCSCSIRATE (10 * MEGA)
  70 #define MAXULTRASYNCSCSIRATE (20 * MEGA)
  71 #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
  72 #define MAXASYNCCORERATE (25 * MEGA)
  73 #define MAXSYNCCORERATE (25 * MEGA)
  74 #define MAXFASTSYNCCORERATE (50 * MEGA)
  75 #define MAXULTRASYNCCORERATE (80 * MEGA)
  76 #define MAXULTRA2SYNCCORERATE (160 * MEGA)
  77
  78
  79 #define X_MSG   1
  80 #define X_MSG_SDTR 1
  81 #define X_MSG_WDTR 3
  82
  83 struct na_patch {
  84         unsigned lwoff;
  85         unsigned char type;
  86 };
  87
  88 typedef struct Ncr {
  89         uchar scntl0;   /* 00 */
  90         uchar scntl1;
  91         uchar scntl2;
  92         uchar scntl3;
  93
  94         uchar scid;     /* 04 */
  95         uchar sxfer;
  96         uchar sdid;
  97         uchar gpreg;
  98
  99         uchar sfbr;     /* 08 */
 100         uchar socl;
 101         uchar ssid;
 102         uchar sbcl;
 103
 104         uchar dstat;    /* 0c */
 105         uchar sstat0;
 106         uchar sstat1;
 107         uchar sstat2;
 108
 109         uchar dsa[4];   /* 10 */
 110
 111         uchar istat;    /* 14 */
 112         uchar istatpad[3];
 113
 114         uchar ctest0;   /* 18 */
 115         uchar ctest1;
 116         uchar ctest2;
 117         uchar ctest3;
 118
 119         uchar temp[4];  /* 1c */
 120
 121         uchar dfifo;    /* 20 */
 122         uchar ctest4;
 123         uchar ctest5;
 124         uchar ctest6;
 125
 126         uchar dbc[3];   /* 24 */
 127         uchar dcmd;     /* 27 */
 128
 129         uchar dnad[4];  /* 28 */
 130         uchar dsp[4];   /* 2c */
 131         uchar dsps[4];  /* 30 */
 132
 133         uchar scratcha[4];      /* 34 */
 134
 135         uchar dmode;    /* 38 */
 136         uchar dien;
 137         uchar dwt;
 138         uchar dcntl;
 139
 140         uchar adder[4]; /* 3c */
 141
 142         uchar sien0;    /* 40 */
 143         uchar sien1;
 144         uchar sist0;
 145         uchar sist1;
 146
 147         uchar slpar;    /* 44 */
 148         uchar slparpad0;
 149         uchar macntl;
 150         uchar gpcntl;
 151
 152         uchar stime0;   /* 48 */
 153         uchar stime1;
 154         uchar respid;
 155         uchar respidpad0;
 156
 157         uchar stest0;   /* 4c */
 158         uchar stest1;
 159         uchar stest2;
 160         uchar stest3;
 161
 162         uchar sidl;     /* 50 */
 163         uchar sidlpad[3];
 164
 165         uchar sodl;     /* 54 */
 166         uchar sodlpad[3];
 167
 168         uchar sbdl;     /* 58 */
 169         uchar sbdlpad[3];
 170
 171         uchar scratchb[4];      /* 5c */
 172 } Ncr;
 173
 174 typedef struct Movedata {
 175         uchar dbc[4];
 176         uchar pa[4];
 177 } Movedata;
 178
 179 typedef enum NegoState {
 180         NeitherDone, WideInit, WideResponse, WideDone,
 181         SyncInit, SyncResponse, BothDone
 182 } NegoState;
 183
 184 typedef enum State {
 185         Allocated, Queued, Active, Done
 186 } State;
 187
 188 typedef struct Dsa Dsa;
 189 struct Dsa {
 190         uchar stateb;
 191         uchar result;
 192         uchar dmablks;
 193         uchar flag;     /* setbyte(state,3,...) */
 194
 195         uchar dmaaddr[4];       /* For block transfer: NCR order (little-endian) */
 196
 197         uchar target;                   /* Target */
 198         uchar pad0[3];
 199
 200         uchar lun;                      /* Logical Unit Number */
 201         uchar pad1[3];
 202
 203         uchar scntl3;                   /* Sync */
 204         uchar sxfer;
 205         uchar pad2[2];
 206
 207         uchar next[4];                  /* chaining for SCRIPT (NCR byte order) */
 208
 209         Dsa     *freechain;             /* chaining for freelist */
 210         Rendez;
 211
 212         uchar scsi_id_buf[4];
 213         Movedata msg_out_buf;
 214         Movedata cmd_buf;
 215         Movedata data_buf;
 216         Movedata status_buf;
 217
 218         uchar msg_out[10];              /* enough to include SDTR */
 219         uchar status;
 220         int p9status;
 221         uchar parityerror;
 222 };
 223
 224 typedef enum Feature {
 225         BigFifo = 1,                    /* 536 byte fifo */
 226         BurstOpCodeFetch = 2,           /* burst fetch opcodes */
 227         Prefetch = 4,                   /* prefetch 8 longwords */
 228         LocalRAM = 8,                   /* 4K longwords of local RAM */
 229         Differential = 16,              /* Differential support */
 230         Wide = 32,                      /* Wide capable */
 231         Ultra = 64,                     /* Ultra capable */
 232         ClockDouble = 128,              /* Has clock doubler */
 233         ClockQuad = 256,                /* Has clock quadrupler (same as Ultra2) */
 234         Ultra2 = 256,
 235 } Feature;
 236
 237 typedef enum Burst {
 238         Burst2 = 0,
 239         Burst4 = 1,
 240         Burst8 = 2,
 241         Burst16 = 3,
 242         Burst32 = 4,
 243         Burst64 = 5,
 244         Burst128 = 6
 245 } Burst;
 246
 247 typedef struct Variant {
 248         ushort did;
 249         uchar maxrid;                   /* maximum allowed revision ID */
 250         char *name;
 251         Burst burst;                    /* codings for max burst */
 252         uchar maxsyncoff;               /* max synchronous offset */
 253         uchar registers;                /* number of 32 bit registers */
 254         unsigned feature;
 255 } Variant;
 256
 257 static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
 258 #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
 259 #define NULTRASCF (NULTRA2SCF - 2)
 260 #define NSCF (NULTRASCF - 1)
 261
 262 typedef struct Controller {
 263         Lock;
 264         struct {
 265                 uchar scntl3;
 266                 uchar stest2;
 267         } bios;
 268         uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
 269         NegoState s[MAXTARGET];
 270         uchar scntl3[MAXTARGET];
 271         uchar sxfer[MAXTARGET];
 272         uchar cap[MAXTARGET];           /* capabilities byte from Identify */
 273         ushort capvalid;                /* bit per target for validity of cap[] */
 274         ushort wide;                    /* bit per target set if wide negotiated */
 275         ulong sclk;                     /* clock speed of controller */
 276         uchar clockmult;                /* set by synctabinit */
 277         uchar ccf;                      /* CCF bits */
 278         uchar tpf;                      /* best tpf value for this controller */
 279         uchar feature;                  /* requested features */
 280         int running;                    /* is the script processor running? */
 281         int ssm;                        /* single step mode */
 282         Ncr *n;                         /* pointer to registers */
 283         Variant *v;                     /* pointer to variant type */
 284         ulong *script;                  /* where the real script is */
 285         ulong scriptpa;                 /* where the real script is */
 286         Pcidev* pcidev;
 287         SDev*   sdev;
 288
 289         struct {
 290                 Lock;
 291                 uchar head[4];          /* head of free list (NCR byte order) */
 292                 Dsa     *freechain;
 293         } dsalist;
 294
 295         QLock q[MAXTARGET];             /* queues for each target */
 296 } Controller;
 297
 298 #define SYNCOFFMASK(c)          (((c)->v->maxsyncoff * 2) - 1)
 299 #define SSIDMASK(c)             (((c)->v->feature & Wide) ? 15 : 7)
 300
 301 /* ISTAT */
 302 enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
 303
 304 /* DSTAT */
 305 enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
 306
 307 /* SSTAT */
 308 enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
 309
 310 static void setmovedata(Movedata*, ulong, ulong);
 311 static void advancedata(Movedata*, long);
 312 static int bios_set_differential(Controller *c);
 313
 314 static char *phase[] = {
 315         "data out", "data in", "command", "status",
 316         "reserved out", "reserved in", "message out", "message in"
 317 };
 318
 319 #ifdef BOOTDEBUG
 320 #define DEBUGSIZE 10240
 321 char debugbuf[DEBUGSIZE];
 322 char *debuglast;
 323
 324 static void
 325 intrprint(char *format, ...)
 326 {
 327         if (debuglast == 0)
 328                 debuglast = debugbuf;
 329         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
 330 }
 331
 332 static void
 333 iflush()
 334 {
 335         int s;
 336         char *endp;
 337         s = splhi();
 338         if (debuglast == 0)
 339                 debuglast = debugbuf;
 340         if (debuglast == debugbuf) {
 341                 splx(s);
 342                 return;
 343         }
 344         endp = debuglast;
 345         splx(s);
 346         screenputs(debugbuf, endp - debugbuf);
 347         s = splhi();
 348         memmove(debugbuf, endp, debuglast - endp);
 349         debuglast -= endp - debugbuf;
 350         splx(s);
 351 }
 352
 353 static void
 354 oprint(char *format, ...)
 355 {
 356         int s;
 357
 358         iflush();
 359         s = splhi();
 360         if (debuglast == 0)
 361                 debuglast = debugbuf;
 362         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
 363         splx(s);
 364         iflush();
 365 }
 366 #endif
 367
 368 #include "../pc/sd53c8xx.i"
 369
 370 /*
 371  * We used to use a linked list of Dsas with nil as the terminator,
 372  * but occasionally the 896 card seems not to notice that the 0
 373  * is really a 0, and then it tries to reference the Dsa at address 0.
 374  * To address this, we use a sentinel dsa that links back to itself
 375  * and has state A_STATE_END.  If the card takes an iteration or
 376  * two to notice that the state says A_STATE_END, that's no big
 377  * deal.  Clearly this isn't the right approach, but I'm just
 378  * stumped.  Even with this, we occasionally get prints about
 379  * "WSR set", usually with about the same frequency that the
 380  * card used to walk past 0.
 381  */
 382 static Dsa *dsaend;
 383
 384 static Dsa *
 385 dsaalloc(Controller *c, int target, int lun)
 386 {
 387         Dsa *d;
 388
 389         ilock(&c->dsalist);
 390         if ((d = c->dsalist.freechain) != nil) {
 391                 c->dsalist.freechain = d->freechain;
 392                 d->freechain = nil;
 393                 if (DEBUG(1))
 394                         IPRINT(PRINTPREFIX "%d/%d: reused dsa %#p\n", target, lun, d);
 395         } else {
 396                 /* c->dsalist must be ilocked */
 397                 d = xalloc(sizeof *d);
 398                 if (d == nil)
 399                         panic("sd53c8xx dsaallocnew: no memory");
 400                 d->freechain = nil;
 401                 lesetl(d->next, legetl(c->dsalist.head));
 402                 lesetl(&d->stateb, A_STATE_FREE);
 403                 coherence();
 404                 lesetl(c->dsalist.head, DMASEG(d));
 405                 coherence();
 406                 if (DEBUG(1))
 407                         IPRINT(PRINTPREFIX "%d/%d: allocated dsa %#p\n", target, lun, d);
 408         }
 409         lesetl(&d->stateb, A_STATE_ALLOCATED);
 410         iunlock(&c->dsalist);
 411         d->target = target;
 412         d->lun = lun;
 413         return d;
 414 }
 415
 416 static void
 417 dsafree(Controller *c, Dsa *d)
 418 {
 419         ilock(&c->dsalist);
 420         d->freechain = c->dsalist.freechain;
 421         c->dsalist.freechain = d;
 422         lesetl(&d->stateb, A_STATE_FREE);
 423         iunlock(&c->dsalist);
 424 }
 425
 426 static void
 427 dsadump(Controller *c)
 428 {
 429         Dsa *d;
 430         u32int *a;
 431
 432         iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
 433         for(d=KPTR(legetl(c->dsalist.head)); d != nil && d != dsaend; d=KPTR(legetl(d->next))){
 434                 a = (u32int*)d;
 435                 iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
 436         }
 437
 438 /*
 439         a = KPTR(c->scriptpa+E_dsa_addr);
 440         iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
 441                 a[0], a[1], a[2], a[3], a[4]);
 442         a = KPTR(c->scriptpa+E_issue_addr);
 443         iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
 444                 a[0], a[1], a[2], a[3], a[4]);
 445
 446         a = KPTR(c->scriptpa+E_issue_test_begin);
 447         e = KPTR(c->scriptpa+E_issue_test_end);
 448         iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
 449
 450         i = 0;
 451         for(; a<e; a++){
 452                 iprint(" %.8ux", *a);
 453                 if(++i%8 == 0)
 454                         iprint("\n");
 455         }
 456         if(i%8)
 457                 iprint("\n");
 458 */
 459 }
 460
 461 static Dsa *
 462 dsafind(Controller *c, uchar target, uchar lun, uchar state)
 463 {
 464         Dsa *d;
 465
 466         for (d = KPTR(legetl(c->dsalist.head)); d != nil && d != dsaend; d = KPTR(legetl(d->next))) {
 467                 if (d->target != 0xff && d->target != target)
 468                         continue;
 469                 if (lun != 0xff && d->lun != lun)
 470                         continue;
 471                 if (state != 0xff && d->stateb != state)
 472                         continue;
 473                 break;
 474         }
 475         return d;
 476 }
 477
 478 static void
 479 dumpncrregs(Controller *c, int intr)
 480 {
 481         int i;
 482         Ncr *n = c->n;
 483         int depth = c->v->registers / 4;
 484
 485         if (intr) {
 486                 IPRINT("sa = %.8lux\n", c->scriptpa);
 487         }
 488         else {
 489                 KPRINT("sa = %.8lux\n", c->scriptpa);
 490         }
 491         for (i = 0; i < depth; i++) {
 492                 int j;
 493                 for (j = 0; j < 4; j++) {
 494                         int k = j * depth + i;
 495                         uchar *p;
 496
 497                         /* display little-endian to make 32-bit values readable */
 498                         p = (uchar*)n+k*4;
 499                         if (intr) {
 500                                 IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
 501                         }
 502                         else {
 503                                 KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
 504                         }
 505                         USED(p);
 506                 }
 507                 if (intr) {
 508                         IPRINT("\n");
 509                 }
 510                 else {
 511                         KPRINT("\n");
 512                 }
 513         }
 514 }
 515
 516 static int
 517 chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
 518 {
 519         /* find lowest entry >= tpf */
 520         int besttpf = 1000;
 521         int bestscfi = 0;
 522         int bestxferp = 0;
 523         int scf, xferp;
 524         int maxscf;
 525
 526         if (c->v->feature & Ultra2)
 527                 maxscf = NULTRA2SCF;
 528         else if (c->v->feature & Ultra)
 529                 maxscf = NULTRASCF;
 530         else
 531                 maxscf = NSCF;
 532
 533         /*
 534          * search large clock factors first since this should
 535          * result in more reliable transfers
 536          */
 537         for (scf = maxscf; scf >= 1; scf--) {
 538                 for (xferp = 0; xferp < 8; xferp++) {
 539                         unsigned char v = c->synctab[scf - 1][xferp];
 540                         if (v == 0)
 541                                 continue;
 542                         if (v >= tpf && v < besttpf) {
 543                                 besttpf = v;
 544                                 bestscfi = scf;
 545                                 bestxferp = xferp;
 546                         }
 547                 }
 548         }
 549         if (besttpf == 1000)
 550                 return 0;
 551         if (scfp)
 552                 *scfp = bestscfi;
 553         if (xferpp)
 554                 *xferpp = bestxferp;
 555         return besttpf;
 556 }
 557
 558 static void
 559 synctabinit(Controller *c)
 560 {
 561         int scf;
 562         unsigned long scsilimit;
 563         int xferp;
 564         unsigned long cr, sr;
 565         int tpf;
 566         int fast;
 567         int maxscf;
 568
 569         if (c->v->feature & Ultra2)
 570                 maxscf = NULTRA2SCF;
 571         else if (c->v->feature & Ultra)
 572                 maxscf = NULTRASCF;
 573         else
 574                 maxscf = NSCF;
 575
 576         /*
 577          * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
 578          * first spin of the 875), assume 80MHz
 579          * otherwise use the internal (33 Mhz) or external (40MHz) default
 580          */
 581
 582         if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
 583                 c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
 584         else
 585                 c->sclk = SCLK;
 586
 587         /*
 588          * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
 589          * invoke the doubler
 590          */
 591
 592         if (SCLK <= 40000000) {
 593                 if (c->v->feature & ClockDouble) {
 594                         c->sclk *= 2;
 595                         c->clockmult = 1;
 596                 }
 597                 else if (c->v->feature & ClockQuad) {
 598                         c->sclk *= 4;
 599                         c->clockmult = 1;
 600                 }
 601                 else
 602                         c->clockmult = 0;
 603         }
 604         else
 605                 c->clockmult = 0;
 606
 607         /* derive CCF from sclk */
 608         /* woebetide anyone with SCLK < 16.7 or > 80MHz */
 609         if (c->sclk <= 25 * MEGA)
 610                 c->ccf = 1;
 611         else if (c->sclk <= 3750000)
 612                 c->ccf = 2;
 613         else if (c->sclk <= 50 * MEGA)
 614                 c->ccf = 3;
 615         else if (c->sclk <= 75 * MEGA)
 616                 c->ccf = 4;
 617         else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
 618                 c->ccf = 5;
 619         else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
 620                 c->ccf = 6;
 621         else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
 622                 c->ccf = 7;
 623
 624         for (scf = 1; scf < maxscf; scf++) {
 625                 /* check for legal core rate */
 626                 /* round up so we run slower for safety */
 627                 cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
 628                 if (cr <= MAXSYNCCORERATE) {
 629                         scsilimit = MAXSYNCSCSIRATE;
 630                         fast = 0;
 631                 }
 632                 else if (cr <= MAXFASTSYNCCORERATE) {
 633                         scsilimit = MAXFASTSYNCSCSIRATE;
 634                         fast = 1;
 635                 }
 636                 else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
 637                         scsilimit = MAXULTRASYNCSCSIRATE;
 638                         fast = 2;
 639                 }
 640                 else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
 641                         scsilimit = MAXULTRA2SYNCSCSIRATE;
 642                         fast = 3;
 643                 }
 644                 else
 645                         continue;
 646                 for (xferp = 11; xferp >= 4; xferp--) {
 647                         int ok;
 648                         int tp;
 649                         /* calculate scsi rate - round up again */
 650                         /* start from sclk for accuracy */
 651                         int totaldivide = xferp * cf2[scf];
 652                         sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
 653                         if (sr > scsilimit)
 654                                 break;
 655                         /*
 656                          * now work out transfer period
 657                          * round down now so that period is pessimistic
 658                          */
 659                         tp = (MEGA * 1000) / sr;
 660                         /*
 661                          * bounds check it
 662                          */
 663                         if (tp < 25 || tp > 255 * 4)
 664                                 continue;
 665                         /*
 666                          * spot stupid special case for Ultra or Ultra2
 667                          * while working out factor
 668                          */
 669                         if (tp == 25)
 670                                 tpf = 10;
 671                         else if (tp == 50)
 672                                 tpf = 12;
 673                         else if (tp < 52)
 674                                 continue;
 675                         else
 676                                 tpf = tp / 4;
 677                         /*
 678                          * now check tpf looks sensible
 679                          * given core rate
 680                          */
 681                         switch (fast) {
 682                         case 0:
 683                                 /* scf must be ccf for SCSI 1 */
 684                                 ok = tpf >= 50 && scf == c->ccf;
 685                                 break;
 686                         case 1:
 687                                 ok = tpf >= 25 && tpf < 50;
 688                                 break;
 689                         case 2:
 690                                 /*
 691                                  * must use xferp of 4, or 5 at a pinch
 692                                  * for an Ultra transfer
 693                                  */
 694                                 ok = xferp <= 5 && tpf >= 12 && tpf < 25;
 695                                 break;
 696                         case 3:
 697                                 ok = xferp == 4 && (tpf == 10 || tpf == 11);
 698                                 break;
 699                         default:
 700                                 ok = 0;
 701                         }
 702                         if (!ok)
 703                                 continue;
 704                         c->synctab[scf - 1][xferp - 4] = tpf;
 705                 }
 706         }
 707
 708 #ifndef NO_ULTRA2
 709         if (c->v->feature & Ultra2)
 710                 tpf = 10;
 711         else
 712 #endif
 713         if (c->v->feature & Ultra)
 714                 tpf = 12;
 715         else
 716                 tpf = 25;
 717         for (; tpf < 256; tpf++) {
 718                 if (chooserate(c, tpf, &scf, &xferp) == tpf) {
 719                         unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
 720                         unsigned long khz = (MEGA + tp - 1) / (tp);
 721                         KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
 722                             tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
 723                             xferp + 4, khz / 1000, khz % 1000);
 724                         USED(khz);
 725                         if (c->tpf == 0)
 726                                 c->tpf = tpf;   /* note lowest value for controller */
 727                 }
 728         }
 729 }
 730
 731 static void
 732 synctodsa(Dsa *dsa, Controller *c)
 733 {
 734 /*
 735         KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
 736             dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
 737 */
 738         dsa->scntl3 = c->scntl3[dsa->target];
 739         dsa->sxfer = c->sxfer[dsa->target];
 740 }
 741
 742 static void
 743 setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
 744 {
 745         c->scntl3[target] =
 746             (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
 747         c->sxfer[target] = (xferp << 5) | reqack;
 748         c->s[target] = BothDone;
 749         if (dsa) {
 750                 synctodsa(dsa, c);
 751                 c->n->scntl3 = c->scntl3[target];
 752                 c->n->sxfer = c->sxfer[target];
 753         }
 754 }
 755
 756 static void
 757 setasync(Dsa *dsa, Controller *c, int target)
 758 {
 759         setsync(dsa, c, target, 0, c->ccf, 0, 0);
 760 }
 761
 762 static void
 763 setwide(Dsa *dsa, Controller *c, int target, uchar wide)
 764 {
 765         c->scntl3[target] = wide ? (1 << 3) : 0;
 766         setasync(dsa, c, target);
 767         c->s[target] = WideDone;
 768 }
 769
 770 static int
 771 buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
 772 {
 773         *buf++ = X_MSG;
 774         *buf++ = 3;
 775         *buf++ = X_MSG_SDTR;
 776         *buf++ = tpf;
 777         *buf = offset;
 778         return 5;
 779 }
 780
 781 static int
 782 buildwdtrmsg(uchar *buf, uchar expo)
 783 {
 784         *buf++ = X_MSG;
 785         *buf++ = 2;
 786         *buf++ = X_MSG_WDTR;
 787         *buf = expo;
 788         return 4;
 789 }
 790
 791 static void
 792 start(Controller *c, long entry)
 793 {
 794         ulong p;
 795
 796         if (c->running)
 797                 panic(PRINTPREFIX "start called while running");
 798         c->running = 1;
 799         p = c->scriptpa + entry;
 800         lesetl(c->n->dsp, p);
 801         coherence();
 802         if (c->ssm)
 803                 c->n->dcntl |= 0x4;             /* start DMA in SSI mode */
 804 }
 805
 806 static void
 807 ncrcontinue(Controller *c)
 808 {
 809         if (c->running)
 810                 panic(PRINTPREFIX "ncrcontinue called while running");
 811         /* set the start DMA bit to continue execution */
 812         c->running = 1;
 813         coherence();
 814         c->n->dcntl |= 0x4;
 815 }
 816
 817 static void
 818 softreset(Controller *c)
 819 {
 820         Ncr *n = c->n;
 821
 822         n->istat = Srst;                /* software reset */
 823         n->istat = 0;
 824         /* general initialisation */
 825         n->scid = (1 << 6) | 7;         /* respond to reselect, ID 7 */
 826         n->respid = 1 << 7;             /* response ID = 7 */
 827
 828 #ifdef INTERNAL_SCLK
 829         n->stest1 = 0x80;               /* disable external scsi clock */
 830 #else
 831         n->stest1 = 0x00;
 832 #endif
 833
 834         n->stime0 = 0xdd;               /* about 0.5 second timeout on each device */
 835         n->scntl0 |= 0x8;               /* Enable parity checking */
 836
 837         /* continued setup */
 838         n->sien0 = 0x8f;
 839         n->sien1 = 0x04;
 840         n->dien = 0x7d;
 841         n->stest3 = 0x80;               /* TolerANT enable */
 842         c->running = 0;
 843
 844         if (c->v->feature & BigFifo)
 845                 n->ctest5 = (1 << 5);
 846         n->dmode = c->v->burst << 6;    /* set burst length bits */
 847         if (c->v->burst & 4)
 848                 n->ctest5 |= (1 << 2);  /* including overflow into ctest5 bit 2 */
 849         if (c->v->feature & Prefetch)
 850                 n->dcntl |= (1 << 5);   /* prefetch enable */
 851         else if (c->v->feature & BurstOpCodeFetch)
 852                 n->dmode |= (1 << 1);   /* burst opcode fetch */
 853         if (c->v->feature & Differential) {
 854                 /* chip capable */
 855                 if ((c->feature & Differential) || bios_set_differential(c)) {
 856                         /* user enabled, or some evidence bios set differential */
 857                         if (n->sstat2 & (1 << 2))
 858                                 print(PRINTPREFIX "can't go differential; wrong cable\n");
 859                         else {
 860                                 n->stest2 = (1 << 5);
 861                                 print(PRINTPREFIX "differential mode set\n");
 862                         }
 863                 }
 864         }
 865         if (c->clockmult) {
 866                 n->stest1 |= (1 << 3);  /* power up doubler */
 867                 delay(2);
 868                 n->stest3 |= (1 << 5);  /* stop clock */
 869                 n->stest1 |= (1 << 2);  /* enable doubler */
 870                 n->stest3 &= ~(1 << 5); /* start clock */
 871                 /* pray */
 872         }
 873 }
 874
 875 static void
 876 msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
 877 {
 878         uchar histpf, hisreqack;
 879         int tpf;
 880         int scf, xferp;
 881         int len;
 882
 883         Ncr *n = c->n;
 884
 885         switch (c->s[dsa->target]) {
 886         case SyncInit:
 887                 switch (msg) {
 888                 case A_SIR_MSG_SDTR:
 889                         /* reply to my SDTR */
 890                         histpf = n->scratcha[2];
 891                         hisreqack = n->scratcha[3];
 892                         KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
 893                             dsa->target, histpf, hisreqack);
 894
 895                         if (hisreqack == 0)
 896                                 setasync(dsa, c, dsa->target);
 897                         else {
 898                                 /* hisreqack should be <= c->v->maxsyncoff */
 899                                 tpf = chooserate(c, histpf, &scf, &xferp);
 900                                 KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
 901                                     dsa->target, tpf, hisreqack);
 902                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
 903                         }
 904                         *cont = -2;
 905                         return;
 906                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
 907                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
 908                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
 909                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
 910                         setasync(dsa, c, dsa->target);
 911                         *cont = E_to_decisions;
 912                         return;
 913                 case A_SIR_MSG_REJECT:
 914                         /* rejection of my SDTR */
 915                         KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
 916                 //async:
 917                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
 918                         setasync(dsa, c, dsa->target);
 919                         *cont = -2;
 920                         return;
 921                 }
 922                 break;
 923         case WideInit:
 924                 switch (msg) {
 925                 case A_SIR_MSG_WDTR:
 926                         /* reply to my WDTR */
 927                         KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
 928                             dsa->target, n->scratcha[2]);
 929                         setwide(dsa, c, dsa->target, n->scratcha[2]);
 930                         *cont = -2;
 931                         return;
 932                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
 933                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
 934                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
 935                         setwide(dsa, c, dsa->target, 0);
 936                         *cont = E_to_decisions;
 937                         return;
 938                 case A_SIR_MSG_REJECT:
 939                         /* rejection of my SDTR */
 940                         KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
 941                         setwide(dsa, c, dsa->target, 0);
 942                         *cont = -2;
 943                         return;
 944                 }
 945                 break;
 946
 947         case NeitherDone:
 948         case WideDone:
 949         case BothDone:
 950                 switch (msg) {
 951                 case A_SIR_MSG_WDTR: {
 952                         uchar hiswide, mywide;
 953                         hiswide = n->scratcha[2];
 954                         mywide = (c->v->feature & Wide) != 0;
 955                         KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
 956                             dsa->target, hiswide);
 957                         if (hiswide < mywide)
 958                                 mywide = hiswide;
 959                         KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
 960                             dsa->target, mywide);
 961                         setwide(dsa, c, dsa->target, mywide);
 962                         len = buildwdtrmsg(dsa->msg_out, mywide);
 963                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
 964                         *cont = E_response;
 965                         c->s[dsa->target] = WideResponse;
 966                         return;
 967                 }
 968                 case A_SIR_MSG_SDTR:
 969 #ifdef ASYNC_ONLY
 970                         *cont = E_reject;
 971                         return;
 972 #else
 973                         /* target decides to renegotiate */
 974                         histpf = n->scratcha[2];
 975                         hisreqack = n->scratcha[3];
 976                         KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
 977                             dsa->target, histpf, hisreqack);
 978                         if (hisreqack == 0) {
 979                                 /* he wants asynchronous */
 980                                 setasync(dsa, c, dsa->target);
 981                                 tpf = 0;
 982                         }
 983                         else {
 984                                 /* he wants synchronous */
 985                                 tpf = chooserate(c, histpf, &scf, &xferp);
 986                                 if (hisreqack > c->v->maxsyncoff)
 987                                         hisreqack = c->v->maxsyncoff;
 988                                 KPRINT(PRINTPREFIX "%d: using %d %d\n",
 989                                     dsa->target, tpf, hisreqack);
 990                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
 991                         }
 992                         /* build my SDTR message */
 993                         len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
 994                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
 995                         *cont = E_response;
 996                         c->s[dsa->target] = SyncResponse;
 997                         return;
 998 #endif
 999                 }
1000                 break;
1001         case WideResponse:
1002                 switch (msg) {
1003                 case A_SIR_EV_RESPONSE_OK:
1004                         c->s[dsa->target] = WideDone;
1005                         KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
1006                         *cont = -2;
1007                         return;
1008                 case A_SIR_MSG_REJECT:
1009                         setwide(dsa, c, dsa->target, 0);
1010                         KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
1011                         *cont = -2;
1012                         return;
1013                 }
1014                 break;
1015         case SyncResponse:
1016                 switch (msg) {
1017                 case A_SIR_EV_RESPONSE_OK:
1018                         c->s[dsa->target] = BothDone;
1019                         KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
1020                             dsa->target, phase[n->sstat1 & 7]);
1021                         *cont = -2;
1022                         return; /* chf */
1023                 case A_SIR_MSG_REJECT:
1024                         setasync(dsa, c, dsa->target);
1025                         KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
1026                         *cont = -2;
1027                         return;
1028                 }
1029                 break;
1030         }
1031         KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
1032             dsa->target, c->s[dsa->target], msg);
1033         *wakeme = 1;
1034         return;
1035 }
1036
1037 static void
1038 calcblockdma(Dsa *d, ulong base, ulong count)
1039 {
1040         ulong blocks;
1041         if (DEBUG(3))
1042                 blocks = 0;
1043         else {
1044                 blocks = count / A_BSIZE;
1045                 if (blocks > 255)
1046                         blocks = 255;
1047         }
1048         d->dmablks = blocks;
1049         d->dmaaddr[0] = base;
1050         d->dmaaddr[1] = base >> 8;
1051         d->dmaaddr[2] = base >> 16;
1052         d->dmaaddr[3] = base >> 24;
1053         setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
1054         d->flag = legetl(d->data_buf.dbc) == 0;
1055 }
1056
1057 static ulong
1058 read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
1059 {
1060         ulong dbc;
1061         uchar dfifo = n->dfifo;
1062         int inchip;
1063
1064         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1065         if (n->ctest5 & (1 << 5))
1066                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
1067         else
1068                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
1069         if (inchip) {
1070                 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
1071                     dsa->target, dsa->lun, inchip);
1072         }
1073         if (n->sxfer & SYNCOFFMASK(c)) {
1074                 /* SCSI FIFO */
1075                 uchar fifo = n->sstat1 >> 4;
1076                 if (c->v->maxsyncoff > 8)
1077                         fifo |= (n->sstat2 & (1 << 4));
1078                 if (fifo) {
1079                         inchip += fifo;
1080                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
1081                             dsa->target, dsa->lun, fifo);
1082                 }
1083         }
1084         else {
1085                 if (n->sstat0 & (1 << 7)) {
1086                         inchip++;
1087                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
1088                             dsa->target, dsa->lun);
1089                 }
1090                 if (n->sstat2 & (1 << 7)) {
1091                         inchip++;
1092                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
1093                             dsa->target, dsa->lun);
1094                 }
1095         }
1096         USED(inchip);
1097         return dbc;
1098 }
1099
1100 static ulong
1101 write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
1102 {
1103         ulong dbc;
1104         uchar dfifo = n->dfifo;
1105         int inchip;
1106
1107         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1108         USED(dsa);
1109         if (n->ctest5 & (1 << 5))
1110                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
1111         else
1112                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
1113 #ifdef WMR_DEBUG
1114         if (inchip) {
1115                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
1116                     dsa->target, dsa->lun, inchip);
1117         }
1118 #endif
1119         if (n->sstat0 & (1 << 5)) {
1120                 inchip++;
1121 #ifdef WMR_DEBUG
1122                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
1123 #endif
1124         }
1125         if (n->sstat2 & (1 << 5)) {
1126                 inchip++;
1127 #ifdef WMR_DEBUG
1128                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
1129 #endif
1130         }
1131         if (n->sxfer & SYNCOFFMASK(c)) {
1132                 /* synchronous SODR */
1133                 if (n->sstat0 & (1 << 6)) {
1134                         inchip++;
1135 #ifdef WMR_DEBUG
1136                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
1137                             dsa->target, dsa->lun);
1138 #endif
1139                 }
1140                 if (n->sstat2 & (1 << 6)) {
1141                         inchip++;
1142 #ifdef WMR_DEBUG
1143                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
1144                             dsa->target, dsa->lun);
1145 #endif
1146                 }
1147         }
1148         /* clear the dma fifo */
1149         n->ctest3 |= (1 << 2);
1150         /* wait till done */
1151         while ((n->dstat & Dfe) == 0)
1152                 ;
1153         return dbc + inchip;
1154 }
1155
1156 static void
1157 sd53c8xxinterrupt(Ureg *ur, void *a)
1158 {
1159         uchar istat, dstat;
1160         ushort sist;
1161         int wakeme = 0;
1162         int cont = -1;
1163         Dsa *dsa;
1164         ulong dsapa;
1165         Controller *c = a;
1166         Ncr *n = c->n;
1167
1168         USED(ur);
1169         if (DEBUG(1)) {
1170                 IPRINT(PRINTPREFIX "int\n");
1171         }
1172         ilock(c);
1173         istat = n->istat;
1174         if (istat & Intf) {
1175                 Dsa *d;
1176                 int wokesomething = 0;
1177                 if (DEBUG(1)) {
1178                         IPRINT(PRINTPREFIX "Intfly\n");
1179                 }
1180                 n->istat = Intf;
1181                 /* search for structures in A_STATE_DONE */
1182                 for (d = KPTR(legetl(c->dsalist.head)); d != nil && d != dsaend; d = KPTR(legetl(d->next))) {
1183                         if (d->stateb == A_STATE_DONE) {
1184                                 d->p9status = d->status;
1185                                 if (DEBUG(1)) {
1186                                         IPRINT(PRINTPREFIX "waking up dsa %#p\n", d);
1187                                 }
1188                                 wakeup(d);
1189                                 wokesomething = 1;
1190                         }
1191                 }
1192                 if (!wokesomething) {
1193                         IPRINT(PRINTPREFIX "nothing to wake up\n");
1194                 }
1195         }
1196
1197         if ((istat & (Sip | Dip)) == 0) {
1198                 if (DEBUG(1)) {
1199                         IPRINT(PRINTPREFIX "int end %x\n", istat);
1200                 }
1201                 iunlock(c);
1202                 return;
1203         }
1204
1205         sist = (n->sist1<<8)|n->sist0;  /* BUG? can two-byte read be inconsistent? */
1206         dstat = n->dstat;
1207         dsapa = legetl(n->dsa);
1208
1209         /*
1210          * Can't compute dsa until we know that dsapa is valid.
1211          */
1212         if(DMASEG_TO_PADDR(dsapa) < -KZERO)
1213                 dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
1214         else{
1215                 dsa = nil;
1216                 /*
1217                  * happens at startup on some cards but we
1218                  * don't actually deref dsa because none of the
1219                  * flags we are about are set.
1220                  * still, print in case that changes and we're
1221                  * about to dereference nil.
1222                  */
1223                 iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
1224         }
1225
1226         c->running = 0;
1227         if (istat & Sip) {
1228                 if (DEBUG(1)) {
1229                         IPRINT("sist = %.4x\n", sist);
1230                 }
1231                 if (sist & 0x80) {
1232                         ulong addr;
1233                         ulong sa;
1234                         ulong dbc;
1235                         ulong tbc;
1236                         int dmablks;
1237                         ulong dmaaddr;
1238
1239                         addr = legetl(n->dsp);
1240                         sa = addr - c->scriptpa;
1241                         if (DEBUG(1) || DEBUG(2)) {
1242                                 IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
1243                                     dsa->target, dsa->lun, sa);
1244                         }
1245                         /*
1246                          * now recover
1247                          */
1248                         if (sa == E_data_in_mismatch) {
1249                                 /*
1250                                  * though this is a failure in the residue, there may have been blocks
1251                                  * as well. if so, dmablks will not have been zeroed, since the state
1252                                  * was not saved by the microcode.
1253                                  */
1254                                 dbc = read_mismatch_recover(c, n, dsa);
1255                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
1256                                 dsa->dmablks = 0;
1257                                 n->scratcha[2] = 0;
1258                                 advancedata(&dsa->data_buf, tbc);
1259                                 if (DEBUG(1) || DEBUG(2)) {
1260                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
1261                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
1262                                 }
1263                                 cont = E_data_mismatch_recover;
1264                         }
1265                         else if (sa == E_data_in_block_mismatch) {
1266                                 dbc = read_mismatch_recover(c, n, dsa);
1267                                 tbc = A_BSIZE - dbc;
1268                                 /* recover current state from registers */
1269                                 dmablks = n->scratcha[2];
1270                                 dmaaddr = legetl(n->scratchb);
1271                                 /* we have got to dmaaddr + tbc */
1272                                 /* we have dmablks * A_BSIZE - tbc + residue left to do */
1273                                 /* so remaining transfer is */
1274                                 IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
1275                                     dmaaddr, tbc, dmablks);
1276                                 calcblockdma(dsa, dmaaddr + tbc,
1277                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
1278                                 /* copy changes into scratch registers */
1279                                 IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
1280                                     dsa->dmablks, legetl(dsa->dmaaddr),
1281                                     legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
1282                                 n->scratcha[2] = dsa->dmablks;
1283                                 lesetl(n->scratchb, *((ulong*)dsa->dmaaddr));
1284                                 cont = E_data_block_mismatch_recover;
1285                         }
1286                         else if (sa == E_data_out_mismatch) {
1287                                 dbc = write_mismatch_recover(c, n, dsa);
1288                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
1289                                 dsa->dmablks = 0;
1290                                 n->scratcha[2] = 0;
1291                                 advancedata(&dsa->data_buf, tbc);
1292                                 if (DEBUG(1) || DEBUG(2)) {
1293                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
1294                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
1295                                 }
1296                                 cont = E_data_mismatch_recover;
1297                         }
1298                         else if (sa == E_data_out_block_mismatch) {
1299                                 dbc = write_mismatch_recover(c, n, dsa);
1300                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
1301                                 /* recover current state from registers */
1302                                 dmablks = n->scratcha[2];
1303                                 dmaaddr = legetl(n->scratchb);
1304                                 /* we have got to dmaaddr + tbc */
1305                                 /* we have dmablks blocks - tbc + residue left to do */
1306                                 /* so remaining transfer is */
1307                                 IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
1308                                     dmaaddr, tbc, dmablks);
1309                                 calcblockdma(dsa, dmaaddr + tbc,
1310                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
1311                                 /* copy changes into scratch registers */
1312                                 n->scratcha[2] = dsa->dmablks;
1313                                 lesetl(n->scratchb, *((ulong*)dsa->dmaaddr));
1314                                 cont = E_data_block_mismatch_recover;
1315                         }
1316                         else if (sa == E_id_out_mismatch) {
1317                                 /*
1318                                  * target switched phases while attention held during
1319                                  * message out. The possibilities are:
1320                                  * 1. It didn't like the last message. This is indicated
1321                                  *    by the new phase being message_in. Use script to recover
1322                                  *
1323                                  * 2. It's not SCSI-II compliant. The new phase will be other
1324                                  *    than message_in. We should also indicate that the device
1325                                  *    is asynchronous, if it's the SDTR that got ignored
1326                                  *
1327                                  * For now, if the phase switch is not to message_in, and
1328                                  * and it happens after IDENTIFY and before SDTR, we
1329                                  * notify the negotiation state machine.
1330                                  */
1331                                 ulong lim = legetl(dsa->msg_out_buf.dbc);
1332                                 uchar p = n->sstat1 & 7;
1333                                 dbc = write_mismatch_recover(c, n, dsa);
1334                                 tbc = lim - dbc;
1335                                 IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
1336                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
1337                                 if (p != MessageIn && tbc == 1) {
1338                                         msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
1339                                 }
1340                                 else
1341                                         cont = E_id_out_mismatch_recover;
1342                         }
1343                         else if (sa == E_cmd_out_mismatch) {
1344                                 /*
1345                                  * probably the command count is longer than the device wants ...
1346                                  */
1347                                 ulong lim = legetl(dsa->cmd_buf.dbc);
1348                                 uchar p = n->sstat1 & 7;
1349                                 dbc = write_mismatch_recover(c, n, dsa);
1350                                 tbc = lim - dbc;
1351                                 IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
1352                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
1353                                 USED(p, tbc);
1354                                 cont = E_to_decisions;
1355                         }
1356                         else {
1357                                 IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
1358                                     dsa->target, dsa->lun, sa,
1359                                     phase[n->dcmd & 7],
1360                                     phase[n->sstat1 & 7]);
1361                                 dumpncrregs(c, 1);
1362                                 dsa->p9status = SDeio;  /* chf */
1363                                 wakeme = 1;
1364                         }
1365                 }
1366                 /*else*/ if (sist & 0x400) {
1367                         if (DEBUG(0)) {
1368                                 IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
1369                         }
1370                         dsa->p9status = SDtimeout;
1371                         dsa->stateb = A_STATE_DONE;
1372                         coherence();
1373                         softreset(c);
1374                         cont = E_issue_check;
1375                         wakeme = 1;
1376                 }
1377                 if (sist & 0x1) {
1378                         IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
1379                         dsa->parityerror = 1;
1380                 }
1381                 if (sist & 0x4) {
1382                         IPRINT(PRINTPREFIX "%s%d lun %d: unexpected disconnect\n",
1383                                 c->sdev->name, dsa->target, dsa->lun);
1384                         dumpncrregs(c, 1);
1385                         //wakeme = 1;
1386                         dsa->p9status = SDeio;
1387                 }
1388         }
1389         if (istat & Dip) {
1390                 if (DEBUG(1)) {
1391                         IPRINT("dstat = %.2x\n", dstat);
1392                 }
1393                 /*else*/ if (dstat & Ssi) {
1394                         ulong w = legetl(n->dsp) - c->scriptpa;
1395                         IPRINT("[%lux]", w);
1396                         USED(w);
1397                         cont = -2;      /* restart */
1398                 }
1399                 if (dstat & Sir) {
1400                         switch (legetl(n->dsps)) {
1401                         case A_SIR_MSG_IO_COMPLETE:
1402                                 dsa->p9status = dsa->status;
1403                                 wakeme = 1;
1404                                 break;
1405                         case A_SIR_MSG_SDTR:
1406                         case A_SIR_MSG_WDTR:
1407                         case A_SIR_MSG_REJECT:
1408                         case A_SIR_EV_RESPONSE_OK:
1409                                 msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
1410                                 break;
1411                         case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
1412                                 /* back up one in the data transfer */
1413                                 IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
1414                                     dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
1415                                 if (dsa->flag == 2) {
1416                                         IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
1417                                             dsa->target, dsa->lun);
1418                                 }
1419                                 else {
1420                                         calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
1421                                             dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
1422                                 }
1423                                 cont = -2;
1424                                 break;
1425                         case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
1426                                 IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
1427                                     n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
1428                                 dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
1429                                 dumpncrregs(c, 1);
1430                                 wakeme = 1;
1431                                 break;
1432                         case A_SIR_NOTIFY_LOAD_STATE:
1433                                 IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
1434                                 if (dsa == nil) {
1435                                         dsadump(c);
1436                                         dumpncrregs(c, 1);
1437                                         panic("bad dsa in load_state");
1438                                 }
1439                                 cont = -2;
1440                                 break;
1441                         case A_SIR_NOTIFY_MSG_IN:
1442                                 IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
1443                                     dsa->target, dsa->lun, n->sfbr);
1444                                 cont = -2;
1445                                 break;
1446                         case A_SIR_NOTIFY_DISC:
1447                                 IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
1448                                 goto dsadump;
1449                         case A_SIR_NOTIFY_STATUS:
1450                                 IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
1451                                 cont = -2;
1452                                 break;
1453                         case A_SIR_NOTIFY_COMMAND:
1454                                 IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
1455                                 cont = -2;
1456                                 break;
1457                         case A_SIR_NOTIFY_DATA_IN:
1458                                 IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
1459                                     dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
1460                                 cont = -2;
1461                                 break;
1462                         case A_SIR_NOTIFY_BLOCK_DATA_IN:
1463                                 IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
1464                                     dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
1465                                 cont = -2;
1466                                 break;
1467                         case A_SIR_NOTIFY_DATA_OUT:
1468                                 IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
1469                                 cont = -2;
1470                                 break;
1471                         case A_SIR_NOTIFY_DUMP:
1472                                 IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
1473                                 dumpncrregs(c, 1);
1474                                 cont = -2;
1475                                 break;
1476                         case A_SIR_NOTIFY_DUMP2:
1477                                 IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
1478                                 IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
1479                                 IPRINT(" dsa %lux", legetl(n->dsa));
1480                                 IPRINT(" sfbr %ux", n->sfbr);
1481                                 IPRINT(" a %lux", legetl(n->scratcha));
1482                                 IPRINT(" b %lux", legetl(n->scratchb));
1483                                 IPRINT(" ssid %ux", n->ssid);
1484                                 IPRINT("\n");
1485                                 cont = -2;
1486                                 break;
1487                         case A_SIR_NOTIFY_WAIT_RESELECT:
1488                                 IPRINT(PRINTPREFIX "wait reselect\n");
1489                                 cont = -2;
1490                                 break;
1491                         case A_SIR_NOTIFY_RESELECT:
1492                                 IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
1493                                     n->ssid, n->sfbr, TK2MS(m->ticks));
1494                                 cont = -2;
1495                                 break;
1496                         case A_SIR_NOTIFY_ISSUE:
1497                                 IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
1498                         dsadump:
1499                                 IPRINT(" tgt=%d", dsa->target);
1500                                 IPRINT(" time=%ld", TK2MS(m->ticks));
1501                                 IPRINT("\n");
1502                                 cont = -2;
1503                                 break;
1504                         case A_SIR_NOTIFY_ISSUE_CHECK:
1505                                 IPRINT(PRINTPREFIX "issue check\n");
1506                                 cont = -2;
1507                                 break;
1508                         case A_SIR_NOTIFY_SIGP:
1509                                 IPRINT(PRINTPREFIX "responded to SIGP\n");
1510                                 cont = -2;
1511                                 break;
1512                         case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
1513                                 ulong *dsp = &c->script[(legetl(n->dsp)-c->scriptpa)/4];
1514                                 int x;
1515                                 IPRINT(PRINTPREFIX "code at %lux", (ulong)(dsp - c->script));
1516                                 for (x = 0; x < 6; x++) {
1517                                         IPRINT(" %.8lux", dsp[x]);
1518                                 }
1519                                 IPRINT("\n");
1520                                 USED(dsp);
1521                                 cont = -2;
1522                                 break;
1523                         }
1524                         case A_SIR_NOTIFY_WSR:
1525                                 IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
1526                                 cont = -2;
1527                                 break;
1528                         case A_SIR_NOTIFY_LOAD_SYNC:
1529                                 IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
1530                                     dsa->target, dsa->lun, n->scntl3, n->sxfer);
1531                                 cont = -2;
1532                                 break;
1533                         case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
1534                                 if (DEBUG(2)) {
1535                                         IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
1536                                             dsa->target, dsa->lun);
1537                                 }
1538                                 cont = -2;
1539                                 break;
1540                         case A_error_reselected:                /* dsa isn't valid here */
1541                                 iprint(PRINTPREFIX "reselection error\n");
1542                                 dumpncrregs(c, 1);
1543                                 for (dsa = KPTR(legetl(c->dsalist.head)); dsa != nil && dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
1544                                         IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
1545                                 }
1546                                 break;
1547                         default:
1548                                 IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
1549                                         dsa->target, dsa->lun, legetl(n->dsps));
1550                                 dumpncrregs(c, 1);
1551                                 wakeme = 1;
1552                         }
1553                 }
1554                 /*else*/ if (dstat & Iid) {
1555                         int i, target, lun;
1556                         ulong addr, dbc, *v;
1557
1558                         addr = legetl(n->dsp);
1559                         if(dsa){
1560                                 target = dsa->target;
1561                                 lun = dsa->lun;
1562                         }else{
1563                                 target = -1;
1564                                 lun = -1;
1565                         }
1566                         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1567
1568                 //      if(dsa == nil)
1569                                 idebug++;
1570                         IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
1571                             target, lun,
1572                             addr, addr - c->scriptpa, dbc);
1573                         addr -= c->scriptpa;
1574                         addr -= 64;
1575                         addr &= ~63;
1576                         v = &c->script[addr/4];
1577                         for(i=0; i<8; i++){
1578                                 IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n",
1579                                         addr, v[0], v[1], v[2], v[3]);
1580                                 addr += 4*4;
1581                                 v += 4;
1582                         }
1583                         USED(addr, dbc);
1584                         if(dsa == nil){
1585                                 dsadump(c);
1586                                 dumpncrregs(c, 1);
1587                                 panic("bad dsa");
1588                         }
1589                         dsa->p9status = SDeio;
1590                         wakeme = 1;
1591                 }
1592                 /*else*/ if (dstat & Bf) {
1593                         IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
1594                         dumpncrregs(c, 1);
1595                         dsa->p9status = SDeio;
1596                         wakeme = 1;
1597                 }
1598         }
1599         if (cont == -2)
1600                 ncrcontinue(c);
1601         else if (cont >= 0)
1602                 start(c, cont);
1603         if (wakeme){
1604                 if(dsa->p9status == SDnostatus)
1605                         dsa->p9status = SDeio;
1606                 wakeup(dsa);
1607         }
1608         iunlock(c);
1609         if (DEBUG(1)) {
1610                 IPRINT(PRINTPREFIX "int end 1\n");
1611         }
1612 }
1613
1614 static int
1615 done(void *arg)
1616 {
1617         return ((Dsa *)arg)->p9status != SDnostatus;
1618 }
1619
1620 static void
1621 setmovedata(Movedata *d, ulong pa, ulong bc)
1622 {
1623         d->pa[0] = pa;
1624         d->pa[1] = pa>>8;
1625         d->pa[2] = pa>>16;
1626         d->pa[3] = pa>>24;
1627         d->dbc[0] = bc;
1628         d->dbc[1] = bc>>8;
1629         d->dbc[2] = bc>>16;
1630         d->dbc[3] = bc>>24;
1631 }
1632
1633 static void
1634 advancedata(Movedata *d, long v)
1635 {
1636         lesetl(d->pa, legetl(d->pa) + v);
1637         lesetl(d->dbc, legetl(d->dbc) - v);
1638 }
1639
1640 static void
1641 dumpwritedata(uchar *data, int datalen)
1642 {
1643         int i;
1644         uchar *bp;
1645         if (!DEBUG(0)){
1646                 USED(data, datalen);
1647                 return;
1648         }
1649
1650         if (datalen) {
1651                 KPRINT(PRINTPREFIX "write:");
1652                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
1653                         KPRINT("%.2ux", *bp);
1654                 }
1655                 if (i < datalen) {
1656                         KPRINT("...");
1657                 }
1658                 KPRINT("\n");
1659         }
1660 }
1661
1662 static void
1663 dumpreaddata(uchar *data, int datalen)
1664 {
1665         int i;
1666         uchar *bp;
1667         if (!DEBUG(0)){
1668                 USED(data, datalen);
1669                 return;
1670         }
1671
1672         if (datalen) {
1673                 KPRINT(PRINTPREFIX "read:");
1674                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
1675                         KPRINT("%.2ux", *bp);
1676                 }
1677                 if (i < datalen) {
1678                         KPRINT("...");
1679                 }
1680                 KPRINT("\n");
1681         }
1682 }
1683
1684 static void
1685 busreset(Controller *c)
1686 {
1687         int x, ntarget;
1688
1689         /* bus reset */
1690         c->n->scntl1 |= (1 << 3);
1691         delay(500);
1692         c->n->scntl1 &= ~(1 << 3);
1693         if(!(c->v->feature & Wide))
1694                 ntarget = 8;
1695         else
1696                 ntarget = MAXTARGET;
1697         for (x = 0; x < ntarget; x++) {
1698                 setwide(0, c, x, 0);
1699 #ifndef ASYNC_ONLY
1700                 c->s[x] = NeitherDone;
1701 #endif
1702         }
1703         c->capvalid = 0;
1704 }
1705
1706 static void
1707 reset(Controller *c)
1708 {
1709         /* should wakeup all pending tasks */
1710         softreset(c);
1711         busreset(c);
1712 }
1713
1714 static int
1715 sd53c8xxrio(SDreq* r)
1716 {
1717         Dsa *d;
1718         uchar *bp;
1719         Controller *c;
1720         uchar target_expo, my_expo;
1721         int bc, check, i, status, target;
1722
1723         if((target = r->unit->subno) == 0x07)
1724                 return r->status = SDtimeout;   /* assign */
1725
1726         c = r->unit->dev->ctlr;
1727
1728         check = 0;
1729         d = dsaalloc(c, target, r->lun);
1730
1731         qlock(&c->q[target]);                   /* obtain access to target */
1732 docheck:
1733         /* load the transfer control stuff */
1734         d->scsi_id_buf[0] = 0;
1735         d->scsi_id_buf[1] = c->sxfer[target];
1736         d->scsi_id_buf[2] = target;
1737         d->scsi_id_buf[3] = c->scntl3[target];
1738         synctodsa(d, c);
1739
1740         bc = 0;
1741
1742         d->msg_out[bc] = 0x80 | r->lun;
1743
1744 #ifndef NO_DISCONNECT
1745         d->msg_out[bc] |= (1 << 6);
1746 #endif
1747         bc++;
1748
1749         /* work out what to do about negotiation */
1750         switch (c->s[target]) {
1751         default:
1752                 KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
1753                 c->s[target] = NeitherDone;
1754                 /* fall through */
1755         case NeitherDone:
1756                 if ((c->capvalid & (1 << target)) == 0)
1757                         break;
1758                 target_expo = (c->cap[target] >> 5) & 3;
1759                 my_expo = (c->v->feature & Wide) != 0;
1760                 if (target_expo < my_expo)
1761                         my_expo = target_expo;
1762 #ifdef ALWAYS_DO_WDTR
1763                 bc += buildwdtrmsg(d->msg_out + bc, my_expo);
1764                 KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
1765                 c->s[target] = WideInit;
1766                 break;
1767 #else
1768                 if (my_expo) {
1769                         bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
1770                         KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
1771                         c->s[target] = WideInit;
1772                         break;
1773                 }
1774                 KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
1775                 /* fall through */
1776 #endif
1777         case WideDone:
1778                 if (c->cap[target] & (1 << 4)) {
1779                         KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
1780                         bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
1781                         c->s[target] = SyncInit;
1782                         break;
1783                 }
1784                 KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
1785                 c->s[target] = BothDone;
1786                 break;
1787
1788         case BothDone:
1789                 break;
1790         }
1791
1792         setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
1793         setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
1794         calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
1795
1796         if (DEBUG(0)) {
1797                 KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
1798                 for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
1799                         KPRINT("%.2ux", *bp);
1800                 }
1801                 KPRINT("\n");
1802                 if (!r->write) {
1803                         KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
1804                           target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
1805                 }
1806                 else
1807                         dumpwritedata(r->data, r->dlen);
1808         }
1809
1810         setmovedata(&d->status_buf, DMASEG(&d->status), 1);
1811
1812         d->p9status = SDnostatus;
1813         d->parityerror = 0;
1814         coherence();
1815         d->stateb = A_STATE_ISSUE;              /* start operation */
1816         coherence();
1817
1818         ilock(c);
1819         if (c->ssm)
1820                 c->n->dcntl |= 0x10;            /* single step */
1821         if (c->running) {
1822                 c->n->istat = Sigp;
1823         }
1824         else {
1825                 start(c, E_issue_check);
1826         }
1827         iunlock(c);
1828
1829         while(waserror())
1830                 ;
1831         tsleep(d, done, d, 600 * 1000);
1832         poperror();
1833
1834         if (!done(d)) {
1835                 KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
1836                 dumpncrregs(c, 0);
1837                 dsafree(c, d);
1838                 reset(c);
1839                 qunlock(&c->q[target]);
1840                 r->status = SDtimeout;
1841                 return r->status = SDtimeout;   /* assign */
1842         }
1843
1844         if((status = d->p9status) == SDeio)
1845                 c->s[target] = NeitherDone;
1846         if (d->parityerror) {
1847                 status = SDeio;
1848         }
1849
1850         /*
1851          * adjust datalen
1852          */
1853         r->rlen = r->dlen;
1854         if (DEBUG(0)) {
1855                 KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
1856                     target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
1857         }
1858         r->rlen = r->dlen;
1859         if (d->flag != 2) {
1860                 r->rlen -= d->dmablks * A_BSIZE;
1861                 r->rlen -= legetl(d->data_buf.dbc);
1862         }
1863         if(!r->write)
1864                 dumpreaddata(r->data, r->rlen);
1865         if (DEBUG(0)) {
1866                 KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
1867                     target, r->lun, d->p9status, status, r->rlen);
1868         }
1869         /*
1870          * spot the identify
1871          */
1872         if ((c->capvalid & (1 << target)) == 0
1873          && (status == SDok || status == SDcheck)
1874          && r->cmd[0] == 0x12 && r->dlen >= 8) {
1875                 c->capvalid |= 1 << target;
1876                 bp = r->data;
1877                 c->cap[target] = bp[7];
1878                 KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
1879         }
1880         if(!check && status == SDcheck && !(r->flags & SDnosense)){
1881                 check = 1;
1882                 r->write = 0;
1883                 memset(r->cmd, 0, sizeof(r->cmd));
1884                 r->cmd[0] = 0x03;
1885                 r->cmd[1] = r->lun<<5;
1886                 r->cmd[4] = sizeof(r->sense)-1;
1887                 r->clen = 6;
1888                 r->data = r->sense;
1889                 r->dlen = sizeof(r->sense)-1;
1890                 /*
1891                  * Clear out the microcode state
1892                  * so the Dsa can be re-used.
1893                  */
1894                 lesetl(&d->stateb, A_STATE_ALLOCATED);
1895                 coherence();
1896                 goto docheck;
1897         }
1898         qunlock(&c->q[target]);
1899         dsafree(c, d);
1900
1901         if(status == SDok && check){
1902                 status = SDcheck;
1903                 r->flags |= SDvalidsense;
1904         }
1905         if(DEBUG(0))
1906                 KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
1907                         target, r->flags, status, r->rlen);
1908         if(r->flags & SDvalidsense){
1909                 if(!DEBUG(0))
1910                         KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
1911                                 target, r->flags, status, r->rlen);
1912                 for(i = 0; i < r->rlen; i++)
1913                         KPRINT(" %2.2uX", r->sense[i]);
1914                 KPRINT("\n");
1915         }
1916         return r->status = status;
1917 }
1918
1919 static void
1920 cribbios(Controller *c)
1921 {
1922         c->bios.scntl3 = c->n->scntl3;
1923         c->bios.stest2 = c->n->stest2;
1924         print(PRINTPREFIX "%s: bios scntl3(%.2x) stest2(%.2x)\n",
1925                 c->sdev->name, c->bios.scntl3, c->bios.stest2);
1926 }
1927
1928 static int
1929 bios_set_differential(Controller *c)
1930 {
1931         /* Concept lifted from FreeBSD - thanks Gerard */
1932         /* basically, if clock conversion factors are set, then there is
1933          * evidence the bios had a go at the chip, and if so, it would
1934          * have set the differential enable bit in stest2
1935          */
1936         return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
1937 }
1938
1939 #define NCR_VID         0x1000
1940 #define NCR_810_DID     0x0001
1941 #define NCR_820_DID     0x0002  /* don't know enough about this one to support it */
1942 #define NCR_825_DID     0x0003
1943 #define NCR_815_DID     0x0004
1944 #define SYM_810AP_DID   0x0005
1945 #define SYM_860_DID     0x0006
1946 #define SYM_896_DID     0x000b
1947 #define SYM_895_DID     0x000c
1948 #define SYM_885_DID     0x000d  /* ditto */
1949 #define SYM_875_DID     0x000f  /* ditto */
1950 #define SYM_1010_DID    0x0020
1951 #define SYM_1011_DID    0x0021
1952 #define SYM_875J_DID    0x008f
1953
1954 static Variant variant[] = {
1955 { NCR_810_DID,   0x0f, "NCR53C810",     Burst16,   8, 24, 0 },
1956 { NCR_810_DID,   0x1f, "SYM53C810ALV",  Burst16,   8, 24, Prefetch },
1957 { NCR_810_DID,   0xff, "SYM53C810A",    Burst16,   8, 24, Prefetch },
1958 { SYM_810AP_DID, 0xff, "SYM53C810AP",   Burst16,   8, 24, Prefetch },
1959 { NCR_815_DID,   0xff, "NCR53C815",     Burst16,   8, 24, BurstOpCodeFetch },
1960 { NCR_825_DID,   0x0f, "NCR53C825",     Burst16,   8, 24, Wide|BurstOpCodeFetch|Differential },
1961 { NCR_825_DID,   0xff, "SYM53C825A",    Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
1962 { SYM_860_DID,   0x0f, "SYM53C860",     Burst16,   8, 24, Prefetch|Ultra },
1963 { SYM_860_DID,   0xff, "SYM53C860LV",   Burst16,   8, 24, Prefetch|Ultra },
1964 { SYM_875_DID,   0x01, "SYM53C875r1",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
1965 { SYM_875_DID,   0xff, "SYM53C875",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
1966 { SYM_875J_DID,   0xff, "SYM53C875j",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
1967 { SYM_885_DID,   0xff, "SYM53C885",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
1968 { SYM_895_DID,   0xff, "SYM53C895",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1969 { SYM_896_DID,   0xff, "SYM53C896",     Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1970 { SYM_1010_DID,  0xff, "SYM53C1010",    Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1971 { SYM_1011_DID,   0xff, "SYM53C1010",   Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1972 };
1973
1974 static int
1975 xfunc(Controller *c, enum na_external x, unsigned long *v)
1976 {
1977         switch (x) {
1978         default:
1979                 print("xfunc: can't find external %d\n", x);
1980                 return 0;
1981         case X_scsi_id_buf:
1982                 *v = offsetof(Dsa, scsi_id_buf[0]);
1983                 break;
1984         case X_msg_out_buf:
1985                 *v = offsetof(Dsa, msg_out_buf);
1986                 break;
1987         case X_cmd_buf:
1988                 *v = offsetof(Dsa, cmd_buf);
1989                 break;
1990         case X_data_buf:
1991                 *v = offsetof(Dsa, data_buf);
1992                 break;
1993         case X_status_buf:
1994                 *v = offsetof(Dsa, status_buf);
1995                 break;
1996         case X_dsa_head:
1997                 *v = DMASEG(&c->dsalist.head[0]);
1998                 break;
1999         case X_ssid_mask:
2000                 *v = SSIDMASK(c);
2001                 break;
2002         }
2003         return 1;
2004 }
2005
2006 static int
2007 na_fixup(Controller *c, ulong pa_reg,
2008     struct na_patch *patch, int patches,
2009     int (*externval)(Controller*, int, ulong*))
2010 {
2011         int p;
2012         int v;
2013         ulong *script, pa_script;
2014         unsigned long lw, lv;
2015
2016         script = c->script;
2017         pa_script = c->scriptpa;
2018         for (p = 0; p < patches; p++) {
2019                 switch (patch[p].type) {
2020                 case 1:
2021                         /* script relative */
2022                         script[patch[p].lwoff] += pa_script;
2023                         break;
2024                 case 2:
2025                         /* register i/o relative */
2026                         script[patch[p].lwoff] += pa_reg;
2027                         break;
2028                 case 3:
2029                         /* data external */
2030                         lw = script[patch[p].lwoff];
2031                         v = (lw >> 8) & 0xff;
2032                         if (!(*externval)(c, v, &lv))
2033                                 return 0;
2034                         v = lv & 0xff;
2035                         script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
2036                         break;
2037                 case 4:
2038                         /* 32 bit external */
2039                         lw = script[patch[p].lwoff];
2040                         if (!(*externval)(c, lw, &lv))
2041                                 return 0;
2042                         script[patch[p].lwoff] = lv;
2043                         break;
2044                 case 5:
2045                         /* 24 bit external */
2046                         lw = script[patch[p].lwoff];
2047                         if (!(*externval)(c, lw & 0xffffff, &lv))
2048                                 return 0;
2049                         script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
2050                         break;
2051                 }
2052         }
2053         return 1;
2054 }
2055
2056 static SDev*
2057 sd53c8xxpnp(void)
2058 {
2059         char *cp;
2060         Pcidev *p;
2061         Variant *v;
2062         int ba, nctlr;
2063         void *scriptma;
2064         Controller *ctlr;
2065         SDev *sdev, *head, *tail;
2066         ulong regpa, *script, scriptpa;
2067         void *regva, *scriptva;
2068
2069         if(cp = getconf("*maxsd53c8xx"))
2070                 nctlr = strtoul(cp, 0, 0);
2071         else
2072                 nctlr = 32;
2073
2074         p = nil;
2075         head = tail = nil;
2076         while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
2077                 for(v = variant; v < &variant[nelem(variant)]; v++){
2078                         if(p->did == v->did && p->rid <= v->maxrid)
2079                                 break;
2080                 }
2081                 if(v >= &variant[nelem(variant)]) {
2082                         print("no match\n");
2083                         continue;
2084                 }
2085                 print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
2086                         v->name, p->rid, p->intl, p->pcr);
2087
2088                 regpa = p->mem[1].bar;
2089                 ba = 2;
2090                 if(regpa & 0x04){
2091                         if(p->mem[2].bar)
2092                                 continue;
2093                         ba++;
2094                 }
2095                 if(regpa == 0)
2096                         print("regpa 0\n");
2097                 regpa &= ~0xF;
2098                 regva = vmap(regpa, p->mem[1].size);
2099                 if(regva == 0)
2100                         continue;
2101
2102                 script = nil;
2103                 scriptpa = 0;
2104                 scriptva = nil;
2105                 scriptma = nil;
2106                 if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
2107                         scriptpa = p->mem[ba].bar;
2108                         if((scriptpa & 0x04) && p->mem[ba+1].bar){
2109                                 vunmap(regva, p->mem[1].size);
2110                                 continue;
2111                         }
2112                         scriptpa &= ~0x0F;
2113                         scriptva = vmap(scriptpa, p->mem[ba].size);
2114                         if(scriptva)
2115                                 script = scriptva;
2116                 }
2117                 if(scriptpa == 0){
2118                         /*
2119                          * Either the map failed, or this chip does not have
2120                          * local RAM. It will need a copy of the microcode.
2121                          */
2122                         scriptma = malloc(sizeof(na_script));
2123                         if(scriptma == nil){
2124                                 vunmap(regva, p->mem[1].size);
2125                                 continue;
2126                         }
2127                         scriptpa = DMASEG(scriptma);
2128                         script = scriptma;
2129                 }
2130
2131                 ctlr = malloc(sizeof(Controller));
2132                 sdev = malloc(sizeof(SDev));
2133                 if(ctlr == nil || sdev == nil){
2134 buggery:
2135                         if(ctlr)
2136                                 free(ctlr);
2137                         if(sdev)
2138                                 free(sdev);
2139                         if(scriptma)
2140                                 free(scriptma);
2141                         else if(scriptva)
2142                                 vunmap(scriptva, p->mem[ba].size);
2143                         if(regva)
2144                                 vunmap(regva, p->mem[1].size);
2145                         continue;
2146                 }
2147
2148                 lock(&ctlr->dsalist);
2149                 ctlr->dsalist.freechain = nil;
2150                 if(dsaend == nil)
2151                         dsaend = xalloc(sizeof *dsaend);
2152                 if(dsaend == nil)
2153                         panic("sd53c8xxpnp: no memory");
2154                 lesetl(&dsaend->stateb, A_STATE_END);
2155                 lesetl(dsaend->next, DMASEG(dsaend));
2156                 coherence();
2157                 lesetl(ctlr->dsalist.head, DMASEG(dsaend));
2158                 coherence();
2159                 unlock(&ctlr->dsalist);
2160
2161                 ctlr->n = regva;
2162                 ctlr->v = v;
2163                 ctlr->script = script;
2164                 memmove(ctlr->script, na_script, sizeof(na_script));
2165
2166                 /*
2167                  * Because we don't yet have an abstraction for the
2168                  * addresses as seen from the controller side (and on
2169                  * the 386 it doesn't matter), the following two lines
2170                  * are different between the 386 and alpha copies of
2171                  * this driver.
2172                  */
2173                 ctlr->scriptpa = scriptpa;
2174                 if(!na_fixup(ctlr, regpa, na_patches, NA_PATCHES, xfunc)){
2175                         print("script fixup failed\n");
2176                         goto buggery;
2177                 }
2178                 swabl(ctlr->script, ctlr->script, sizeof(na_script));
2179
2180                 ctlr->pcidev = p;
2181
2182                 sdev->ifc = &sd53c8xxifc;
2183                 sdev->ctlr = ctlr;
2184                 sdev->idno = '0';
2185                 if(!(v->feature & Wide))
2186                         sdev->nunit = 8;
2187                 else
2188                         sdev->nunit = MAXTARGET;
2189                 ctlr->sdev = sdev;
2190
2191                 if(head != nil)
2192                         tail->next = sdev;
2193                 else
2194                         head = sdev;
2195                 tail = sdev;
2196
2197                 nctlr--;
2198         }
2199
2200         return head;
2201 }
2202
2203 static int
2204 sd53c8xxenable(SDev* sdev)
2205 {
2206         Pcidev *pcidev;
2207         Controller *ctlr;
2208         char name[32];
2209
2210         ctlr = sdev->ctlr;
2211         pcidev = ctlr->pcidev;
2212
2213         pcisetbme(pcidev);
2214
2215         ilock(ctlr);
2216         synctabinit(ctlr);
2217         cribbios(ctlr);
2218         reset(ctlr);
2219         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2220         intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
2221         iunlock(ctlr);
2222
2223         return 1;
2224 }
2225
2226 SDifc sd53c8xxifc = {
2227         "53c8xx",                       /* name */
2228
2229         sd53c8xxpnp,                    /* pnp */
2230         nil,                            /* legacy */
2231         sd53c8xxenable,                 /* enable */
2232         nil,                            /* disable */
2233
2234         scsiverify,                     /* verify */
2235         scsionline,                     /* online */
2236         sd53c8xxrio,                    /* rio */
2237         nil,                            /* rctl */
2238         nil,                            /* wctl */
2239
2240         scsibio,                        /* bio */
2241         nil,                            /* probe */
2242         nil,                            /* clear */
2243         nil,                            /* rtopctl */
2244         nil,                            /* wtopctl */
2245 };