2 * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
3 * Nigel Roles (nigel@9fs.org)
5 * 27/5/02 Fixed problems with transfers >= 256 * 512
7 * 13/3/01 Fixed microcode to support targets > 7
9 * 01/12/00 Removed previous comments. Fixed a small problem in
10 * mismatch recovery for targets with synchronous offsets of >=16
11 * connected to >=875s. Thanks, Jean.
15 * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
18 #define MAXTARGET 16 /* can be 8 or 16 */
21 #include "../port/lib.h"
27 #include "../port/sd.h"
28 extern SDifc sd53c8xxifc;
30 /**********************************/
31 /* Portable configuration macros */
32 /**********************************/
36 //#define INTERNAL_SCLK
37 //#define ALWAYS_DO_WDTR
40 /**********************************/
41 /* CPU specific macros */
42 /**********************************/
44 #define PRINTPREFIX "sd53c8xx: "
49 #define IPRINT intrprint
51 #define IFLUSH() iflush()
55 static int idebug = 1;
56 #define KPRINT if(0) iprint
57 #define IPRINT if(idebug) iprint
61 #endif /* BOOTDEBUG */
63 /*******************************/
65 /*******************************/
68 #define DMASEG(x) PCIWADDR(x)
69 #define legetl(x) (*(ulong*)(x))
70 #define lesetl(x,v) (*(ulong*)(x) = (v))
74 #define DMASEG_TO_KADDR(x) KADDR((x)-PCIWINDOW)
75 #define KPTR(x) ((x) == 0 ? 0 : DMASEG_TO_KADDR(x))
79 #define SCLK (33 * MEGA)
81 #define SCLK (40 * MEGA)
82 #endif /* INTERNAL_SCLK */
83 #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
85 #define MAXSYNCSCSIRATE (5 * MEGA)
86 #define MAXFASTSYNCSCSIRATE (10 * MEGA)
87 #define MAXULTRASYNCSCSIRATE (20 * MEGA)
88 #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
89 #define MAXASYNCCORERATE (25 * MEGA)
90 #define MAXSYNCCORERATE (25 * MEGA)
91 #define MAXFASTSYNCCORERATE (50 * MEGA)
92 #define MAXULTRASYNCCORERATE (80 * MEGA)
93 #define MAXULTRA2SYNCCORERATE (160 * MEGA)
106 uchar scntl0; /* 00 */
121 uchar dstat; /* 0c */
126 uchar dsa[4]; /* 10 */
128 uchar istat; /* 14 */
131 uchar ctest0; /* 18 */
136 uchar temp[4]; /* 1c */
138 uchar dfifo; /* 20 */
143 uchar dbc[3]; /* 24 */
146 uchar dnad[4]; /* 28 */
147 uchar dsp[4]; /* 2c */
148 uchar dsps[4]; /* 30 */
150 uchar scratcha[4]; /* 34 */
152 uchar dmode; /* 38 */
157 uchar adder[4]; /* 3c */
159 uchar sien0; /* 40 */
164 uchar slpar; /* 44 */
169 uchar stime0; /* 48 */
174 uchar stest0; /* 4c */
188 uchar scratchb[4]; /* 5c */
191 typedef struct Movedata {
196 typedef enum NegoState {
197 NeitherDone, WideInit, WideResponse, WideDone,
198 SyncInit, SyncResponse, BothDone
202 Allocated, Queued, Active, Done
205 typedef struct Dsa Dsa;
210 uchar flag; /* setbyte(state,3,...) */
213 ulong dmancr; /* For block transfer: NCR order (little-endian) */
217 uchar target; /* Target */
220 uchar lun; /* Logical Unit Number */
227 uchar next[4]; /* chaining for SCRIPT (NCR byte order) */
228 Dsa *freechain; /* chaining for freelist */
230 uchar scsi_id_buf[4];
231 Movedata msg_out_buf;
235 uchar msg_out[10]; /* enough to include SDTR */
241 typedef enum Feature {
242 BigFifo = 1, /* 536 byte fifo */
243 BurstOpCodeFetch = 2, /* burst fetch opcodes */
244 Prefetch = 4, /* prefetch 8 longwords */
245 LocalRAM = 8, /* 4K longwords of local RAM */
246 Differential = 16, /* Differential support */
247 Wide = 32, /* Wide capable */
248 Ultra = 64, /* Ultra capable */
249 ClockDouble = 128, /* Has clock doubler */
250 ClockQuad = 256, /* Has clock quadrupler (same as Ultra2) */
264 typedef struct Variant {
266 uchar maxrid; /* maximum allowed revision ID */
268 Burst burst; /* codings for max burst */
269 uchar maxsyncoff; /* max synchronous offset */
270 uchar registers; /* number of 32 bit registers */
274 static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
275 #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
276 #define NULTRASCF (NULTRA2SCF - 2)
277 #define NSCF (NULTRASCF - 1)
279 typedef struct Controller {
285 uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
286 NegoState s[MAXTARGET];
287 uchar scntl3[MAXTARGET];
288 uchar sxfer[MAXTARGET];
289 uchar cap[MAXTARGET]; /* capabilities byte from Identify */
290 ushort capvalid; /* bit per target for validity of cap[] */
291 ushort wide; /* bit per target set if wide negotiated */
292 ulong sclk; /* clock speed of controller */
293 uchar clockmult; /* set by synctabinit */
294 uchar ccf; /* CCF bits */
295 uchar tpf; /* best tpf value for this controller */
296 uchar feature; /* requested features */
297 int running; /* is the script processor running? */
298 int ssm; /* single step mode */
299 Ncr *n; /* pointer to registers */
300 Variant *v; /* pointer to variant type */
301 ulong *script; /* where the real script is */
302 ulong scriptpa; /* where the real script is */
308 uchar head[4]; /* head of free list (NCR byte order) */
312 QLock q[MAXTARGET]; /* queues for each target */
315 #define SYNCOFFMASK(c) (((c)->v->maxsyncoff * 2) - 1)
316 #define SSIDMASK(c) (((c)->v->feature & Wide) ? 15 : 7)
319 enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
322 enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
325 enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
327 static void setmovedata(Movedata*, ulong, ulong);
328 static void advancedata(Movedata*, long);
329 static int bios_set_differential(Controller *c);
331 static char *phase[] = {
332 "data out", "data in", "command", "status",
333 "reserved out", "reserved in", "message out", "message in"
337 #define DEBUGSIZE 10240
338 char debugbuf[DEBUGSIZE];
342 intrprint(char *format, ...)
345 debuglast = debugbuf;
346 debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
356 debuglast = debugbuf;
357 if (debuglast == debugbuf) {
363 screenputs(debugbuf, endp - debugbuf);
365 memmove(debugbuf, endp, debuglast - endp);
366 debuglast -= endp - debugbuf;
371 oprint(char *format, ...)
378 debuglast = debugbuf;
379 debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
385 #include "sd53c8xx.i"
388 * We used to use a linked list of Dsas with nil as the terminator,
389 * but occasionally the 896 card seems not to notice that the 0
390 * is really a 0, and then it tries to reference the Dsa at address 0.
391 * To address this, we use a sentinel dsa that links back to itself
392 * and has state A_STATE_END. If the card takes an iteration or
393 * two to notice that the state says A_STATE_END, that's no big
394 * deal. Clearly this isn't the right approach, but I'm just
395 * stumped. Even with this, we occasionally get prints about
396 * "WSR set", usually with about the same frequency that the
397 * card used to walk past 0.
402 dsaallocnew(Controller *c)
406 /* c->dsalist must be ilocked */
407 d = xalloc(sizeof *d);
409 panic("sd53c8xx dsaallocnew: no memory");
410 lesetl(d->next, legetl(c->dsalist.head));
411 lesetl(&d->stateb, A_STATE_FREE);
413 lesetl(c->dsalist.head, DMASEG(d));
419 dsaalloc(Controller *c, int target, int lun)
424 if ((d = c->dsalist.freechain) != 0) {
426 IPRINT(PRINTPREFIX "%d/%d: reused dsa %lux\n", target, lun, (ulong)d);
430 IPRINT(PRINTPREFIX "%d/%d: allocated dsa %lux\n", target, lun, (ulong)d);
432 c->dsalist.freechain = d->freechain;
433 lesetl(&d->stateb, A_STATE_ALLOCATED);
434 iunlock(&c->dsalist);
441 dsafree(Controller *c, Dsa *d)
444 d->freechain = c->dsalist.freechain;
445 c->dsalist.freechain = d;
446 lesetl(&d->stateb, A_STATE_FREE);
447 iunlock(&c->dsalist);
451 dsadump(Controller *c)
456 iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
457 for(d=KPTR(legetl(c->dsalist.head)); d != dsaend; d=KPTR(legetl(d->next))){
459 iprint("\t dsa %p\n", d);
463 iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
467 a = KPTR(c->scriptpa+E_dsa_addr);
468 iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
469 a[0], a[1], a[2], a[3], a[4]);
470 a = KPTR(c->scriptpa+E_issue_addr);
471 iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
472 a[0], a[1], a[2], a[3], a[4]);
474 a = KPTR(c->scriptpa+E_issue_test_begin);
475 e = KPTR(c->scriptpa+E_issue_test_end);
476 iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
480 iprint(" %.8ux", *a);
490 dsafind(Controller *c, uchar target, uchar lun, uchar state)
493 for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
494 if (d->target != 0xff && d->target != target)
496 if (lun != 0xff && d->lun != lun)
498 if (state != 0xff && d->stateb != state)
506 dumpncrregs(Controller *c, int intr)
510 int depth = c->v->registers / 4;
513 IPRINT("sa = %.8lux\n", c->scriptpa);
516 KPRINT("sa = %.8lux\n", c->scriptpa);
518 for (i = 0; i < depth; i++) {
520 for (j = 0; j < 4; j++) {
521 int k = j * depth + i;
524 /* display little-endian to make 32-bit values readable */
527 IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
530 KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
544 chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
546 /* find lowest entry >= tpf */
553 if (c->v->feature & Ultra2)
555 else if (c->v->feature & Ultra)
561 * search large clock factors first since this should
562 * result in more reliable transfers
564 for (scf = maxscf; scf >= 1; scf--) {
565 for (xferp = 0; xferp < 8; xferp++) {
566 unsigned char v = c->synctab[scf - 1][xferp];
569 if (v >= tpf && v < besttpf) {
586 synctabinit(Controller *c)
589 unsigned long scsilimit;
591 unsigned long cr, sr;
596 if (c->v->feature & Ultra2)
598 else if (c->v->feature & Ultra)
604 * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
605 * first spin of the 875), assume 80MHz
606 * otherwise use the internal (33 Mhz) or external (40MHz) default
609 if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
610 c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
615 * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
619 if (SCLK <= 40000000) {
620 if (c->v->feature & ClockDouble) {
624 else if (c->v->feature & ClockQuad) {
634 /* derive CCF from sclk */
635 /* woebetide anyone with SCLK < 16.7 or > 80MHz */
636 if (c->sclk <= 25 * MEGA)
638 else if (c->sclk <= 3750000)
640 else if (c->sclk <= 50 * MEGA)
642 else if (c->sclk <= 75 * MEGA)
644 else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
646 else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
648 else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
651 for (scf = 1; scf < maxscf; scf++) {
652 /* check for legal core rate */
653 /* round up so we run slower for safety */
654 cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
655 if (cr <= MAXSYNCCORERATE) {
656 scsilimit = MAXSYNCSCSIRATE;
659 else if (cr <= MAXFASTSYNCCORERATE) {
660 scsilimit = MAXFASTSYNCSCSIRATE;
663 else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
664 scsilimit = MAXULTRASYNCSCSIRATE;
667 else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
668 scsilimit = MAXULTRA2SYNCSCSIRATE;
673 for (xferp = 11; xferp >= 4; xferp--) {
676 /* calculate scsi rate - round up again */
677 /* start from sclk for accuracy */
678 int totaldivide = xferp * cf2[scf];
679 sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
683 * now work out transfer period
684 * round down now so that period is pessimistic
686 tp = (MEGA * 1000) / sr;
690 if (tp < 25 || tp > 255 * 4)
693 * spot stupid special case for Ultra or Ultra2
694 * while working out factor
705 * now check tpf looks sensible
710 /* scf must be ccf for SCSI 1 */
711 ok = tpf >= 50 && scf == c->ccf;
714 ok = tpf >= 25 && tpf < 50;
718 * must use xferp of 4, or 5 at a pinch
719 * for an Ultra transfer
721 ok = xferp <= 5 && tpf >= 12 && tpf < 25;
724 ok = xferp == 4 && (tpf == 10 || tpf == 11);
731 c->synctab[scf - 1][xferp - 4] = tpf;
736 if (c->v->feature & Ultra2)
740 if (c->v->feature & Ultra)
744 for (; tpf < 256; tpf++) {
745 if (chooserate(c, tpf, &scf, &xferp) == tpf) {
746 unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
747 unsigned long khz = (MEGA + tp - 1) / (tp);
748 KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
749 tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
750 xferp + 4, khz / 1000, khz % 1000);
753 c->tpf = tpf; /* note lowest value for controller */
759 synctodsa(Dsa *dsa, Controller *c)
762 KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
763 dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
765 dsa->scntl3 = c->scntl3[dsa->target];
766 dsa->sxfer = c->sxfer[dsa->target];
770 setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
773 (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
774 c->sxfer[target] = (xferp << 5) | reqack;
775 c->s[target] = BothDone;
778 c->n->scntl3 = c->scntl3[target];
779 c->n->sxfer = c->sxfer[target];
784 setasync(Dsa *dsa, Controller *c, int target)
786 setsync(dsa, c, target, 0, c->ccf, 0, 0);
790 setwide(Dsa *dsa, Controller *c, int target, uchar wide)
792 c->scntl3[target] = wide ? (1 << 3) : 0;
793 setasync(dsa, c, target);
794 c->s[target] = WideDone;
798 buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
809 buildwdtrmsg(uchar *buf, uchar expo)
819 start(Controller *c, long entry)
824 panic(PRINTPREFIX "start called while running");
826 p = c->scriptpa + entry;
827 lesetl(c->n->dsp, p);
830 c->n->dcntl |= 0x4; /* start DMA in SSI mode */
834 ncrcontinue(Controller *c)
837 panic(PRINTPREFIX "ncrcontinue called while running");
838 /* set the start DMA bit to continue execution */
845 softreset(Controller *c)
849 n->istat = Srst; /* software reset */
851 /* general initialisation */
852 n->scid = (1 << 6) | 7; /* respond to reselect, ID 7 */
853 n->respid = 1 << 7; /* response ID = 7 */
856 n->stest1 = 0x80; /* disable external scsi clock */
861 n->stime0 = 0xdd; /* about 0.5 second timeout on each device */
862 n->scntl0 |= 0x8; /* Enable parity checking */
864 /* continued setup */
868 n->stest3 = 0x80; /* TolerANT enable */
871 if (c->v->feature & BigFifo)
872 n->ctest5 = (1 << 5);
873 n->dmode = c->v->burst << 6; /* set burst length bits */
875 n->ctest5 |= (1 << 2); /* including overflow into ctest5 bit 2 */
876 if (c->v->feature & Prefetch)
877 n->dcntl |= (1 << 5); /* prefetch enable */
878 else if (c->v->feature & BurstOpCodeFetch)
879 n->dmode |= (1 << 1); /* burst opcode fetch */
880 if (c->v->feature & Differential) {
882 if ((c->feature & Differential) || bios_set_differential(c)) {
883 /* user enabled, or some evidence bios set differential */
884 if (n->sstat2 & (1 << 2))
885 print(PRINTPREFIX "can't go differential; wrong cable\n");
887 n->stest2 = (1 << 5);
888 print(PRINTPREFIX "differential mode set\n");
893 n->stest1 |= (1 << 3); /* power up doubler */
895 n->stest3 |= (1 << 5); /* stop clock */
896 n->stest1 |= (1 << 2); /* enable doubler */
897 n->stest3 &= ~(1 << 5); /* start clock */
903 msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
905 uchar histpf, hisreqack;
912 switch (c->s[dsa->target]) {
916 /* reply to my SDTR */
917 histpf = n->scratcha[2];
918 hisreqack = n->scratcha[3];
919 KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
920 dsa->target, histpf, hisreqack);
923 setasync(dsa, c, dsa->target);
925 /* hisreqack should be <= c->v->maxsyncoff */
926 tpf = chooserate(c, histpf, &scf, &xferp);
927 KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
928 dsa->target, tpf, hisreqack);
929 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
933 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
934 /* target ignored ATN for message after IDENTIFY - not SCSI-II */
935 KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
936 KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
937 setasync(dsa, c, dsa->target);
938 *cont = E_to_decisions;
940 case A_SIR_MSG_REJECT:
941 /* rejection of my SDTR */
942 KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
944 KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
945 setasync(dsa, c, dsa->target);
953 /* reply to my WDTR */
954 KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
955 dsa->target, n->scratcha[2]);
956 setwide(dsa, c, dsa->target, n->scratcha[2]);
959 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
960 /* target ignored ATN for message after IDENTIFY - not SCSI-II */
961 KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
962 setwide(dsa, c, dsa->target, 0);
963 *cont = E_to_decisions;
965 case A_SIR_MSG_REJECT:
966 /* rejection of my SDTR */
967 KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
968 setwide(dsa, c, dsa->target, 0);
978 case A_SIR_MSG_WDTR: {
979 uchar hiswide, mywide;
980 hiswide = n->scratcha[2];
981 mywide = (c->v->feature & Wide) != 0;
982 KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
983 dsa->target, hiswide);
984 if (hiswide < mywide)
986 KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
987 dsa->target, mywide);
988 setwide(dsa, c, dsa->target, mywide);
989 len = buildwdtrmsg(dsa->msg_out, mywide);
990 setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
992 c->s[dsa->target] = WideResponse;
1000 /* target decides to renegotiate */
1001 histpf = n->scratcha[2];
1002 hisreqack = n->scratcha[3];
1003 KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
1004 dsa->target, histpf, hisreqack);
1005 if (hisreqack == 0) {
1006 /* he wants asynchronous */
1007 setasync(dsa, c, dsa->target);
1011 /* he wants synchronous */
1012 tpf = chooserate(c, histpf, &scf, &xferp);
1013 if (hisreqack > c->v->maxsyncoff)
1014 hisreqack = c->v->maxsyncoff;
1015 KPRINT(PRINTPREFIX "%d: using %d %d\n",
1016 dsa->target, tpf, hisreqack);
1017 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
1019 /* build my SDTR message */
1020 len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
1021 setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
1023 c->s[dsa->target] = SyncResponse;
1030 case A_SIR_EV_RESPONSE_OK:
1031 c->s[dsa->target] = WideDone;
1032 KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
1035 case A_SIR_MSG_REJECT:
1036 setwide(dsa, c, dsa->target, 0);
1037 KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
1044 case A_SIR_EV_RESPONSE_OK:
1045 c->s[dsa->target] = BothDone;
1046 KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
1047 dsa->target, phase[n->sstat1 & 7]);
1050 case A_SIR_MSG_REJECT:
1051 setasync(dsa, c, dsa->target);
1052 KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
1058 KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
1059 dsa->target, c->s[dsa->target], msg);
1065 calcblockdma(Dsa *d, ulong base, ulong count)
1071 blocks = count / A_BSIZE;
1075 d->dmablks = blocks;
1076 d->dmaaddr[0] = base;
1077 d->dmaaddr[1] = base >> 8;
1078 d->dmaaddr[2] = base >> 16;
1079 d->dmaaddr[3] = base >> 24;
1080 setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
1081 d->flag = legetl(d->data_buf.dbc) == 0;
1085 read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
1088 uchar dfifo = n->dfifo;
1091 dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1092 if (n->ctest5 & (1 << 5))
1093 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
1095 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
1097 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
1098 dsa->target, dsa->lun, inchip);
1100 if (n->sxfer & SYNCOFFMASK(c)) {
1102 uchar fifo = n->sstat1 >> 4;
1103 if (c->v->maxsyncoff > 8)
1104 fifo |= (n->sstat2 & (1 << 4));
1107 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
1108 dsa->target, dsa->lun, fifo);
1112 if (n->sstat0 & (1 << 7)) {
1114 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
1115 dsa->target, dsa->lun);
1117 if (n->sstat2 & (1 << 7)) {
1119 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
1120 dsa->target, dsa->lun);
1128 write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
1131 uchar dfifo = n->dfifo;
1134 dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1136 if (n->ctest5 & (1 << 5))
1137 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
1139 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
1142 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
1143 dsa->target, dsa->lun, inchip);
1146 if (n->sstat0 & (1 << 5)) {
1149 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
1152 if (n->sstat2 & (1 << 5)) {
1155 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
1158 if (n->sxfer & SYNCOFFMASK(c)) {
1159 /* synchronous SODR */
1160 if (n->sstat0 & (1 << 6)) {
1163 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
1164 dsa->target, dsa->lun);
1167 if (n->sstat2 & (1 << 6)) {
1170 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
1171 dsa->target, dsa->lun);
1175 /* clear the dma fifo */
1176 n->ctest3 |= (1 << 2);
1177 /* wait till done */
1178 while ((n->dstat & Dfe) == 0)
1180 return dbc + inchip;
1184 sd53c8xxinterrupt(Ureg *ur, void *a)
1197 IPRINT(PRINTPREFIX "int\n");
1203 int wokesomething = 0;
1205 IPRINT(PRINTPREFIX "Intfly\n");
1208 /* search for structures in A_STATE_DONE */
1209 for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
1210 if (d->stateb == A_STATE_DONE) {
1211 d->p9status = d->status;
1213 IPRINT(PRINTPREFIX "waking up dsa %lux\n", (ulong)d);
1219 if (!wokesomething) {
1220 IPRINT(PRINTPREFIX "nothing to wake up\n");
1224 if ((istat & (Sip | Dip)) == 0) {
1226 IPRINT(PRINTPREFIX "int end %x\n", istat);
1232 sist = (n->sist1<<8)|n->sist0; /* BUG? can two-byte read be inconsistent? */
1234 dsapa = legetl(n->dsa);
1237 * Can't compute dsa until we know that dsapa is valid.
1240 dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
1244 * happens at startup on some cards but we
1245 * don't actually deref dsa because none of the
1246 * flags we are about are set.
1247 * still, print in case that changes and we're
1248 * about to dereference nil.
1250 iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
1256 IPRINT("sist = %.4x\n", sist);
1266 addr = legetl(n->dsp);
1267 sa = addr - c->scriptpa;
1268 if (DEBUG(1) || DEBUG(2)) {
1269 IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
1270 dsa->target, dsa->lun, sa);
1275 if (sa == E_data_in_mismatch) {
1277 * though this is a failure in the residue, there may have been blocks
1278 * as well. if so, dmablks will not have been zeroed, since the state
1279 * was not saved by the microcode.
1281 dbc = read_mismatch_recover(c, n, dsa);
1282 tbc = legetl(dsa->data_buf.dbc) - dbc;
1285 advancedata(&dsa->data_buf, tbc);
1286 if (DEBUG(1) || DEBUG(2)) {
1287 IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
1288 dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
1290 cont = E_data_mismatch_recover;
1292 else if (sa == E_data_in_block_mismatch) {
1293 dbc = read_mismatch_recover(c, n, dsa);
1294 tbc = A_BSIZE - dbc;
1295 /* recover current state from registers */
1296 dmablks = n->scratcha[2];
1297 dmaaddr = legetl(n->scratchb);
1298 /* we have got to dmaaddr + tbc */
1299 /* we have dmablks * A_BSIZE - tbc + residue left to do */
1300 /* so remaining transfer is */
1301 IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
1302 dmaaddr, tbc, dmablks);
1303 calcblockdma(dsa, dmaaddr + tbc,
1304 dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
1305 /* copy changes into scratch registers */
1306 IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
1307 dsa->dmablks, legetl(dsa->dmaaddr),
1308 legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
1309 n->scratcha[2] = dsa->dmablks;
1310 lesetl(n->scratchb, dsa->dmancr);
1311 cont = E_data_block_mismatch_recover;
1313 else if (sa == E_data_out_mismatch) {
1314 dbc = write_mismatch_recover(c, n, dsa);
1315 tbc = legetl(dsa->data_buf.dbc) - dbc;
1318 advancedata(&dsa->data_buf, tbc);
1319 if (DEBUG(1) || DEBUG(2)) {
1320 IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
1321 dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
1323 cont = E_data_mismatch_recover;
1325 else if (sa == E_data_out_block_mismatch) {
1326 dbc = write_mismatch_recover(c, n, dsa);
1327 tbc = legetl(dsa->data_buf.dbc) - dbc;
1328 /* recover current state from registers */
1329 dmablks = n->scratcha[2];
1330 dmaaddr = legetl(n->scratchb);
1331 /* we have got to dmaaddr + tbc */
1332 /* we have dmablks blocks - tbc + residue left to do */
1333 /* so remaining transfer is */
1334 IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
1335 dmaaddr, tbc, dmablks);
1336 calcblockdma(dsa, dmaaddr + tbc,
1337 dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
1338 /* copy changes into scratch registers */
1339 n->scratcha[2] = dsa->dmablks;
1340 lesetl(n->scratchb, dsa->dmancr);
1341 cont = E_data_block_mismatch_recover;
1343 else if (sa == E_id_out_mismatch) {
1345 * target switched phases while attention held during
1346 * message out. The possibilities are:
1347 * 1. It didn't like the last message. This is indicated
1348 * by the new phase being message_in. Use script to recover
1350 * 2. It's not SCSI-II compliant. The new phase will be other
1351 * than message_in. We should also indicate that the device
1352 * is asynchronous, if it's the SDTR that got ignored
1354 * For now, if the phase switch is not to message_in, and
1355 * and it happens after IDENTIFY and before SDTR, we
1356 * notify the negotiation state machine.
1358 ulong lim = legetl(dsa->msg_out_buf.dbc);
1359 uchar p = n->sstat1 & 7;
1360 dbc = write_mismatch_recover(c, n, dsa);
1362 IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
1363 dsa->target, dsa->lun, tbc, lim, phase[p]);
1364 if (p != MessageIn && tbc == 1) {
1365 msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
1368 cont = E_id_out_mismatch_recover;
1370 else if (sa == E_cmd_out_mismatch) {
1372 * probably the command count is longer than the device wants ...
1374 ulong lim = legetl(dsa->cmd_buf.dbc);
1375 uchar p = n->sstat1 & 7;
1376 dbc = write_mismatch_recover(c, n, dsa);
1378 IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
1379 dsa->target, dsa->lun, tbc, lim, phase[p]);
1381 cont = E_to_decisions;
1384 IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
1385 dsa->target, dsa->lun, sa,
1387 phase[n->sstat1 & 7]);
1389 dsa->p9status = SDeio; /* chf */
1393 /*else*/ if (sist & 0x400) {
1395 IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
1397 dsa->p9status = SDtimeout;
1398 dsa->stateb = A_STATE_DONE;
1401 cont = E_issue_check;
1405 IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
1406 dsa->parityerror = 1;
1409 IPRINT(PRINTPREFIX "%s%d lun %d: unexpected disconnect\n",
1410 c->sdev->name, dsa->target, dsa->lun);
1413 dsa->p9status = SDeio;
1418 IPRINT("dstat = %.2x\n", dstat);
1420 /*else*/ if (dstat & Ssi) {
1421 ulong w = legetl(n->dsp) - c->scriptpa;
1422 IPRINT("[%lux]", w);
1424 cont = -2; /* restart */
1427 switch (legetl(n->dsps)) {
1428 case A_SIR_MSG_IO_COMPLETE:
1429 dsa->p9status = dsa->status;
1432 case A_SIR_MSG_SDTR:
1433 case A_SIR_MSG_WDTR:
1434 case A_SIR_MSG_REJECT:
1435 case A_SIR_EV_RESPONSE_OK:
1436 msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
1438 case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
1439 /* back up one in the data transfer */
1440 IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
1441 dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
1442 if (dsa->flag == 2) {
1443 IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
1444 dsa->target, dsa->lun);
1447 calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
1448 dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
1452 case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
1453 IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
1454 n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
1455 dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
1459 case A_SIR_NOTIFY_LOAD_STATE:
1460 IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
1461 if (dsa == (void*)KZERO || dsa == (void*)-1) {
1464 panic("bad dsa in load_state");
1468 case A_SIR_NOTIFY_MSG_IN:
1469 IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
1470 dsa->target, dsa->lun, n->sfbr);
1473 case A_SIR_NOTIFY_DISC:
1474 IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
1476 case A_SIR_NOTIFY_STATUS:
1477 IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
1480 case A_SIR_NOTIFY_COMMAND:
1481 IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
1484 case A_SIR_NOTIFY_DATA_IN:
1485 IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
1486 dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
1489 case A_SIR_NOTIFY_BLOCK_DATA_IN:
1490 IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
1491 dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
1494 case A_SIR_NOTIFY_DATA_OUT:
1495 IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
1498 case A_SIR_NOTIFY_DUMP:
1499 IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
1503 case A_SIR_NOTIFY_DUMP2:
1504 IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
1505 IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
1506 IPRINT(" dsa %lux", legetl(n->dsa));
1507 IPRINT(" sfbr %ux", n->sfbr);
1508 IPRINT(" a %lux", legetl(n->scratcha));
1509 IPRINT(" b %lux", legetl(n->scratchb));
1510 IPRINT(" ssid %ux", n->ssid);
1514 case A_SIR_NOTIFY_WAIT_RESELECT:
1515 IPRINT(PRINTPREFIX "wait reselect\n");
1518 case A_SIR_NOTIFY_RESELECT:
1519 IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
1520 n->ssid, n->sfbr, TK2MS(m->ticks));
1523 case A_SIR_NOTIFY_ISSUE:
1524 IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
1526 IPRINT(" tgt=%d", dsa->target);
1527 IPRINT(" time=%ld", TK2MS(m->ticks));
1531 case A_SIR_NOTIFY_ISSUE_CHECK:
1532 IPRINT(PRINTPREFIX "issue check\n");
1535 case A_SIR_NOTIFY_SIGP:
1536 IPRINT(PRINTPREFIX "responded to SIGP\n");
1539 case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
1540 ulong *dsp = c->script + (legetl(n->dsp)-c->scriptpa)/4;
1542 IPRINT(PRINTPREFIX "code at %lux", dsp - c->script);
1543 for (x = 0; x < 6; x++) {
1544 IPRINT(" %.8lux", dsp[x]);
1551 case A_SIR_NOTIFY_WSR:
1552 IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
1555 case A_SIR_NOTIFY_LOAD_SYNC:
1556 IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
1557 dsa->target, dsa->lun, n->scntl3, n->sxfer);
1560 case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
1562 IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
1563 dsa->target, dsa->lun);
1567 case A_error_reselected: /* dsa isn't valid here */
1568 iprint(PRINTPREFIX "reselection error\n");
1570 for (dsa = KPTR(legetl(c->dsalist.head)); dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
1571 IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
1575 IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
1576 dsa->target, dsa->lun, legetl(n->dsps));
1581 /*else*/ if (dstat & Iid) {
1583 ulong addr, dbc, *v;
1585 addr = legetl(n->dsp);
1587 target = dsa->target;
1593 dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
1597 IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
1599 addr, addr - c->scriptpa, dbc);
1600 addr = (ulong)c->script + addr - c->scriptpa;
1605 IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n",
1606 addr, v[0], v[1], v[2], v[3]);
1616 dsa->p9status = SDeio;
1619 /*else*/ if (dstat & Bf) {
1620 IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
1622 dsa->p9status = SDeio;
1631 if(dsa->p9status == SDnostatus)
1632 dsa->p9status = SDeio;
1637 IPRINT(PRINTPREFIX "int end 1\n");
1644 return ((Dsa *)arg)->p9status != SDnostatus;
1648 setmovedata(Movedata *d, ulong pa, ulong bc)
1661 advancedata(Movedata *d, long v)
1663 lesetl(d->pa, legetl(d->pa) + v);
1664 lesetl(d->dbc, legetl(d->dbc) - v);
1668 dumpwritedata(uchar *data, int datalen)
1673 USED(data, datalen);
1678 KPRINT(PRINTPREFIX "write:");
1679 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
1680 KPRINT("%.2ux", *bp);
1690 dumpreaddata(uchar *data, int datalen)
1695 USED(data, datalen);
1700 KPRINT(PRINTPREFIX "read:");
1701 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
1702 KPRINT("%.2ux", *bp);
1712 busreset(Controller *c)
1717 c->n->scntl1 |= (1 << 3);
1719 c->n->scntl1 &= ~(1 << 3);
1720 if(!(c->v->feature & Wide))
1723 ntarget = MAXTARGET;
1724 for (x = 0; x < ntarget; x++) {
1725 setwide(0, c, x, 0);
1727 c->s[x] = NeitherDone;
1734 reset(Controller *c)
1736 /* should wakeup all pending tasks */
1742 sd53c8xxrio(SDreq* r)
1747 uchar target_expo, my_expo;
1748 int bc, check, i, status, target;
1750 if((target = r->unit->subno) == 0x07)
1751 return r->status = SDtimeout; /* assign */
1753 c = r->unit->dev->ctlr;
1756 d = dsaalloc(c, target, r->lun);
1758 qlock(&c->q[target]); /* obtain access to target */
1760 /* load the transfer control stuff */
1761 d->scsi_id_buf[0] = 0;
1762 d->scsi_id_buf[1] = c->sxfer[target];
1763 d->scsi_id_buf[2] = target;
1764 d->scsi_id_buf[3] = c->scntl3[target];
1769 d->msg_out[bc] = 0x80 | r->lun;
1771 #ifndef NO_DISCONNECT
1772 d->msg_out[bc] |= (1 << 6);
1776 /* work out what to do about negotiation */
1777 switch (c->s[target]) {
1779 KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
1780 c->s[target] = NeitherDone;
1783 if ((c->capvalid & (1 << target)) == 0)
1785 target_expo = (c->cap[target] >> 5) & 3;
1786 my_expo = (c->v->feature & Wide) != 0;
1787 if (target_expo < my_expo)
1788 my_expo = target_expo;
1789 #ifdef ALWAYS_DO_WDTR
1790 bc += buildwdtrmsg(d->msg_out + bc, my_expo);
1791 KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
1792 c->s[target] = WideInit;
1796 bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
1797 KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
1798 c->s[target] = WideInit;
1801 KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
1805 if (c->cap[target] & (1 << 4)) {
1806 KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
1807 bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
1808 c->s[target] = SyncInit;
1811 KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
1812 c->s[target] = BothDone;
1819 setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
1820 setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
1821 calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
1824 KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
1825 for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
1826 KPRINT("%.2ux", *bp);
1830 KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
1831 target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
1834 dumpwritedata(r->data, r->dlen);
1837 setmovedata(&d->status_buf, DMASEG(&d->status), 1);
1839 d->p9status = SDnostatus;
1842 d->stateb = A_STATE_ISSUE; /* start operation */
1847 c->n->dcntl |= 0x10; /* single step */
1852 start(c, E_issue_check);
1858 tsleep(d, done, d, 600 * 1000);
1862 KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
1866 qunlock(&c->q[target]);
1867 r->status = SDtimeout;
1868 return r->status = SDtimeout; /* assign */
1871 if((status = d->p9status) == SDeio)
1872 c->s[target] = NeitherDone;
1873 if (d->parityerror) {
1882 KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
1883 target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
1887 r->rlen -= d->dmablks * A_BSIZE;
1888 r->rlen -= legetl(d->data_buf.dbc);
1891 dumpreaddata(r->data, r->rlen);
1893 KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
1894 target, r->lun, d->p9status, status, r->rlen);
1899 if ((c->capvalid & (1 << target)) == 0
1900 && (status == SDok || status == SDcheck)
1901 && r->cmd[0] == 0x12 && r->dlen >= 8) {
1902 c->capvalid |= 1 << target;
1904 c->cap[target] = bp[7];
1905 KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
1907 if(!check && status == SDcheck && !(r->flags & SDnosense)){
1910 memset(r->cmd, 0, sizeof(r->cmd));
1912 r->cmd[1] = r->lun<<5;
1913 r->cmd[4] = sizeof(r->sense)-1;
1916 r->dlen = sizeof(r->sense)-1;
1918 * Clear out the microcode state
1919 * so the Dsa can be re-used.
1921 lesetl(&d->stateb, A_STATE_ALLOCATED);
1925 qunlock(&c->q[target]);
1928 if(status == SDok && check){
1930 r->flags |= SDvalidsense;
1933 KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
1934 target, r->flags, status, r->rlen);
1935 if(r->flags & SDvalidsense){
1937 KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
1938 target, r->flags, status, r->rlen);
1939 for(i = 0; i < r->rlen; i++)
1940 KPRINT(" %2.2uX", r->sense[i]);
1943 return r->status = status;
1947 cribbios(Controller *c)
1949 c->bios.scntl3 = c->n->scntl3;
1950 c->bios.stest2 = c->n->stest2;
1951 print(PRINTPREFIX "%s: bios scntl3(%.2x) stest2(%.2x)\n",
1952 c->sdev->name, c->bios.scntl3, c->bios.stest2);
1956 bios_set_differential(Controller *c)
1958 /* Concept lifted from FreeBSD - thanks Gerard */
1959 /* basically, if clock conversion factors are set, then there is
1960 * evidence the bios had a go at the chip, and if so, it would
1961 * have set the differential enable bit in stest2
1963 return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
1966 #define NCR_VID 0x1000
1967 #define NCR_810_DID 0x0001
1968 #define NCR_820_DID 0x0002 /* don't know enough about this one to support it */
1969 #define NCR_825_DID 0x0003
1970 #define NCR_815_DID 0x0004
1971 #define SYM_810AP_DID 0x0005
1972 #define SYM_860_DID 0x0006
1973 #define SYM_896_DID 0x000b
1974 #define SYM_895_DID 0x000c
1975 #define SYM_885_DID 0x000d /* ditto */
1976 #define SYM_875_DID 0x000f /* ditto */
1977 #define SYM_1010_DID 0x0020
1978 #define SYM_1011_DID 0x0021
1979 #define SYM_875J_DID 0x008f
1981 static Variant variant[] = {
1982 { NCR_810_DID, 0x0f, "NCR53C810", Burst16, 8, 24, 0 },
1983 { NCR_810_DID, 0x1f, "SYM53C810ALV", Burst16, 8, 24, Prefetch },
1984 { NCR_810_DID, 0xff, "SYM53C810A", Burst16, 8, 24, Prefetch },
1985 { SYM_810AP_DID, 0xff, "SYM53C810AP", Burst16, 8, 24, Prefetch },
1986 { NCR_815_DID, 0xff, "NCR53C815", Burst16, 8, 24, BurstOpCodeFetch },
1987 { NCR_825_DID, 0x0f, "NCR53C825", Burst16, 8, 24, Wide|BurstOpCodeFetch|Differential },
1988 { NCR_825_DID, 0xff, "SYM53C825A", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
1989 { SYM_860_DID, 0x0f, "SYM53C860", Burst16, 8, 24, Prefetch|Ultra },
1990 { SYM_860_DID, 0xff, "SYM53C860LV", Burst16, 8, 24, Prefetch|Ultra },
1991 { SYM_875_DID, 0x01, "SYM53C875r1", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
1992 { SYM_875_DID, 0xff, "SYM53C875", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
1993 { SYM_875J_DID, 0xff, "SYM53C875j", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
1994 { SYM_885_DID, 0xff, "SYM53C885", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
1995 { SYM_895_DID, 0xff, "SYM53C895", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1996 { SYM_896_DID, 0xff, "SYM53C896", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1997 { SYM_1010_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
1998 { SYM_1011_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
2002 xfunc(Controller *c, enum na_external x, unsigned long *v)
2006 print("xfunc: can't find external %d\n", x);
2009 *v = offsetof(Dsa, scsi_id_buf[0]);
2012 *v = offsetof(Dsa, msg_out_buf);
2015 *v = offsetof(Dsa, cmd_buf);
2018 *v = offsetof(Dsa, data_buf);
2021 *v = offsetof(Dsa, status_buf);
2024 *v = DMASEG(&c->dsalist.head[0]);
2034 na_fixup(Controller *c, ulong pa_reg,
2035 struct na_patch *patch, int patches,
2036 int (*externval)(Controller*, int, ulong*))
2040 ulong *script, pa_script;
2041 unsigned long lw, lv;
2044 pa_script = c->scriptpa;
2045 for (p = 0; p < patches; p++) {
2046 switch (patch[p].type) {
2048 /* script relative */
2049 script[patch[p].lwoff] += pa_script;
2052 /* register i/o relative */
2053 script[patch[p].lwoff] += pa_reg;
2057 lw = script[patch[p].lwoff];
2058 v = (lw >> 8) & 0xff;
2059 if (!(*externval)(c, v, &lv))
2062 script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
2065 /* 32 bit external */
2066 lw = script[patch[p].lwoff];
2067 if (!(*externval)(c, lw, &lv))
2069 script[patch[p].lwoff] = lv;
2072 /* 24 bit external */
2073 lw = script[patch[p].lwoff];
2074 if (!(*externval)(c, lw & 0xffffff, &lv))
2076 script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
2092 SDev *sdev, *head, *tail;
2093 ulong regpa, *script, scriptpa;
2094 void *regva, *scriptva;
2096 if(cp = getconf("*maxsd53c8xx"))
2097 nctlr = strtoul(cp, 0, 0);
2103 while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
2104 for(v = variant; v < &variant[nelem(variant)]; v++){
2105 if(p->did == v->did && p->rid <= v->maxrid)
2108 if(v >= &variant[nelem(variant)]) {
2109 print("no match\n");
2112 print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
2113 v->name, p->rid, p->intl, p->pcr);
2115 regpa = p->mem[1].bar;
2125 regva = vmap(regpa, p->mem[1].size);
2133 if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
2134 scriptpa = p->mem[ba].bar;
2135 if((scriptpa & 0x04) && p->mem[ba+1].bar){
2136 vunmap(regva, p->mem[1].size);
2140 scriptva = vmap(scriptpa, p->mem[ba].size);
2146 * Either the map failed, or this chip does not have
2147 * local RAM. It will need a copy of the microcode.
2149 scriptma = malloc(sizeof(na_script));
2150 if(scriptma == nil){
2151 vunmap(regva, p->mem[1].size);
2154 scriptpa = DMASEG(scriptma);
2158 ctlr = malloc(sizeof(Controller));
2159 sdev = malloc(sizeof(SDev));
2160 if(ctlr == nil || sdev == nil){
2169 vunmap(scriptva, p->mem[ba].size);
2171 vunmap(regva, p->mem[1].size);
2176 dsaend = xalloc(sizeof *dsaend);
2178 panic("sd53c8xxpnp: no memory");
2179 lesetl(&dsaend->stateb, A_STATE_END);
2180 // lesetl(dsaend->next, DMASEG(dsaend));
2182 lesetl(ctlr->dsalist.head, DMASEG(dsaend));
2184 ctlr->dsalist.freechain = 0;
2188 ctlr->script = script;
2189 memmove(ctlr->script, na_script, sizeof(na_script));
2192 * Because we don't yet have an abstraction for the
2193 * addresses as seen from the controller side (and on
2194 * the 386 it doesn't matter), the following two lines
2195 * are different between the 386 and alpha copies of
2198 ctlr->scriptpa = scriptpa;
2199 if(!na_fixup(ctlr, regpa, na_patches, NA_PATCHES, xfunc)){
2200 print("script fixup failed\n");
2203 swabl(ctlr->script, ctlr->script, sizeof(na_script));
2207 sdev->ifc = &sd53c8xxifc;
2210 if(!(v->feature & Wide))
2213 sdev->nunit = MAXTARGET;
2229 sd53c8xxenable(SDev* sdev)
2236 pcidev = ctlr->pcidev;
2244 snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
2245 intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
2251 SDifc sd53c8xxifc = {
2252 "53c8xx", /* name */
2254 sd53c8xxpnp, /* pnp */
2256 sd53c8xxenable, /* enable */
2259 scsiverify, /* verify */
2260 scsionline, /* online */
2261 sd53c8xxrio, /* rio */