3 * Needs a massive rewrite.
6 #include "../port/lib.h"
11 #include "../port/error.h"
13 #define DBG if(0) pcilog
22 pcilog(char *fmt, ...)
29 n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;
32 memmove(PCICONS.output+PCICONS.ptr, buf, n);
38 { /* configuration mechanism #1 */
39 PciADDR = 0xCF8, /* CONFIG_ADDRESS */
40 PciDATA = 0xCFC, /* CONFIG_DATA */
42 /* configuration mechanism #2 */
43 PciCSE = 0xCF8, /* configuration space enable */
44 PciFORWARD = 0xCFA, /* which bus */
51 { /* command register */
60 static Lock pcicfglock;
61 static Lock pcicfginitlock;
62 static int pcicfgmode = -1;
63 static int pcimaxbno = 7;
65 static Pcidev* pciroot;
66 static Pcidev* pcilist;
67 static Pcidev* pcitail;
68 static int nobios, nopcirouting;
69 static BIOS32si* pcibiossi;
71 static int pcicfgrw8raw(int, int, int, int);
72 static int pcicfgrw16raw(int, int, int, int);
73 static int pcicfgrw32raw(int, int, int, int);
75 static int (*pcicfgrw8)(int, int, int, int) = pcicfgrw8raw;
76 static int (*pcicfgrw16)(int, int, int, int) = pcicfgrw16raw;
77 static int (*pcicfgrw32)(int, int, int, int) = pcicfgrw32raw;
79 static char* bustypes[] = {
107 if((p = malloc(READSTR)) == nil)
108 return fmtstrcpy(fmt, "(tbdfconv)");
112 tbdf = va_arg(fmt->args, int);
113 if(tbdf == BUSUNKNOWN)
114 snprint(p, READSTR, "unknown");
116 type = BUSTYPE(tbdf);
117 if(type < nelem(bustypes))
118 l = snprint(p, READSTR, bustypes[type]);
120 l = snprint(p, READSTR, "%d", type);
121 snprint(p+l, READSTR-l, ".%d.%d.%d",
122 BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
127 snprint(p, READSTR, "(tbdfconv)");
130 r = fmtstrcpy(fmt, p);
137 pcibarsize(Pcidev *p, int rno)
141 v = pcicfgrw32(p->tbdf, rno, 0, 1);
142 pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
143 size = pcicfgrw32(p->tbdf, rno, 0, 1);
146 pcicfgrw32(p->tbdf, rno, v, 0);
148 return -(size & ~0x0F);
152 pcisizcmp(void *a, void *b)
158 return aa->siz - bb->siz;
167 for(m = 1<<(m-1); m != 0; m >>= 1) {
181 pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
184 int ntb, i, size, rno, hole;
185 ulong v, mema, ioa, sioa, smema, base, limit;
186 Pcisiz *table, *tptr, *mtb, *itb;
194 DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
195 wrreg, root->tbdf, mema, ioa);
198 for(p = root; p != nil; p = p->link)
201 ntb *= (PciCIS-PciBAR0)/4;
202 table = malloc(2*ntb*sizeof(Pcisiz));
207 * Build a table of sizes
209 for(p = root; p != nil; p = p->link) {
210 if(p->ccrb == 0x06) {
211 if(p->ccru != 0x04 || p->bridge == nil) {
212 // DBG("pci: ignored bridge %T\n", p->tbdf);
218 pcibusmap(p->bridge, &smema, &sioa, 0);
220 hole = pcimask(smema-mema);
225 hole = pcimask(sioa-ioa);
233 itb->siz = p->ioa.size;
238 mtb->siz = p->mema.size;
243 for(i = 0; i <= 5; i++) {
245 v = pcicfgrw32(p->tbdf, rno, 0, 1);
246 size = pcibarsize(p, rno);
263 p->mem[i].size = size;
268 * Sort both tables IO smallest first, Memory largest
270 qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp);
272 qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
275 * Allocate IO address space on this bus
277 for(tptr = table; tptr < itb; tptr++) {
281 ioa = (ioa+hole-1) & ~(hole-1);
288 p->mem[tptr->bar].bar = ioa|1;
290 pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
297 * Allocate Memory address space on this bus
299 for(tptr = table+ntb; tptr < mtb; tptr++) {
303 mema = (mema+hole-1) & ~(hole-1);
310 p->mem[tptr->bar].bar = mema;
312 pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0);
325 * Finally set all the bridge addresses & registers
327 for(p = root; p != nil; p = p->link) {
328 if(p->bridge == nil) {
329 pcicfgrw8(p->tbdf, PciLTR, 64, 0);
332 pcicfgrw16(p->tbdf, PciPCR, p->pcr, 0);
337 limit = base+p->ioa.size-1;
338 v = pcicfgrw32(p->tbdf, PciIBR, 0, 1);
339 v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8);
340 pcicfgrw32(p->tbdf, PciIBR, v, 0);
341 v = (limit & 0xFFFF0000)|(base>>16);
342 pcicfgrw32(p->tbdf, PciIUBR, v, 0);
345 limit = base+p->mema.size-1;
346 v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16);
347 pcicfgrw32(p->tbdf, PciMBR, v, 0);
350 * Disable memory prefetch
352 pcicfgrw32(p->tbdf, PciPMBR, 0x0000FFFF, 0);
353 pcicfgrw8(p->tbdf, PciLTR, 64, 0);
358 p->pcr |= IOen|MEMen|MASen;
359 pcicfgrw32(p->tbdf, PciPCR, 0xFFFF0000|p->pcr , 0);
363 pcibusmap(p->bridge, &smema, &sioa, 1);
368 pcilscan(int bno, Pcidev** list)
370 Pcidev *p, *head, *tail;
371 int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
376 for(dno = 0; dno <= pcimaxdno; dno++){
378 for(fno = 0; fno <= maxfno; fno++){
380 * For this possible device, form the
381 * bus+device+function triplet needed to address it
382 * and try to read the vendor and device ID.
383 * If successful, allocate a device struct and
384 * start to fill it in with some useful information
385 * from the device's configuration space.
387 tbdf = MKBUS(BusPCI, bno, dno, fno);
388 l = pcicfgrw32(tbdf, PciVID, 0, 1);
389 if(l == 0xFFFFFFFF || l == 0)
391 p = malloc(sizeof(*p));
402 p->pcr = pcicfgr16(p, PciPCR);
403 p->rid = pcicfgr8(p, PciRID);
404 p->ccrp = pcicfgr8(p, PciCCRp);
405 p->ccru = pcicfgr8(p, PciCCRu);
406 p->ccrb = pcicfgr8(p, PciCCRb);
407 p->cls = pcicfgr8(p, PciCLS);
408 p->ltr = pcicfgr8(p, PciLTR);
410 p->intl = pcicfgr8(p, PciINTL);
413 * If the device is a multi-function device adjust the
414 * loop count so all possible functions are checked.
416 hdt = pcicfgr8(p, PciHDT);
421 * If appropriate, read the base address registers
422 * and work out the sizes.
425 case 0x01: /* mass storage controller */
426 case 0x02: /* network controller */
427 case 0x03: /* display controller */
428 case 0x04: /* multimedia device */
429 case 0x07: /* simple comm. controllers */
430 case 0x08: /* base system peripherals */
431 case 0x09: /* input devices */
432 case 0x0A: /* docking stations */
433 case 0x0B: /* processors */
434 case 0x0C: /* serial bus controllers */
435 if((hdt & 0x7F) != 0)
438 for(i = 0; i < nelem(p->mem); i++) {
440 p->mem[i].bar = pcicfgr32(p, rno);
441 p->mem[i].size = pcibarsize(p, rno);
446 case 0x05: /* memory controller */
447 case 0x06: /* bridge device */
461 for(p = head; p != nil; p = p->link){
463 * Find PCI-PCI bridges and recursively descend the tree.
465 if(p->ccrb != 0x06 || p->ccru != 0x04)
469 * If the secondary or subordinate bus number is not
470 * initialised try to do what the PCI BIOS should have
471 * done and fill in the numbers as the tree is descended.
472 * On the way down the subordinate bus number is set to
473 * the maximum as it's not known how many buses are behind
474 * this one; the final value is set on the way back up.
476 sbn = pcicfgr8(p, PciSBN);
477 ubn = pcicfgr8(p, PciUBN);
479 if(sbn == 0 || ubn == 0 || nobios) {
482 * Make sure memory, I/O and master enables are
483 * off, set the primary, secondary and subordinate
484 * bus numbers and clear the secondary status before
485 * attempting to scan the secondary bus.
487 * Initialisation of the bridge should be done here.
489 pcicfgw32(p, PciPCR, 0xFFFF0000);
490 l = (MaxUBN<<16)|(sbn<<8)|bno;
491 pcicfgw32(p, PciPBN, l);
492 pcicfgw16(p, PciSPSR, 0xFFFF);
493 maxubn = pcilscan(sbn, &p->bridge);
494 l = (maxubn<<16)|(sbn<<8)|bno;
496 pcicfgw32(p, PciPBN, l);
501 pcilscan(sbn, &p->bridge);
509 pciscan(int bno, Pcidev **list)
513 lock(&pcicfginitlock);
514 ubn = pcilscan(bno, list);
515 unlock(&pcicfginitlock);
520 pIIxget(Pcidev *router, uchar link)
524 /* link should be 0x60, 0x61, 0x62, 0x63 */
525 pirq = pcicfgr8(router, link);
526 return (pirq < 16)? pirq: 0;
530 pIIxset(Pcidev *router, uchar link, uchar irq)
532 pcicfgw8(router, link, irq);
536 viaget(Pcidev *router, uchar link)
540 /* link should be 1, 2, 3, 5 */
541 pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
543 return (link & 1)? (pirq >> 4): (pirq & 15);
547 viaset(Pcidev *router, uchar link, uchar irq)
551 pirq = pcicfgr8(router, 0x55 + (link >> 1));
552 pirq &= (link & 1)? 0x0f: 0xf0;
553 pirq |= (link & 1)? (irq << 4): (irq & 15);
554 pcicfgw8(router, 0x55 + (link>>1), pirq);
558 optiget(Pcidev *router, uchar link)
562 /* link should be 0x02, 0x12, 0x22, 0x32 */
563 if ((link & 0xcf) == 0x02)
564 pirq = pcicfgr8(router, 0xb8 + (link >> 5));
565 return (link & 0x10)? (pirq >> 4): (pirq & 15);
569 optiset(Pcidev *router, uchar link, uchar irq)
573 pirq = pcicfgr8(router, 0xb8 + (link >> 5));
574 pirq &= (link & 0x10)? 0x0f : 0xf0;
575 pirq |= (link & 0x10)? (irq << 4): (irq & 15);
576 pcicfgw8(router, 0xb8 + (link >> 5), pirq);
580 aliget(Pcidev *router, uchar link)
582 /* No, you're not dreaming */
583 static const uchar map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
586 /* link should be 0x01..0x08 */
587 pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
588 return (link & 1)? map[pirq&15]: map[pirq>>4];
592 aliset(Pcidev *router, uchar link, uchar irq)
594 /* Inverse of map in aliget */
595 static const uchar map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
598 pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
599 pirq &= (link & 1)? 0x0f: 0xf0;
600 pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
601 pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
605 cyrixget(Pcidev *router, uchar link)
609 /* link should be 1, 2, 3, 4 */
610 pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
611 return ((link & 1)? pirq >> 4: pirq & 15);
615 cyrixset(Pcidev *router, uchar link, uchar irq)
619 pirq = pcicfgr8(router, 0x5c + (link>>1));
620 pirq &= (link & 1)? 0x0f: 0xf0;
621 pirq |= (link & 1)? (irq << 4): (irq & 15);
622 pcicfgw8(router, 0x5c + (link>>1), pirq);
625 typedef struct Bridge Bridge;
630 uchar (*get)(Pcidev *, uchar);
631 void (*set)(Pcidev *, uchar, uchar);
634 static Bridge southbridges[] = {
635 { 0x8086, 0x122e, pIIxget, pIIxset }, /* Intel 82371FB */
636 { 0x8086, 0x1234, pIIxget, pIIxset }, /* Intel 82371MX */
637 { 0x8086, 0x7000, pIIxget, pIIxset }, /* Intel 82371SB */
638 { 0x8086, 0x7110, pIIxget, pIIxset }, /* Intel 82371AB */
639 { 0x8086, 0x7198, pIIxget, pIIxset }, /* Intel 82443MX (fn 1) */
640 { 0x8086, 0x2410, pIIxget, pIIxset }, /* Intel 82801AA */
641 { 0x8086, 0x2420, pIIxget, pIIxset }, /* Intel 82801AB */
642 { 0x8086, 0x2440, pIIxget, pIIxset }, /* Intel 82801BA */
643 { 0x8086, 0x244c, pIIxget, pIIxset }, /* Intel 82801BAM */
644 { 0x8086, 0x2480, pIIxget, pIIxset }, /* Intel 82801CA */
645 { 0x8086, 0x248c, pIIxget, pIIxset }, /* Intel 82801CAM */
646 { 0x8086, 0x24c0, pIIxget, pIIxset }, /* Intel 82801DBL */
647 { 0x8086, 0x24cc, pIIxget, pIIxset }, /* Intel 82801DBM */
648 { 0x8086, 0x24d0, pIIxget, pIIxset }, /* Intel 82801EB */
649 { 0x8086, 0x25a1, pIIxget, pIIxset }, /* Intel 6300ESB */
650 { 0x8086, 0x2640, pIIxget, pIIxset }, /* Intel 82801FB */
651 { 0x8086, 0x2641, pIIxget, pIIxset }, /* Intel 82801FBM */
652 { 0x8086, 0x27b8, pIIxget, pIIxset }, /* Intel 82801GB */
653 { 0x8086, 0x27b9, pIIxget, pIIxset }, /* Intel 82801GBM */
654 { 0x8086, 0x2916, pIIxget, pIIxset }, /* Intel 82801? */
655 { 0x1106, 0x0586, viaget, viaset }, /* Viatech 82C586 */
656 { 0x1106, 0x0596, viaget, viaset }, /* Viatech 82C596 */
657 { 0x1106, 0x0686, viaget, viaset }, /* Viatech 82C686 */
658 { 0x1106, 0x3227, viaget, viaset }, /* Viatech VT8237 */
659 { 0x1045, 0xc700, optiget, optiset }, /* Opti 82C700 */
660 { 0x10b9, 0x1533, aliget, aliset }, /* Al M1533 */
661 { 0x1039, 0x0008, pIIxget, pIIxset }, /* SI 503 */
662 { 0x1039, 0x0496, pIIxget, pIIxset }, /* SI 496 */
663 { 0x1078, 0x0100, cyrixget, cyrixset }, /* Cyrix 5530 Legacy */
665 { 0x1022, 0x746B, nil, nil }, /* AMD 8111 */
666 { 0x10DE, 0x00D1, nil, nil }, /* NVIDIA nForce 3 */
667 { 0x10DE, 0x00E0, nil, nil }, /* NVIDIA nForce 3 250 Series */
668 { 0x10DE, 0x00E1, nil, nil }, /* NVIDIA nForce 3 250 Series */
669 { 0x1166, 0x0200, nil, nil }, /* ServerWorks ServerSet III LE */
670 { 0x1002, 0x4377, nil, nil }, /* ATI Radeon Xpress 200M */
671 { 0x1002, 0x4372, nil, nil }, /* ATI SB400 */
674 typedef struct Slot Slot;
676 uchar bus; /* Pci bus number */
677 uchar dev; /* Pci device number */
678 uchar maps[12]; /* Avoid structs! Link and mask. */
679 uchar slot; /* Add-in/built-in slot */
683 typedef struct Router Router;
685 uchar signature[4]; /* Routing table signature */
686 uchar version[2]; /* Version number */
687 uchar size[2]; /* Total table size */
688 uchar bus; /* Interrupt router bus number */
689 uchar devfn; /* Router's devfunc */
690 uchar pciirqs[2]; /* Exclusive PCI irqs */
691 uchar compat[4]; /* Compatible PCI interrupt router */
692 uchar miniport[4]; /* Miniport data */
697 static ushort pciirqs; /* Exclusive PCI irqs */
698 static Bridge *southbridge; /* Which southbridge to use. */
705 int size, i, fn, tbdf;
707 uchar *p, pin, irq, link, *map;
709 /* Search for PCI interrupt routing table in BIOS */
710 for(p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
711 if(p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
714 if(p >= (uchar *)KADDR(0xfffff))
719 // print("PCI interrupt routing table version %d.%d at %.6uX\n",
720 // r->version[0], r->version[1], (ulong)r & 0xfffff);
722 tbdf = (BusPCI << 24)|(r->bus << 16)|(r->devfn << 8);
723 sbpci = pcimatchtbdf(tbdf);
725 print("pcirouting: Cannot find south bridge %T\n", tbdf);
729 for(i = 0; i != nelem(southbridges); i++)
730 if(sbpci->vid == southbridges[i].vid && sbpci->did == southbridges[i].did)
733 if(i == nelem(southbridges)) {
734 print("pcirouting: ignoring south bridge %T %.4uX/%.4uX\n", tbdf, sbpci->vid, sbpci->did);
737 southbridge = &southbridges[i];
738 if(southbridge->get == nil || southbridge->set == nil)
741 pciirqs = (r->pciirqs[1] << 8)|r->pciirqs[0];
743 size = (r->size[1] << 8)|r->size[0];
744 for(e = (Slot *)&r[1]; (uchar *)e < p + size; e++) {
746 print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
747 for (i = 0; i != 4; i++) {
748 uchar *m = &e->maps[i * 3];
749 print("[%d] %.2uX %.4uX ",
750 i, m[0], (m[2] << 8)|m[1]);
754 for(fn = 0; fn != 8; fn++) {
755 tbdf = (BusPCI << 24)|(e->bus << 16)|((e->dev | fn) << 8);
756 pci = pcimatchtbdf(tbdf);
759 pin = pcicfgr8(pci, PciINTP);
760 if(pin == 0 || pin == 0xff)
763 map = &e->maps[(pin - 1) * 3];
765 irq = southbridge->get(sbpci, link);
766 if(irq == 0 || irq == pci->intl)
768 if(pci->intl != 0 && pci->intl != 0xFF) {
769 print("pcirouting: BIOS workaround: %T at pin %d link %d irq %d -> %d\n",
770 tbdf, pin, link, irq, pci->intl);
771 southbridge->set(sbpci, link, pci->intl);
774 print("pcirouting: %T at pin %d link %d irq %d\n", tbdf, pin, link, irq);
775 pcicfgw8(pci, PciINTL, irq);
781 static void pcireservemem(void);
784 pcicfgrw8bios(int tbdf, int rno, int data, int read)
791 memset(&ci, 0, sizeof(BIOS32ci));
792 ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
796 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
797 return ci.ecx & 0xFF;
801 ci.ecx = data & 0xFF;
802 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
810 pcicfgrw16bios(int tbdf, int rno, int data, int read)
817 memset(&ci, 0, sizeof(BIOS32ci));
818 ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
822 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
823 return ci.ecx & 0xFFFF;
827 ci.ecx = data & 0xFFFF;
828 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
836 pcicfgrw32bios(int tbdf, int rno, int data, int read)
843 memset(&ci, 0, sizeof(BIOS32ci));
844 ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
848 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
854 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
867 if((si = bios32open("$PCI")) == nil)
870 memset(&ci, 0, sizeof(BIOS32ci));
872 if(bios32ci(si, &ci) || ci.edx != ((' '<<24)|('I'<<16)|('C'<<8)|'P')){
880 pcimaxbno = ci.ecx & 0xff;
886 pcibussize(Pcidev *root, ulong *msize, ulong *iosize)
890 pcibusmap(root, msize, iosize, 0);
901 lock(&pcicfginitlock);
906 if(getconf("*nobios"))
908 else if(getconf("*pcibios"))
910 if(getconf("*nopcirouting"))
914 * Try to determine which PCI configuration mode is implemented.
915 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
916 * a DWORD at 0xCF8 and another at 0xCFC and will pass through
917 * any non-DWORD accesses as normal I/O cycles. There shouldn't be
918 * a device behind these addresses so if Mode1 accesses fail try
919 * for Mode2 (Mode2 is deprecated).
923 * Bits [30:24] of PciADDR must be 0,
924 * according to the spec.
927 if(!(n & 0x7F000000)){
928 outl(PciADDR, 0x80000000);
930 if(inl(PciADDR) & 0x80000000){
939 * The 'key' part of PciCSE should be 0.
944 if(inb(PciCSE) == 0x0E){
953 if(pcicfgmode < 0 || pcibios) {
954 if((pcibiossi = pcibiosinit()) == nil)
956 pcicfgrw8 = pcicfgrw8bios;
957 pcicfgrw16 = pcicfgrw16bios;
958 pcicfgrw32 = pcicfgrw32bios;
962 fmtinstall('T', tbdffmt);
964 if(p = getconf("*pcimaxbno")){
965 n = strtoul(p, 0, 0);
969 if(p = getconf("*pcimaxdno")){
970 n = strtoul(p, 0, 0);
976 for(bno = 0; bno <= pcimaxbno; bno++) {
978 bno = pcilscan(bno, list);
981 list = &(*list)->link;
987 * If we have found a PCI-to-Cardbus bridge, make sure
988 * it has no valid mappings anymore.
990 for(pci = pciroot; pci != nil; pci = pci->link){
991 if (pci->ccrb == 6 && pci->ccru == 7) {
994 /* reset the cardbus */
995 bcr = pcicfgr16(pci, PciBCR);
996 pcicfgw16(pci, PciBCR, 0x40 | bcr);
1008 * Work out how big the top bus is
1010 pcibussize(pciroot, &mema, &ioa);
1013 * Align the windows and map it
1018 pcilog("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
1020 pcibusmap(pciroot, &mema, &ioa, 1);
1021 DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
1023 unlock(&pcicfginitlock);
1032 unlock(&pcicfginitlock);
1034 if(getconf("*pcihinv"))
1045 * mark all the physical address space claimed by pci devices
1046 * as in use, so that upaalloc doesn't give it out.
1048 for(p=pciroot; p; p=p->list)
1049 for(i=0; i<nelem(p->mem); i++)
1050 if(p->mem[i].bar && (p->mem[i].bar&1) == 0)
1051 upareserve(p->mem[i].bar&~0x0F, p->mem[i].size);
1055 pcicfgrw8raw(int tbdf, int rno, int data, int read)
1059 if(pcicfgmode == -1)
1067 if(BUSDNO(tbdf) > pcimaxdno)
1076 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
1080 outb(PciDATA+o, data);
1085 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
1086 outb(PciFORWARD, BUSBNO(tbdf));
1088 x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
1090 outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
1094 unlock(&pcicfglock);
1100 pcicfgr8(Pcidev* pcidev, int rno)
1102 return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
1106 pcicfgw8(Pcidev* pcidev, int rno, int data)
1108 pcicfgrw8(pcidev->tbdf, rno, data, 0);
1112 pcicfgrw16raw(int tbdf, int rno, int data, int read)
1116 if(pcicfgmode == -1)
1124 if(BUSDNO(tbdf) > pcimaxdno)
1133 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
1137 outs(PciDATA+o, data);
1142 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
1143 outb(PciFORWARD, BUSBNO(tbdf));
1145 x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
1147 outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
1151 unlock(&pcicfglock);
1157 pcicfgr16(Pcidev* pcidev, int rno)
1159 return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
1163 pcicfgw16(Pcidev* pcidev, int rno, int data)
1165 pcicfgrw16(pcidev->tbdf, rno, data, 0);
1169 pcicfgrw32raw(int tbdf, int rno, int data, int read)
1173 if(pcicfgmode == -1)
1181 if(BUSDNO(tbdf) > pcimaxdno)
1189 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
1193 outl(PciDATA, data);
1198 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
1199 outb(PciFORWARD, BUSBNO(tbdf));
1201 x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
1203 outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
1207 unlock(&pcicfglock);
1213 pcicfgr32(Pcidev* pcidev, int rno)
1215 return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
1219 pcicfgw32(Pcidev* pcidev, int rno, int data)
1221 pcicfgrw32(pcidev->tbdf, rno, data, 0);
1225 pcimatch(Pcidev* prev, int vid, int did)
1227 if(pcicfgmode == -1)
1236 if((vid == 0 || prev->vid == vid)
1237 && (did == 0 || prev->did == did))
1245 pcimatchtbdf(int tbdf)
1249 if(pcicfgmode == -1)
1252 for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
1253 if(pcidev->tbdf == tbdf)
1260 pciipin(Pcidev *pci, uchar pin)
1268 if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
1271 if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
1286 putstrn(PCICONS.output, PCICONS.ptr);
1288 print("bus dev type vid did intl memory\n");
1290 for(t = p; t != nil; t = t->link) {
1291 print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
1292 BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
1293 t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
1295 for(i = 0; i < nelem(p->mem); i++) {
1296 if(t->mem[i].size == 0)
1298 print("%d:%.8lux %d ", i,
1299 t->mem[i].bar, t->mem[i].size);
1301 if(t->ioa.bar || t->ioa.size)
1302 print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size);
1303 if(t->mema.bar || t->mema.size)
1304 print("mema:%.8lux %d ", t->mema.bar, t->mema.size);
1306 print("->%d", BUSBNO(t->bridge->tbdf));
1310 if(p->bridge != nil)
1311 pcilhinv(p->bridge);
1319 if(pcicfgmode == -1)
1321 lock(&pcicfginitlock);
1323 unlock(&pcicfginitlock);
1331 if(pcicfgmode == -1)
1334 for(p = pcilist; p != nil; p = p->list) {
1335 /* don't mess with the bridges */
1343 pcisetioe(Pcidev* p)
1346 pcicfgw16(p, PciPCR, p->pcr);
1350 pciclrioe(Pcidev* p)
1353 pcicfgw16(p, PciPCR, p->pcr);
1357 pcisetbme(Pcidev* p)
1360 pcicfgw16(p, PciPCR, p->pcr);
1364 pciclrbme(Pcidev* p)
1367 pcicfgw16(p, PciPCR, p->pcr);
1371 pcisetmwi(Pcidev* p)
1374 pcicfgw16(p, PciPCR, p->pcr);
1378 pciclrmwi(Pcidev* p)
1380 p->pcr &= ~MemWrInv;
1381 pcicfgw16(p, PciPCR, p->pcr);
1385 pcigetpmrb(Pcidev* p)
1394 * If there are no extended capabilities implemented,
1395 * (bit 4 in the status register) assume there's no standard
1396 * power management method.
1397 * Find the capabilities pointer based on PCI header type.
1399 if(!(pcicfgr16(p, PciPSR) & 0x0010))
1401 switch(pcicfgr8(p, PciHDT)){
1404 case 0: /* all other */
1405 case 1: /* PCI to PCI bridge */
1408 case 2: /* CardBus bridge */
1412 ptr = pcicfgr32(p, ptr);
1416 * Check for validity.
1417 * Can't be in standard header and must be double
1420 if(ptr < 0x40 || (ptr & ~0xFC))
1422 if(pcicfgr8(p, ptr) == 0x01){
1427 ptr = pcicfgr8(p, ptr+1);
1434 pcigetpms(Pcidev* p)
1438 if((ptr = pcigetpmrb(p)) == -1)
1442 * Power Management Register Block:
1443 * offset 0: Capability ID
1444 * 1: next item pointer
1447 * 6: bridge support extensions
1450 pmcsr = pcicfgr16(p, ptr+4);
1452 return pmcsr & 0x0003;
1456 pcisetpms(Pcidev* p, int state)
1458 int ostate, pmc, pmcsr, ptr;
1460 if((ptr = pcigetpmrb(p)) == -1)
1463 pmc = pcicfgr16(p, ptr+2);
1464 pmcsr = pcicfgr16(p, ptr+4);
1465 ostate = pmcsr & 0x0003;
1485 pcicfgw16(p, ptr+4, pmcsr);
1491 pcinextcap(Pcidev *pci, int offset)
1494 if((pcicfgr16(pci, PciPSR) & (1<<4)) == 0)
1495 return 0; /* no capabilities */
1498 return pcicfgr8(pci, offset+1) & ~3;