3 * Needs a massive rewrite.
6 #include "../port/lib.h"
11 #include "../port/error.h"
13 #define DBG if(0) print
16 { /* configuration mechanism #1 */
17 PciADDR = 0xCF8, /* CONFIG_ADDRESS */
18 PciDATA = 0xCFC, /* CONFIG_DATA */
20 /* configuration mechanism #2 */
21 PciCSE = 0xCF8, /* configuration space enable */
22 PciFORWARD = 0xCFA, /* which bus */
29 { /* command register */
38 static Lock pcicfglock;
39 static Lock pcicfginitlock;
40 static int pcicfgmode = -1;
41 static int pcimaxbno = 255;
43 static Pcidev* pciroot;
44 static Pcidev* pcilist;
45 static Pcidev* pcitail;
46 static int nobios, nopcirouting;
47 static BIOS32si* pcibiossi;
49 static int pcicfgrw8raw(int, int, int, int);
50 static int pcicfgrw16raw(int, int, int, int);
51 static int pcicfgrw32raw(int, int, int, int);
53 static int (*pcicfgrw8)(int, int, int, int) = pcicfgrw8raw;
54 static int (*pcicfgrw16)(int, int, int, int) = pcicfgrw16raw;
55 static int (*pcicfgrw32)(int, int, int, int) = pcicfgrw32raw;
57 static char* bustypes[] = {
85 if((p = malloc(READSTR)) == nil)
86 return fmtstrcpy(fmt, "(tbdfconv)");
90 tbdf = va_arg(fmt->args, int);
91 if(tbdf == BUSUNKNOWN)
92 snprint(p, READSTR, "unknown");
95 if(type < nelem(bustypes))
96 l = snprint(p, READSTR, bustypes[type]);
98 l = snprint(p, READSTR, "%d", type);
99 snprint(p+l, READSTR-l, ".%d.%d.%d",
100 BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
105 snprint(p, READSTR, "(tbdfconv)");
108 r = fmtstrcpy(fmt, p);
115 pcibarsize(Pcidev *p, int rno)
119 v = pcicfgrw32(p->tbdf, rno, 0, 1);
120 pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
121 size = pcicfgrw32(p->tbdf, rno, 0, 1);
124 pcicfgrw32(p->tbdf, rno, v, 0);
126 return -(size & ~0x0F);
130 pcisizcmp(void *a, void *b)
136 return aa->siz - bb->siz;
145 for(m = 1<<(m-1); m != 0; m >>= 1) {
159 pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
162 int ntb, i, size, rno, hole;
163 ulong v, mema, ioa, sioa, smema, base, limit;
164 Pcisiz *table, *tptr, *mtb, *itb;
172 DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
173 wrreg, root->tbdf, mema, ioa);
176 for(p = root; p != nil; p = p->link)
179 ntb *= (PciCIS-PciBAR0)/4;
180 table = malloc(2*ntb*sizeof(Pcisiz));
182 panic("pcibusmap: can't allocate memory");
187 * Build a table of sizes
189 for(p = root; p != nil; p = p->link) {
190 if(p->ccrb == 0x06) {
191 if(p->ccru != 0x04 || p->bridge == nil) {
192 DBG("pci: ignored bridge %T\n", p->tbdf);
198 pcibusmap(p->bridge, &smema, &sioa, 0);
200 hole = pcimask(smema-mema);
205 hole = pcimask(sioa-ioa);
213 itb->siz = p->ioa.size;
218 mtb->siz = p->mema.size;
223 for(i = 0; i <= 5; i++) {
225 v = pcicfgrw32(p->tbdf, rno, 0, 1);
226 size = pcibarsize(p, rno);
230 p->mem[i].size = size;
250 * Sort both tables IO smallest first, Memory largest
252 qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp);
254 qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
257 * Allocate IO address space on this bus
259 for(tptr = table; tptr < itb; tptr++) {
263 ioa = (ioa+hole-1) & ~(hole-1);
270 p->mem[tptr->bar].bar = ioa|1;
272 pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
279 * Allocate Memory address space on this bus
281 for(tptr = table+ntb; tptr < mtb; tptr++) {
285 mema = (mema+hole-1) & ~(hole-1);
292 p->mem[tptr->bar].bar = mema;
294 pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0);
307 * Finally set all the bridge addresses & registers
309 for(p = root; p != nil; p = p->link) {
310 if(p->bridge == nil) {
311 pcicfgrw8(p->tbdf, PciLTR, 64, 0);
314 pcicfgrw16(p->tbdf, PciPCR, p->pcr, 0);
319 limit = base+p->ioa.size-1;
320 v = pcicfgrw32(p->tbdf, PciIBR, 0, 1);
321 v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8);
322 pcicfgrw32(p->tbdf, PciIBR, v, 0);
323 v = (limit & 0xFFFF0000)|(base>>16);
324 pcicfgrw32(p->tbdf, PciIUBR, v, 0);
327 limit = base+p->mema.size-1;
328 v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16);
329 pcicfgrw32(p->tbdf, PciMBR, v, 0);
332 * Disable memory prefetch
334 pcicfgrw32(p->tbdf, PciPMBR, 0x0000FFFF, 0);
335 pcicfgrw8(p->tbdf, PciLTR, 64, 0);
340 p->pcr |= IOen|MEMen|MASen;
341 pcicfgrw32(p->tbdf, PciPCR, 0xFFFF0000|p->pcr , 0);
345 pcibusmap(p->bridge, &smema, &sioa, 1);
350 pcilscan(int bno, Pcidev** list, Pcidev *parent)
352 Pcidev *p, *head, *tail;
353 int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
358 for(dno = 0; dno <= pcimaxdno; dno++){
360 for(fno = 0; fno <= maxfno; fno++){
362 * For this possible device, form the
363 * bus+device+function triplet needed to address it
364 * and try to read the vendor and device ID.
365 * If successful, allocate a device struct and
366 * start to fill it in with some useful information
367 * from the device's configuration space.
369 tbdf = MKBUS(BusPCI, bno, dno, fno);
370 l = pcicfgrw32(tbdf, PciVID, 0, 1);
371 if(l == 0xFFFFFFFF || l == 0)
373 p = malloc(sizeof(*p));
375 panic("pcilscan: can't allocate memory");
386 p->pcr = pcicfgr16(p, PciPCR);
387 p->rid = pcicfgr8(p, PciRID);
388 p->ccrp = pcicfgr8(p, PciCCRp);
389 p->ccru = pcicfgr8(p, PciCCRu);
390 p->ccrb = pcicfgr8(p, PciCCRb);
391 p->cls = pcicfgr8(p, PciCLS);
392 p->ltr = pcicfgr8(p, PciLTR);
394 p->intl = pcicfgr8(p, PciINTL);
397 * If the device is a multi-function device adjust the
398 * loop count so all possible functions are checked.
400 hdt = pcicfgr8(p, PciHDT);
405 * If appropriate, read the base address registers
406 * and work out the sizes.
409 case 0x00: /* prehistoric */
410 case 0x01: /* mass storage controller */
411 case 0x02: /* network controller */
412 case 0x03: /* display controller */
413 case 0x04: /* multimedia device */
414 case 0x07: /* simple comm. controllers */
415 case 0x08: /* base system peripherals */
416 case 0x09: /* input devices */
417 case 0x0A: /* docking stations */
418 case 0x0B: /* processors */
419 case 0x0C: /* serial bus controllers */
420 case 0x0D: /* wireless controllers */
421 case 0x0E: /* intelligent I/O controllers */
422 case 0x0F: /* sattelite communication controllers */
423 case 0x10: /* encryption/decryption controllers */
424 case 0x11: /* signal processing controllers */
425 if((hdt & 0x7F) != 0)
428 for(i = 0; i <= 5; i++) {
429 p->mem[i].bar = pcicfgr32(p, rno);
430 p->mem[i].size = pcibarsize(p, rno);
431 if((p->mem[i].bar & 7) == 4 && i < 5){
435 hi = pcicfgr32(p, rno);
437 print("ignoring 64-bit bar %d: %llux %d from %T\n",
438 i, (uvlong)hi<<32 | p->mem[i].bar, p->mem[i].size, p->tbdf);
448 case 0x05: /* memory controller */
449 case 0x06: /* bridge device */
464 for(p = head; p != nil; p = p->link){
466 * Find PCI-PCI bridges and recursively descend the tree.
468 if(p->ccrb != 0x06 || p->ccru != 0x04)
472 * If the secondary or subordinate bus number is not
473 * initialised try to do what the PCI BIOS should have
474 * done and fill in the numbers as the tree is descended.
475 * On the way down the subordinate bus number is set to
476 * the maximum as it's not known how many buses are behind
477 * this one; the final value is set on the way back up.
479 sbn = pcicfgr8(p, PciSBN);
480 ubn = pcicfgr8(p, PciUBN);
482 if(sbn == 0 || ubn == 0 || nobios) {
485 * Make sure memory, I/O and master enables are
486 * off, set the primary, secondary and subordinate
487 * bus numbers and clear the secondary status before
488 * attempting to scan the secondary bus.
490 * Initialisation of the bridge should be done here.
492 pcicfgw32(p, PciPCR, 0xFFFF0000);
493 l = (MaxUBN<<16)|(sbn<<8)|bno;
494 pcicfgw32(p, PciPBN, l);
495 pcicfgw16(p, PciSPSR, 0xFFFF);
496 maxubn = pcilscan(sbn, &p->bridge, p);
497 l = (maxubn<<16)|(sbn<<8)|bno;
499 pcicfgw32(p, PciPBN, l);
504 pcilscan(sbn, &p->bridge, p);
512 pciscan(int bno, Pcidev **list)
516 lock(&pcicfginitlock);
517 ubn = pcilscan(bno, list, nil);
518 unlock(&pcicfginitlock);
523 pIIxget(Pcidev *router, uchar link)
527 /* link should be 0x60, 0x61, 0x62, 0x63 */
528 pirq = pcicfgr8(router, link);
529 return (pirq < 16)? pirq: 0;
533 pIIxset(Pcidev *router, uchar link, uchar irq)
535 pcicfgw8(router, link, irq);
539 viaget(Pcidev *router, uchar link)
543 /* link should be 1, 2, 3, 5 */
544 pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
546 return (link & 1)? (pirq >> 4): (pirq & 15);
550 viaset(Pcidev *router, uchar link, uchar irq)
554 pirq = pcicfgr8(router, 0x55 + (link >> 1));
555 pirq &= (link & 1)? 0x0f: 0xf0;
556 pirq |= (link & 1)? (irq << 4): (irq & 15);
557 pcicfgw8(router, 0x55 + (link>>1), pirq);
561 optiget(Pcidev *router, uchar link)
565 /* link should be 0x02, 0x12, 0x22, 0x32 */
566 if ((link & 0xcf) == 0x02)
567 pirq = pcicfgr8(router, 0xb8 + (link >> 5));
568 return (link & 0x10)? (pirq >> 4): (pirq & 15);
572 optiset(Pcidev *router, uchar link, uchar irq)
576 pirq = pcicfgr8(router, 0xb8 + (link >> 5));
577 pirq &= (link & 0x10)? 0x0f : 0xf0;
578 pirq |= (link & 0x10)? (irq << 4): (irq & 15);
579 pcicfgw8(router, 0xb8 + (link >> 5), pirq);
583 aliget(Pcidev *router, uchar link)
585 /* No, you're not dreaming */
586 static const uchar map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
589 /* link should be 0x01..0x08 */
590 pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
591 return (link & 1)? map[pirq&15]: map[pirq>>4];
595 aliset(Pcidev *router, uchar link, uchar irq)
597 /* Inverse of map in aliget */
598 static const uchar map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
601 pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
602 pirq &= (link & 1)? 0x0f: 0xf0;
603 pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
604 pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
608 cyrixget(Pcidev *router, uchar link)
612 /* link should be 1, 2, 3, 4 */
613 pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
614 return ((link & 1)? pirq >> 4: pirq & 15);
618 cyrixset(Pcidev *router, uchar link, uchar irq)
622 pirq = pcicfgr8(router, 0x5c + (link>>1));
623 pirq &= (link & 1)? 0x0f: 0xf0;
624 pirq |= (link & 1)? (irq << 4): (irq & 15);
625 pcicfgw8(router, 0x5c + (link>>1), pirq);
628 typedef struct Bridge Bridge;
633 uchar (*get)(Pcidev *, uchar);
634 void (*set)(Pcidev *, uchar, uchar);
637 static Bridge southbridges[] = {
638 { 0x8086, 0x122e, pIIxget, pIIxset }, /* Intel 82371FB */
639 { 0x8086, 0x1234, pIIxget, pIIxset }, /* Intel 82371MX */
640 { 0x8086, 0x7000, pIIxget, pIIxset }, /* Intel 82371SB */
641 { 0x8086, 0x7110, pIIxget, pIIxset }, /* Intel 82371AB */
642 { 0x8086, 0x7198, pIIxget, pIIxset }, /* Intel 82443MX (fn 1) */
643 { 0x8086, 0x2410, pIIxget, pIIxset }, /* Intel 82801AA */
644 { 0x8086, 0x2420, pIIxget, pIIxset }, /* Intel 82801AB */
645 { 0x8086, 0x2440, pIIxget, pIIxset }, /* Intel 82801BA */
646 { 0x8086, 0x2448, pIIxget, pIIxset }, /* Intel 82801BAM/CAM/DBM */
647 { 0x8086, 0x244c, pIIxget, pIIxset }, /* Intel 82801BAM */
648 { 0x8086, 0x244e, pIIxget, pIIxset }, /* Intel 82801 */
649 { 0x8086, 0x2480, pIIxget, pIIxset }, /* Intel 82801CA */
650 { 0x8086, 0x248c, pIIxget, pIIxset }, /* Intel 82801CAM */
651 { 0x8086, 0x24c0, pIIxget, pIIxset }, /* Intel 82801DBL */
652 { 0x8086, 0x24cc, pIIxget, pIIxset }, /* Intel 82801DBM */
653 { 0x8086, 0x24d0, pIIxget, pIIxset }, /* Intel 82801EB */
654 { 0x8086, 0x25a1, pIIxget, pIIxset }, /* Intel 6300ESB */
655 { 0x8086, 0x2640, pIIxget, pIIxset }, /* Intel 82801FB */
656 { 0x8086, 0x2641, pIIxget, pIIxset }, /* Intel 82801FBM */
657 { 0x8086, 0x2670, pIIxget, pIIxset }, /* Intel 632xesb */
658 { 0x8086, 0x27b8, pIIxget, pIIxset }, /* Intel 82801GB */
659 { 0x8086, 0x27b9, pIIxget, pIIxset }, /* Intel 82801GBM */
660 { 0x8086, 0x27bd, pIIxget, pIIxset }, /* Intel 82801GB/GR */
661 { 0x8086, 0x3a16, pIIxget, pIIxset }, /* Intel 82801JIR */
662 { 0x8086, 0x3a40, pIIxget, pIIxset }, /* Intel 82801JI */
663 { 0x8086, 0x3a42, pIIxget, pIIxset }, /* Intel 82801JI */
664 { 0x8086, 0x3a48, pIIxget, pIIxset }, /* Intel 82801JI */
665 { 0x8086, 0x2916, pIIxget, pIIxset }, /* Intel 82801? */
666 { 0x8086, 0x1c02, pIIxget, pIIxset }, /* Intel 6 Series/C200 */
667 { 0x8086, 0x1e53, pIIxget, pIIxset }, /* Intel 7 Series/C216 */
668 { 0x8086, 0x8c56, pIIxget, pIIxset }, /* Intel 8 Series/C226 */
669 { 0x8086, 0x2810, pIIxget, pIIxset }, /* Intel 82801HB/HR (ich8/r) */
670 { 0x8086, 0x2812, pIIxget, pIIxset }, /* Intel 82801HH (ich8dh) */
671 { 0x8086, 0x2912, pIIxget, pIIxset }, /* Intel 82801ih ich9dh */
672 { 0x8086, 0x2914, pIIxget, pIIxset }, /* Intel 82801io ich9do */
673 { 0x8086, 0x2916, pIIxget, pIIxset }, /* Intel 82801ibr ich9r */
674 { 0x8086, 0x2917, pIIxget, pIIxset }, /* Intel 82801iem ich9m-e */
675 { 0x8086, 0x2918, pIIxget, pIIxset }, /* Intel 82801ib ich9 */
676 { 0x8086, 0x2919, pIIxget, pIIxset }, /* Intel 82801? ich9m */
677 { 0x8086, 0x3a16, pIIxget, pIIxset }, /* Intel 82801jir ich10r */
678 { 0x8086, 0x3a18, pIIxget, pIIxset }, /* Intel 82801jib ich10 */
679 { 0x8086, 0x3a40, pIIxget, pIIxset }, /* Intel 82801ji */
680 { 0x8086, 0x3a42, pIIxget, pIIxset }, /* Intel 82801ji */
681 { 0x8086, 0x3a48, pIIxget, pIIxset }, /* Intel 82801ji */
682 { 0x8086, 0x3b06, pIIxget, pIIxset }, /* Intel 82801? ibex peak */
683 { 0x8086, 0x3b14, pIIxget, pIIxset }, /* Intel 82801? 3420 */
684 { 0x8086, 0x1c49, pIIxget, pIIxset }, /* Intel 82hm65 cougar point pch */
685 { 0x8086, 0x1c4b, pIIxget, pIIxset }, /* Intel 82hm67 */
686 { 0x8086, 0x1c4f, pIIxget, pIIxset }, /* Intel 82qm67 cougar point pch */
687 { 0x8086, 0x1c52, pIIxget, pIIxset }, /* Intel 82q65 cougar point pch */
688 { 0x8086, 0x1c54, pIIxget, pIIxset }, /* Intel 82q67 cougar point pch */
689 { 0x8086, 0x1e55, pIIxget, pIIxset }, /* Intel QM77 panter point lpc */
691 { 0x1106, 0x0586, viaget, viaset }, /* Viatech 82C586 */
692 { 0x1106, 0x0596, viaget, viaset }, /* Viatech 82C596 */
693 { 0x1106, 0x0686, viaget, viaset }, /* Viatech 82C686 */
694 { 0x1106, 0x3177, viaget, viaset }, /* Viatech VT8235 */
695 { 0x1106, 0x3227, viaget, viaset }, /* Viatech VT8237 */
696 { 0x1106, 0x3287, viaget, viaset }, /* Viatech VT8251 */
697 { 0x1106, 0x8410, viaget, viaset }, /* Viatech PV530 bridge */
698 { 0x1045, 0xc700, optiget, optiset }, /* Opti 82C700 */
699 { 0x10b9, 0x1533, aliget, aliset }, /* Al M1533 */
700 { 0x1039, 0x0008, pIIxget, pIIxset }, /* SI 503 */
701 { 0x1039, 0x0496, pIIxget, pIIxset }, /* SI 496 */
702 { 0x1078, 0x0100, cyrixget, cyrixset }, /* Cyrix 5530 Legacy */
704 { 0x1022, 0x790e, nil, nil }, /* AMD FCH LPC bridge */
705 { 0x1022, 0x746b, nil, nil }, /* AMD 8111 */
706 { 0x10de, 0x00d1, nil, nil }, /* NVIDIA nForce 3 */
707 { 0x10de, 0x00e0, nil, nil }, /* NVIDIA nForce 3 250 Series */
708 { 0x10de, 0x00e1, nil, nil }, /* NVIDIA nForce 3 250 Series */
709 { 0x1166, 0x0200, nil, nil }, /* ServerWorks ServerSet III LE */
710 { 0x1002, 0x4377, nil, nil }, /* ATI Radeon Xpress 200M */
711 { 0x1002, 0x4372, nil, nil }, /* ATI SB400 */
712 { 0x1002, 0x9601, nil, nil }, /* AMD SB710 */
713 { 0x1002, 0x438d, nil, nil }, /* AMD SB600 */
714 { 0x1002, 0x439d, nil, nil }, /* AMD SB810 */
717 typedef struct Slot Slot;
719 uchar bus; /* Pci bus number */
720 uchar dev; /* Pci device number */
721 uchar maps[12]; /* Avoid structs! Link and mask. */
722 uchar slot; /* Add-in/built-in slot */
726 typedef struct Router Router;
728 uchar signature[4]; /* Routing table signature */
729 uchar version[2]; /* Version number */
730 uchar size[2]; /* Total table size */
731 uchar bus; /* Interrupt router bus number */
732 uchar devfn; /* Router's devfunc */
733 uchar pciirqs[2]; /* Exclusive PCI irqs */
734 uchar compat[4]; /* Compatible PCI interrupt router */
735 uchar miniport[4]; /* Miniport data */
740 static ushort pciirqs; /* Exclusive PCI irqs */
741 static Bridge *southbridge; /* Which southbridge to use. */
750 uchar *p, pin, irq, link, *map;
752 if((p = sigsearch("$PIR", 0)) == nil)
756 size = (r->size[1] << 8)|r->size[0];
757 if(size < sizeof(Router) || checksum(r, size))
760 if(0) print("PCI interrupt routing table version %d.%d at %p\n",
761 r->version[0], r->version[1], r);
763 tbdf = MKBUS(BusPCI, r->bus, (r->devfn>>3)&0x1f, r->devfn&7);
764 sbpci = pcimatchtbdf(tbdf);
766 print("pcirouting: Cannot find south bridge %T\n", tbdf);
770 for(i = 0; i < nelem(southbridges); i++)
771 if(sbpci->vid == southbridges[i].vid && sbpci->did == southbridges[i].did)
774 if(i == nelem(southbridges)) {
775 print("pcirouting: ignoring south bridge %T %.4uX/%.4uX\n", tbdf, sbpci->vid, sbpci->did);
778 southbridge = &southbridges[i];
779 if(southbridge->get == nil)
782 pciirqs = (r->pciirqs[1] << 8)|r->pciirqs[0];
783 for(e = (Slot *)&r[1]; (uchar *)e < p + size; e++) {
785 print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
786 for (i = 0; i < 4; i++) {
787 map = &e->maps[i * 3];
788 print("[%d] %.2uX %.4uX ", i, map[0], (map[2] << 8)|map[1]);
792 for(i = 0; i < 8; i++) {
793 tbdf = MKBUS(BusPCI, e->bus, (e->dev>>3)&0x1f, i);
794 pci = pcimatchtbdf(tbdf);
797 pin = pcicfgr8(pci, PciINTP);
798 if(pin == 0 || pin == 0xff)
801 map = &e->maps[((pin - 1) % 4) * 3];
803 irq = southbridge->get(sbpci, link);
806 if(irq == 0 || (irq & 0x80) != 0){
808 if(irq == 0 || irq == 0xff)
810 if(southbridge->set == nil)
812 southbridge->set(sbpci, link, irq);
814 print("pcirouting: %T at pin %d link %.2uX irq %d -> %d\n", tbdf, pin, link, pci->intl, irq);
815 pcicfgw8(pci, PciINTL, irq);
821 static void pcireservemem(void);
824 pcicfgrw8bios(int tbdf, int rno, int data, int read)
831 memset(&ci, 0, sizeof(BIOS32ci));
832 ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
836 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
837 return ci.ecx & 0xFF;
841 ci.ecx = data & 0xFF;
842 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
850 pcicfgrw16bios(int tbdf, int rno, int data, int read)
857 memset(&ci, 0, sizeof(BIOS32ci));
858 ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
862 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
863 return ci.ecx & 0xFFFF;
867 ci.ecx = data & 0xFFFF;
868 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
876 pcicfgrw32bios(int tbdf, int rno, int data, int read)
883 memset(&ci, 0, sizeof(BIOS32ci));
884 ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
888 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
894 if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
907 if((si = bios32open("$PCI")) == nil)
910 memset(&ci, 0, sizeof(BIOS32ci));
912 if(bios32ci(si, &ci) || ci.edx != ((' '<<24)|('I'<<16)|('C'<<8)|'P')){
920 pcimaxbno = ci.ecx & 0xff;
926 pcibussize(Pcidev *root, ulong *msize, ulong *iosize)
930 pcibusmap(root, msize, iosize, 0);
941 lock(&pcicfginitlock);
946 if(getconf("*nobios"))
948 else if(getconf("*pcibios"))
950 if(getconf("*nopcirouting"))
954 * Try to determine which PCI configuration mode is implemented.
955 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
956 * a DWORD at 0xCF8 and another at 0xCFC and will pass through
957 * any non-DWORD accesses as normal I/O cycles. There shouldn't be
958 * a device behind these addresses so if Mode1 accesses fail try
959 * for Mode2 (Mode2 is deprecated).
963 * Bits [30:24] of PciADDR must be 0,
964 * according to the spec.
967 if(!(n & 0x7F000000)){
968 outl(PciADDR, 0x80000000);
970 if(inl(PciADDR) & 0x80000000){
979 * The 'key' part of PciCSE should be 0.
984 if(inb(PciCSE) == 0x0E){
993 if(pcicfgmode < 0 || pcibios) {
994 if((pcibiossi = pcibiosinit()) == nil)
996 pcicfgrw8 = pcicfgrw8bios;
997 pcicfgrw16 = pcicfgrw16bios;
998 pcicfgrw32 = pcicfgrw32bios;
1002 fmtinstall('T', tbdffmt);
1004 if(p = getconf("*pcimaxbno"))
1005 pcimaxbno = strtoul(p, 0, 0);
1006 if(p = getconf("*pcimaxdno")){
1007 n = strtoul(p, 0, 0);
1013 for(bno = 0; bno <= pcimaxbno; bno++) {
1015 bno = pcilscan(bno, list, nil);
1018 list = &(*list)->link;
1024 * If we have found a PCI-to-Cardbus bridge, make sure
1025 * it has no valid mappings anymore.
1027 for(pci = pciroot; pci != nil; pci = pci->link){
1028 if (pci->ccrb == 6 && pci->ccru == 7) {
1031 /* reset the cardbus */
1032 bcr = pcicfgr16(pci, PciBCR);
1033 pcicfgw16(pci, PciBCR, 0x40 | bcr);
1045 * Work out how big the top bus is
1047 pcibussize(pciroot, &mema, &ioa);
1050 * Align the windows and map it
1055 DBG("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
1057 pcibusmap(pciroot, &mema, &ioa, 1);
1058 DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
1068 unlock(&pcicfginitlock);
1070 if(getconf("*pcihinv"))
1081 * mark all the physical address space claimed by pci devices
1082 * as in use, so that upaalloc doesn't give it out.
1084 for(p=pciroot; p; p=p->list)
1085 for(i=0; i<nelem(p->mem); i++)
1086 if((p->mem[i].bar&~4) != 0 && (p->mem[i].bar&1) == 0)
1087 upaalloc(p->mem[i].bar&~0x0F, p->mem[i].size, 0);
1091 pcicfgrw8raw(int tbdf, int rno, int data, int read)
1095 if(pcicfgmode == -1)
1103 if(BUSDNO(tbdf) > pcimaxdno)
1112 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
1116 outb(PciDATA+o, data);
1121 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
1122 outb(PciFORWARD, BUSBNO(tbdf));
1124 x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
1126 outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
1130 unlock(&pcicfglock);
1136 pcicfgr8(Pcidev* pcidev, int rno)
1138 return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
1142 pcicfgw8(Pcidev* pcidev, int rno, int data)
1144 pcicfgrw8(pcidev->tbdf, rno, data, 0);
1148 pcicfgrw16raw(int tbdf, int rno, int data, int read)
1152 if(pcicfgmode == -1)
1160 if(BUSDNO(tbdf) > pcimaxdno)
1169 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
1173 outs(PciDATA+o, data);
1178 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
1179 outb(PciFORWARD, BUSBNO(tbdf));
1181 x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
1183 outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
1187 unlock(&pcicfglock);
1193 pcicfgr16(Pcidev* pcidev, int rno)
1195 return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
1199 pcicfgw16(Pcidev* pcidev, int rno, int data)
1201 pcicfgrw16(pcidev->tbdf, rno, data, 0);
1205 pcicfgrw32raw(int tbdf, int rno, int data, int read)
1209 if(pcicfgmode == -1)
1217 if(BUSDNO(tbdf) > pcimaxdno)
1225 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
1229 outl(PciDATA, data);
1234 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
1235 outb(PciFORWARD, BUSBNO(tbdf));
1237 x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
1239 outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
1243 unlock(&pcicfglock);
1249 pcicfgr32(Pcidev* pcidev, int rno)
1251 return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
1255 pcicfgw32(Pcidev* pcidev, int rno, int data)
1257 pcicfgrw32(pcidev->tbdf, rno, data, 0);
1261 pcimatch(Pcidev* prev, int vid, int did)
1263 if(pcicfgmode == -1)
1272 if((vid == 0 || prev->vid == vid)
1273 && (did == 0 || prev->did == did))
1281 pcimatchtbdf(int tbdf)
1285 if(pcicfgmode == -1)
1288 for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
1289 if(pcidev->tbdf == tbdf)
1296 pciipin(Pcidev *pci, uchar pin)
1304 if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
1307 if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
1323 print("bus dev type vid did intl memory\n");
1325 for(t = p; t != nil; t = t->link) {
1326 print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
1327 BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
1328 t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
1330 for(i = 0; i < nelem(p->mem); i++) {
1331 if(t->mem[i].size == 0)
1333 print("%d:%.8lux %d ", i,
1334 t->mem[i].bar, t->mem[i].size);
1336 if(t->ioa.bar || t->ioa.size)
1337 print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size);
1338 if(t->mema.bar || t->mema.size)
1339 print("mema:%.8lux %d ", t->mema.bar, t->mema.size);
1341 print("->%d", BUSBNO(t->bridge->tbdf));
1345 if(p->bridge != nil)
1346 pcilhinv(p->bridge);
1354 if(pcicfgmode == -1)
1356 lock(&pcicfginitlock);
1358 unlock(&pcicfginitlock);
1366 if(pcicfgmode == -1)
1369 for(p = pcilist; p != nil; p = p->list) {
1370 /* don't mess with the bridges */
1378 pcisetioe(Pcidev* p)
1381 pcicfgw16(p, PciPCR, p->pcr);
1385 pciclrioe(Pcidev* p)
1388 pcicfgw16(p, PciPCR, p->pcr);
1392 pcisetbme(Pcidev* p)
1395 pcicfgw16(p, PciPCR, p->pcr);
1399 pciclrbme(Pcidev* p)
1402 pcicfgw16(p, PciPCR, p->pcr);
1406 pcisetmwi(Pcidev* p)
1409 pcicfgw16(p, PciPCR, p->pcr);
1413 pciclrmwi(Pcidev* p)
1415 p->pcr &= ~MemWrInv;
1416 pcicfgw16(p, PciPCR, p->pcr);
1420 enumcaps(Pcidev *p, int (*fmatch)(Pcidev*, int, int, int), int arg)
1424 /* status register bit 4 has capabilities */
1425 if((pcicfgr16(p, PciPSR) & 1<<4) == 0)
1427 switch(pcicfgr8(p, PciHDT) & 0x7F){
1431 case 1: /* pci to pci bridge */
1434 case 2: /* cardbus bridge */
1439 off = pcicfgr8(p, off);
1440 if(off < 0x40 || (off & 3))
1443 cap = pcicfgr8(p, off);
1446 r = (*fmatch)(p, cap, off, arg);
1457 matchcap(Pcidev *, int cap, int, int arg)
1463 matchhtcap(Pcidev *p, int cap, int off, int arg)
1467 if(cap != PciCapHTC)
1469 if(arg == 0x00 || arg == 0x20)
1473 cap = pcicfgr8(p, off+3);
1474 return (cap & mask) != arg;
1478 pcicap(Pcidev *p, int cap)
1480 return enumcaps(p, matchcap, cap);
1484 pcihtcap(Pcidev *p, int cap)
1486 return enumcaps(p, matchhtcap, cap);
1490 pcigetpmrb(Pcidev* p)
1494 return p->pmrb = pcicap(p, PciCapPMG);
1498 pcigetpms(Pcidev* p)
1502 if((ptr = pcigetpmrb(p)) == -1)
1506 * Power Management Register Block:
1507 * offset 0: Capability ID
1508 * 1: next item pointer
1511 * 6: bridge support extensions
1514 pmcsr = pcicfgr16(p, ptr+4);
1516 return pmcsr & 0x0003;
1520 pcisetpms(Pcidev* p, int state)
1522 int ostate, pmc, pmcsr, ptr;
1524 if((ptr = pcigetpmrb(p)) == -1)
1527 pmc = pcicfgr16(p, ptr+2);
1528 pmcsr = pcicfgr16(p, ptr+4);
1529 ostate = pmcsr & 0x0003;
1549 pcicfgw16(p, ptr+4, pmcsr);
1555 pcinextcap(Pcidev *pci, int offset)
1558 if((pcicfgr16(pci, PciPSR) & (1<<4)) == 0)
1559 return 0; /* no capabilities */
1562 return pcicfgr8(pci, offset+1) & ~3;
1566 pcienable(Pcidev *p)
1574 pcienable(p->parent);
1576 switch(pcisetpms(p, 0)){
1578 print("pcienable %T: wakeup from D1\n", p->tbdf);
1581 print("pcienable %T: wakeup from D2\n", p->tbdf);
1582 if(p->bridge != nil)
1583 delay(100); /* B2: minimum delay 50ms */
1585 delay(1); /* D2: minimum delay 200µs */
1588 print("pcienable %T: wakeup from D3\n", p->tbdf);
1589 delay(100); /* D3: minimum delay 50ms */
1591 /* restore registers */
1592 for(i = 0; i < 6; i++)
1593 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1594 pcicfgw8(p, PciINTL, p->intl);
1595 pcicfgw8(p, PciLTR, p->ltr);
1596 pcicfgw8(p, PciCLS, p->cls);
1597 pcicfgw16(p, PciPCR, p->pcr);
1601 if(p->bridge != nil)
1602 pcr = IOen|MEMen|MASen;
1605 for(i = 0; i < 6; i++){
1606 if(p->mem[i].size == 0)
1608 if(p->mem[i].bar & 1)
1615 if((p->pcr & pcr) != pcr){
1616 print("pcienable %T: pcr %ux->%ux\n", p->tbdf, p->pcr, p->pcr|pcr);
1618 pcicfgrw32(p->tbdf, PciPCR, 0xFFFF0000|p->pcr, 0);
1623 pcidisable(Pcidev *p)