2 * MultiProcessor Specification Version 1.[14].
4 typedef struct { /* floating pointer */
5 uchar signature[4]; /* "_MP_" */
6 long physaddr; /* physical address of MP configuration table */
8 uchar specrev; /* [14] */
9 uchar checksum; /* all bytes must add up to 0 */
10 uchar type; /* MP system configuration type */
15 #define _MP_sz (4+4+1+1+1+1+1+3)
17 typedef struct { /* configuration table header */
18 uchar signature[4]; /* "PCMP" */
19 ushort length; /* total table length */
20 uchar version; /* [14] */
21 uchar checksum; /* all bytes must add up to 0 */
22 uchar product[20]; /* product id */
23 ulong oemtable; /* OEM table pointer */
24 ushort oemlength; /* OEM table length */
25 ushort entry; /* entry count */
26 ulong lapicbase; /* address of local APIC */
27 ushort xlength; /* extended table length */
28 uchar xchecksum; /* extended table checksum */
32 #define PCMPsz (4+2+1+1+20+4+2+2+4+2+1+1)
34 typedef struct { /* processor table entry */
35 uchar type; /* entry type (0) */
36 uchar apicno; /* local APIC id */
37 uchar version; /* local APIC verison */
38 uchar flags; /* CPU flags */
39 uchar signature[4]; /* CPU signature */
40 ulong feature; /* feature flags from CPUID instruction */
44 #define PCMPprocessorsz (1+1+1+1+4+4+8)
46 typedef struct { /* bus table entry */
47 uchar type; /* entry type (1) */
48 uchar busno; /* bus id */
49 char string[6]; /* bus type string */
52 #define PCMPbussz (1+1+6)
54 typedef struct { /* I/O APIC table entry */
55 uchar type; /* entry type (2) */
56 uchar apicno; /* I/O APIC id */
57 uchar version; /* I/O APIC version */
58 uchar flags; /* I/O APIC flags */
59 ulong addr; /* I/O APIC address */
62 #define PCMPioapicsz (1+1+1+1+4)
64 typedef struct { /* interrupt table entry */
65 uchar type; /* entry type ([34]) */
66 uchar intr; /* interrupt type */
67 ushort flags; /* interrupt flag */
68 uchar busno; /* source bus id */
69 uchar irq; /* source bus irq */
70 uchar apicno; /* destination APIC id */
71 uchar intin; /* destination APIC [L]INTIN# */
74 #define PCMPintrsz (1+1+2+1+1+1+1)
76 typedef struct { /* system address space mapping entry */
77 uchar type; /* entry type (128) */
78 uchar length; /* of this entry (20) */
79 uchar busno; /* bus id */
85 #define PCMPsasmsz (1+1+1+1+8+8)
87 typedef struct { /* bus hierarchy descriptor entry */
88 uchar type; /* entry type (129) */
89 uchar length; /* of this entry (8) */
90 uchar busno; /* bus id */
91 uchar info; /* bus info */
92 uchar parent; /* parent bus */
96 #define PCMPhirarchysz (1+1+1+1+1+3)
98 typedef struct { /* compatibility bus address space modifier entry */
99 uchar type; /* entry type (130) */
100 uchar length; /* of this entry (8) */
101 uchar busno; /* bus id */
102 uchar modifier; /* address modifier */
103 ulong range; /* predefined range list */
106 #define PCMPcbasmsz (1+1+1+1+4)
108 enum { /* table entry types */
109 PcmpPROCESSOR = 0x00, /* one entry per processor */
110 PcmpBUS = 0x01, /* one entry per bus */
111 PcmpIOAPIC = 0x02, /* one entry per I/O APIC */
112 PcmpIOINTR = 0x03, /* one entry per bus interrupt source */
113 PcmpLINTR = 0x04, /* one entry per system interrupt source */
116 PcmpHIERARCHY = 0x81,
119 /* PCMPprocessor and PCMPioapic flags */
120 PcmpEN = 0x01, /* enabled */
121 PcmpBP = 0x02, /* bootstrap processor */
123 /* PCMPiointr and PCMPlintr flags */
124 PcmpPOMASK = 0x03, /* polarity conforms to specifications of bus */
125 PcmpHIGH = 0x01, /* active high */
126 PcmpLOW = 0x03, /* active low */
127 PcmpELMASK = 0x0C, /* trigger mode of APIC input signals */
128 PcmpEDGE = 0x04, /* edge-triggered */
129 PcmpLEVEL = 0x0C, /* level-triggered */
131 /* PCMPiointr and PCMPlintr interrupt type */
132 PcmpINT = 0x00, /* vectored interrupt from APIC Rdt */
133 PcmpNMI = 0x01, /* non-maskable interrupt */
134 PcmpSMI = 0x02, /* system management interrupt */
135 PcmpExtINT = 0x03, /* vectored interrupt from external PIC */
137 /* PCMPsasm addrtype */
138 PcmpIOADDR = 0x00, /* I/O address */
139 PcmpMADDR = 0x01, /* memory address */
140 PcmpPADDR = 0x02, /* prefetch address */
142 /* PCMPhierarchy info */
143 PcmpSD = 0x01, /* subtractive decode bus */
145 /* PCMPcbasm modifier */
146 PcmpPR = 0x01, /* predefined range list */
150 * Condensed form of the MP Configuration Table.
151 * This is created during a single pass through the MP Configuration
154 typedef struct Aintr Aintr;
155 typedef struct Bus Bus;
156 typedef struct Apic Apic;
164 Aintr* aintr; /* interrupts tied to this bus */
168 typedef struct Aintr {
174 typedef struct Apic {
177 ulong* addr; /* register base address */
179 int flags; /* PcmpBP|PcmpEN */
181 Lock; /* I/O APIC: register access */
182 int mre; /* I/O APIC: maximum redirection entry */
183 int gsibase; /* I/O APIC: global system interrupt base (acpi) */
185 int lintr[2]; /* Local APIC */
192 MaxAPICNO = 254, /* 255 is physical broadcast */
195 enum { /* I/O APIC registers */
196 IoapicID = 0x00, /* ID */
197 IoapicVER = 0x01, /* version */
198 IoapicARB = 0x02, /* arbitration ID */
199 IoapicRDT = 0x10, /* redirection table */
204 * I/O APIC Redirection Table Entry;
205 * Local APIC Local Interrupt Vector Table;
206 * Local APIC Inter-Processor Interrupt;
207 * Local APIC Timer Vector Table.
210 ApicFIXED = 0x00000000, /* [10:8] Delivery Mode */
211 ApicLOWEST = 0x00000100, /* Lowest priority */
212 ApicSMI = 0x00000200, /* System Management Interrupt */
213 ApicRR = 0x00000300, /* Remote Read */
214 ApicNMI = 0x00000400,
215 ApicINIT = 0x00000500, /* INIT/RESET */
216 ApicSTARTUP = 0x00000600, /* Startup IPI */
217 ApicExtINT = 0x00000700,
219 ApicPHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */
220 ApicLOGICAL = 0x00000800,
222 ApicDELIVS = 0x00001000, /* [12] Delivery Status (RO) */
223 ApicHIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */
224 ApicLOW = 0x00002000,
225 ApicRemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */
226 ApicEDGE = 0x00000000, /* [15] Trigger Mode (RW) */
227 ApicLEVEL = 0x00008000,
228 ApicIMASK = 0x00010000, /* [16] Interrupt Mask */
231 extern void ioapicinit(Apic*, int);
232 extern void ioapicrdtr(Apic*, int, int*, int*);
233 extern void ioapicrdtw(Apic*, int, int, int);
235 extern void lapicclock(Ureg*, void*);
236 extern int lapiceoi(int);
237 extern void lapicerror(Ureg*, void*);
238 extern void lapicicrw(ulong, ulong);
239 extern void lapicinit(Apic*);
240 extern void lapicintroff(void);
241 extern void lapicintron(void);
242 extern int lapicisr(int);
243 extern void lapicnmidisable(void);
244 extern void lapicnmienable(void);
245 extern void lapiconline(void);
246 extern void lapicspurious(Ureg*, void*);
247 extern void lapicstartap(Apic*, int);
248 extern void lapictimerset(uvlong);
250 extern int mpintrinit(Bus*, PCMPintr*, int, int);
251 extern void mpinit(void);
252 extern int mpintrenable(Vctl*);
253 extern void mpshutdown(void);
254 extern void mpstartap(Apic*);
257 extern Bus* mpbuslast;
259 extern int mpeisabus;
260 extern Apic *mpioapic[];
261 extern Apic *mpapic[];