2 #include "../port/lib.h"
10 #include "apbootstrap.h"
12 /* filled in by pcmpinit or acpiinit */
17 Apic *mpioapic[MaxAPICNO+1];
18 Apic *mpapic[MaxAPICNO+1];
21 mpintrinit(Bus* bus, PCMPintr* intr, int vno, int /*irq*/)
26 * Parse an I/O or Local APIC interrupt table entry and
27 * return the encoded vector.
31 po = intr->flags & PcmpPOMASK;
32 el = intr->flags & PcmpELMASK;
35 default: /* PcmpINT */
36 v |= ApicFIXED; /* no-op */
52 * The AMI Goliath doesn't boot successfully with it's LINTR0
53 * entry which decodes to low+level. The PPro manual says ExtINT
54 * should be level, whereas the Pentium is edge. Setting the
55 * Goliath to edge+high seems to cure the problem. Other PPro
56 * MP tables (e.g. ASUS P/I-P65UP5 have a entry which decodes
57 * to edge+high, so who knows.
58 * Perhaps it would be best just to not set an ExtINT entry at
59 * all, it shouldn't be needed for SMP mode.
68 if(bus->type == BusEISA && !po && !el /*&& !(i8259elcr & (1<<irq))*/){
76 else if(po != PcmpHIGH){
77 print("mpintrinit: bad polarity 0x%uX\n", po);
85 else if(el != PcmpEDGE){
86 print("mpintrinit: bad trigger 0x%uX\n", el);
100 * If there are MTRR registers, snarf them for validation.
102 if(!(m->cpuiddx & Mtrr))
105 rdmsr(0x0FE, &m->mtrrcap);
106 rdmsr(0x2FF, &m->mtrrdef);
107 if(m->mtrrcap & 0x0100){
108 rdmsr(0x250, &m->mtrrfix[0]);
109 rdmsr(0x258, &m->mtrrfix[1]);
110 rdmsr(0x259, &m->mtrrfix[2]);
111 for(i = 0; i < 8; i++)
112 rdmsr(0x268+i, &m->mtrrfix[(i+3)]);
114 vcnt = m->mtrrcap & 0x00FF;
115 if(vcnt > nelem(m->mtrrvar))
116 vcnt = nelem(m->mtrrvar);
117 for(i = 0; i < vcnt; i++)
118 rdmsr(0x200+i, &m->mtrrvar[i]);
121 * If not the bootstrap processor, compare.
127 if(mach0->mtrrcap != m->mtrrcap)
128 print("mtrrcap%d: %lluX %lluX\n",
129 m->machno, mach0->mtrrcap, m->mtrrcap);
130 if(mach0->mtrrdef != m->mtrrdef)
131 print("mtrrdef%d: %lluX %lluX\n",
132 m->machno, mach0->mtrrdef, m->mtrrdef);
133 for(i = 0; i < 11; i++){
134 if(mach0->mtrrfix[i] != m->mtrrfix[i])
135 print("mtrrfix%d: i%d: %lluX %lluX\n",
136 m->machno, i, mach0->mtrrfix[i], m->mtrrfix[i]);
138 for(i = 0; i < vcnt; i++){
139 if(mach0->mtrrvar[i] != m->mtrrvar[i])
140 print("mtrrvar%d: i%d: %lluX %lluX\n",
141 m->machno, i, mach0->mtrrvar[i], m->mtrrvar[i]);
151 cycles(&m->tscticks); /* Uses the rdtsc instruction */
160 if(arch->fastclock != tscticks)
167 x = MACHP(0)->tscticks;
168 while(x == MACHP(0)->tscticks)
170 wrmsr(0x10, MACHP(0)->tscticks);
171 cycles(&m->tscticks);
178 // iprint("Hello Squidboy\n");
198 active.machs |= 1<<m->machno;
201 while(!active.thunderbirdsarego)
208 mpstartap(Apic* apic)
210 ulong *apbootp, *pdb, *pte;
218 * Initialise the AP page-tables and Mach structure. The page-tables
219 * are the same as for the bootstrap processor with the exception of
220 * the PTE for the Mach structure.
221 * Xspanalloc will panic if an allocation can't be made.
223 p = xspanalloc(4*BY2PG, BY2PG, 0);
225 memmove(pdb, mach0->pdb, BY2PG);
228 if((pte = mmuwalk(pdb, MACHADDR, 1, 0)) == nil)
230 memmove(p, KADDR(PPN(*pte)), BY2PG);
231 *pte = PADDR(p)|PTEWRITE|PTEVALID;
237 if((pte = mmuwalk(pdb, MACHADDR, 2, 0)) == nil)
239 *pte = PADDR(mach)|PTEWRITE|PTEVALID;
244 machno = apic->machno;
245 MACHP(machno) = mach;
246 mach->machno = machno;
248 mach->gdt = (Segdesc*)p; /* filled by mmuinit */
251 * Tell the AP where its kernel vector and pdb are.
252 * The offsets are known in the AP bootstrap code.
254 apbootp = (ulong*)(APBOOTSTRAP+0x08);
255 *apbootp++ = (ulong)squidboy; /* assembler jumps here eventually */
256 *apbootp++ = PADDR(pdb);
257 *apbootp = (ulong)apic;
260 * Universal Startup Algorithm.
262 p = KADDR(0x467); /* warm-reset vector */
263 *p++ = PADDR(APBOOTSTRAP);
264 *p++ = PADDR(APBOOTSTRAP)>>8;
265 i = (PADDR(APBOOTSTRAP) & ~0xFFFF)/16;
266 /* code assumes i==0 */
268 print("mp: bad APBOOTSTRAP\n");
273 nvramwrite(0x0F, 0x0A); /* shutdown code: warm reset upon init ipi */
274 lapicstartap(apic, PADDR(APBOOTSTRAP));
275 for(i = 0; i < 1000; i++){
280 nvramwrite(0x0F, 0x00);
293 if(getconf("*apicdebug")){
298 for(i=0; i<=MaxAPICNO; i++){
300 print("LAPIC%d: pa=%lux va=%lux flags=%x\n",
301 i, apic->paddr, (ulong)apic->addr, apic->flags);
302 if(apic = mpioapic[i])
303 print("IOAPIC%d: pa=%lux va=%lux flags=%x gsibase=%d mre=%d\n",
304 i, apic->paddr, (ulong)apic->addr, apic->flags, apic->gsibase, apic->mre);
306 for(b = mpbus; b; b = b->next){
307 print("BUS%d type=%d flags=%x\n", b->busno, b->type, b->po|b->el);
308 for(ai = b->aintr; ai; ai = ai->next){
310 print("\ttype=%d irq=%d (%d [%c]) apic=%d intin=%d flags=%x\n",
311 pi->type, pi->irq, pi->irq>>2, "ABCD"[pi->irq&3],
312 pi->apicno, pi->intin, pi->flags);
318 for(i=0; i<=MaxAPICNO; i++){
321 if(mpapic[i]->flags & PcmpBP){
328 panic("mpinit: no bootstrap processor");
336 * These interrupts are local to the processor
337 * and do not appear in the I/O APIC so it is OK
340 intrenable(IrqTIMER, lapicclock, 0, BUSUNKNOWN, "clock");
341 intrenable(IrqERROR, lapicerror, 0, BUSUNKNOWN, "lapicerror");
342 intrenable(IrqSPURIOUS, lapicspurious, 0, BUSUNKNOWN, "lapicspurious");
348 * Initialise the application processors.
350 if(cp = getconf("*ncpu")){
351 ncpu = strtol(cp, 0, 0);
354 else if(ncpu > MAXMACH)
359 memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
360 for(i=0; i<nelem(mpapic); i++){
361 if((apic = mpapic[i]) == nil)
365 if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN){
373 * we don't really know the number of processors till
376 * set conf.copymode here if nmach > 1.
377 * Should look for an ExtINT line and enable it.
379 if(X86FAMILY(m->cpuidax) == 3 || conf.nmach > 1)
386 static Lock physidlock;
391 * The bulk of this code was written ~1995, when there was
392 * one architecture and one generation of hardware, the number
393 * of CPUs was up to 4(8) and the choices for interrupt routing
394 * were physical, or flat logical (optionally with lowest
395 * priority interrupt). Logical mode hasn't scaled well with
396 * the increasing number of packages/cores/threads, so the
397 * fall-back is to physical mode, which works across all processor
398 * generations, both AMD and Intel, using the APIC and xAPIC.
400 * Interrupt routing policy can be set here.
401 * Currently, just assign each interrupt to a different CPU on
402 * a round-robin basis. Some idea of the packages/cores/thread
403 * topology would be useful here, e.g. to not assign interrupts
404 * to more than one thread in a core, or to use a "noise" core.
405 * But, as usual, Intel make that an onerous task.
410 if(physid >= nelem(mpapic))
414 if(mpapic[i]->online)
419 return mpapic[i]->apicno;
423 * With the APIC a unique vector can be assigned to each
424 * request to enable an interrupt. There are two reasons this
426 * 1) to prevent lost interrupts, no more than 2 interrupts
427 * should be assigned per block of 16 vectors (there is an
428 * in-service entry and a holding entry for each priority
429 * level and there is one priority level per block of 16
431 * 2) each input pin on the IOAPIC will receive a different
432 * vector regardless of whether the devices on that pin use
433 * the same IRQ as devices on another pin.
438 static int round = 0, num = 0;
443 vno = VectorAPIC + num;
444 if(vno < MaxVectorAPIC-7)
453 mpintrenablex(Vctl* v, int tbdf)
459 int bno, dno, pin, hi, irq, lo, n, type, vno;
461 type = BUSTYPE(tbdf);
468 if(pcidev = pcimatchtbdf(tbdf))
469 pin = pcicfgr8(pcidev, PciINTP);
470 } else if(type == BusISA)
474 for(bus = mpbus; bus != nil; bus = bus->next){
475 if(bus->type != type)
477 if(bus->busno == bno)
483 * if the PCI device is behind a PCI-PCI bridge thats not described
484 * by the MP or ACPI tables then walk up the bus translating interrupt
487 if(pcidev && pcidev->parent && pin > 0){
488 pin = ((dno+(pin-1))%4)+1;
489 pcidev = pcidev->parent;
490 bno = BUSBNO(pcidev->tbdf);
491 dno = BUSDNO(pcidev->tbdf);
494 print("mpintrenable: can't find bus type %d, number %d\n", type, bno);
499 * For PCI devices the interrupt pin (INT[ABCD]) and device
500 * number are encoded into the entry irq field, so create something
503 if(bus->type == BusPCI){
505 irq = (dno<<2)|(pin-1);
513 * Find a matching interrupt entry from the list of interrupts
514 * attached to this bus.
516 for(aintr = bus->aintr; aintr; aintr = aintr->next){
517 if(aintr->intr->irq != irq)
520 PCMPintr* p = aintr->intr;
521 print("mpintrenablex: bus %d intin %d irq %d\n",
522 p->busno, p->intin, p->irq);
525 * Check if already enabled. Multifunction devices may share
526 * INT[A-D]# so, if already enabled, check the polarity matches
527 * and the trigger is level.
529 * Should check the devices differ only in the function number,
530 * but that can wait for the planned enable/disable rewrite.
531 * The RDT read here is safe for now as currently interrupts
532 * are never disabled once enabled.
535 ioapicrdtr(apic, aintr->intr->intin, 0, &lo);
536 if(!(lo & ApicIMASK)){
538 if(0) print("%s vector %d (!imask)\n", v->name, vno);
539 n = mpintrinit(bus, aintr->intr, vno, v->irq);
540 n |= ApicPHYSICAL; /* no-op */
541 lo &= ~(ApicRemoteIRR|ApicDELIVS);
543 print("mpintrenable: multiple botch irq %d, tbdf %uX, lo %8.8uX, n %8.8uX\n",
544 v->irq, tbdf, lo, n);
553 hi = mpintrcpu()<<24;
554 lo = mpintrinit(bus, aintr->intr, vno, v->irq);
555 lo |= ApicPHYSICAL; /* no-op */
557 print("mpintrenable: disabled irq %d, tbdf %uX, lo %8.8uX, hi %8.8uX\n",
558 v->irq, tbdf, lo, hi);
561 if((apic->flags & PcmpEN) && apic->type == PcmpIOAPIC)
562 ioapicrdtw(apic, aintr->intr->intin, hi, lo);
573 MSICtrl = 0x02, /* message control register (16 bit) */
574 MSIAddr = 0x04, /* message address register (64 bit) */
575 MSIData32 = 0x08, /* message data register for 32 bit MSI (16 bit) */
576 MSIData64 = 0x0C, /* message data register for 64 bit MSI (16 bit) */
586 htmsicapenable(Pcidev *p)
590 if((cap = pcihtcap(p, HTMSIMapping)) <= 0)
592 flags = pcicfgr8(p, cap + HTMSIFlags);
593 if((flags & HTMSIFlagsEn) == 0)
594 pcicfgw8(p, cap + HTMSIFlags, flags | HTMSIFlagsEn);
599 htmsienable(Pcidev *pdev)
604 while((p = pcimatch(p, 0x1022, 0)) != nil)
605 if(p->did == 0x1103 || p->did == 0x1203)
609 return 0; /* not hypertransport platform */
612 while((p = pcimatch(p, 0x10de, 0)) != nil){
614 case 0x02f0: /* NVIDIA NFORCE C51 MEMC0 */
615 case 0x02f1: /* NVIDIA NFORCE C51 MEMC1 */
616 case 0x02f2: /* NVIDIA NFORCE C51 MEMC2 */
617 case 0x02f3: /* NVIDIA NFORCE C51 MEMC3 */
618 case 0x02f4: /* NVIDIA NFORCE C51 MEMC4 */
619 case 0x02f5: /* NVIDIA NFORCE C51 MEMC5 */
620 case 0x02f6: /* NVIDIA NFORCE C51 MEMC6 */
621 case 0x02f7: /* NVIDIA NFORCE C51 MEMC7 */
622 case 0x0369: /* NVIDIA NFORCE MCP55 MEMC */
628 if(htmsicapenable(pdev) == 0)
631 for(p = pdev->parent; p != nil; p = p->parent)
632 if(htmsicapenable(p) == 0)
639 msiintrenable(Vctl *v)
641 int tbdf, vno, cap, cpu, ok64;
644 if(getconf("*nomsi") != nil)
647 if(tbdf == BUSUNKNOWN || BUSTYPE(tbdf) != BusPCI)
649 pci = pcimatchtbdf(tbdf);
651 print("msiintrenable: could not find Pcidev for tbdf %uX\n", tbdf);
654 if(htmsienable(pci) < 0)
656 cap = pcicap(pci, PciCapMSI);
661 ok64 = (pcicfgr16(pci, cap + MSICtrl) & (1<<7)) != 0;
662 pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
663 if(ok64) pcicfgw32(pci, cap + MSIAddr + 4, 0);
664 pcicfgw16(pci, cap + (ok64 ? MSIData64 : MSIData32), vno | (1<<14));
665 pcicfgw16(pci, cap + MSICtrl, 1);
672 mpintrenable(Vctl* v)
676 vno = msiintrenable(v);
681 * If the bus is known, try it.
682 * BUSUNKNOWN is given both by [E]ISA devices and by
683 * interrupts local to the processor (local APIC, coprocessor
684 * breakpoint and page-fault).
687 if(tbdf != BUSUNKNOWN && (vno = mpintrenablex(v, tbdf)) != -1)
691 if(irq >= IrqLINT0 && irq <= MaxIrqLAPIC){
692 if(irq != IrqSPURIOUS)
694 return VectorPIC+irq;
696 if(irq < 0 || irq > MaxIrqPIC){
697 print("mpintrenable: irq %d out of range\n", irq);
702 * Either didn't find it or have to try the default buses
703 * (ISA and EISA). This hack is due to either over-zealousness
704 * or laziness on the part of some manufacturers.
706 * The MP configuration table on some older systems
707 * (e.g. ASUS PCI/E-P54NP4) has an entry for the EISA bus
708 * but none for ISA. It also has the interrupt type and
709 * polarity set to 'default for this bus' which wouldn't
710 * be compatible with ISA.
713 vno = mpintrenablex(v, MKBUS(BusEISA, 0, 0, 0));
718 vno = mpintrenablex(v, MKBUS(BusISA, 0, 0, 0));
722 print("mpintrenable: out of choices eisa %d isa %d tbdf %uX irq %d\n",
723 mpeisabus, mpisabus, v->tbdf, v->irq);
731 static Lock shutdownlock;
736 if(!canlock(&shutdownlock)){
738 * If this processor received the CTRL-ALT-DEL from
739 * the keyboard, acknowledge it. Send an INIT to self.
742 if(lapicisr(VectorKBD))
744 #endif /* FIX THIS */
749 print("apshutdown: active = %#8.8ux\n", active.machs);
754 * INIT all excluding self.
756 lapicicrw(0, 0x000C0000|ApicINIT);
762 * Often the BIOS hangs during restart if a conventional 8042
763 * warm-boot sequence is tried. The following is Intel specific and
764 * seems to perform a cold-boot, but at least it comes back.
765 * And sometimes there is no keyboard...
767 * The reset register (0xcf9) is usually in one of the bridge
768 * chips. The actual location and sequence could be extracted from
769 * ACPI but why bother, this is the end of the line anyway.
771 print("no kbd; trying bios warm boot...");
772 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
776 print("can't reset\n");