2 #include "../port/lib.h"
10 #include "apbootstrap.h"
14 static Bus* mpbuslast;
15 static int mpisabus = -1;
16 static int mpeisabus = -1;
17 extern int i8259elcr; /* mask of level-triggered interrupts */
18 static Apic mpapic[MaxAPICNO+1];
19 static int machno2apicno[MaxAPICNO+1]; /* inverse map: machno -> APIC ID */
20 static Ref mpvnoref; /* unique vector assignment */
21 static int mpmachno = 1;
22 static Lock mpphysidlock;
25 static char* buses[] = {
48 mkprocessor(PCMPprocessor* p)
54 if(!(p->flags & PcmpEN) || apicno > MaxAPICNO)
57 apic = &mpapic[apicno];
58 apic->type = PcmpPROCESSOR;
59 apic->apicno = apicno;
60 apic->flags = p->flags;
61 apic->lintr[0] = ApicIMASK;
62 apic->lintr[1] = ApicIMASK;
64 if(p->flags & PcmpBP){
65 machno2apicno[0] = apicno;
69 machno2apicno[mpmachno] = apicno;
70 apic->machno = mpmachno;
83 for(i = 0; buses[i]; i++){
84 if(strncmp(buses[i], p->string, sizeof(p->string)) == 0)
90 bus = xalloc(sizeof(Bus));
92 mpbuslast->next = bus;
98 bus->busno = p->busno;
99 if(bus->type == BusEISA){
103 print("mkbus: more than one EISA bus\n");
104 mpeisabus = bus->busno;
106 else if(bus->type == BusPCI){
110 else if(bus->type == BusISA){
114 print("mkbus: more than one ISA bus\n");
115 mpisabus = bus->busno;
130 for(bus = mpbus; bus; bus = bus->next){
131 if(bus->busno == busno)
134 print("mpgetbus: can't find bus %d\n", busno);
140 mkioapic(PCMPioapic* p)
147 if(!(p->flags & PcmpEN) || apicno > MaxAPICNO)
153 if((va = vmap(p->addr, 1024)) == nil)
156 apic = &mpapic[apicno];
158 print("mkioapic: APIC ID conflict at %d\n", p->apicno);
159 apic->type = PcmpIOAPIC;
160 apic->apicno = apicno;
162 apic->paddr = p->addr;
163 apic->flags = p->flags;
169 mkiointr(PCMPintr* p)
176 * According to the MultiProcessor Specification, a destination
177 * I/O APIC of 0xFF means the signal is routed to all I/O APICs.
178 * It's unclear how that can possibly be correct so treat it as
181 if(p->apicno == 0xFF)
183 if((bus = mpgetbus(p->busno)) == 0)
186 aintr = xalloc(sizeof(Aintr));
190 print("iointr: type %d intr type %d flags %#o "
191 "bus %d irq %d apicno %d intin %d\n",
192 p->type, p->intr, p->flags,
193 p->busno, p->irq, p->apicno, p->intin);
195 * Hack for Intel SR1520ML motherboard, which BIOS describes
196 * the i82575 dual ethernet controllers incorrectly.
198 if(memcmp(mppcmp->product, "INTEL X38MLST ", 20) == 0){
199 if(p->busno == 1 && p->intin == 16 && p->irq == 1){
200 pcmpintr = malloc(sizeof(PCMPintr));
201 memmove(pcmpintr, p, sizeof(PCMPintr));
202 print("mkiointr: %20.20s bus %d intin %d irq %d\n",
203 (char*)mppcmp->product,
204 pcmpintr->busno, pcmpintr->intin,
206 pcmpintr->intin = 17;
207 aintr->intr = pcmpintr;
210 aintr->apic = &mpapic[p->apicno];
211 aintr->next = bus->aintr;
218 mpintrinit(Bus* bus, PCMPintr* intr, int vno, int /*irq*/)
223 * Parse an I/O or Local APIC interrupt table entry and
224 * return the encoded vector.
228 po = intr->flags & PcmpPOMASK;
229 el = intr->flags & PcmpELMASK;
233 default: /* PcmpINT */
234 v |= ApicFIXED; /* no-op */
250 * The AMI Goliath doesn't boot successfully with it's LINTR0
251 * entry which decodes to low+level. The PPro manual says ExtINT
252 * should be level, whereas the Pentium is edge. Setting the
253 * Goliath to edge+high seems to cure the problem. Other PPro
254 * MP tables (e.g. ASUS P/I-P65UP5 have a entry which decodes
255 * to edge+high, so who knows.
256 * Perhaps it would be best just to not set an ExtINT entry at
257 * all, it shouldn't be needed for SMP mode.
266 if(bus->type == BusEISA && !po && !el /*&& !(i8259elcr & (1<<irq))*/){
274 else if(po != PcmpHIGH){
275 print("mpintrinit: bad polarity 0x%uX\n", po);
283 else if(el != PcmpEDGE){
284 print("mpintrinit: bad trigger 0x%uX\n", el);
299 * The offsets of vectors for LINT[01] are known to be
300 * 0 and 1 from the local APIC vector space at VectorLAPIC.
302 if((bus = mpgetbus(p->busno)) == 0)
307 * Pentium Pros have problems if LINT[01] are set to ExtINT
308 * so just bag it, SMP mode shouldn't need ExtINT anyway.
310 if(p->intr == PcmpExtINT || p->intr == PcmpNMI)
313 v = mpintrinit(bus, p, VectorLAPIC+intin, p->irq);
315 if(p->apicno == 0xFF){
316 for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
317 if((apic->flags & PcmpEN)
318 && apic->type == PcmpPROCESSOR)
319 apic->lintr[intin] = v;
323 apic = &mpapic[p->apicno];
324 if((apic->flags & PcmpEN) && apic->type == PcmpPROCESSOR)
325 apic->lintr[intin] = v;
338 * If there are MTRR registers, snarf them for validation.
340 if(!(m->cpuiddx & 0x1000))
343 rdmsr(0x0FE, &m->mtrrcap);
344 rdmsr(0x2FF, &m->mtrrdef);
345 if(m->mtrrcap & 0x0100){
346 rdmsr(0x250, &m->mtrrfix[0]);
347 rdmsr(0x258, &m->mtrrfix[1]);
348 rdmsr(0x259, &m->mtrrfix[2]);
349 for(i = 0; i < 8; i++)
350 rdmsr(0x268+i, &m->mtrrfix[(i+3)]);
352 vcnt = m->mtrrcap & 0x00FF;
353 if(vcnt > nelem(m->mtrrvar))
354 vcnt = nelem(m->mtrrvar);
355 for(i = 0; i < vcnt; i++)
356 rdmsr(0x200+i, &m->mtrrvar[i]);
359 * If not the bootstrap processor, compare.
365 if(mach0->mtrrcap != m->mtrrcap)
366 print("mtrrcap%d: %lluX %lluX\n",
367 m->machno, mach0->mtrrcap, m->mtrrcap);
368 if(mach0->mtrrdef != m->mtrrdef)
369 print("mtrrdef%d: %lluX %lluX\n",
370 m->machno, mach0->mtrrdef, m->mtrrdef);
371 for(i = 0; i < 11; i++){
372 if(mach0->mtrrfix[i] != m->mtrrfix[i])
373 print("mtrrfix%d: i%d: %lluX %lluX\n",
374 m->machno, i, mach0->mtrrfix[i], m->mtrrfix[i]);
376 for(i = 0; i < vcnt; i++){
377 if(mach0->mtrrvar[i] != m->mtrrvar[i])
378 print("mtrrvar%d: i%d: %lluX %lluX\n",
379 m->machno, i, mach0->mtrrvar[i], m->mtrrvar[i]);
386 // iprint("Hello Squidboy\n");
405 active.machs |= 1<<m->machno;
408 while(!active.thunderbirdsarego)
415 mpstartap(Apic* apic)
417 ulong *apbootp, *pdb, *pte;
425 * Initialise the AP page-tables and Mach structure. The page-tables
426 * are the same as for the bootstrap processor with the exception of
427 * the PTE for the Mach structure.
428 * Xspanalloc will panic if an allocation can't be made.
430 p = xspanalloc(4*BY2PG, BY2PG, 0);
432 memmove(pdb, mach0->pdb, BY2PG);
435 if((pte = mmuwalk(pdb, MACHADDR, 1, 0)) == nil)
437 memmove(p, KADDR(PPN(*pte)), BY2PG);
438 *pte = PADDR(p)|PTEWRITE|PTEVALID;
444 if((pte = mmuwalk(pdb, MACHADDR, 2, 0)) == nil)
446 *pte = PADDR(mach)|PTEWRITE|PTEVALID;
451 machno = apic->machno;
452 MACHP(machno) = mach;
453 mach->machno = machno;
455 mach->gdt = (Segdesc*)p; /* filled by mmuinit */
458 * Tell the AP where its kernel vector and pdb are.
459 * The offsets are known in the AP bootstrap code.
461 apbootp = (ulong*)(APBOOTSTRAP+0x08);
462 *apbootp++ = (ulong)squidboy;
463 *apbootp++ = PADDR(pdb);
464 *apbootp = (ulong)apic;
467 * Universal Startup Algorithm.
470 *p++ = PADDR(APBOOTSTRAP);
471 *p++ = PADDR(APBOOTSTRAP)>>8;
472 i = (PADDR(APBOOTSTRAP) & ~0xFFFF)/16;
473 /* code assumes i==0 */
475 print("mp: bad APBOOTSTRAP\n");
479 nvramwrite(0x0F, 0x0A);
480 lapicstartap(apic, PADDR(APBOOTSTRAP));
481 for(i = 0; i < 1000; i++){
486 nvramwrite(0x0F, 0x00);
490 dumpmp(uchar *p, uchar *e)
494 for(i = 0; p < e; p++) {
495 if((i % 16) == 0) print("*mp%d=", i/16);
497 if((++i % 16) == 0) print("\n");
499 if((i % 16) != 0) print("\n");
503 mpoverride(uchar** newp, uchar** e)
510 size = atoi(getconf("*mp"));
511 if(size == 0) panic("mpoverride: invalid size in *mp");
512 *newp = p = malloc(size);
513 if(p == nil) panic("mpoverride: can't allocate memory");
516 snprint(buf, sizeof buf, "*mp%d", i);
520 j = strtol(s, &s, 16);
521 if(*s && *s != ' ' || j < 0 || j > 0xff) panic("mpoverride: invalid entry in %s", buf);
522 if(p >= *e) panic("mpoverride: overflow in %s", buf);
526 if(p != *e) panic("mpoverride: size doesn't match");
544 pcmp = KADDR(_mp_->physaddr);
547 * Map the local APIC.
549 if((va = vmap(pcmp->lapicbase, 1024)) == nil)
552 print("LAPIC: %.8lux %.8lux\n", pcmp->lapicbase, (ulong)va);
557 * Run through the table saving information needed for starting
558 * application processors and initialising any I/O APICs. The table
559 * is guaranteed to be in order such that only one pass is necessary.
561 p = ((uchar*)pcmp)+sizeof(PCMP);
562 e = ((uchar*)pcmp)+pcmp->length;
563 if(getconf("*dumpmp") != nil)
565 if(getconf("*mp") != nil)
567 while(p < e) switch(*p){
570 print("mpinit: unknown PCMP type 0x%uX (e-p 0x%luX)\n",
579 if(apic = mkprocessor((PCMPprocessor*)p)){
581 * Must take a note of bootstrap processor APIC
582 * now as it will be needed in order to start the
583 * application processors later and there's no
584 * guarantee that the bootstrap processor appears
585 * first in the table before the others.
588 apic->paddr = pcmp->lapicbase;
589 if(apic->flags & PcmpBP)
592 p += sizeof(PCMPprocessor);
597 p += sizeof(PCMPbus);
601 if(apic = mkioapic((PCMPioapic*)p))
602 ioapicinit(apic, ((PCMPioapic*)p)->apicno);
603 p += sizeof(PCMPioapic);
607 mkiointr((PCMPintr*)p);
608 p += sizeof(PCMPintr);
612 mklintr((PCMPintr*)p);
613 p += sizeof(PCMPintr);
618 * No bootstrap processor, no need to go further.
627 * These interrupts are local to the processor
628 * and do not appear in the I/O APIC so it is OK
631 intrenable(IrqTIMER, lapicclock, 0, BUSUNKNOWN, "clock");
632 intrenable(IrqERROR, lapicerror, 0, BUSUNKNOWN, "lapicerror");
633 intrenable(IrqSPURIOUS, lapicspurious, 0, BUSUNKNOWN, "lapicspurious");
639 * Initialise the application processors.
641 if(cp = getconf("*ncpu")){
642 ncpu = strtol(cp, 0, 0);
645 else if(ncpu > MAXMACH)
650 memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
651 for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
654 if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN
655 && apic->type == PcmpPROCESSOR){
663 * we don't really know the number of processors till
666 * set conf.copymode here if nmach > 1.
667 * Should look for an ExtINT line and enable it.
669 if(X86FAMILY(m->cpuidax) == 3 || conf.nmach > 1)
679 * The bulk of this code was written ~1995, when there was
680 * one architecture and one generation of hardware, the number
681 * of CPUs was up to 4(8) and the choices for interrupt routing
682 * were physical, or flat logical (optionally with lowest
683 * priority interrupt). Logical mode hasn't scaled well with
684 * the increasing number of packages/cores/threads, so the
685 * fall-back is to physical mode, which works across all processor
686 * generations, both AMD and Intel, using the APIC and xAPIC.
688 * Interrupt routing policy can be set here.
689 * Currently, just assign each interrupt to a different CPU on
690 * a round-robin basis. Some idea of the packages/cores/thread
691 * topology would be useful here, e.g. to not assign interrupts
692 * to more than one thread in a core, or to use a "noise" core.
693 * But, as usual, Intel make that an onerous task.
698 if(mpphysid >= MaxAPICNO+1)
703 unlock(&mpphysidlock);
705 return mpapic[i].apicno;
708 /* hardcoded VectorAPIC and stuff. bad. */
712 static int round = 0, num = 1;
718 if(++round >= 8) round = 0;
721 vno = 64 + num++ * 8 + round;
727 mpintrenablex(Vctl* v, int tbdf)
733 int bno, dno, hi, irq, lo, n, type, vno;
738 type = BUSTYPE(tbdf);
743 for(bus = mpbus; bus != nil; bus = bus->next){
744 if(bus->type != type)
746 if(bus->busno == bno)
750 print("ioapicirq: can't find bus type %d, number %d\n", type, bno);
755 * For PCI devices the interrupt pin (INT[ABCD]) and device
756 * number are encoded into the entry irq field, so create something
757 * to match on. The interrupt pin used by the device has to be
758 * obtained from the PCI config space.
760 if(bus->type == BusPCI){
761 pcidev = pcimatchtbdf(tbdf);
762 if(pcidev != nil && (n = pcicfgr8(pcidev, PciINTP)) != 0)
763 irq = (dno<<2)|(n-1);
766 //print("pcidev %uX: irq %uX v->irq %uX\n", tbdf, irq, v->irq);
772 * Find a matching interrupt entry from the list of interrupts
773 * attached to this bus.
775 for(aintr = bus->aintr; aintr; aintr = aintr->next){
776 if(aintr->intr->irq != irq)
779 PCMPintr* p = aintr->intr;
781 print("mpintrenablex: bus %d intin %d irq %d\n",
782 p->busno, p->intin, p->irq);
785 * Check if already enabled. Multifunction devices may share
786 * INT[A-D]# so, if already enabled, check the polarity matches
787 * and the trigger is level.
789 * Should check the devices differ only in the function number,
790 * but that can wait for the planned enable/disable rewrite.
791 * The RDT read here is safe for now as currently interrupts
792 * are never disabled once enabled.
795 ioapicrdtr(apic, aintr->intr->intin, 0, &lo);
796 if(!(lo & ApicIMASK)){
798 //print("%s vector %d (!imask)\n", v->name, vno);
799 n = mpintrinit(bus, aintr->intr, vno, v->irq);
800 n |= ApicPHYSICAL; /* no-op */
801 lo &= ~(ApicRemoteIRR|ApicDELIVS);
802 if(n != lo || !(n & ApicLEVEL)){
803 print("mpintrenable: multiple botch irq%d, tbdf %uX, lo %8.8uX, n %8.8uX\n",
804 v->irq, tbdf, lo, n);
815 * With the APIC a unique vector can be assigned to each
816 * request to enable an interrupt. There are two reasons this
818 * 1) to prevent lost interrupts, no more than 2 interrupts
819 * should be assigned per block of 16 vectors (there is an
820 * in-service entry and a holding entry for each priority
821 * level and there is one priority level per block of 16
823 * 2) each input pin on the IOAPIC will receive a different
824 * vector regardless of whether the devices on that pin use
825 * the same IRQ as devices on another pin.
828 hi = mpintrcpu()<<24;
829 lo = mpintrinit(bus, aintr->intr, vno, v->irq);
830 //print("lo 0x%uX: busno %d intr %d vno %d irq %d elcr 0x%uX\n",
831 // lo, bus->busno, aintr->intr->irq, vno,
832 // v->irq, i8259elcr);
836 lo |= ApicPHYSICAL; /* no-op */
838 if((apic->flags & PcmpEN) && apic->type == PcmpIOAPIC)
839 ioapicrdtw(apic, aintr->intr->intin, hi, lo);
841 // print("lo not enabled 0x%uX %d\n",
842 // apic->flags, apic->type);
854 MSICtrl = 0x02, /* message control register (16 bit) */
855 MSIAddr = 0x04, /* message address register (64 bit) */
856 MSIData = 0x0C, /* message data register (16 bit) */
860 msiintrenable(Vctl *v)
862 int tbdf, vno, cap, cpu;
865 if(getconf("*msi") == nil)
868 if(tbdf == BUSUNKNOWN || BUSTYPE(tbdf) != BusPCI)
870 pci = pcimatchtbdf(tbdf);
872 print("msiintrenable: could not find Pcidev for tbdf %.8x\n", tbdf);
877 cap = pcinextcap(pci, cap);
880 if(pcicfgr8(pci, cap) == 0x05) /* MSI block */
886 pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
887 pcicfgw32(pci, cap + MSIAddr + 4, 0);
888 pcicfgw16(pci, cap + MSIData, vno | (1<<14));
889 pcicfgw16(pci, cap + MSICtrl, 1);
890 print("msiintrenable: success with tbdf %.8x, vector %d, cpu %d\n", tbdf, vno, cpu);
897 mpintrenable(Vctl* v)
901 vno = msiintrenable(v);
906 * If the bus is known, try it.
907 * BUSUNKNOWN is given both by [E]ISA devices and by
908 * interrupts local to the processor (local APIC, coprocessor
909 * breakpoint and page-fault).
912 if(tbdf != BUSUNKNOWN && (vno = mpintrenablex(v, tbdf)) != -1)
916 if(irq >= IrqLINT0 && irq <= MaxIrqLAPIC){
917 if(irq != IrqSPURIOUS)
919 return VectorPIC+irq;
921 if(irq < 0 || irq > MaxIrqPIC){
922 print("mpintrenable: irq %d out of range\n", irq);
927 * Either didn't find it or have to try the default buses
928 * (ISA and EISA). This hack is due to either over-zealousness
929 * or laziness on the part of some manufacturers.
931 * The MP configuration table on some older systems
932 * (e.g. ASUS PCI/E-P54NP4) has an entry for the EISA bus
933 * but none for ISA. It also has the interrupt type and
934 * polarity set to 'default for this bus' which wouldn't
935 * be compatible with ISA.
938 vno = mpintrenablex(v, MKBUS(BusEISA, 0, 0, 0));
943 vno = mpintrenablex(v, MKBUS(BusISA, 0, 0, 0));
947 print("mpintrenable: out of choices eisa %d isa %d tbdf %#ux irq %d\n",
948 mpeisabus, mpisabus, v->tbdf, v->irq);
952 static Lock mpshutdownlock;
960 if(!canlock(&mpshutdownlock)){
962 * If this processor received the CTRL-ALT-DEL from
963 * the keyboard, acknowledge it. Send an INIT to self.
966 if(lapicisr(VectorKBD))
968 #endif /* FIX THIS */
973 print("apshutdown: active = %#8.8ux\n", active.machs);
978 * INIT all excluding self.
980 lapicicrw(0, 0x000C0000|ApicINIT);
986 * Often the BIOS hangs during restart if a conventional 8042
987 * warm-boot sequence is tried. The following is Intel specific and
988 * seems to perform a cold-boot, but at least it comes back.
989 * And sometimes there is no keyboard...
991 * The reset register (0xcf9) is usually in one of the bridge
992 * chips. The actual location and sequence could be extracted from
993 * ACPI but why bother, this is the end of the line anyway.
995 print("no kbd; trying bios warm boot...");
996 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
1000 print("can't reset\n");