2 #include "../port/lib.h"
10 #include "apbootstrap.h"
14 static Bus* mpbuslast;
15 static int mpisabus = -1;
16 static int mpeisabus = -1;
17 extern int i8259elcr; /* mask of level-triggered interrupts */
18 static Apic mpapic[MaxAPICNO+1];
19 static int machno2apicno[MaxAPICNO+1]; /* inverse map: machno -> APIC ID */
20 static int mpapicremap[MaxAPICNO+1];
21 static int mpmachno = 1;
22 static Lock mpphysidlock;
25 static char* buses[] = {
48 mkprocessor(PCMPprocessor* p)
54 if(!(p->flags & PcmpEN) || apicno > MaxAPICNO)
57 apic = &mpapic[apicno];
58 apic->type = PcmpPROCESSOR;
59 apic->apicno = apicno;
60 apic->flags = p->flags;
61 apic->lintr[0] = ApicIMASK;
62 apic->lintr[1] = ApicIMASK;
64 if(p->flags & PcmpBP){
65 machno2apicno[0] = apicno;
69 machno2apicno[mpmachno] = apicno;
70 apic->machno = mpmachno;
83 for(i = 0; buses[i]; i++){
84 if(strncmp(buses[i], p->string, sizeof(p->string)) == 0)
90 bus = xalloc(sizeof(Bus));
92 mpbuslast->next = bus;
98 bus->busno = p->busno;
99 if(bus->type == BusEISA){
103 print("mkbus: more than one EISA bus\n");
104 mpeisabus = bus->busno;
106 else if(bus->type == BusPCI){
110 else if(bus->type == BusISA){
114 print("mkbus: more than one ISA bus\n");
115 mpisabus = bus->busno;
130 for(bus = mpbus; bus; bus = bus->next){
131 if(bus->busno == busno)
134 print("mpgetbus: can't find bus %d\n", busno);
144 for(i = 0; i < MaxAPICNO+1; i++)
145 if(mpapic[i].flags == 0)
151 mkioapic(PCMPioapic* p)
158 if(!(p->flags & PcmpEN) || apicno > MaxAPICNO)
164 if((va = vmap(p->addr, 1024)) == nil)
167 apic = &mpapic[apicno];
168 if(apic->flags != 0) {
171 print("mkioapic: out of APIC IDs\n");
173 mpapicremap[p->apicno] = new;
174 print("mkioapic: APIC ID conflict at %d, remapping to %d\n", p->apicno, new);
175 p->apicno = apicno = new;
176 apic = &mpapic[apicno];
179 mpapicremap[p->apicno] = p->apicno;
180 apic->type = PcmpIOAPIC;
181 apic->apicno = apicno;
183 apic->paddr = p->addr;
184 apic->flags = p->flags;
190 mkiointr(PCMPintr* p)
197 * According to the MultiProcessor Specification, a destination
198 * I/O APIC of 0xFF means the signal is routed to all I/O APICs.
199 * It's unclear how that can possibly be correct so treat it as
202 if(p->apicno > MaxAPICNO)
205 if(mpapicremap[p->apicno] < 0) {
206 print("iointr: non-existing IOAPIC %d\n", p->apicno);
209 p->apicno = mpapicremap[p->apicno];
210 if((bus = mpgetbus(p->busno)) == 0)
213 aintr = xalloc(sizeof(Aintr));
217 print("iointr: type %d intr type %d flags %#o "
218 "bus %d irq %d apicno %d intin %d\n",
219 p->type, p->intr, p->flags,
220 p->busno, p->irq, p->apicno, p->intin);
222 * Hack for Intel SR1520ML motherboard, which BIOS describes
223 * the i82575 dual ethernet controllers incorrectly.
225 if(memcmp(mppcmp->product, "INTEL X38MLST ", 20) == 0){
226 if(p->busno == 1 && p->intin == 16 && p->irq == 1){
227 pcmpintr = malloc(sizeof(PCMPintr));
228 memmove(pcmpintr, p, sizeof(PCMPintr));
229 print("mkiointr: %20.20s bus %d intin %d irq %d\n",
230 (char*)mppcmp->product,
231 pcmpintr->busno, pcmpintr->intin,
233 pcmpintr->intin = 17;
234 aintr->intr = pcmpintr;
237 aintr->apic = &mpapic[p->apicno];
238 aintr->next = bus->aintr;
245 mpintrinit(Bus* bus, PCMPintr* intr, int vno, int /*irq*/)
250 * Parse an I/O or Local APIC interrupt table entry and
251 * return the encoded vector.
255 po = intr->flags & PcmpPOMASK;
256 el = intr->flags & PcmpELMASK;
260 default: /* PcmpINT */
261 v |= ApicFIXED; /* no-op */
277 * The AMI Goliath doesn't boot successfully with it's LINTR0
278 * entry which decodes to low+level. The PPro manual says ExtINT
279 * should be level, whereas the Pentium is edge. Setting the
280 * Goliath to edge+high seems to cure the problem. Other PPro
281 * MP tables (e.g. ASUS P/I-P65UP5 have a entry which decodes
282 * to edge+high, so who knows.
283 * Perhaps it would be best just to not set an ExtINT entry at
284 * all, it shouldn't be needed for SMP mode.
293 if(bus->type == BusEISA && !po && !el /*&& !(i8259elcr & (1<<irq))*/){
301 else if(po != PcmpHIGH){
302 print("mpintrinit: bad polarity 0x%uX\n", po);
310 else if(el != PcmpEDGE){
311 print("mpintrinit: bad trigger 0x%uX\n", el);
326 * The offsets of vectors for LINT[01] are known to be
327 * 0 and 1 from the local APIC vector space at VectorLAPIC.
329 if((bus = mpgetbus(p->busno)) == 0)
334 * Pentium Pros have problems if LINT[01] are set to ExtINT
335 * so just bag it, SMP mode shouldn't need ExtINT anyway.
337 if(p->intr == PcmpExtINT || p->intr == PcmpNMI)
340 v = mpintrinit(bus, p, VectorLAPIC+intin, p->irq);
342 if(p->apicno == 0xFF){
343 for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
344 if((apic->flags & PcmpEN)
345 && apic->type == PcmpPROCESSOR)
346 apic->lintr[intin] = v;
350 apic = &mpapic[p->apicno];
351 if((apic->flags & PcmpEN) && apic->type == PcmpPROCESSOR)
352 apic->lintr[intin] = v;
365 * If there are MTRR registers, snarf them for validation.
367 if(!(m->cpuiddx & 0x1000))
370 rdmsr(0x0FE, &m->mtrrcap);
371 rdmsr(0x2FF, &m->mtrrdef);
372 if(m->mtrrcap & 0x0100){
373 rdmsr(0x250, &m->mtrrfix[0]);
374 rdmsr(0x258, &m->mtrrfix[1]);
375 rdmsr(0x259, &m->mtrrfix[2]);
376 for(i = 0; i < 8; i++)
377 rdmsr(0x268+i, &m->mtrrfix[(i+3)]);
379 vcnt = m->mtrrcap & 0x00FF;
380 if(vcnt > nelem(m->mtrrvar))
381 vcnt = nelem(m->mtrrvar);
382 for(i = 0; i < vcnt; i++)
383 rdmsr(0x200+i, &m->mtrrvar[i]);
386 * If not the bootstrap processor, compare.
392 if(mach0->mtrrcap != m->mtrrcap)
393 print("mtrrcap%d: %lluX %lluX\n",
394 m->machno, mach0->mtrrcap, m->mtrrcap);
395 if(mach0->mtrrdef != m->mtrrdef)
396 print("mtrrdef%d: %lluX %lluX\n",
397 m->machno, mach0->mtrrdef, m->mtrrdef);
398 for(i = 0; i < 11; i++){
399 if(mach0->mtrrfix[i] != m->mtrrfix[i])
400 print("mtrrfix%d: i%d: %lluX %lluX\n",
401 m->machno, i, mach0->mtrrfix[i], m->mtrrfix[i]);
403 for(i = 0; i < vcnt; i++){
404 if(mach0->mtrrvar[i] != m->mtrrvar[i])
405 print("mtrrvar%d: i%d: %lluX %lluX\n",
406 m->machno, i, mach0->mtrrvar[i], m->mtrrvar[i]);
413 // iprint("Hello Squidboy\n");
432 active.machs |= 1<<m->machno;
435 while(!active.thunderbirdsarego)
442 mpstartap(Apic* apic)
444 ulong *apbootp, *pdb, *pte;
452 * Initialise the AP page-tables and Mach structure. The page-tables
453 * are the same as for the bootstrap processor with the exception of
454 * the PTE for the Mach structure.
455 * Xspanalloc will panic if an allocation can't be made.
457 p = xspanalloc(4*BY2PG, BY2PG, 0);
459 memmove(pdb, mach0->pdb, BY2PG);
462 if((pte = mmuwalk(pdb, MACHADDR, 1, 0)) == nil)
464 memmove(p, KADDR(PPN(*pte)), BY2PG);
465 *pte = PADDR(p)|PTEWRITE|PTEVALID;
471 if((pte = mmuwalk(pdb, MACHADDR, 2, 0)) == nil)
473 *pte = PADDR(mach)|PTEWRITE|PTEVALID;
478 machno = apic->machno;
479 MACHP(machno) = mach;
480 mach->machno = machno;
482 mach->gdt = (Segdesc*)p; /* filled by mmuinit */
485 * Tell the AP where its kernel vector and pdb are.
486 * The offsets are known in the AP bootstrap code.
488 apbootp = (ulong*)(APBOOTSTRAP+0x08);
489 *apbootp++ = (ulong)squidboy;
490 *apbootp++ = PADDR(pdb);
491 *apbootp = (ulong)apic;
494 * Universal Startup Algorithm.
497 *p++ = PADDR(APBOOTSTRAP);
498 *p++ = PADDR(APBOOTSTRAP)>>8;
499 i = (PADDR(APBOOTSTRAP) & ~0xFFFF)/16;
500 /* code assumes i==0 */
502 print("mp: bad APBOOTSTRAP\n");
506 nvramwrite(0x0F, 0x0A);
507 lapicstartap(apic, PADDR(APBOOTSTRAP));
508 for(i = 0; i < 1000; i++){
513 nvramwrite(0x0F, 0x00);
517 dumpmp(uchar *p, uchar *e)
521 for(i = 0; p < e; p++) {
522 if((i % 16) == 0) print("*mp%d=", i/16);
524 if((++i % 16) == 0) print("\n");
526 if((i % 16) != 0) print("\n");
530 mpoverride(uchar** newp, uchar** e)
537 size = atoi(getconf("*mp"));
538 if(size == 0) panic("mpoverride: invalid size in *mp");
539 *newp = p = malloc(size);
540 if(p == nil) panic("mpoverride: can't allocate memory");
543 snprint(buf, sizeof buf, "*mp%d", i);
547 j = strtol(s, &s, 16);
548 if(*s && *s != ' ' || j < 0 || j > 0xff) panic("mpoverride: invalid entry in %s", buf);
549 if(p >= *e) panic("mpoverride: overflow in %s", buf);
553 if(p != *e) panic("mpoverride: size doesn't match");
571 pcmp = KADDR(_mp_->physaddr);
574 * Map the local APIC.
576 if((va = vmap(pcmp->lapicbase, 1024)) == nil)
579 print("LAPIC: %.8lux %.8lux\n", pcmp->lapicbase, (ulong)va);
583 for(i = 0; i <= MaxAPICNO; i++)
587 * Run through the table saving information needed for starting
588 * application processors and initialising any I/O APICs. The table
589 * is guaranteed to be in order such that only one pass is necessary.
591 p = ((uchar*)pcmp)+sizeof(PCMP);
592 e = ((uchar*)pcmp)+pcmp->length;
593 if(getconf("*dumpmp") != nil)
595 if(getconf("*mp") != nil)
597 while(p < e) switch(*p){
600 print("mpinit: unknown PCMP type 0x%uX (e-p 0x%luX)\n",
609 if(apic = mkprocessor((PCMPprocessor*)p)){
611 * Must take a note of bootstrap processor APIC
612 * now as it will be needed in order to start the
613 * application processors later and there's no
614 * guarantee that the bootstrap processor appears
615 * first in the table before the others.
618 apic->paddr = pcmp->lapicbase;
619 if(apic->flags & PcmpBP)
622 p += sizeof(PCMPprocessor);
627 p += sizeof(PCMPbus);
631 if(apic = mkioapic((PCMPioapic*)p))
632 ioapicinit(apic, ((PCMPioapic*)p)->apicno);
633 p += sizeof(PCMPioapic);
637 mkiointr((PCMPintr*)p);
638 p += sizeof(PCMPintr);
642 mklintr((PCMPintr*)p);
643 p += sizeof(PCMPintr);
648 * No bootstrap processor, no need to go further.
657 * These interrupts are local to the processor
658 * and do not appear in the I/O APIC so it is OK
661 intrenable(IrqTIMER, lapicclock, 0, BUSUNKNOWN, "clock");
662 intrenable(IrqERROR, lapicerror, 0, BUSUNKNOWN, "lapicerror");
663 intrenable(IrqSPURIOUS, lapicspurious, 0, BUSUNKNOWN, "lapicspurious");
669 * Initialise the application processors.
671 if(cp = getconf("*ncpu")){
672 ncpu = strtol(cp, 0, 0);
675 else if(ncpu > MAXMACH)
680 memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
681 for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
684 if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN
685 && apic->type == PcmpPROCESSOR){
693 * we don't really know the number of processors till
696 * set conf.copymode here if nmach > 1.
697 * Should look for an ExtINT line and enable it.
699 if(X86FAMILY(m->cpuidax) == 3 || conf.nmach > 1)
709 * The bulk of this code was written ~1995, when there was
710 * one architecture and one generation of hardware, the number
711 * of CPUs was up to 4(8) and the choices for interrupt routing
712 * were physical, or flat logical (optionally with lowest
713 * priority interrupt). Logical mode hasn't scaled well with
714 * the increasing number of packages/cores/threads, so the
715 * fall-back is to physical mode, which works across all processor
716 * generations, both AMD and Intel, using the APIC and xAPIC.
718 * Interrupt routing policy can be set here.
719 * Currently, just assign each interrupt to a different CPU on
720 * a round-robin basis. Some idea of the packages/cores/thread
721 * topology would be useful here, e.g. to not assign interrupts
722 * to more than one thread in a core, or to use a "noise" core.
723 * But, as usual, Intel make that an onerous task.
728 if(mpphysid >= MaxAPICNO+1)
733 unlock(&mpphysidlock);
735 return mpapic[i].apicno;
738 /* hardcoded VectorAPIC and stuff. bad. */
742 static int round = 0, num = 1;
748 if(++round >= 8) round = 0;
751 vno = 64 + num++ * 8 + round;
757 mpintrenablex(Vctl* v, int tbdf)
763 int bno, dno, hi, irq, lo, n, type, vno;
768 type = BUSTYPE(tbdf);
773 for(bus = mpbus; bus != nil; bus = bus->next){
774 if(bus->type != type)
776 if(bus->busno == bno)
780 print("ioapicirq: can't find bus type %d, number %d\n", type, bno);
785 * For PCI devices the interrupt pin (INT[ABCD]) and device
786 * number are encoded into the entry irq field, so create something
787 * to match on. The interrupt pin used by the device has to be
788 * obtained from the PCI config space.
790 if(bus->type == BusPCI){
791 pcidev = pcimatchtbdf(tbdf);
792 if(pcidev != nil && (n = pcicfgr8(pcidev, PciINTP)) != 0)
793 irq = (dno<<2)|(n-1);
796 //print("pcidev %uX: irq %uX v->irq %uX\n", tbdf, irq, v->irq);
802 * Find a matching interrupt entry from the list of interrupts
803 * attached to this bus.
805 for(aintr = bus->aintr; aintr; aintr = aintr->next){
806 if(aintr->intr->irq != irq)
809 PCMPintr* p = aintr->intr;
811 print("mpintrenablex: bus %d intin %d irq %d\n",
812 p->busno, p->intin, p->irq);
815 * Check if already enabled. Multifunction devices may share
816 * INT[A-D]# so, if already enabled, check the polarity matches
817 * and the trigger is level.
819 * Should check the devices differ only in the function number,
820 * but that can wait for the planned enable/disable rewrite.
821 * The RDT read here is safe for now as currently interrupts
822 * are never disabled once enabled.
825 ioapicrdtr(apic, aintr->intr->intin, 0, &lo);
826 if(!(lo & ApicIMASK)){
828 //print("%s vector %d (!imask)\n", v->name, vno);
829 n = mpintrinit(bus, aintr->intr, vno, v->irq);
830 n |= ApicPHYSICAL; /* no-op */
831 lo &= ~(ApicRemoteIRR|ApicDELIVS);
832 if(n != lo || !(n & ApicLEVEL)){
833 print("mpintrenable: multiple botch irq%d, tbdf %uX, lo %8.8uX, n %8.8uX\n",
834 v->irq, tbdf, lo, n);
845 * With the APIC a unique vector can be assigned to each
846 * request to enable an interrupt. There are two reasons this
848 * 1) to prevent lost interrupts, no more than 2 interrupts
849 * should be assigned per block of 16 vectors (there is an
850 * in-service entry and a holding entry for each priority
851 * level and there is one priority level per block of 16
853 * 2) each input pin on the IOAPIC will receive a different
854 * vector regardless of whether the devices on that pin use
855 * the same IRQ as devices on another pin.
858 hi = mpintrcpu()<<24;
859 lo = mpintrinit(bus, aintr->intr, vno, v->irq);
860 //print("lo 0x%uX: busno %d intr %d vno %d irq %d elcr 0x%uX\n",
861 // lo, bus->busno, aintr->intr->irq, vno,
862 // v->irq, i8259elcr);
866 lo |= ApicPHYSICAL; /* no-op */
868 if((apic->flags & PcmpEN) && apic->type == PcmpIOAPIC)
869 ioapicrdtw(apic, aintr->intr->intin, hi, lo);
871 // print("lo not enabled 0x%uX %d\n",
872 // apic->flags, apic->type);
884 MSICtrl = 0x02, /* message control register (16 bit) */
885 MSIAddr = 0x04, /* message address register (64 bit) */
886 MSIData32 = 0x08, /* message data register for 32 bit MSI (16 bit) */
887 MSIData64 = 0x0C, /* message data register for 64 bit MSI (16 bit) */
891 msiintrenable(Vctl *v)
893 int tbdf, vno, cap, cpu, ok64;
896 if(getconf("*msi") == nil)
899 if(tbdf == BUSUNKNOWN || BUSTYPE(tbdf) != BusPCI)
901 pci = pcimatchtbdf(tbdf);
903 print("msiintrenable: could not find Pcidev for tbdf %.8x\n", tbdf);
908 cap = pcinextcap(pci, cap);
911 if(pcicfgr8(pci, cap) == 0x05) /* MSI block */
917 ok64 = (pcicfgr16(pci, cap + MSICtrl) & (1<<7)) != 0;
918 pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
919 if(ok64) pcicfgw32(pci, cap + MSIAddr + 4, 0);
920 pcicfgw16(pci, cap + (ok64 ? MSIData64 : MSIData32), vno | (1<<14));
921 pcicfgw16(pci, cap + MSICtrl, 1);
922 print("msiintrenable: success with tbdf %.8x, vector %d, cpu %d\n", tbdf, vno, cpu);
929 mpintrenable(Vctl* v)
933 vno = msiintrenable(v);
938 * If the bus is known, try it.
939 * BUSUNKNOWN is given both by [E]ISA devices and by
940 * interrupts local to the processor (local APIC, coprocessor
941 * breakpoint and page-fault).
944 if(tbdf != BUSUNKNOWN && (vno = mpintrenablex(v, tbdf)) != -1)
948 if(irq >= IrqLINT0 && irq <= MaxIrqLAPIC){
949 if(irq != IrqSPURIOUS)
951 return VectorPIC+irq;
953 if(irq < 0 || irq > MaxIrqPIC){
954 print("mpintrenable: irq %d out of range\n", irq);
959 * Either didn't find it or have to try the default buses
960 * (ISA and EISA). This hack is due to either over-zealousness
961 * or laziness on the part of some manufacturers.
963 * The MP configuration table on some older systems
964 * (e.g. ASUS PCI/E-P54NP4) has an entry for the EISA bus
965 * but none for ISA. It also has the interrupt type and
966 * polarity set to 'default for this bus' which wouldn't
967 * be compatible with ISA.
970 vno = mpintrenablex(v, MKBUS(BusEISA, 0, 0, 0));
975 vno = mpintrenablex(v, MKBUS(BusISA, 0, 0, 0));
979 print("mpintrenable: out of choices eisa %d isa %d tbdf %#ux irq %d\n",
980 mpeisabus, mpisabus, v->tbdf, v->irq);
984 static Lock mpshutdownlock;
992 if(!canlock(&mpshutdownlock)){
994 * If this processor received the CTRL-ALT-DEL from
995 * the keyboard, acknowledge it. Send an INIT to self.
998 if(lapicisr(VectorKBD))
1000 #endif /* FIX THIS */
1005 print("apshutdown: active = %#8.8ux\n", active.machs);
1010 * INIT all excluding self.
1012 lapicicrw(0, 0x000C0000|ApicINIT);
1018 * Often the BIOS hangs during restart if a conventional 8042
1019 * warm-boot sequence is tried. The following is Intel specific and
1020 * seems to perform a cold-boot, but at least it comes back.
1021 * And sometimes there is no keyboard...
1023 * The reset register (0xcf9) is usually in one of the bridge
1024 * chips. The actual location and sequence could be extracted from
1025 * ACPI but why bother, this is the end of the line anyway.
1027 print("no kbd; trying bios warm boot...");
1028 *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
1032 print("can't reset\n");