4 #define PADDR(a) ((a) & ~KZERO)
5 #define KADDR(a) (KZERO|(a))
8 * Some machine instructions not handled by 8[al].
10 #define OP16 BYTE $0x66
11 #define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
12 #define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument in AX */
13 #define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
14 #define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
15 #define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) */
16 #define HLT BYTE $0xF4
17 #define INVLPG BYTE $0x0F; BYTE $0x01; BYTE $0x39 /* INVLPG (%ecx) */
18 #define WBINVD BYTE $0x0F; BYTE $0x09
21 * Macros for calculating offsets within the page directory base
22 * and page tables. Note that these are assembler-specific hence
25 #define PDO(a) (((((a))>>22) & 0x03FF)<<2)
26 #define PTO(a) (((((a))>>12) & 0x03FF)<<2)
29 * For backwards compatiblity with 9load - should go away when 9load is changed
30 * 9load currently sets up the mmu, however the first 16MB of memory is identity
31 * mapped, so behave as if the mmu was not setup
33 TEXT _startKADDR(SB), $0
34 MOVL $_startPADDR(SB), AX
39 * Must be 4-byte aligned.
41 TEXT _multibootheader(SB), $0
42 LONG $0x1BADB002 /* magic */
43 LONG $0x00010003 /* flags */
44 LONG $-(0x1BADB002 + 0x00010003) /* checksum */
45 LONG $_multibootheader-KZERO(SB) /* header_addr */
46 LONG $_startKADDR-KZERO(SB) /* load_addr */
47 LONG $edata-KZERO(SB) /* load_end_addr */
48 LONG $end-KZERO(SB) /* bss_end_addr */
49 LONG $_multibootentry-KZERO(SB) /* entry_addr */
50 LONG $0 /* mode_type */
56 * the kernel expects the data segment to be page-aligned
57 * multiboot bootloaders put the data segment right behind text
59 TEXT _multibootentry(SB), $0
60 MOVL $etext-KZERO(SB), SI
64 MOVL $edata-KZERO(SB), CX
72 MOVL BX, multiboot-KZERO(SB)
73 MOVL $_startPADDR(SB), AX
77 /* multiboot structure pointer */
78 TEXT multiboot(SB), $0
82 * In protected mode with paging turned off and segment registers setup
83 * to linear map all memory. Entered via a jump to PADDR(entry),
84 * the physical address of the virtual kernel entry point of KADDR(entry).
85 * Make the basic page tables for processor 0. Six pages are needed for
88 * page tables for mapping the first 8MB of physical memory to KZERO;
90 * virtual and physical pages for mapping the Mach structure.
91 * The remaining PTEs will be allocated later when memory is sized.
92 * An identity mmu map is also needed for the switch to virtual mode.
93 * This identity mapping is removed once the MMU is going and the JMP has
94 * been made to virtual memory.
96 TEXT _startPADDR(SB), $0
97 CLI /* make sure interrupts are off */
99 /* set up the gdt so we have sane plan 9 style gdts. */
100 MOVL $tgdtptr(SB), AX
106 /* clear prefetch queue (weird code to avoid optimizations) */
109 /* set segs to something sane (avoid traps later) */
117 /* JMP $(2<<3):$mode32bit(SB) /**/
119 LONG $mode32bit-KZERO(SB)
123 * gdt to get us to 32-bit/segmented/unpaged mode
127 /* null descriptor */
131 /* data segment descriptor for 4 gigabytes (PL 0) */
133 LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
135 /* exec segment descriptor for 4 gigabytes (PL 0) */
137 LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
140 * pointer to initial gdt
141 * Note the -KZERO which puts the physical address in the gdtptr.
142 * that's needed as we start executing in physical addresses.
148 TEXT m0rgdtptr(SB), $0
150 LONG $(CPU0GDT-KZERO)
152 TEXT m0gdtptr(SB), $0
156 TEXT m0idtptr(SB), $0
160 TEXT mode32bit(SB), $0
161 /* At this point, the GDT setup is done. */
163 MOVL $PADDR(CPU0PDB), DI /* clear 4 pages for the tables etc. */
171 MOVL $PADDR(CPU0PDB), AX
172 ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
173 MOVL $PADDR(CPU0PTE), (AX) /* PTE's for KZERO */
174 MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
178 MOVL $PADDR(CPU0PTE1), (AX) /* PTE's for KZERO+4MB */
179 MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
182 MOVL $PADDR(CPU0PTE), AX /* first page of page table */
183 MOVL $1024, CX /* 1024 pages in 4MB */
186 ADDL $(1<<PGSHIFT), BX
190 MOVL $PADDR(CPU0PTE1), AX /* second page of page table */
191 MOVL $1024, CX /* 1024 pages in 4MB */
194 ADDL $(1<<PGSHIFT), BX
198 MOVL $PADDR(CPU0PTE), AX
199 ADDL $PTO(MACHADDR), AX /* page table entry offset for MACHADDR */
200 MOVL $PADDR(CPU0MACH), (AX) /* PTE for Mach */
201 MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
205 * Now ready to use the new map. Make sure the processor options are what is wanted.
206 * It is necessary on some processors to immediately follow mode switching with a JMP instruction
207 * to clear the prefetch queues.
209 MOVL $PADDR(CPU0PDB), CX /* load address of page directory */
210 MOVL (PDO(KZERO))(CX), DX /* double-map KZERO at 0 */
211 MOVL DX, (PDO(0))(CX)
216 ORL $0x80010000, DX /* PG|WP */
217 ANDL $~0x6000000A, DX /* ~(CD|NW|TS|MP) */
219 MOVL $_startpg(SB), AX /* this is a virtual address */
220 MOVL DX, CR0 /* turn on paging */
221 JMP* AX /* jump to the virtual nirvana */
224 * Basic machine environment set, can clear BSS and create a stack.
225 * The stack starts at the top of the page containing the Mach structure.
226 * The x86 architecture forces the use of the same virtual address for
227 * each processor's Mach structure, so the global Mach pointer 'm' can
228 * be initialised here.
230 TEXT _startpg(SB), $0
231 MOVL $0, (PDO(0))(CX) /* undo double-map of KZERO at 0 */
232 MOVL CX, CR3 /* load and flush the mmu */
238 SUBL DI, CX /* end-edata bytes */
239 SHRL $2, CX /* end-edata doublewords */
242 REP; STOSL /* clear BSS */
245 MOVL SP, m(SB) /* initialise global Mach pointer */
246 MOVL $0, 0(SP) /* initialise m->machno */
249 ADDL $(MACHSIZE-4), SP /* initialise stack */
252 * Need to do one final thing to ensure a clean machine environment,
253 * clear the EFLAGS register, which can only be done once there is a stack.
262 * Park a processor. Should never fall through a return from main to here,
263 * should only be called by application processors when shutting down.
285 TEXT saveregs(SB), $0
306 XCHGL 32(SP), AX /* swap return PC and saved flags */
311 TEXT restoreregs(SB), $0
323 XCHGL 32(SP), AX /* swap return PC and saved flags */
340 TEXT bios32call(SB), $0
350 MOVL 12(SP), BP /* ptr */
351 BYTE $0xFF; BYTE $0x5D; BYTE $0x00 /* CALL FAR 0(BP) */
370 * in[bsl] input a byte|short|long
371 * ins[bsl] input a string of bytes|shorts|longs
372 * out[bsl] output a byte|short|long
373 * outs[bsl] output a string of bytes|shorts|longs
383 MOVL address+4(FP), DI
397 MOVL address+4(FP), DI
410 MOVL address+4(FP), DI
424 MOVL address+4(FP), SI
438 MOVL address+4(FP), SI
452 MOVL address+4(FP), SI
459 * Read/write various system registers.
460 * CR4 and the 'model specific registers' should only be read/written
461 * after it has been determined the processor supports them
463 TEXT lgdt(SB), $0 /* GDTR - global descriptor table */
464 MOVL gdtptr+0(FP), AX
468 TEXT lldt(SB), $0 /* LDTR - local descriptor table */
470 BYTE $0x0F; BYTE $0x00; BYTE $0xD0 /* LLDT AX */
473 TEXT lidt(SB), $0 /* IDTR - interrupt descriptor table */
474 MOVL idtptr+0(FP), AX
478 TEXT ltr(SB), $0 /* TR - task register */
483 TEXT getcr0(SB), $0 /* CR0 - processor control */
487 TEXT getcr2(SB), $0 /* CR2 - page fault linear address */
491 TEXT getcr3(SB), $0 /* CR3 - page directory base */
505 TEXT getcr4(SB), $0 /* CR4 - extensions */
524 TEXT _cycles(SB), $0 /* time stamp counter */
526 MOVL vlong+0(FP), CX /* &vlong */
527 MOVL AX, 0(CX) /* lo */
528 MOVL DX, 4(CX) /* hi */
533 * time stamp counter; low-order 32 bits of 64-bit cycle counter
534 * Runs at fasthz/4 cycles per second (m->clkin>>3)
536 TEXT lcycles(SB),1,$0
540 TEXT rdmsr(SB), $0 /* model-specific register */
543 TEXT _rdmsrinst(SB), $0
545 MOVL vlong+4(FP), CX /* &vlong */
546 MOVL AX, 0(CX) /* lo */
547 MOVL DX, 4(CX) /* hi */
548 MOVL BP, AX /* BP set to -1 if traped */
556 TEXT _wrmsrinst(SB), $0
558 MOVL BP, AX /* BP set to -1 if traped */
562 * Try to determine the CPU type which requires fiddling with EFLAGS.
563 * If the Id bit can be toggled then the CPUID instruction can be used
564 * to determine CPU identity and features. First have to check if it's
565 * a 386 (Ac bit can't be set). If it's not a 386 and the Id bit can't be
566 * toggled then it's an older 486 of some kind.
568 * cpuid(fun, regs[4]);
573 POPFL /* set Id|Ac */
575 POPL BX /* retrieve value */
578 POPFL /* clear Id|Ac, EFLAGS initialised */
580 POPL AX /* retrieve value */
582 TESTL $0x040000, AX /* Ac */
583 JZ _cpu386 /* can't set this bit on 386 */
584 TESTL $0x200000, AX /* Id */
585 JZ _cpu486 /* can't toggle this bit on some 486 */
611 * Basic timing loop to determine CPU frequency.
622 * Note: the encodings for the FCLEX, FINIT, FSAVE, FSTCW, FSENV and FSTSW
623 * instructions do NOT have the WAIT prefix byte (i.e. they act like their
624 * FNxxx variations) so WAIT instructions must be explicitly placed in the
629 ANDL $0xC, AX /* EM, TS */ ;\
635 ANDL $~0x4, AX /* EM=0 */ ;\
636 ORL $0x28, AX /* NE=1, TS=1 */ ;\
641 ANDL $~0xC, AX /* EM=0, TS=0 */ ;\
644 TEXT fpoff(SB), $0 /* disable */
648 TEXT fpinit(SB), $0 /* enable and init */
652 /* setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL) */
653 /* note that low 6 bits are masks, not enables, on this chip */
660 TEXT fpsave(SB), $0 /* save state and disable */
662 FSAVE 0(AX) /* no WAIT */
666 TEXT fprestore(SB), $0 /* enable and restore state */
673 TEXT fpstatus(SB), $0 /* get floating point status */
677 TEXT fpenv(SB), $0 /* save state without waiting */
682 TEXT fpclear(SB), $0 /* clear pending exceptions */
696 MOVL $(MACHADDR+0x04), CX /* save PC in m->splpc */
709 MOVL $(MACHADDR+0x04), CX /* clear m->splpc */
727 ANDL $0x200, AX /* interrupt enable flag */
736 XCHGL AX, (BX) /* lock->key */
739 TEXT _xinc(SB), $0 /* void _xinc(long*); */
744 TEXT _xdec(SB), $0 /* long _xdec(long*); */
759 POPL AX /* return PC */
794 TEXT cmpswap486(SB), $0
799 BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
807 TEXT mul64fract(SB), $0
809 * Multiply two 64-bit number s and keep the middle 64 bits from the 128-bit result
810 * See ../port/tod.c for motivation.
813 XORL BX, BX /* BX = 0 */
816 MULL b+16(FP) /* a1*b1 */
817 MOVL AX, 4(CX) /* r2 = lo(a1*b1) */
820 MULL b+12(FP) /* a1*b0 */
821 MOVL AX, 0(CX) /* r1 = lo(a1*b0) */
822 ADDL DX, 4(CX) /* r2 += hi(a1*b0) */
825 MULL b+16(FP) /* a0*b1 */
826 ADDL AX, 0(CX) /* r1 += lo(a0*b1) */
827 ADCL DX, 4(CX) /* r2 += hi(a0*b1) + carry */
830 MULL b+12(FP) /* a0*b0 */
831 ADDL DX, 0(CX) /* r1 += hi(a0*b0) */
832 ADCL BX, 4(CX) /* r2 += carry */
836 * label consists of a stack pointer and a PC
838 TEXT gotolabel(SB), $0
840 MOVL 0(AX), SP /* restore sp */
841 MOVL 4(AX), AX /* put return pc on the stack */
843 MOVL $1, AX /* return 1 */
846 TEXT setlabel(SB), $0
848 MOVL SP, 0(AX) /* store sp */
849 MOVL 0(SP), BX /* store return pc */
851 MOVL $0, AX /* return 0 */
855 * Attempt at power saving. -rsc
875 BYTE $0x0f; BYTE $0x01; BYTE $0xc8 /* MONITOR */
880 BYTE $0x0f; BYTE $0x01; BYTE $0xc9 /* MWAIT */
885 * Interrupt/exception handling.
886 * Each entry in the vector table calls either _strayintr or _strayintrx depending
887 * on whether an error code has been automatically pushed onto the stack
888 * (_strayintrx) or not, in which case a dummy entry must be pushed before retrieving
889 * the trap type from the vector table entry and placing it on the stack as part
890 * of the Ureg structure.
891 * The size of each entry in the vector table (6 bytes) is known in trapinit().
893 TEXT _strayintr(SB), $0
894 PUSHL AX /* save AX */
895 MOVL 4(SP), AX /* return PC from vectortable(SB) */
898 TEXT _strayintrx(SB), $0
899 XCHGL AX, (SP) /* swap AX with vectortable CALL PC */
901 PUSHL DS /* save DS */
903 POPL DS /* fix up DS */
904 MOVBLZX (AX), AX /* trap type -> AX */
905 XCHGL AX, 4(SP) /* exchange trap type with saved AX */
907 PUSHL ES /* save ES */
909 POPL ES /* fix up ES */
911 PUSHL FS /* save the rest of the Ureg struct */
915 PUSHL SP /* Ureg* argument to trap */
921 TEXT _forkretpopgs(SB), $0
923 TEXT _forkretpopfs(SB), $0
925 TEXT _forkretpopes(SB), $0
927 TEXT _forkretpopds(SB), $0
929 ADDL $8, SP /* pop error code and trap type */
930 TEXT _forkretiret(SB), $0
933 TEXT vectortable(SB), $0
934 CALL _strayintr(SB); BYTE $0x00 /* divide error */
935 CALL _strayintr(SB); BYTE $0x01 /* debug exception */
936 CALL _strayintr(SB); BYTE $0x02 /* NMI interrupt */
937 CALL _strayintr(SB); BYTE $0x03 /* breakpoint */
938 CALL _strayintr(SB); BYTE $0x04 /* overflow */
939 CALL _strayintr(SB); BYTE $0x05 /* bound */
940 CALL _strayintr(SB); BYTE $0x06 /* invalid opcode */
941 CALL _strayintr(SB); BYTE $0x07 /* no coprocessor available */
942 CALL _strayintrx(SB); BYTE $0x08 /* double fault */
943 CALL _strayintr(SB); BYTE $0x09 /* coprocessor segment overflow */
944 CALL _strayintrx(SB); BYTE $0x0A /* invalid TSS */
945 CALL _strayintrx(SB); BYTE $0x0B /* segment not available */
946 CALL _strayintrx(SB); BYTE $0x0C /* stack exception */
947 CALL _strayintrx(SB); BYTE $0x0D /* general protection error */
948 CALL _strayintrx(SB); BYTE $0x0E /* page fault */
949 CALL _strayintr(SB); BYTE $0x0F /* */
950 CALL _strayintr(SB); BYTE $0x10 /* coprocessor error */
951 CALL _strayintrx(SB); BYTE $0x11 /* alignment check */
952 CALL _strayintr(SB); BYTE $0x12 /* machine check */
953 CALL _strayintr(SB); BYTE $0x13
954 CALL _strayintr(SB); BYTE $0x14
955 CALL _strayintr(SB); BYTE $0x15
956 CALL _strayintr(SB); BYTE $0x16
957 CALL _strayintr(SB); BYTE $0x17
958 CALL _strayintr(SB); BYTE $0x18
959 CALL _strayintr(SB); BYTE $0x19
960 CALL _strayintr(SB); BYTE $0x1A
961 CALL _strayintr(SB); BYTE $0x1B
962 CALL _strayintr(SB); BYTE $0x1C
963 CALL _strayintr(SB); BYTE $0x1D
964 CALL _strayintr(SB); BYTE $0x1E
965 CALL _strayintr(SB); BYTE $0x1F
966 CALL _strayintr(SB); BYTE $0x20 /* VectorLAPIC */
967 CALL _strayintr(SB); BYTE $0x21
968 CALL _strayintr(SB); BYTE $0x22
969 CALL _strayintr(SB); BYTE $0x23
970 CALL _strayintr(SB); BYTE $0x24
971 CALL _strayintr(SB); BYTE $0x25
972 CALL _strayintr(SB); BYTE $0x26
973 CALL _strayintr(SB); BYTE $0x27
974 CALL _strayintr(SB); BYTE $0x28
975 CALL _strayintr(SB); BYTE $0x29
976 CALL _strayintr(SB); BYTE $0x2A
977 CALL _strayintr(SB); BYTE $0x2B
978 CALL _strayintr(SB); BYTE $0x2C
979 CALL _strayintr(SB); BYTE $0x2D
980 CALL _strayintr(SB); BYTE $0x2E
981 CALL _strayintr(SB); BYTE $0x2F
982 CALL _strayintr(SB); BYTE $0x30
983 CALL _strayintr(SB); BYTE $0x31
984 CALL _strayintr(SB); BYTE $0x32
985 CALL _strayintr(SB); BYTE $0x33
986 CALL _strayintr(SB); BYTE $0x34
987 CALL _strayintr(SB); BYTE $0x35
988 CALL _strayintr(SB); BYTE $0x36
989 CALL _strayintr(SB); BYTE $0x37
990 CALL _strayintr(SB); BYTE $0x38
991 CALL _strayintr(SB); BYTE $0x39
992 CALL _strayintr(SB); BYTE $0x3A
993 CALL _strayintr(SB); BYTE $0x3B
994 CALL _strayintr(SB); BYTE $0x3C
995 CALL _strayintr(SB); BYTE $0x3D
996 CALL _strayintr(SB); BYTE $0x3E
997 CALL _strayintr(SB); BYTE $0x3F
998 CALL _syscallintr(SB); BYTE $0x40 /* VectorSYSCALL */
999 CALL _strayintr(SB); BYTE $0x41
1000 CALL _strayintr(SB); BYTE $0x42
1001 CALL _strayintr(SB); BYTE $0x43
1002 CALL _strayintr(SB); BYTE $0x44
1003 CALL _strayintr(SB); BYTE $0x45
1004 CALL _strayintr(SB); BYTE $0x46
1005 CALL _strayintr(SB); BYTE $0x47
1006 CALL _strayintr(SB); BYTE $0x48
1007 CALL _strayintr(SB); BYTE $0x49
1008 CALL _strayintr(SB); BYTE $0x4A
1009 CALL _strayintr(SB); BYTE $0x4B
1010 CALL _strayintr(SB); BYTE $0x4C
1011 CALL _strayintr(SB); BYTE $0x4D
1012 CALL _strayintr(SB); BYTE $0x4E
1013 CALL _strayintr(SB); BYTE $0x4F
1014 CALL _strayintr(SB); BYTE $0x50
1015 CALL _strayintr(SB); BYTE $0x51
1016 CALL _strayintr(SB); BYTE $0x52
1017 CALL _strayintr(SB); BYTE $0x53
1018 CALL _strayintr(SB); BYTE $0x54
1019 CALL _strayintr(SB); BYTE $0x55
1020 CALL _strayintr(SB); BYTE $0x56
1021 CALL _strayintr(SB); BYTE $0x57
1022 CALL _strayintr(SB); BYTE $0x58
1023 CALL _strayintr(SB); BYTE $0x59
1024 CALL _strayintr(SB); BYTE $0x5A
1025 CALL _strayintr(SB); BYTE $0x5B
1026 CALL _strayintr(SB); BYTE $0x5C
1027 CALL _strayintr(SB); BYTE $0x5D
1028 CALL _strayintr(SB); BYTE $0x5E
1029 CALL _strayintr(SB); BYTE $0x5F
1030 CALL _strayintr(SB); BYTE $0x60
1031 CALL _strayintr(SB); BYTE $0x61
1032 CALL _strayintr(SB); BYTE $0x62
1033 CALL _strayintr(SB); BYTE $0x63
1034 CALL _strayintr(SB); BYTE $0x64
1035 CALL _strayintr(SB); BYTE $0x65
1036 CALL _strayintr(SB); BYTE $0x66
1037 CALL _strayintr(SB); BYTE $0x67
1038 CALL _strayintr(SB); BYTE $0x68
1039 CALL _strayintr(SB); BYTE $0x69
1040 CALL _strayintr(SB); BYTE $0x6A
1041 CALL _strayintr(SB); BYTE $0x6B
1042 CALL _strayintr(SB); BYTE $0x6C
1043 CALL _strayintr(SB); BYTE $0x6D
1044 CALL _strayintr(SB); BYTE $0x6E
1045 CALL _strayintr(SB); BYTE $0x6F
1046 CALL _strayintr(SB); BYTE $0x70
1047 CALL _strayintr(SB); BYTE $0x71
1048 CALL _strayintr(SB); BYTE $0x72
1049 CALL _strayintr(SB); BYTE $0x73
1050 CALL _strayintr(SB); BYTE $0x74
1051 CALL _strayintr(SB); BYTE $0x75
1052 CALL _strayintr(SB); BYTE $0x76
1053 CALL _strayintr(SB); BYTE $0x77
1054 CALL _strayintr(SB); BYTE $0x78
1055 CALL _strayintr(SB); BYTE $0x79
1056 CALL _strayintr(SB); BYTE $0x7A
1057 CALL _strayintr(SB); BYTE $0x7B
1058 CALL _strayintr(SB); BYTE $0x7C
1059 CALL _strayintr(SB); BYTE $0x7D
1060 CALL _strayintr(SB); BYTE $0x7E
1061 CALL _strayintr(SB); BYTE $0x7F
1062 CALL _strayintr(SB); BYTE $0x80 /* Vector[A]PIC */
1063 CALL _strayintr(SB); BYTE $0x81
1064 CALL _strayintr(SB); BYTE $0x82
1065 CALL _strayintr(SB); BYTE $0x83
1066 CALL _strayintr(SB); BYTE $0x84
1067 CALL _strayintr(SB); BYTE $0x85
1068 CALL _strayintr(SB); BYTE $0x86
1069 CALL _strayintr(SB); BYTE $0x87
1070 CALL _strayintr(SB); BYTE $0x88
1071 CALL _strayintr(SB); BYTE $0x89
1072 CALL _strayintr(SB); BYTE $0x8A
1073 CALL _strayintr(SB); BYTE $0x8B
1074 CALL _strayintr(SB); BYTE $0x8C
1075 CALL _strayintr(SB); BYTE $0x8D
1076 CALL _strayintr(SB); BYTE $0x8E
1077 CALL _strayintr(SB); BYTE $0x8F
1078 CALL _strayintr(SB); BYTE $0x90
1079 CALL _strayintr(SB); BYTE $0x91
1080 CALL _strayintr(SB); BYTE $0x92
1081 CALL _strayintr(SB); BYTE $0x93
1082 CALL _strayintr(SB); BYTE $0x94
1083 CALL _strayintr(SB); BYTE $0x95
1084 CALL _strayintr(SB); BYTE $0x96
1085 CALL _strayintr(SB); BYTE $0x97
1086 CALL _strayintr(SB); BYTE $0x98
1087 CALL _strayintr(SB); BYTE $0x99
1088 CALL _strayintr(SB); BYTE $0x9A
1089 CALL _strayintr(SB); BYTE $0x9B
1090 CALL _strayintr(SB); BYTE $0x9C
1091 CALL _strayintr(SB); BYTE $0x9D
1092 CALL _strayintr(SB); BYTE $0x9E
1093 CALL _strayintr(SB); BYTE $0x9F
1094 CALL _strayintr(SB); BYTE $0xA0
1095 CALL _strayintr(SB); BYTE $0xA1
1096 CALL _strayintr(SB); BYTE $0xA2
1097 CALL _strayintr(SB); BYTE $0xA3
1098 CALL _strayintr(SB); BYTE $0xA4
1099 CALL _strayintr(SB); BYTE $0xA5
1100 CALL _strayintr(SB); BYTE $0xA6
1101 CALL _strayintr(SB); BYTE $0xA7
1102 CALL _strayintr(SB); BYTE $0xA8
1103 CALL _strayintr(SB); BYTE $0xA9
1104 CALL _strayintr(SB); BYTE $0xAA
1105 CALL _strayintr(SB); BYTE $0xAB
1106 CALL _strayintr(SB); BYTE $0xAC
1107 CALL _strayintr(SB); BYTE $0xAD
1108 CALL _strayintr(SB); BYTE $0xAE
1109 CALL _strayintr(SB); BYTE $0xAF
1110 CALL _strayintr(SB); BYTE $0xB0
1111 CALL _strayintr(SB); BYTE $0xB1
1112 CALL _strayintr(SB); BYTE $0xB2
1113 CALL _strayintr(SB); BYTE $0xB3
1114 CALL _strayintr(SB); BYTE $0xB4
1115 CALL _strayintr(SB); BYTE $0xB5
1116 CALL _strayintr(SB); BYTE $0xB6
1117 CALL _strayintr(SB); BYTE $0xB7
1118 CALL _strayintr(SB); BYTE $0xB8
1119 CALL _strayintr(SB); BYTE $0xB9
1120 CALL _strayintr(SB); BYTE $0xBA
1121 CALL _strayintr(SB); BYTE $0xBB
1122 CALL _strayintr(SB); BYTE $0xBC
1123 CALL _strayintr(SB); BYTE $0xBD
1124 CALL _strayintr(SB); BYTE $0xBE
1125 CALL _strayintr(SB); BYTE $0xBF
1126 CALL _strayintr(SB); BYTE $0xC0
1127 CALL _strayintr(SB); BYTE $0xC1
1128 CALL _strayintr(SB); BYTE $0xC2
1129 CALL _strayintr(SB); BYTE $0xC3
1130 CALL _strayintr(SB); BYTE $0xC4
1131 CALL _strayintr(SB); BYTE $0xC5
1132 CALL _strayintr(SB); BYTE $0xC6
1133 CALL _strayintr(SB); BYTE $0xC7
1134 CALL _strayintr(SB); BYTE $0xC8
1135 CALL _strayintr(SB); BYTE $0xC9
1136 CALL _strayintr(SB); BYTE $0xCA
1137 CALL _strayintr(SB); BYTE $0xCB
1138 CALL _strayintr(SB); BYTE $0xCC
1139 CALL _strayintr(SB); BYTE $0xCD
1140 CALL _strayintr(SB); BYTE $0xCE
1141 CALL _strayintr(SB); BYTE $0xCF
1142 CALL _strayintr(SB); BYTE $0xD0
1143 CALL _strayintr(SB); BYTE $0xD1
1144 CALL _strayintr(SB); BYTE $0xD2
1145 CALL _strayintr(SB); BYTE $0xD3
1146 CALL _strayintr(SB); BYTE $0xD4
1147 CALL _strayintr(SB); BYTE $0xD5
1148 CALL _strayintr(SB); BYTE $0xD6
1149 CALL _strayintr(SB); BYTE $0xD7
1150 CALL _strayintr(SB); BYTE $0xD8
1151 CALL _strayintr(SB); BYTE $0xD9
1152 CALL _strayintr(SB); BYTE $0xDA
1153 CALL _strayintr(SB); BYTE $0xDB
1154 CALL _strayintr(SB); BYTE $0xDC
1155 CALL _strayintr(SB); BYTE $0xDD
1156 CALL _strayintr(SB); BYTE $0xDE
1157 CALL _strayintr(SB); BYTE $0xDF
1158 CALL _strayintr(SB); BYTE $0xE0
1159 CALL _strayintr(SB); BYTE $0xE1
1160 CALL _strayintr(SB); BYTE $0xE2
1161 CALL _strayintr(SB); BYTE $0xE3
1162 CALL _strayintr(SB); BYTE $0xE4
1163 CALL _strayintr(SB); BYTE $0xE5
1164 CALL _strayintr(SB); BYTE $0xE6
1165 CALL _strayintr(SB); BYTE $0xE7
1166 CALL _strayintr(SB); BYTE $0xE8
1167 CALL _strayintr(SB); BYTE $0xE9
1168 CALL _strayintr(SB); BYTE $0xEA
1169 CALL _strayintr(SB); BYTE $0xEB
1170 CALL _strayintr(SB); BYTE $0xEC
1171 CALL _strayintr(SB); BYTE $0xED
1172 CALL _strayintr(SB); BYTE $0xEE
1173 CALL _strayintr(SB); BYTE $0xEF
1174 CALL _strayintr(SB); BYTE $0xF0
1175 CALL _strayintr(SB); BYTE $0xF1
1176 CALL _strayintr(SB); BYTE $0xF2
1177 CALL _strayintr(SB); BYTE $0xF3
1178 CALL _strayintr(SB); BYTE $0xF4
1179 CALL _strayintr(SB); BYTE $0xF5
1180 CALL _strayintr(SB); BYTE $0xF6
1181 CALL _strayintr(SB); BYTE $0xF7
1182 CALL _strayintr(SB); BYTE $0xF8
1183 CALL _strayintr(SB); BYTE $0xF9
1184 CALL _strayintr(SB); BYTE $0xFA
1185 CALL _strayintr(SB); BYTE $0xFB
1186 CALL _strayintr(SB); BYTE $0xFC
1187 CALL _strayintr(SB); BYTE $0xFD
1188 CALL _strayintr(SB); BYTE $0xFE
1189 CALL _strayintr(SB); BYTE $0xFF