4 #define PADDR(a) ((a) & ~KZERO)
5 #define KADDR(a) (KZERO|(a))
8 * Some machine instructions not handled by 8[al].
10 #define OP16 BYTE $0x66
11 #define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
12 #define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument in AX */
13 #define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
14 #define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
15 #define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) */
16 #define HLT BYTE $0xF4
17 #define INVLPG BYTE $0x0F; BYTE $0x01; BYTE $0x39 /* INVLPG (%ecx) */
18 #define WBINVD BYTE $0x0F; BYTE $0x09
20 #define VectorSYSCALL 0x40
23 * Macros for calculating offsets within the page directory base
24 * and page tables. Note that these are assembler-specific hence
27 #define PDO(a) (((((a))>>22) & 0x03FF)<<2)
28 #define PTO(a) (((((a))>>12) & 0x03FF)<<2)
31 * For backwards compatiblity with 9load - should go away when 9load is changed
32 * 9load currently sets up the mmu, however the first 16MB of memory is identity
33 * mapped, so behave as if the mmu was not setup
35 TEXT _startKADDR(SB), $0
36 MOVL $_startPADDR(SB), AX
41 * Must be 4-byte aligned.
43 TEXT _multibootheader(SB), $0
44 LONG $0x1BADB002 /* magic */
45 LONG $0x00010007 /* flags */
46 LONG $-(0x1BADB002 + 0x00010007) /* checksum */
47 LONG $_multibootheader-KZERO(SB) /* header_addr */
48 LONG $_startKADDR-KZERO(SB) /* load_addr */
49 LONG $edata-KZERO(SB) /* load_end_addr */
50 LONG $end-KZERO(SB) /* bss_end_addr */
51 LONG $_multibootentry-KZERO(SB) /* entry_addr */
52 LONG $0 /* mode_type */
58 * the kernel expects the data segment to be page-aligned
59 * multiboot bootloaders put the data segment right behind text
61 TEXT _multibootentry(SB), $0
62 MOVL $etext-KZERO(SB), SI
66 MOVL $edata-KZERO(SB), CX
70 INCL CX /* one more for post decrement */
73 MOVL BX, multibootptr-KZERO(SB)
74 MOVL $_startPADDR-KZERO(SB), AX
77 /* multiboot structure pointer (physical address) */
78 TEXT multibootptr(SB), $0
82 * In protected mode with paging turned off and segment registers setup
83 * to linear map all memory. Entered via a jump to PADDR(entry),
84 * the physical address of the virtual kernel entry point of KADDR(entry).
85 * Make the basic page tables for processor 0. Six pages are needed for
88 * page tables for mapping the first 8MB of physical memory to KZERO;
90 * virtual and physical pages for mapping the Mach structure.
91 * The remaining PTEs will be allocated later when memory is sized.
92 * An identity mmu map is also needed for the switch to virtual mode.
93 * This identity mapping is removed once the MMU is going and the JMP has
94 * been made to virtual memory.
96 TEXT _startPADDR(SB), $0
97 CLI /* make sure interrupts are off */
99 /* set up the gdt so we have sane plan 9 style gdts. */
100 MOVL $tgdtptr-KZERO(SB), AX
105 /* clear prefetch queue (weird code to avoid optimizations) */
108 /* set segs to something sane (avoid traps later) */
116 /* JMP $(2<<3):$mode32bit(SB) /**/
118 LONG $mode32bit-KZERO(SB)
122 * gdt to get us to 32-bit/segmented/unpaged mode
126 /* null descriptor */
130 /* data segment descriptor for 4 gigabytes (PL 0) */
132 LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
134 /* exec segment descriptor for 4 gigabytes (PL 0) */
136 LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
139 * pointer to initial gdt
140 * Note the -KZERO which puts the physical address in the gdtptr.
141 * that's needed as we start executing in physical addresses.
147 TEXT m0rgdtptr(SB), $0
149 LONG $(CPU0GDT-KZERO)
151 TEXT m0gdtptr(SB), $0
155 TEXT m0idtptr(SB), $0
159 TEXT vtgdtptr(SB), $0
163 TEXT mode32bit(SB), $0
164 MOVL $((CPU0END-CPU0PDB)>>2), CX
165 MOVL $PADDR(CPU0PDB), DI
171 MOVL $PADDR(CPU0PTE), DX
172 MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
175 MOVL $PADDR(CPU0PDB), AX
176 ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
178 MOVL DX, 0(AX) /* PTE's for KZERO */
180 MOVL DX, 4(AX) /* PTE's for KZERO+4MB */
182 MOVL DX, 8(AX) /* PTE's for KZERO+8MB */
184 MOVL DX, 12(AX) /* PTE's for KZERO+12MB */
186 MOVL $PADDR(CPU0PTE), AX /* first page of page table */
187 MOVL $end-KZERO(SB), CX
189 ADDL $(16*1024), CX /* qemu puts multiboot data after the kernel */
192 ANDL $~(BY2XPG-1), CX /* round to 4MB */
193 MOVL CX, MemMin-KZERO(SB) /* see memory.c */
202 MOVL $PADDR(CPU0PTE), AX
203 ADDL $PTO(MACHADDR), AX /* page table entry offset for MACHADDR */
204 ORL $PADDR(CPU0MACH), BX
205 MOVL BX, (AX) /* PTE for Mach */
208 * Now ready to use the new map. Make sure the processor options are what is wanted.
209 * It is necessary on some processors to immediately follow mode switching with a JMP instruction
210 * to clear the prefetch queues.
212 MOVL $PADDR(CPU0PDB), CX /* load address of page directory */
213 MOVL (PDO(KZERO))(CX), DX /* double-map KZERO at 0 */
214 MOVL DX, (PDO(0))(CX)
219 ORL $0x80010000, DX /* PG|WP */
220 ANDL $~0x6000000A, DX /* ~(CD|NW|TS|MP) */
222 MOVL $_startpg(SB), AX /* this is a virtual address */
223 MOVL DX, CR0 /* turn on paging */
224 JMP* AX /* jump to the virtual nirvana */
227 * Basic machine environment set, can clear BSS and create a stack.
228 * The stack starts at the top of the page containing the Mach structure.
229 * The x86 architecture forces the use of the same virtual address for
230 * each processor's Mach structure, so the global Mach pointer 'm' can
231 * be initialised here.
233 TEXT _startpg(SB), $0
234 MOVL $vtgdtptr(SB), AX
237 MOVL $0, (PDO(0))(CX) /* undo double-map of KZERO at 0 */
238 MOVL CX, CR3 /* load and flush the mmu */
244 SUBL DI, CX /* end-edata bytes */
245 SHRL $2, CX /* end-edata doublewords */
248 REP; STOSL /* clear BSS */
251 MOVL SP, m(SB) /* initialise global Mach pointer */
252 MOVL $0, 0(SP) /* initialise m->machno */
255 ADDL $(MACHSIZE-4), SP /* initialise stack */
258 * Need to do one final thing to ensure a clean machine environment,
259 * clear the EFLAGS register, which can only be done once there is a stack.
268 * Park a processor. Should never fall through a return from main to here,
269 * should only be called by application processors when shutting down.
291 TEXT bios32call(SB), $0
301 MOVL 12(SP), BP /* ptr */
302 BYTE $0xFF; BYTE $0x5D; BYTE $0x00 /* CALL FAR 0(BP) */
321 * in[bsl] input a byte|short|long
322 * ins[bsl] input a string of bytes|shorts|longs
323 * out[bsl] output a byte|short|long
324 * outs[bsl] output a string of bytes|shorts|longs
334 MOVL address+4(FP), DI
348 MOVL address+4(FP), DI
361 MOVL address+4(FP), DI
375 MOVL address+4(FP), SI
389 MOVL address+4(FP), SI
403 MOVL address+4(FP), SI
410 * Read/write various system registers.
411 * CR4 and the 'model specific registers' should only be read/written
412 * after it has been determined the processor supports them
414 TEXT lgdt(SB), $0 /* GDTR - global descriptor table */
415 MOVL gdtptr+0(FP), AX
419 TEXT lldt(SB), $0 /* LDTR - local descriptor table */
421 BYTE $0x0F; BYTE $0x00; BYTE $0xD0 /* LLDT AX */
424 TEXT lidt(SB), $0 /* IDTR - interrupt descriptor table */
425 MOVL idtptr+0(FP), AX
429 TEXT ltr(SB), $0 /* TR - task register */
434 TEXT getcr0(SB), $0 /* CR0 - processor control */
438 TEXT getcr2(SB), $0 /* CR2 - page fault linear address */
447 TEXT getcr3(SB), $0 /* CR3 - page directory base */
461 TEXT getcr4(SB), $0 /* CR4 - extensions */
480 TEXT _cycles(SB), $0 /* time stamp counter */
482 MOVL vlong+0(FP), CX /* &vlong */
483 MOVL AX, 0(CX) /* lo */
484 MOVL DX, 4(CX) /* hi */
489 * time stamp counter; low-order 32 bits of 64-bit cycle counter
490 * Runs at fasthz/4 cycles per second (m->clkin>>3)
492 TEXT lcycles(SB),1,$0
496 TEXT rdmsr(SB), $0 /* model-specific register */
499 TEXT _rdmsrinst(SB), $0
501 MOVL vlong+4(FP), CX /* &vlong */
502 MOVL AX, 0(CX) /* lo */
503 MOVL DX, 4(CX) /* hi */
504 MOVL BP, AX /* BP set to -1 if traped */
512 TEXT _wrmsrinst(SB), $0
514 MOVL BP, AX /* BP set to -1 if traped */
517 /* fault-proof memcpy */
523 TEXT _peekinst(SB), $0
529 * Try to determine the CPU type which requires fiddling with EFLAGS.
530 * If the Id bit can be toggled then the CPUID instruction can be used
531 * to determine CPU identity and features. First have to check if it's
532 * a 386 (Ac bit can't be set). If it's not a 386 and the Id bit can't be
533 * toggled then it's an older 486 of some kind.
535 * cpuid(fun, regs[4]);
540 POPFL /* set Id|Ac */
542 POPL BX /* retrieve value */
545 POPFL /* clear Id|Ac, EFLAGS initialised */
547 POPL AX /* retrieve value */
549 TESTL $0x040000, AX /* Ac */
550 JZ _cpu386 /* can't set this bit on 386 */
551 TESTL $0x200000, AX /* Id */
552 JZ _cpu486 /* can't toggle this bit on some 486 */
578 * Basic timing loop to determine CPU frequency.
589 * Note: the encodings for the FCLEX, FINIT, FSAVE, FSTCW, FSENV and FSTSW
590 * instructions do NOT have the WAIT prefix byte (i.e. they act like their
591 * FNxxx variations) so WAIT instructions must be explicitly placed in the
596 ORL $0x28, AX /* NE=1, TS=1 */ ;\
601 ANDL $~0xC, AX /* EM=0, TS=0 */ ;\
604 TEXT fpoff(SB), $0 /* disable */
608 TEXT fpinit(SB), $0 /* enable and init */
612 /* setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL) */
613 /* note that low 6 bits are masks, not enables, on this chip */
620 TEXT fpx87save0(SB), $0 /* save state and disable */
622 FSAVE 0(AX) /* no WAIT */
626 TEXT fpx87restore0(SB), $0 /* enable and restore state */
633 TEXT fpclear(SB), $0 /* clear pending exceptions */
639 TEXT fpssesave(SB), $0 /* save state and disable */
641 FXSAVE 0(AX) /* no WAIT */
645 TEXT fpsserestore(SB), $0 /* enable and restore state */
652 TEXT ldmxcsr(SB), $0 /* Load MXCSR */
664 MOVL $(MACHADDR+0x04), CX /* save PC in m->splpc */
677 MOVL $(MACHADDR+0x04), CX /* clear m->splpc */
695 ANDL $0x200, AX /* interrupt enable flag */
705 XCHGL AX, (BX) /* lock->key */
709 POPL AX /* return PC */
744 TEXT cmpswap486(SB), $0
749 BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
757 TEXT mul64fract(SB), $0
759 * Multiply two 64-bit number s and keep the middle 64 bits from the 128-bit result
760 * See ../port/tod.c for motivation.
763 XORL BX, BX /* BX = 0 */
766 MULL b+16(FP) /* a1*b1 */
767 MOVL AX, 4(CX) /* r2 = lo(a1*b1) */
770 MULL b+12(FP) /* a1*b0 */
771 MOVL AX, 0(CX) /* r1 = lo(a1*b0) */
772 ADDL DX, 4(CX) /* r2 += hi(a1*b0) */
775 MULL b+16(FP) /* a0*b1 */
776 ADDL AX, 0(CX) /* r1 += lo(a0*b1) */
777 ADCL DX, 4(CX) /* r2 += hi(a0*b1) + carry */
780 MULL b+12(FP) /* a0*b0 */
781 ADDL DX, 0(CX) /* r1 += hi(a0*b0) */
782 ADCL BX, 4(CX) /* r2 += carry */
786 * label consists of a stack pointer and a PC
788 TEXT gotolabel(SB), $0
790 MOVL 0(AX), SP /* restore sp */
791 MOVL 4(AX), AX /* put return pc on the stack */
793 MOVL $1, AX /* return 1 */
796 TEXT setlabel(SB), $0
798 MOVL SP, 0(AX) /* store sp */
799 MOVL 0(SP), BX /* store return pc */
801 MOVL $0, AX /* return 0 */
805 * Attempt at power saving. -rsc
825 BYTE $0x0f; BYTE $0x01; BYTE $0xc8 /* MONITOR */
830 BYTE $0x0f; BYTE $0x01; BYTE $0xc9 /* MWAIT */
834 #define RDRANDAX BYTE $0x0f; BYTE $0xc7; BYTE $0xf0
836 TEXT rdrand32(SB), $-4
842 TEXT rdrandbuf(SB), $0
866 /* debug register access */
885 TEXT putdr01236(SB), $0
903 /* VMX instructions */
906 BYTE $0xf3; BYTE $0x0f; BYTE $0xc7; BYTE $0x74; BYTE $0x24; BYTE $0x04
910 BYTE $0x0f; BYTE $0x01; BYTE $0xc4
915 BYTE $0x66; BYTE $0x0f; BYTE $0xc7; BYTE $0x74; BYTE $0x24; BYTE $0x04
918 TEXT vmlaunch(SB), $0
921 BYTE $0x0f; BYTE $0x79; BYTE $0xfa /* VMWRITE DX, DI */
924 MOVL $vmrestore(SB), DX
925 BYTE $0x0f; BYTE $0x79; BYTE $0xfa /* VMWRITE DX, DI */
928 MOVL resume+4(FP), AX
939 BYTE $0x0f; BYTE $0x01; BYTE $0xc2 /* VMLAUNCH */
942 BYTE $0x0f; BYTE $0x01; BYTE $0xc3 /* VMRESUME */
945 TEXT vmrestore(SB), $0
960 BYTE $0x0f; BYTE $0xc7; BYTE $0x74; BYTE $0x24; BYTE $0x04
967 BYTE $0x0f; BYTE $0x79; BYTE $0xfa
973 /* VMREAD (SI), DI */
974 BYTE $0x0f; BYTE $0x78; BYTE $0x3e
979 /* INVEPT AX, 8(SP) */
980 BYTE $0x66; BYTE $0x0f; BYTE $0x38; BYTE $0x80; BYTE $0x44; BYTE $0x24; BYTE $0x08
985 /* INVVPID AX, 8(SP) */
986 BYTE $0x66; BYTE $0x0f; BYTE $0x38; BYTE $0x81; BYTE $0x44; BYTE $0x24; BYTE $0x08
1002 * Used to get to the first process:
1003 * set up an interrupt return frame and IRET to user level.
1006 PUSHL $(UDSEL) /* old ss */
1007 MOVL sp+0(FP), AX /* old sp */
1009 MOVL $0x200, AX /* interrupt enable flag */
1010 PUSHL AX /* old flags */
1011 PUSHL $(UESEL) /* old cs */
1012 PUSHL $(UTZERO+32) /* old pc */
1021 * Interrupt/exception handling.
1022 * Each entry in the vector table calls either _strayintr or _strayintrx depending
1023 * on whether an error code has been automatically pushed onto the stack
1024 * (_strayintrx) or not, in which case a dummy entry must be pushed before retrieving
1025 * the trap type from the vector table entry and placing it on the stack as part
1026 * of the Ureg structure.
1027 * The size of each entry in the vector table (6 bytes) is known in trapinit().
1029 TEXT _strayintr(SB), $0
1030 PUSHL AX /* save AX */
1031 MOVL 4(SP), AX /* return PC from vectortable(SB) */
1034 TEXT _strayintrx(SB), $0
1035 XCHGL AX, (SP) /* swap AX with vectortable CALL PC */
1037 PUSHL DS /* save DS */
1039 POPL DS /* fix up DS */
1040 MOVBLZX (AX), AX /* trap type -> AX */
1041 XCHGL AX, 4(SP) /* exchange trap type with saved AX */
1043 PUSHL ES /* save ES */
1045 POPL ES /* fix up ES */
1047 PUSHL FS /* save the rest of the Ureg struct */
1051 PUSHL SP /* Ureg* argument to trap */
1054 TEXT forkret(SB), $0
1057 TEXT _forkretpopgs(SB), $0
1059 TEXT _forkretpopfs(SB), $0
1061 TEXT _forkretpopes(SB), $0
1063 TEXT _forkretpopds(SB), $0
1065 ADDL $8, SP /* pop error code and trap type */
1066 TEXT _forkretiret(SB), $0
1070 * This is merely _strayintr optimised to vector
1071 * to syscall() without going through trap().
1073 TEXT _syscallintr(SB), $0
1074 PUSHL $VectorSYSCALL /* trap type */
1085 MOVL $syscall(SB), AX
1087 PUSHL SP /* Ureg* argument to syscall */
1088 PUSHL $forkret(SB) /* return pc */
1091 TEXT vectortable(SB), $0
1092 CALL _strayintr(SB); BYTE $0x00 /* divide error */
1093 CALL _strayintr(SB); BYTE $0x01 /* debug exception */
1094 CALL _strayintr(SB); BYTE $0x02 /* NMI interrupt */
1095 CALL _strayintr(SB); BYTE $0x03 /* breakpoint */
1096 CALL _strayintr(SB); BYTE $0x04 /* overflow */
1097 CALL _strayintr(SB); BYTE $0x05 /* bound */
1098 CALL _strayintr(SB); BYTE $0x06 /* invalid opcode */
1099 CALL _strayintr(SB); BYTE $0x07 /* no coprocessor available */
1100 CALL _strayintrx(SB); BYTE $0x08 /* double fault */
1101 CALL _strayintr(SB); BYTE $0x09 /* coprocessor segment overflow */
1102 CALL _strayintrx(SB); BYTE $0x0A /* invalid TSS */
1103 CALL _strayintrx(SB); BYTE $0x0B /* segment not available */
1104 CALL _strayintrx(SB); BYTE $0x0C /* stack exception */
1105 CALL _strayintrx(SB); BYTE $0x0D /* general protection error */
1106 CALL _strayintrx(SB); BYTE $0x0E /* page fault */
1107 CALL _strayintr(SB); BYTE $0x0F /* */
1108 CALL _strayintr(SB); BYTE $0x10 /* coprocessor error */
1109 CALL _strayintrx(SB); BYTE $0x11 /* alignment check */
1110 CALL _strayintr(SB); BYTE $0x12 /* machine check */
1111 CALL _strayintr(SB); BYTE $0x13 /* simd error */
1112 CALL _strayintr(SB); BYTE $0x14
1113 CALL _strayintr(SB); BYTE $0x15
1114 CALL _strayintr(SB); BYTE $0x16
1115 CALL _strayintr(SB); BYTE $0x17
1116 CALL _strayintr(SB); BYTE $0x18
1117 CALL _strayintr(SB); BYTE $0x19
1118 CALL _strayintr(SB); BYTE $0x1A
1119 CALL _strayintr(SB); BYTE $0x1B
1120 CALL _strayintr(SB); BYTE $0x1C
1121 CALL _strayintr(SB); BYTE $0x1D
1122 CALL _strayintr(SB); BYTE $0x1E
1123 CALL _strayintr(SB); BYTE $0x1F
1124 CALL _strayintr(SB); BYTE $0x20 /* VectorLAPIC */
1125 CALL _strayintr(SB); BYTE $0x21
1126 CALL _strayintr(SB); BYTE $0x22
1127 CALL _strayintr(SB); BYTE $0x23
1128 CALL _strayintr(SB); BYTE $0x24
1129 CALL _strayintr(SB); BYTE $0x25
1130 CALL _strayintr(SB); BYTE $0x26
1131 CALL _strayintr(SB); BYTE $0x27
1132 CALL _strayintr(SB); BYTE $0x28
1133 CALL _strayintr(SB); BYTE $0x29
1134 CALL _strayintr(SB); BYTE $0x2A
1135 CALL _strayintr(SB); BYTE $0x2B
1136 CALL _strayintr(SB); BYTE $0x2C
1137 CALL _strayintr(SB); BYTE $0x2D
1138 CALL _strayintr(SB); BYTE $0x2E
1139 CALL _strayintr(SB); BYTE $0x2F
1140 CALL _strayintr(SB); BYTE $0x30
1141 CALL _strayintr(SB); BYTE $0x31
1142 CALL _strayintr(SB); BYTE $0x32
1143 CALL _strayintr(SB); BYTE $0x33
1144 CALL _strayintr(SB); BYTE $0x34
1145 CALL _strayintr(SB); BYTE $0x35
1146 CALL _strayintr(SB); BYTE $0x36
1147 CALL _strayintr(SB); BYTE $0x37
1148 CALL _strayintr(SB); BYTE $0x38
1149 CALL _strayintr(SB); BYTE $0x39
1150 CALL _strayintr(SB); BYTE $0x3A
1151 CALL _strayintr(SB); BYTE $0x3B
1152 CALL _strayintr(SB); BYTE $0x3C
1153 CALL _strayintr(SB); BYTE $0x3D
1154 CALL _strayintr(SB); BYTE $0x3E
1155 CALL _strayintr(SB); BYTE $0x3F
1156 CALL _syscallintr(SB); BYTE $0x40 /* VectorSYSCALL */
1157 CALL _strayintr(SB); BYTE $0x41
1158 CALL _strayintr(SB); BYTE $0x42
1159 CALL _strayintr(SB); BYTE $0x43
1160 CALL _strayintr(SB); BYTE $0x44
1161 CALL _strayintr(SB); BYTE $0x45
1162 CALL _strayintr(SB); BYTE $0x46
1163 CALL _strayintr(SB); BYTE $0x47
1164 CALL _strayintr(SB); BYTE $0x48
1165 CALL _strayintr(SB); BYTE $0x49
1166 CALL _strayintr(SB); BYTE $0x4A
1167 CALL _strayintr(SB); BYTE $0x4B
1168 CALL _strayintr(SB); BYTE $0x4C
1169 CALL _strayintr(SB); BYTE $0x4D
1170 CALL _strayintr(SB); BYTE $0x4E
1171 CALL _strayintr(SB); BYTE $0x4F
1172 CALL _strayintr(SB); BYTE $0x50
1173 CALL _strayintr(SB); BYTE $0x51
1174 CALL _strayintr(SB); BYTE $0x52
1175 CALL _strayintr(SB); BYTE $0x53
1176 CALL _strayintr(SB); BYTE $0x54
1177 CALL _strayintr(SB); BYTE $0x55
1178 CALL _strayintr(SB); BYTE $0x56
1179 CALL _strayintr(SB); BYTE $0x57
1180 CALL _strayintr(SB); BYTE $0x58
1181 CALL _strayintr(SB); BYTE $0x59
1182 CALL _strayintr(SB); BYTE $0x5A
1183 CALL _strayintr(SB); BYTE $0x5B
1184 CALL _strayintr(SB); BYTE $0x5C
1185 CALL _strayintr(SB); BYTE $0x5D
1186 CALL _strayintr(SB); BYTE $0x5E
1187 CALL _strayintr(SB); BYTE $0x5F
1188 CALL _strayintr(SB); BYTE $0x60
1189 CALL _strayintr(SB); BYTE $0x61
1190 CALL _strayintr(SB); BYTE $0x62
1191 CALL _strayintr(SB); BYTE $0x63
1192 CALL _strayintr(SB); BYTE $0x64
1193 CALL _strayintr(SB); BYTE $0x65
1194 CALL _strayintr(SB); BYTE $0x66
1195 CALL _strayintr(SB); BYTE $0x67
1196 CALL _strayintr(SB); BYTE $0x68
1197 CALL _strayintr(SB); BYTE $0x69
1198 CALL _strayintr(SB); BYTE $0x6A
1199 CALL _strayintr(SB); BYTE $0x6B
1200 CALL _strayintr(SB); BYTE $0x6C
1201 CALL _strayintr(SB); BYTE $0x6D
1202 CALL _strayintr(SB); BYTE $0x6E
1203 CALL _strayintr(SB); BYTE $0x6F
1204 CALL _strayintr(SB); BYTE $0x70
1205 CALL _strayintr(SB); BYTE $0x71
1206 CALL _strayintr(SB); BYTE $0x72
1207 CALL _strayintr(SB); BYTE $0x73
1208 CALL _strayintr(SB); BYTE $0x74
1209 CALL _strayintr(SB); BYTE $0x75
1210 CALL _strayintr(SB); BYTE $0x76
1211 CALL _strayintr(SB); BYTE $0x77
1212 CALL _strayintr(SB); BYTE $0x78
1213 CALL _strayintr(SB); BYTE $0x79
1214 CALL _strayintr(SB); BYTE $0x7A
1215 CALL _strayintr(SB); BYTE $0x7B
1216 CALL _strayintr(SB); BYTE $0x7C
1217 CALL _strayintr(SB); BYTE $0x7D
1218 CALL _strayintr(SB); BYTE $0x7E
1219 CALL _strayintr(SB); BYTE $0x7F
1220 CALL _strayintr(SB); BYTE $0x80 /* Vector[A]PIC */
1221 CALL _strayintr(SB); BYTE $0x81
1222 CALL _strayintr(SB); BYTE $0x82
1223 CALL _strayintr(SB); BYTE $0x83
1224 CALL _strayintr(SB); BYTE $0x84
1225 CALL _strayintr(SB); BYTE $0x85
1226 CALL _strayintr(SB); BYTE $0x86
1227 CALL _strayintr(SB); BYTE $0x87
1228 CALL _strayintr(SB); BYTE $0x88
1229 CALL _strayintr(SB); BYTE $0x89
1230 CALL _strayintr(SB); BYTE $0x8A
1231 CALL _strayintr(SB); BYTE $0x8B
1232 CALL _strayintr(SB); BYTE $0x8C
1233 CALL _strayintr(SB); BYTE $0x8D
1234 CALL _strayintr(SB); BYTE $0x8E
1235 CALL _strayintr(SB); BYTE $0x8F
1236 CALL _strayintr(SB); BYTE $0x90
1237 CALL _strayintr(SB); BYTE $0x91
1238 CALL _strayintr(SB); BYTE $0x92
1239 CALL _strayintr(SB); BYTE $0x93
1240 CALL _strayintr(SB); BYTE $0x94
1241 CALL _strayintr(SB); BYTE $0x95
1242 CALL _strayintr(SB); BYTE $0x96
1243 CALL _strayintr(SB); BYTE $0x97
1244 CALL _strayintr(SB); BYTE $0x98
1245 CALL _strayintr(SB); BYTE $0x99
1246 CALL _strayintr(SB); BYTE $0x9A
1247 CALL _strayintr(SB); BYTE $0x9B
1248 CALL _strayintr(SB); BYTE $0x9C
1249 CALL _strayintr(SB); BYTE $0x9D
1250 CALL _strayintr(SB); BYTE $0x9E
1251 CALL _strayintr(SB); BYTE $0x9F
1252 CALL _strayintr(SB); BYTE $0xA0
1253 CALL _strayintr(SB); BYTE $0xA1
1254 CALL _strayintr(SB); BYTE $0xA2
1255 CALL _strayintr(SB); BYTE $0xA3
1256 CALL _strayintr(SB); BYTE $0xA4
1257 CALL _strayintr(SB); BYTE $0xA5
1258 CALL _strayintr(SB); BYTE $0xA6
1259 CALL _strayintr(SB); BYTE $0xA7
1260 CALL _strayintr(SB); BYTE $0xA8
1261 CALL _strayintr(SB); BYTE $0xA9
1262 CALL _strayintr(SB); BYTE $0xAA
1263 CALL _strayintr(SB); BYTE $0xAB
1264 CALL _strayintr(SB); BYTE $0xAC
1265 CALL _strayintr(SB); BYTE $0xAD
1266 CALL _strayintr(SB); BYTE $0xAE
1267 CALL _strayintr(SB); BYTE $0xAF
1268 CALL _strayintr(SB); BYTE $0xB0
1269 CALL _strayintr(SB); BYTE $0xB1
1270 CALL _strayintr(SB); BYTE $0xB2
1271 CALL _strayintr(SB); BYTE $0xB3
1272 CALL _strayintr(SB); BYTE $0xB4
1273 CALL _strayintr(SB); BYTE $0xB5
1274 CALL _strayintr(SB); BYTE $0xB6
1275 CALL _strayintr(SB); BYTE $0xB7
1276 CALL _strayintr(SB); BYTE $0xB8
1277 CALL _strayintr(SB); BYTE $0xB9
1278 CALL _strayintr(SB); BYTE $0xBA
1279 CALL _strayintr(SB); BYTE $0xBB
1280 CALL _strayintr(SB); BYTE $0xBC
1281 CALL _strayintr(SB); BYTE $0xBD
1282 CALL _strayintr(SB); BYTE $0xBE
1283 CALL _strayintr(SB); BYTE $0xBF
1284 CALL _strayintr(SB); BYTE $0xC0
1285 CALL _strayintr(SB); BYTE $0xC1
1286 CALL _strayintr(SB); BYTE $0xC2
1287 CALL _strayintr(SB); BYTE $0xC3
1288 CALL _strayintr(SB); BYTE $0xC4
1289 CALL _strayintr(SB); BYTE $0xC5
1290 CALL _strayintr(SB); BYTE $0xC6
1291 CALL _strayintr(SB); BYTE $0xC7
1292 CALL _strayintr(SB); BYTE $0xC8
1293 CALL _strayintr(SB); BYTE $0xC9
1294 CALL _strayintr(SB); BYTE $0xCA
1295 CALL _strayintr(SB); BYTE $0xCB
1296 CALL _strayintr(SB); BYTE $0xCC
1297 CALL _strayintr(SB); BYTE $0xCD
1298 CALL _strayintr(SB); BYTE $0xCE
1299 CALL _strayintr(SB); BYTE $0xCF
1300 CALL _strayintr(SB); BYTE $0xD0
1301 CALL _strayintr(SB); BYTE $0xD1
1302 CALL _strayintr(SB); BYTE $0xD2
1303 CALL _strayintr(SB); BYTE $0xD3
1304 CALL _strayintr(SB); BYTE $0xD4
1305 CALL _strayintr(SB); BYTE $0xD5
1306 CALL _strayintr(SB); BYTE $0xD6
1307 CALL _strayintr(SB); BYTE $0xD7
1308 CALL _strayintr(SB); BYTE $0xD8
1309 CALL _strayintr(SB); BYTE $0xD9
1310 CALL _strayintr(SB); BYTE $0xDA
1311 CALL _strayintr(SB); BYTE $0xDB
1312 CALL _strayintr(SB); BYTE $0xDC
1313 CALL _strayintr(SB); BYTE $0xDD
1314 CALL _strayintr(SB); BYTE $0xDE
1315 CALL _strayintr(SB); BYTE $0xDF
1316 CALL _strayintr(SB); BYTE $0xE0
1317 CALL _strayintr(SB); BYTE $0xE1
1318 CALL _strayintr(SB); BYTE $0xE2
1319 CALL _strayintr(SB); BYTE $0xE3
1320 CALL _strayintr(SB); BYTE $0xE4
1321 CALL _strayintr(SB); BYTE $0xE5
1322 CALL _strayintr(SB); BYTE $0xE6
1323 CALL _strayintr(SB); BYTE $0xE7
1324 CALL _strayintr(SB); BYTE $0xE8
1325 CALL _strayintr(SB); BYTE $0xE9
1326 CALL _strayintr(SB); BYTE $0xEA
1327 CALL _strayintr(SB); BYTE $0xEB
1328 CALL _strayintr(SB); BYTE $0xEC
1329 CALL _strayintr(SB); BYTE $0xED
1330 CALL _strayintr(SB); BYTE $0xEE
1331 CALL _strayintr(SB); BYTE $0xEF
1332 CALL _strayintr(SB); BYTE $0xF0
1333 CALL _strayintr(SB); BYTE $0xF1
1334 CALL _strayintr(SB); BYTE $0xF2
1335 CALL _strayintr(SB); BYTE $0xF3
1336 CALL _strayintr(SB); BYTE $0xF4
1337 CALL _strayintr(SB); BYTE $0xF5
1338 CALL _strayintr(SB); BYTE $0xF6
1339 CALL _strayintr(SB); BYTE $0xF7
1340 CALL _strayintr(SB); BYTE $0xF8
1341 CALL _strayintr(SB); BYTE $0xF9
1342 CALL _strayintr(SB); BYTE $0xFA
1343 CALL _strayintr(SB); BYTE $0xFB
1344 CALL _strayintr(SB); BYTE $0xFC
1345 CALL _strayintr(SB); BYTE $0xFD
1346 CALL _strayintr(SB); BYTE $0xFE
1347 CALL _strayintr(SB); BYTE $0xFF