4 #define PADDR(a) ((a) & ~KZERO)
5 #define KADDR(a) (KZERO|(a))
8 * Some machine instructions not handled by 8[al].
10 #define OP16 BYTE $0x66
11 #define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
12 #define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument in AX */
13 #define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
14 #define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
15 #define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) */
16 #define HLT BYTE $0xF4
17 #define INVLPG BYTE $0x0F; BYTE $0x01; BYTE $0x39 /* INVLPG (%ecx) */
18 #define WBINVD BYTE $0x0F; BYTE $0x09
20 #define VectorSYSCALL 0x40
23 * Macros for calculating offsets within the page directory base
24 * and page tables. Note that these are assembler-specific hence
27 #define PDO(a) (((((a))>>22) & 0x03FF)<<2)
28 #define PTO(a) (((((a))>>12) & 0x03FF)<<2)
31 * For backwards compatiblity with 9load - should go away when 9load is changed
32 * 9load currently sets up the mmu, however the first 16MB of memory is identity
33 * mapped, so behave as if the mmu was not setup
35 TEXT _startKADDR(SB), $0
36 MOVL $_startPADDR(SB), AX
41 * Must be 4-byte aligned.
43 TEXT _multibootheader(SB), $0
44 LONG $0x1BADB002 /* magic */
45 LONG $0x00010003 /* flags */
46 LONG $-(0x1BADB002 + 0x00010003) /* checksum */
47 LONG $_multibootheader-KZERO(SB) /* header_addr */
48 LONG $_startKADDR-KZERO(SB) /* load_addr */
49 LONG $edata-KZERO(SB) /* load_end_addr */
50 LONG $end-KZERO(SB) /* bss_end_addr */
51 LONG $_multibootentry-KZERO(SB) /* entry_addr */
52 LONG $0 /* mode_type */
58 * the kernel expects the data segment to be page-aligned
59 * multiboot bootloaders put the data segment right behind text
61 TEXT _multibootentry(SB), $0
62 MOVL $etext-KZERO(SB), SI
66 MOVL $edata-KZERO(SB), CX
70 INCL CX /* one more for post decrement */
74 MOVL BX, multiboot-KZERO(SB)
75 MOVL $_startPADDR(SB), AX
79 /* multiboot structure pointer */
80 TEXT multiboot(SB), $0
84 * In protected mode with paging turned off and segment registers setup
85 * to linear map all memory. Entered via a jump to PADDR(entry),
86 * the physical address of the virtual kernel entry point of KADDR(entry).
87 * Make the basic page tables for processor 0. Six pages are needed for
90 * page tables for mapping the first 8MB of physical memory to KZERO;
92 * virtual and physical pages for mapping the Mach structure.
93 * The remaining PTEs will be allocated later when memory is sized.
94 * An identity mmu map is also needed for the switch to virtual mode.
95 * This identity mapping is removed once the MMU is going and the JMP has
96 * been made to virtual memory.
98 TEXT _startPADDR(SB), $0
99 CLI /* make sure interrupts are off */
101 /* set up the gdt so we have sane plan 9 style gdts. */
102 MOVL $tgdtptr(SB), AX
108 /* clear prefetch queue (weird code to avoid optimizations) */
111 /* set segs to something sane (avoid traps later) */
119 /* JMP $(2<<3):$mode32bit(SB) /**/
121 LONG $mode32bit-KZERO(SB)
125 * gdt to get us to 32-bit/segmented/unpaged mode
129 /* null descriptor */
133 /* data segment descriptor for 4 gigabytes (PL 0) */
135 LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
137 /* exec segment descriptor for 4 gigabytes (PL 0) */
139 LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
142 * pointer to initial gdt
143 * Note the -KZERO which puts the physical address in the gdtptr.
144 * that's needed as we start executing in physical addresses.
150 TEXT m0rgdtptr(SB), $0
152 LONG $(CPU0GDT-KZERO)
154 TEXT m0gdtptr(SB), $0
158 TEXT m0idtptr(SB), $0
162 TEXT mode32bit(SB), $0
163 /* At this point, the GDT setup is done. */
165 MOVL $((CPU0END-CPU0PDB)>>2), CX
166 MOVL $PADDR(CPU0PDB), DI
172 MOVL $PADDR(CPU0PTE), DX
173 MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
176 MOVL $PADDR(CPU0PDB), AX
177 ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
179 MOVL DX, 0(AX) /* PTE's for KZERO */
181 MOVL DX, 4(AX) /* PTE's for KZERO+4MB */
183 MOVL DX, 8(AX) /* PTE's for KZERO+8MB */
185 MOVL DX, 12(AX) /* PTE's for KZERO+12MB */
187 MOVL $PADDR(CPU0PTE), AX /* first page of page table */
188 MOVL $end-KZERO(SB), CX
190 ADDL $(16*1024), CX /* qemu puts multiboot data after the kernel */
193 ANDL $~(BY2XPG-1), CX /* round to 4MB */
194 MOVL CX, MemMin-KZERO(SB) /* see memory.c */
203 MOVL $PADDR(CPU0PTE), AX
204 ADDL $PTO(MACHADDR), AX /* page table entry offset for MACHADDR */
205 ORL $PADDR(CPU0MACH), BX
206 MOVL BX, (AX) /* PTE for Mach */
209 * Now ready to use the new map. Make sure the processor options are what is wanted.
210 * It is necessary on some processors to immediately follow mode switching with a JMP instruction
211 * to clear the prefetch queues.
213 MOVL $PADDR(CPU0PDB), CX /* load address of page directory */
214 MOVL (PDO(KZERO))(CX), DX /* double-map KZERO at 0 */
215 MOVL DX, (PDO(0))(CX)
220 ORL $0x80010000, DX /* PG|WP */
221 ANDL $~0x6000000A, DX /* ~(CD|NW|TS|MP) */
223 MOVL $_startpg(SB), AX /* this is a virtual address */
224 MOVL DX, CR0 /* turn on paging */
225 JMP* AX /* jump to the virtual nirvana */
228 * Basic machine environment set, can clear BSS and create a stack.
229 * The stack starts at the top of the page containing the Mach structure.
230 * The x86 architecture forces the use of the same virtual address for
231 * each processor's Mach structure, so the global Mach pointer 'm' can
232 * be initialised here.
234 TEXT _startpg(SB), $0
235 MOVL $0, (PDO(0))(CX) /* undo double-map of KZERO at 0 */
236 MOVL CX, CR3 /* load and flush the mmu */
242 SUBL DI, CX /* end-edata bytes */
243 SHRL $2, CX /* end-edata doublewords */
246 REP; STOSL /* clear BSS */
249 MOVL SP, m(SB) /* initialise global Mach pointer */
250 MOVL $0, 0(SP) /* initialise m->machno */
253 ADDL $(MACHSIZE-4), SP /* initialise stack */
256 * Need to do one final thing to ensure a clean machine environment,
257 * clear the EFLAGS register, which can only be done once there is a stack.
266 * Park a processor. Should never fall through a return from main to here,
267 * should only be called by application processors when shutting down.
289 TEXT bios32call(SB), $0
299 MOVL 12(SP), BP /* ptr */
300 BYTE $0xFF; BYTE $0x5D; BYTE $0x00 /* CALL FAR 0(BP) */
319 * in[bsl] input a byte|short|long
320 * ins[bsl] input a string of bytes|shorts|longs
321 * out[bsl] output a byte|short|long
322 * outs[bsl] output a string of bytes|shorts|longs
332 MOVL address+4(FP), DI
346 MOVL address+4(FP), DI
359 MOVL address+4(FP), DI
373 MOVL address+4(FP), SI
387 MOVL address+4(FP), SI
401 MOVL address+4(FP), SI
408 * Read/write various system registers.
409 * CR4 and the 'model specific registers' should only be read/written
410 * after it has been determined the processor supports them
412 TEXT lgdt(SB), $0 /* GDTR - global descriptor table */
413 MOVL gdtptr+0(FP), AX
417 TEXT lldt(SB), $0 /* LDTR - local descriptor table */
419 BYTE $0x0F; BYTE $0x00; BYTE $0xD0 /* LLDT AX */
422 TEXT lidt(SB), $0 /* IDTR - interrupt descriptor table */
423 MOVL idtptr+0(FP), AX
427 TEXT ltr(SB), $0 /* TR - task register */
432 TEXT getcr0(SB), $0 /* CR0 - processor control */
436 TEXT getcr2(SB), $0 /* CR2 - page fault linear address */
440 TEXT getcr3(SB), $0 /* CR3 - page directory base */
454 TEXT getcr4(SB), $0 /* CR4 - extensions */
473 TEXT _cycles(SB), $0 /* time stamp counter */
475 MOVL vlong+0(FP), CX /* &vlong */
476 MOVL AX, 0(CX) /* lo */
477 MOVL DX, 4(CX) /* hi */
482 * time stamp counter; low-order 32 bits of 64-bit cycle counter
483 * Runs at fasthz/4 cycles per second (m->clkin>>3)
485 TEXT lcycles(SB),1,$0
489 TEXT rdmsr(SB), $0 /* model-specific register */
492 TEXT _rdmsrinst(SB), $0
494 MOVL vlong+4(FP), CX /* &vlong */
495 MOVL AX, 0(CX) /* lo */
496 MOVL DX, 4(CX) /* hi */
497 MOVL BP, AX /* BP set to -1 if traped */
505 TEXT _wrmsrinst(SB), $0
507 MOVL BP, AX /* BP set to -1 if traped */
511 * Try to determine the CPU type which requires fiddling with EFLAGS.
512 * If the Id bit can be toggled then the CPUID instruction can be used
513 * to determine CPU identity and features. First have to check if it's
514 * a 386 (Ac bit can't be set). If it's not a 386 and the Id bit can't be
515 * toggled then it's an older 486 of some kind.
517 * cpuid(fun, regs[4]);
522 POPFL /* set Id|Ac */
524 POPL BX /* retrieve value */
527 POPFL /* clear Id|Ac, EFLAGS initialised */
529 POPL AX /* retrieve value */
531 TESTL $0x040000, AX /* Ac */
532 JZ _cpu386 /* can't set this bit on 386 */
533 TESTL $0x200000, AX /* Id */
534 JZ _cpu486 /* can't toggle this bit on some 486 */
560 * Basic timing loop to determine CPU frequency.
571 * Note: the encodings for the FCLEX, FINIT, FSAVE, FSTCW, FSENV and FSTSW
572 * instructions do NOT have the WAIT prefix byte (i.e. they act like their
573 * FNxxx variations) so WAIT instructions must be explicitly placed in the
578 ORL $0x28, AX /* NE=1, TS=1 */ ;\
583 ANDL $~0xC, AX /* EM=0, TS=0 */ ;\
586 TEXT fpoff(SB), $0 /* disable */
590 TEXT fpinit(SB), $0 /* enable and init */
594 /* setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL) */
595 /* note that low 6 bits are masks, not enables, on this chip */
602 TEXT fpx87save0(SB), $0 /* save state and disable */
604 FSAVE 0(AX) /* no WAIT */
608 TEXT fpx87restore0(SB), $0 /* enable and restore state */
615 TEXT fpclear(SB), $0 /* clear pending exceptions */
621 TEXT fpssesave0(SB), $0 /* save state and disable */
623 FXSAVE 0(AX) /* no WAIT */
627 TEXT fpsserestore0(SB), $0 /* enable and restore state */
634 TEXT ldmxcsr(SB), $0 /* Load MXCSR */
646 MOVL $(MACHADDR+0x04), CX /* save PC in m->splpc */
659 MOVL $(MACHADDR+0x04), CX /* clear m->splpc */
677 ANDL $0x200, AX /* interrupt enable flag */
687 XCHGL AX, (BX) /* lock->key */
691 POPL AX /* return PC */
726 TEXT cmpswap486(SB), $0
731 BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
739 TEXT mul64fract(SB), $0
741 * Multiply two 64-bit number s and keep the middle 64 bits from the 128-bit result
742 * See ../port/tod.c for motivation.
745 XORL BX, BX /* BX = 0 */
748 MULL b+16(FP) /* a1*b1 */
749 MOVL AX, 4(CX) /* r2 = lo(a1*b1) */
752 MULL b+12(FP) /* a1*b0 */
753 MOVL AX, 0(CX) /* r1 = lo(a1*b0) */
754 ADDL DX, 4(CX) /* r2 += hi(a1*b0) */
757 MULL b+16(FP) /* a0*b1 */
758 ADDL AX, 0(CX) /* r1 += lo(a0*b1) */
759 ADCL DX, 4(CX) /* r2 += hi(a0*b1) + carry */
762 MULL b+12(FP) /* a0*b0 */
763 ADDL DX, 0(CX) /* r1 += hi(a0*b0) */
764 ADCL BX, 4(CX) /* r2 += carry */
768 * label consists of a stack pointer and a PC
770 TEXT gotolabel(SB), $0
772 MOVL 0(AX), SP /* restore sp */
773 MOVL 4(AX), AX /* put return pc on the stack */
775 MOVL $1, AX /* return 1 */
778 TEXT setlabel(SB), $0
780 MOVL SP, 0(AX) /* store sp */
781 MOVL 0(SP), BX /* store return pc */
783 MOVL $0, AX /* return 0 */
787 * Attempt at power saving. -rsc
807 BYTE $0x0f; BYTE $0x01; BYTE $0xc8 /* MONITOR */
812 BYTE $0x0f; BYTE $0x01; BYTE $0xc9 /* MWAIT */
816 #define RDRANDAX BYTE $0x0f; BYTE $0xc7; BYTE $0xf0
818 TEXT rdrand32(SB), $-4
824 TEXT rdrandbuf(SB), $0
848 /* debug register access */
867 TEXT putdr01236(SB), $0
885 /* VMX instructions */
888 BYTE $0xf3; BYTE $0x0f; BYTE $0xc7; BYTE $0x74; BYTE $0x24; BYTE $0x04
892 BYTE $0x0f; BYTE $0x01; BYTE $0xc4
897 BYTE $0x66; BYTE $0x0f; BYTE $0xc7; BYTE $0x74; BYTE $0x24; BYTE $0x04
900 TEXT vmlaunch(SB), $0
903 BYTE $0x0f; BYTE $0x79; BYTE $0xfa /* VMWRITE DX, DI */
906 MOVL $vmrestore(SB), DX
907 BYTE $0x0f; BYTE $0x79; BYTE $0xfa /* VMWRITE DX, DI */
910 MOVL resume+4(FP), AX
923 BYTE $0x0f; BYTE $0x01; BYTE $0xc2 /* VMLAUNCH */
926 BYTE $0x0f; BYTE $0x01; BYTE $0xc3 /* VMRESUME */
929 TEXT vmrestore(SB), $0
946 BYTE $0x0f; BYTE $0xc7; BYTE $0x74; BYTE $0x24; BYTE $0x04
953 BYTE $0x0f; BYTE $0x79; BYTE $0xfa
959 /* VMREAD (SI), DI */
960 BYTE $0x0f; BYTE $0x78; BYTE $0x3e
965 /* INVEPT AX, 8(SP) */
966 BYTE $0x66; BYTE $0x0f; BYTE $0x38; BYTE $0x80; BYTE $0x44; BYTE $0x24; BYTE $0x08
971 /* INVVPID AX, 8(SP) */
972 BYTE $0x66; BYTE $0x0f; BYTE $0x38; BYTE $0x81; BYTE $0x44; BYTE $0x24; BYTE $0x08
988 * Used to get to the first process:
989 * set up an interrupt return frame and IRET to user level.
992 PUSHL $(UDSEL) /* old ss */
993 MOVL sp+0(FP), AX /* old sp */
995 MOVL $0x200, AX /* interrupt enable flag */
996 PUSHL AX /* old flags */
997 PUSHL $(UESEL) /* old cs */
998 PUSHL $(UTZERO+32) /* old pc */
1007 * Interrupt/exception handling.
1008 * Each entry in the vector table calls either _strayintr or _strayintrx depending
1009 * on whether an error code has been automatically pushed onto the stack
1010 * (_strayintrx) or not, in which case a dummy entry must be pushed before retrieving
1011 * the trap type from the vector table entry and placing it on the stack as part
1012 * of the Ureg structure.
1013 * The size of each entry in the vector table (6 bytes) is known in trapinit().
1015 TEXT _strayintr(SB), $0
1016 PUSHL AX /* save AX */
1017 MOVL 4(SP), AX /* return PC from vectortable(SB) */
1020 TEXT _strayintrx(SB), $0
1021 XCHGL AX, (SP) /* swap AX with vectortable CALL PC */
1023 PUSHL DS /* save DS */
1025 POPL DS /* fix up DS */
1026 MOVBLZX (AX), AX /* trap type -> AX */
1027 XCHGL AX, 4(SP) /* exchange trap type with saved AX */
1029 PUSHL ES /* save ES */
1031 POPL ES /* fix up ES */
1033 PUSHL FS /* save the rest of the Ureg struct */
1037 PUSHL SP /* Ureg* argument to trap */
1040 TEXT forkret(SB), $0
1043 TEXT _forkretpopgs(SB), $0
1045 TEXT _forkretpopfs(SB), $0
1047 TEXT _forkretpopes(SB), $0
1049 TEXT _forkretpopds(SB), $0
1051 ADDL $8, SP /* pop error code and trap type */
1052 TEXT _forkretiret(SB), $0
1056 * This is merely _strayintr optimised to vector
1057 * to syscall() without going through trap().
1059 TEXT _syscallintr(SB), $0
1060 PUSHL $VectorSYSCALL /* trap type */
1071 MOVL $syscall(SB), AX
1073 PUSHL SP /* Ureg* argument to syscall */
1074 PUSHL $forkret(SB) /* return pc */
1077 TEXT vectortable(SB), $0
1078 CALL _strayintr(SB); BYTE $0x00 /* divide error */
1079 CALL _strayintr(SB); BYTE $0x01 /* debug exception */
1080 CALL _strayintr(SB); BYTE $0x02 /* NMI interrupt */
1081 CALL _strayintr(SB); BYTE $0x03 /* breakpoint */
1082 CALL _strayintr(SB); BYTE $0x04 /* overflow */
1083 CALL _strayintr(SB); BYTE $0x05 /* bound */
1084 CALL _strayintr(SB); BYTE $0x06 /* invalid opcode */
1085 CALL _strayintr(SB); BYTE $0x07 /* no coprocessor available */
1086 CALL _strayintrx(SB); BYTE $0x08 /* double fault */
1087 CALL _strayintr(SB); BYTE $0x09 /* coprocessor segment overflow */
1088 CALL _strayintrx(SB); BYTE $0x0A /* invalid TSS */
1089 CALL _strayintrx(SB); BYTE $0x0B /* segment not available */
1090 CALL _strayintrx(SB); BYTE $0x0C /* stack exception */
1091 CALL _strayintrx(SB); BYTE $0x0D /* general protection error */
1092 CALL _strayintrx(SB); BYTE $0x0E /* page fault */
1093 CALL _strayintr(SB); BYTE $0x0F /* */
1094 CALL _strayintr(SB); BYTE $0x10 /* coprocessor error */
1095 CALL _strayintrx(SB); BYTE $0x11 /* alignment check */
1096 CALL _strayintr(SB); BYTE $0x12 /* machine check */
1097 CALL _strayintr(SB); BYTE $0x13 /* simd error */
1098 CALL _strayintr(SB); BYTE $0x14
1099 CALL _strayintr(SB); BYTE $0x15
1100 CALL _strayintr(SB); BYTE $0x16
1101 CALL _strayintr(SB); BYTE $0x17
1102 CALL _strayintr(SB); BYTE $0x18
1103 CALL _strayintr(SB); BYTE $0x19
1104 CALL _strayintr(SB); BYTE $0x1A
1105 CALL _strayintr(SB); BYTE $0x1B
1106 CALL _strayintr(SB); BYTE $0x1C
1107 CALL _strayintr(SB); BYTE $0x1D
1108 CALL _strayintr(SB); BYTE $0x1E
1109 CALL _strayintr(SB); BYTE $0x1F
1110 CALL _strayintr(SB); BYTE $0x20 /* VectorLAPIC */
1111 CALL _strayintr(SB); BYTE $0x21
1112 CALL _strayintr(SB); BYTE $0x22
1113 CALL _strayintr(SB); BYTE $0x23
1114 CALL _strayintr(SB); BYTE $0x24
1115 CALL _strayintr(SB); BYTE $0x25
1116 CALL _strayintr(SB); BYTE $0x26
1117 CALL _strayintr(SB); BYTE $0x27
1118 CALL _strayintr(SB); BYTE $0x28
1119 CALL _strayintr(SB); BYTE $0x29
1120 CALL _strayintr(SB); BYTE $0x2A
1121 CALL _strayintr(SB); BYTE $0x2B
1122 CALL _strayintr(SB); BYTE $0x2C
1123 CALL _strayintr(SB); BYTE $0x2D
1124 CALL _strayintr(SB); BYTE $0x2E
1125 CALL _strayintr(SB); BYTE $0x2F
1126 CALL _strayintr(SB); BYTE $0x30
1127 CALL _strayintr(SB); BYTE $0x31
1128 CALL _strayintr(SB); BYTE $0x32
1129 CALL _strayintr(SB); BYTE $0x33
1130 CALL _strayintr(SB); BYTE $0x34
1131 CALL _strayintr(SB); BYTE $0x35
1132 CALL _strayintr(SB); BYTE $0x36
1133 CALL _strayintr(SB); BYTE $0x37
1134 CALL _strayintr(SB); BYTE $0x38
1135 CALL _strayintr(SB); BYTE $0x39
1136 CALL _strayintr(SB); BYTE $0x3A
1137 CALL _strayintr(SB); BYTE $0x3B
1138 CALL _strayintr(SB); BYTE $0x3C
1139 CALL _strayintr(SB); BYTE $0x3D
1140 CALL _strayintr(SB); BYTE $0x3E
1141 CALL _strayintr(SB); BYTE $0x3F
1142 CALL _syscallintr(SB); BYTE $0x40 /* VectorSYSCALL */
1143 CALL _strayintr(SB); BYTE $0x41
1144 CALL _strayintr(SB); BYTE $0x42
1145 CALL _strayintr(SB); BYTE $0x43
1146 CALL _strayintr(SB); BYTE $0x44
1147 CALL _strayintr(SB); BYTE $0x45
1148 CALL _strayintr(SB); BYTE $0x46
1149 CALL _strayintr(SB); BYTE $0x47
1150 CALL _strayintr(SB); BYTE $0x48
1151 CALL _strayintr(SB); BYTE $0x49
1152 CALL _strayintr(SB); BYTE $0x4A
1153 CALL _strayintr(SB); BYTE $0x4B
1154 CALL _strayintr(SB); BYTE $0x4C
1155 CALL _strayintr(SB); BYTE $0x4D
1156 CALL _strayintr(SB); BYTE $0x4E
1157 CALL _strayintr(SB); BYTE $0x4F
1158 CALL _strayintr(SB); BYTE $0x50
1159 CALL _strayintr(SB); BYTE $0x51
1160 CALL _strayintr(SB); BYTE $0x52
1161 CALL _strayintr(SB); BYTE $0x53
1162 CALL _strayintr(SB); BYTE $0x54
1163 CALL _strayintr(SB); BYTE $0x55
1164 CALL _strayintr(SB); BYTE $0x56
1165 CALL _strayintr(SB); BYTE $0x57
1166 CALL _strayintr(SB); BYTE $0x58
1167 CALL _strayintr(SB); BYTE $0x59
1168 CALL _strayintr(SB); BYTE $0x5A
1169 CALL _strayintr(SB); BYTE $0x5B
1170 CALL _strayintr(SB); BYTE $0x5C
1171 CALL _strayintr(SB); BYTE $0x5D
1172 CALL _strayintr(SB); BYTE $0x5E
1173 CALL _strayintr(SB); BYTE $0x5F
1174 CALL _strayintr(SB); BYTE $0x60
1175 CALL _strayintr(SB); BYTE $0x61
1176 CALL _strayintr(SB); BYTE $0x62
1177 CALL _strayintr(SB); BYTE $0x63
1178 CALL _strayintr(SB); BYTE $0x64
1179 CALL _strayintr(SB); BYTE $0x65
1180 CALL _strayintr(SB); BYTE $0x66
1181 CALL _strayintr(SB); BYTE $0x67
1182 CALL _strayintr(SB); BYTE $0x68
1183 CALL _strayintr(SB); BYTE $0x69
1184 CALL _strayintr(SB); BYTE $0x6A
1185 CALL _strayintr(SB); BYTE $0x6B
1186 CALL _strayintr(SB); BYTE $0x6C
1187 CALL _strayintr(SB); BYTE $0x6D
1188 CALL _strayintr(SB); BYTE $0x6E
1189 CALL _strayintr(SB); BYTE $0x6F
1190 CALL _strayintr(SB); BYTE $0x70
1191 CALL _strayintr(SB); BYTE $0x71
1192 CALL _strayintr(SB); BYTE $0x72
1193 CALL _strayintr(SB); BYTE $0x73
1194 CALL _strayintr(SB); BYTE $0x74
1195 CALL _strayintr(SB); BYTE $0x75
1196 CALL _strayintr(SB); BYTE $0x76
1197 CALL _strayintr(SB); BYTE $0x77
1198 CALL _strayintr(SB); BYTE $0x78
1199 CALL _strayintr(SB); BYTE $0x79
1200 CALL _strayintr(SB); BYTE $0x7A
1201 CALL _strayintr(SB); BYTE $0x7B
1202 CALL _strayintr(SB); BYTE $0x7C
1203 CALL _strayintr(SB); BYTE $0x7D
1204 CALL _strayintr(SB); BYTE $0x7E
1205 CALL _strayintr(SB); BYTE $0x7F
1206 CALL _strayintr(SB); BYTE $0x80 /* Vector[A]PIC */
1207 CALL _strayintr(SB); BYTE $0x81
1208 CALL _strayintr(SB); BYTE $0x82
1209 CALL _strayintr(SB); BYTE $0x83
1210 CALL _strayintr(SB); BYTE $0x84
1211 CALL _strayintr(SB); BYTE $0x85
1212 CALL _strayintr(SB); BYTE $0x86
1213 CALL _strayintr(SB); BYTE $0x87
1214 CALL _strayintr(SB); BYTE $0x88
1215 CALL _strayintr(SB); BYTE $0x89
1216 CALL _strayintr(SB); BYTE $0x8A
1217 CALL _strayintr(SB); BYTE $0x8B
1218 CALL _strayintr(SB); BYTE $0x8C
1219 CALL _strayintr(SB); BYTE $0x8D
1220 CALL _strayintr(SB); BYTE $0x8E
1221 CALL _strayintr(SB); BYTE $0x8F
1222 CALL _strayintr(SB); BYTE $0x90
1223 CALL _strayintr(SB); BYTE $0x91
1224 CALL _strayintr(SB); BYTE $0x92
1225 CALL _strayintr(SB); BYTE $0x93
1226 CALL _strayintr(SB); BYTE $0x94
1227 CALL _strayintr(SB); BYTE $0x95
1228 CALL _strayintr(SB); BYTE $0x96
1229 CALL _strayintr(SB); BYTE $0x97
1230 CALL _strayintr(SB); BYTE $0x98
1231 CALL _strayintr(SB); BYTE $0x99
1232 CALL _strayintr(SB); BYTE $0x9A
1233 CALL _strayintr(SB); BYTE $0x9B
1234 CALL _strayintr(SB); BYTE $0x9C
1235 CALL _strayintr(SB); BYTE $0x9D
1236 CALL _strayintr(SB); BYTE $0x9E
1237 CALL _strayintr(SB); BYTE $0x9F
1238 CALL _strayintr(SB); BYTE $0xA0
1239 CALL _strayintr(SB); BYTE $0xA1
1240 CALL _strayintr(SB); BYTE $0xA2
1241 CALL _strayintr(SB); BYTE $0xA3
1242 CALL _strayintr(SB); BYTE $0xA4
1243 CALL _strayintr(SB); BYTE $0xA5
1244 CALL _strayintr(SB); BYTE $0xA6
1245 CALL _strayintr(SB); BYTE $0xA7
1246 CALL _strayintr(SB); BYTE $0xA8
1247 CALL _strayintr(SB); BYTE $0xA9
1248 CALL _strayintr(SB); BYTE $0xAA
1249 CALL _strayintr(SB); BYTE $0xAB
1250 CALL _strayintr(SB); BYTE $0xAC
1251 CALL _strayintr(SB); BYTE $0xAD
1252 CALL _strayintr(SB); BYTE $0xAE
1253 CALL _strayintr(SB); BYTE $0xAF
1254 CALL _strayintr(SB); BYTE $0xB0
1255 CALL _strayintr(SB); BYTE $0xB1
1256 CALL _strayintr(SB); BYTE $0xB2
1257 CALL _strayintr(SB); BYTE $0xB3
1258 CALL _strayintr(SB); BYTE $0xB4
1259 CALL _strayintr(SB); BYTE $0xB5
1260 CALL _strayintr(SB); BYTE $0xB6
1261 CALL _strayintr(SB); BYTE $0xB7
1262 CALL _strayintr(SB); BYTE $0xB8
1263 CALL _strayintr(SB); BYTE $0xB9
1264 CALL _strayintr(SB); BYTE $0xBA
1265 CALL _strayintr(SB); BYTE $0xBB
1266 CALL _strayintr(SB); BYTE $0xBC
1267 CALL _strayintr(SB); BYTE $0xBD
1268 CALL _strayintr(SB); BYTE $0xBE
1269 CALL _strayintr(SB); BYTE $0xBF
1270 CALL _strayintr(SB); BYTE $0xC0
1271 CALL _strayintr(SB); BYTE $0xC1
1272 CALL _strayintr(SB); BYTE $0xC2
1273 CALL _strayintr(SB); BYTE $0xC3
1274 CALL _strayintr(SB); BYTE $0xC4
1275 CALL _strayintr(SB); BYTE $0xC5
1276 CALL _strayintr(SB); BYTE $0xC6
1277 CALL _strayintr(SB); BYTE $0xC7
1278 CALL _strayintr(SB); BYTE $0xC8
1279 CALL _strayintr(SB); BYTE $0xC9
1280 CALL _strayintr(SB); BYTE $0xCA
1281 CALL _strayintr(SB); BYTE $0xCB
1282 CALL _strayintr(SB); BYTE $0xCC
1283 CALL _strayintr(SB); BYTE $0xCD
1284 CALL _strayintr(SB); BYTE $0xCE
1285 CALL _strayintr(SB); BYTE $0xCF
1286 CALL _strayintr(SB); BYTE $0xD0
1287 CALL _strayintr(SB); BYTE $0xD1
1288 CALL _strayintr(SB); BYTE $0xD2
1289 CALL _strayintr(SB); BYTE $0xD3
1290 CALL _strayintr(SB); BYTE $0xD4
1291 CALL _strayintr(SB); BYTE $0xD5
1292 CALL _strayintr(SB); BYTE $0xD6
1293 CALL _strayintr(SB); BYTE $0xD7
1294 CALL _strayintr(SB); BYTE $0xD8
1295 CALL _strayintr(SB); BYTE $0xD9
1296 CALL _strayintr(SB); BYTE $0xDA
1297 CALL _strayintr(SB); BYTE $0xDB
1298 CALL _strayintr(SB); BYTE $0xDC
1299 CALL _strayintr(SB); BYTE $0xDD
1300 CALL _strayintr(SB); BYTE $0xDE
1301 CALL _strayintr(SB); BYTE $0xDF
1302 CALL _strayintr(SB); BYTE $0xE0
1303 CALL _strayintr(SB); BYTE $0xE1
1304 CALL _strayintr(SB); BYTE $0xE2
1305 CALL _strayintr(SB); BYTE $0xE3
1306 CALL _strayintr(SB); BYTE $0xE4
1307 CALL _strayintr(SB); BYTE $0xE5
1308 CALL _strayintr(SB); BYTE $0xE6
1309 CALL _strayintr(SB); BYTE $0xE7
1310 CALL _strayintr(SB); BYTE $0xE8
1311 CALL _strayintr(SB); BYTE $0xE9
1312 CALL _strayintr(SB); BYTE $0xEA
1313 CALL _strayintr(SB); BYTE $0xEB
1314 CALL _strayintr(SB); BYTE $0xEC
1315 CALL _strayintr(SB); BYTE $0xED
1316 CALL _strayintr(SB); BYTE $0xEE
1317 CALL _strayintr(SB); BYTE $0xEF
1318 CALL _strayintr(SB); BYTE $0xF0
1319 CALL _strayintr(SB); BYTE $0xF1
1320 CALL _strayintr(SB); BYTE $0xF2
1321 CALL _strayintr(SB); BYTE $0xF3
1322 CALL _strayintr(SB); BYTE $0xF4
1323 CALL _strayintr(SB); BYTE $0xF5
1324 CALL _strayintr(SB); BYTE $0xF6
1325 CALL _strayintr(SB); BYTE $0xF7
1326 CALL _strayintr(SB); BYTE $0xF8
1327 CALL _strayintr(SB); BYTE $0xF9
1328 CALL _strayintr(SB); BYTE $0xFA
1329 CALL _strayintr(SB); BYTE $0xFB
1330 CALL _strayintr(SB); BYTE $0xFC
1331 CALL _strayintr(SB); BYTE $0xFD
1332 CALL _strayintr(SB); BYTE $0xFE
1333 CALL _strayintr(SB); BYTE $0xFF