1 #define X86STEPPING(x) ((x) & 0x0F)
2 /* incorporates extended-model and -family bits */
3 #define X86MODEL(x) ((((x)>>4) & 0x0F) | (((x)>>16) & 0x0F)<<4)
4 #define X86FAMILY(x) ((((x)>>8) & 0x0F) | (((x)>>20) & 0xFF)<<4)
7 VectorNMI = 2, /* non-maskable interrupt */
8 VectorBPT = 3, /* breakpoint */
9 VectorUD = 6, /* invalid opcode exception */
10 VectorCNA = 7, /* coprocessor not available */
11 Vector2F = 8, /* double fault */
12 VectorCSO = 9, /* coprocessor segment overrun */
13 VectorSNP = 11, /* segment not present */
14 VectorGPF = 13, /* general protection fault */
15 VectorPF = 14, /* page fault */
16 Vector15 = 15, /* reserved */
17 VectorCERR = 16, /* coprocessor error */
19 VectorPIC = 32, /* external i8259 interrupts */
28 IrqAUX = 12, /* PS/2 port */
29 IrqIRQ13 = 13, /* coprocessor on 386 */
34 VectorLAPIC = VectorPIC+16, /* local APIC interrupts */
35 IrqLINT0 = 16, /* LINT[01] must be offsets 0 and 1 */
40 IrqSPURIOUS = 31, /* must have bits [3-0] == 0x0F */
45 VectorAPIC = 65, /* external APIC interrupts */
50 Vctl* next; /* handlers on this vector */
52 char name[KNAMELEN]; /* of driver */
53 int isintr; /* interrupt or fault/trap */
56 int (*isr)(int); /* get isr bit for this irq */
57 int (*eoi)(int); /* eoi */
59 void (*f)(Ureg*, void*); /* handler to call */
60 void* a; /* argument to call it with */
64 BusCBUS = 0, /* Corollary CBUS */
65 BusCBUSII, /* Corollary CBUS II */
66 BusEISA, /* Extended ISA */
67 BusFUTURE, /* IEEE Futurebus */
68 BusINTERN, /* Internal bus */
69 BusISA, /* Industry Standard Architecture */
70 BusMBI, /* Multibus I */
71 BusMBII, /* Multibus II */
72 BusMCA, /* Micro Channel Architecture */
75 BusNUBUS, /* Apple Macintosh NuBus */
76 BusPCI, /* Peripheral Component Interconnect */
77 BusPCMCIA, /* PC Memory Card International Association */
78 BusTC, /* DEC TurboChannel */
79 BusVL, /* VESA Local bus */
81 BusXPRESS, /* Express System Bus */
84 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
85 #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
86 #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
87 #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
88 #define BUSTYPE(tbdf) ((tbdf)>>24)
89 #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
90 #define BUSUNKNOWN (-1)
100 enum { /* type 0 & type 1 pre-defined header */
101 PciVID = 0x00, /* vendor ID */
102 PciDID = 0x02, /* device ID */
103 PciPCR = 0x04, /* command */
104 PciPSR = 0x06, /* status */
105 PciRID = 0x08, /* revision ID */
106 PciCCRp = 0x09, /* programming interface class code */
107 PciCCRu = 0x0A, /* sub-class code */
108 PciCCRb = 0x0B, /* base class code */
109 PciCLS = 0x0C, /* cache line size */
110 PciLTR = 0x0D, /* latency timer */
111 PciHDT = 0x0E, /* header type */
112 PciBST = 0x0F, /* BIST */
114 PciBAR0 = 0x10, /* base address */
117 PciCAP = 0x34, /* capabilities pointer */
118 PciINTL = 0x3C, /* interrupt line */
119 PciINTP = 0x3D, /* interrupt pin */
122 /* ccrb (base class code) values; controller types */
124 Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
125 Pcibcstore = 1, /* mass storage */
126 Pcibcnet = 2, /* network */
127 Pcibcdisp = 3, /* display */
128 Pcibcmmedia = 4, /* multimedia */
129 Pcibcmem = 5, /* memory */
130 Pcibcbridge = 6, /* bridge */
131 Pcibccomm = 7, /* simple comms (e.g., serial) */
132 Pcibcbasesys = 8, /* base system */
133 Pcibcinput = 9, /* input */
134 Pcibcdock = 0xa, /* docking stations */
135 Pcibcproc = 0xb, /* processors */
136 Pcibcserial = 0xc, /* serial bus (e.g., USB) */
137 Pcibcwireless = 0xd, /* wireless */
138 Pcibcintell = 0xe, /* intelligent i/o */
139 Pcibcsatcom = 0xf, /* satellite comms */
140 Pcibccrypto = 0x10, /* encryption/decryption */
141 Pcibcdacq = 0x11, /* data acquisition & signal proc. */
144 /* ccru (sub-class code) values; common cases only */
147 Pciscscsi = 0, /* SCSI */
148 Pciscide = 1, /* IDE (ATA) */
151 Pciscether = 0, /* Ethernet */
154 Pciscvga = 0, /* VGA */
155 Pciscxga = 1, /* XGA */
156 Pcisc3d = 2, /* 3D */
159 Pcischostpci = 0, /* host/pci */
160 Pciscpcicpci = 1, /* pci/pci */
163 Pciscserial = 0, /* 16450, etc. */
164 Pciscmultiser = 1, /* multiport serial */
167 Pciscusb = 3, /* USB */
170 enum { /* type 0 pre-defined header */
171 PciCIS = 0x28, /* cardbus CIS pointer */
172 PciSVID = 0x2C, /* subsystem vendor ID */
173 PciSID = 0x2E, /* cardbus CIS pointer */
174 PciEBAR0 = 0x30, /* expansion ROM base address */
175 PciMGNT = 0x3E, /* burst period length */
176 PciMLT = 0x3F, /* maximum latency between bursts */
179 enum { /* type 1 pre-defined header */
180 PciPBN = 0x18, /* primary bus number */
181 PciSBN = 0x19, /* secondary bus number */
182 PciUBN = 0x1A, /* subordinate bus number */
183 PciSLTR = 0x1B, /* secondary latency timer */
184 PciIBR = 0x1C, /* I/O base */
185 PciILR = 0x1D, /* I/O limit */
186 PciSPSR = 0x1E, /* secondary status */
187 PciMBR = 0x20, /* memory base */
188 PciMLR = 0x22, /* memory limit */
189 PciPMBR = 0x24, /* prefetchable memory base */
190 PciPMLR = 0x26, /* prefetchable memory limit */
191 PciPUBR = 0x28, /* prefetchable base upper 32 bits */
192 PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
193 PciIUBR = 0x30, /* I/O base upper 16 bits */
194 PciIULR = 0x32, /* I/O limit upper 16 bits */
195 PciEBAR1 = 0x28, /* expansion ROM base address */
196 PciBCR = 0x3E, /* bridge control register */
199 enum { /* type 2 pre-defined header */
202 PciCBPBN = 0x18, /* primary bus number */
203 PciCBSBN = 0x19, /* secondary bus number */
204 PciCBUBN = 0x1A, /* subordinate bus number */
205 PciCBSLTR = 0x1B, /* secondary latency timer */
210 PciCBIBR0 = 0x2C, /* I/O base */
211 PciCBILR0 = 0x30, /* I/O limit */
212 PciCBIBR1 = 0x34, /* I/O base */
213 PciCBILR1 = 0x38, /* I/O limit */
214 PciCBSVID = 0x40, /* subsystem vendor ID */
215 PciCBSID = 0x42, /* subsystem ID */
216 PciCBLMBAR = 0x44, /* legacy mode base address */
221 PciCapPMG = 0x01, /* power management */
223 PciCapVPD = 0x03, /* vital product data */
224 PciCapSID = 0x04, /* slot id */
226 PciCapCHS = 0x06, /* compact pci hot swap */
228 PciCapHTC = 0x08, /* hypertransport irq conf */
229 PciCapVND = 0x09, /* vendor specific information */
233 PciCapHSW = 0x0c, /* hot swap */
236 typedef struct Pcisiz Pcisiz;
244 typedef struct Pcidev Pcidev;
247 int tbdf; /* type+bus+device+function */
248 ushort vid; /* vendor ID */
249 ushort did; /* device ID */
261 ulong bar; /* base address */
269 uchar intl; /* interrupt line */
272 Pcidev* link; /* next device on this bno */
274 Pcidev* parent; /* up a bus */
275 Pcidev* bridge; /* down a bus */
281 int pmrb; /* power management register block */
291 #define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
293 #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
295 /* SMBus transactions */
298 SMBquick, /* sends address only */
301 SMBsend, /* sends address and cmd */
302 SMBbytewrite, /* sends address and cmd and 1 byte */
303 SMBwordwrite, /* sends address and cmd and 2 bytes */
306 SMBrecv, /* sends address, recvs 1 byte */
307 SMBbyteread, /* sends address and cmd, recv's byte */
308 SMBwordread, /* sends address and cmd, recv's 2 bytes */
311 typedef struct SMBus SMBus;
314 Rendez r; /* rendezvous point for completion interrupts */
315 void *arg; /* implementation dependent */
316 ulong base; /* port or memory base of smbus */
318 void (*transact)(SMBus*, int, int, int, uchar*);
322 * PCMCIA support code.
325 typedef struct PCMslot PCMslot;
326 typedef struct PCMconftab PCMconftab;
329 * Map between ISA memory space and PCMCIA card memory space.
332 ulong ca; /* card address */
333 ulong cea; /* card end address */
334 ulong isa; /* ISA address */
335 int len; /* length of the ISA area */
336 int attr; /* attribute memory */
340 /* configuration table entry */
344 ushort irqs; /* legal irqs */
346 uchar bit16; /* true for 16 bit access */
366 void *cp; /* controller for this slot */
367 long memlen; /* memory length */
368 uchar base; /* index register base */
369 uchar slotno; /* slot number */
372 uchar special; /* in use for a special device */
373 uchar already; /* already inited */
383 ulong msec; /* time of last slotinfo call */
384 char verstr[512]; /* version string */
385 int ncfg; /* number of configurations */
387 ushort cpresent; /* config registers present */
388 ulong caddr; /* relative address of config registers */
390 int nctab; /* number of config table entries */
392 PCMconftab *def; /* default conftab */
395 Lock mlock; /* lock down the maps */
397 PCMmap mmap[4]; /* maps, last is always for the kernel */
400 #pragma varargck type "T" int
401 #pragma varargck type "T" uint