sys/src/9/pc/i8259.c

   1 #include "u.h"
   2 #include "../port/lib.h"
   3 #include "mem.h"
   4 #include "dat.h"
   5 #include "fns.h"
   6 #include "io.h"
   7
   8 /*
   9  *  8259 interrupt controllers
  10  */
  11 enum
  12 {
  13         Int0ctl=        0x20,           /* control port (ICW1, OCW2, OCW3) */
  14         Int0aux=        0x21,           /* everything else (ICW2, ICW3, ICW4, OCW1) */
  15         Int1ctl=        0xA0,           /* control port */
  16         Int1aux=        0xA1,           /* everything else (ICW2, ICW3, ICW4, OCW1) */
  17
  18         Icw1=           0x10,           /* select bit in ctl register */
  19         Ocw2=           0x00,
  20         Ocw3=           0x08,
  21
  22         EOI=            0x20,           /* non-specific end of interrupt */
  23
  24         Elcr1=          0x4D0,          /* Edge/Level Triggered Register */
  25         Elcr2=          0x4D1,
  26 };
  27
  28 static Lock i8259lock;
  29 static int i8259mask = 0xFFFF;          /* disabled interrupts */
  30 int i8259elcr;                          /* mask of level-triggered interrupts */
  31
  32 void
  33 i8259init(void)
  34 {
  35         int x;
  36
  37         ioalloc(Int0ctl, 2, 0, "i8259.0");
  38         ioalloc(Int1ctl, 2, 0, "i8259.1");
  39         ilock(&i8259lock);
  40
  41         /*
  42          *  Set up the first 8259 interrupt processor.
  43          *  Make 8259 interrupts start at CPU vector VectorPIC.
  44          *  Set the 8259 as master with edge triggered
  45          *  input with fully nested interrupts.
  46          */
  47         outb(Int0ctl, (1<<4)|(0<<3)|(1<<0));    /* ICW1 - master, edge triggered,
  48                                                    ICW4 will be sent */
  49         outb(Int0aux, VectorPIC);               /* ICW2 - interrupt vector offset */
  50         outb(Int0aux, 0x04);                    /* ICW3 - have slave on level 2 */
  51         outb(Int0aux, 0x01);                    /* ICW4 - 8086 mode, not buffered */
  52
  53         /*
  54          *  Set up the second 8259 interrupt processor.
  55          *  Make 8259 interrupts start at CPU vector VectorPIC+8.
  56          *  Set the 8259 as slave with edge triggered
  57          *  input with fully nested interrupts.
  58          */
  59         outb(Int1ctl, (1<<4)|(0<<3)|(1<<0));    /* ICW1 - master, edge triggered,
  60                                                    ICW4 will be sent */
  61         outb(Int1aux, VectorPIC+8);             /* ICW2 - interrupt vector offset */
  62         outb(Int1aux, 0x02);                    /* ICW3 - I am a slave on level 2 */
  63         outb(Int1aux, 0x01);                    /* ICW4 - 8086 mode, not buffered */
  64         outb(Int1aux, (i8259mask>>8) & 0xFF);
  65
  66         /*
  67          *  pass #2 8259 interrupts to #1
  68          */
  69         i8259mask &= ~0x04;
  70         outb(Int0aux, i8259mask & 0xFF);
  71
  72         /*
  73          * Set Ocw3 to return the ISR when ctl read.
  74          * After initialisation status read is set to IRR.
  75          * Read IRR first to possibly deassert an outstanding
  76          * interrupt.
  77          */
  78         inb(Int0ctl);
  79         outb(Int0ctl, Ocw3|0x03);
  80         inb(Int1ctl);
  81         outb(Int1ctl, Ocw3|0x03);
  82
  83         /*
  84          * Check for Edge/Level register.
  85          * This check may not work for all chipsets.
  86          * First try a non-intrusive test - the bits for
  87          * IRQs 13, 8, 2, 1 and 0 must be edge (0). If
  88          * that's OK try a R/W test.
  89          */
  90         x = (inb(Elcr2)<<8)|inb(Elcr1);
  91         if(!(x & 0x2107)){
  92                 outb(Elcr1, 0);
  93                 if(inb(Elcr1) == 0){
  94                         outb(Elcr1, 0x20);
  95                         if(inb(Elcr1) == 0x20)
  96                                 i8259elcr = x;
  97                         outb(Elcr1, x & 0xFF);
  98                         print("ELCR: %4.4uX\n", i8259elcr);
  99                 }
 100         }
 101         iunlock(&i8259lock);
 102 }
 103
 104 int
 105 i8259isr(int vno)
 106 {
 107         int irq, isr;
 108
 109         if(vno < VectorPIC || vno > VectorPIC+MaxIrqPIC)
 110                 return 0;
 111         irq = vno-VectorPIC;
 112
 113         /*
 114          *  tell the 8259 that we're done with the
 115          *  highest level interrupt (interrupts are still
 116          *  off at this point)
 117          */
 118         ilock(&i8259lock);
 119         isr = inb(Int0ctl);
 120         outb(Int0ctl, EOI);
 121         if(irq >= 8){
 122                 isr |= inb(Int1ctl)<<8;
 123                 outb(Int1ctl, EOI);
 124         }
 125         iunlock(&i8259lock);
 126
 127         return isr & (1<<irq);
 128 }
 129
 130 int
 131 i8259enable(Vctl* v)
 132 {
 133         int irq, irqbit;
 134
 135         /*
 136          * Given an IRQ, enable the corresponding interrupt in the i8259
 137          * and return the vector to be used. The i8259 is set to use a fixed
 138          * range of vectors starting at VectorPIC.
 139          */
 140         irq = v->irq;
 141         if(irq < 0 || irq > MaxIrqPIC){
 142                 print("i8259enable: irq %d out of range\n", irq);
 143                 return -1;
 144         }
 145         irqbit = 1<<irq;
 146
 147         ilock(&i8259lock);
 148         if(!(i8259mask & irqbit) && !(i8259elcr & irqbit)){
 149                 print("i8259enable: irq %d shared but not level\n", irq);
 150                 iunlock(&i8259lock);
 151                 return -1;
 152         }
 153         i8259mask &= ~irqbit;
 154         if(irq < 8)
 155                 outb(Int0aux, i8259mask & 0xFF);
 156         else
 157                 outb(Int1aux, (i8259mask>>8) & 0xFF);
 158
 159         if(i8259elcr & irqbit)
 160                 v->eoi = i8259isr;
 161         else
 162                 v->isr = i8259isr;
 163         iunlock(&i8259lock);
 164
 165         return VectorPIC+irq;
 166 }
 167
 168 int
 169 i8259vecno(int irq)
 170 {
 171         return VectorPIC+irq;
 172 }
 173
 174 int
 175 i8259disable(int irq)
 176 {
 177         int irqbit;
 178
 179         /*
 180          * Given an IRQ, disable the corresponding interrupt
 181          * in the 8259.
 182          */
 183         if(irq < 0 || irq > MaxIrqPIC){
 184                 print("i8259disable: irq %d out of range\n", irq);
 185                 return -1;
 186         }
 187         irqbit = 1<<irq;
 188
 189         ilock(&i8259lock);
 190         if(!(i8259mask & irqbit)){
 191                 i8259mask |= irqbit;
 192                 if(irq < 8)
 193                         outb(Int0aux, i8259mask & 0xFF);
 194                 else
 195                         outb(Int1aux, (i8259mask>>8) & 0xFF);
 196         }
 197         iunlock(&i8259lock);
 198         return 0;
 199 }
 200
 201 void
 202 i8259on(void)
 203 {
 204         outb(Int0aux, i8259mask&0xFF);
 205         outb(Int1aux, (i8259mask>>8)&0xFF);
 206 }
 207
 208 void
 209 i8259off(void)
 210 {
 211         outb(Int0aux, 0xFF);
 212         outb(Int1aux, 0xFF);
 213 }
 214