2 #include "../port/lib.h"
9 * 8259 interrupt controllers
13 Int0ctl= 0x20, /* control port (ICW1, OCW2, OCW3) */
14 Int0aux= 0x21, /* everything else (ICW2, ICW3, ICW4, OCW1) */
15 Int1ctl= 0xA0, /* control port */
16 Int1aux= 0xA1, /* everything else (ICW2, ICW3, ICW4, OCW1) */
18 Icw1= 0x10, /* select bit in ctl register */
22 EOI= 0x20, /* non-specific end of interrupt */
24 Elcr1= 0x4D0, /* Edge/Level Triggered Register */
28 static Lock i8259lock;
29 static int i8259mask = 0xFFFF; /* disabled interrupts */
30 int i8259elcr; /* mask of level-triggered interrupts */
37 ioalloc(Int0ctl, 2, 0, "i8259.0");
38 ioalloc(Int1ctl, 2, 0, "i8259.1");
42 * Set up the first 8259 interrupt processor.
43 * Make 8259 interrupts start at CPU vector VectorPIC.
44 * Set the 8259 as master with edge triggered
45 * input with fully nested interrupts.
47 outb(Int0ctl, (1<<4)|(0<<3)|(1<<0)); /* ICW1 - master, edge triggered,
49 outb(Int0aux, VectorPIC); /* ICW2 - interrupt vector offset */
50 outb(Int0aux, 0x04); /* ICW3 - have slave on level 2 */
51 outb(Int0aux, 0x01); /* ICW4 - 8086 mode, not buffered */
54 * Set up the second 8259 interrupt processor.
55 * Make 8259 interrupts start at CPU vector VectorPIC+8.
56 * Set the 8259 as slave with edge triggered
57 * input with fully nested interrupts.
59 outb(Int1ctl, (1<<4)|(0<<3)|(1<<0)); /* ICW1 - master, edge triggered,
61 outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */
62 outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */
63 outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */
64 outb(Int1aux, (i8259mask>>8) & 0xFF);
67 * pass #2 8259 interrupts to #1
70 outb(Int0aux, i8259mask & 0xFF);
73 * Set Ocw3 to return the ISR when ctl read.
74 * After initialisation status read is set to IRR.
75 * Read IRR first to possibly deassert an outstanding
79 outb(Int0ctl, Ocw3|0x03);
81 outb(Int1ctl, Ocw3|0x03);
84 * Check for Edge/Level register.
85 * This check may not work for all chipsets.
86 * First try a non-intrusive test - the bits for
87 * IRQs 13, 8, 2, 1 and 0 must be edge (0). If
88 * that's OK try a R/W test.
90 x = (inb(Elcr2)<<8)|inb(Elcr1);
95 if(inb(Elcr1) == 0x20)
97 outb(Elcr1, x & 0xFF);
98 print("ELCR: %4.4uX\n", i8259elcr);
109 if(vno < VectorPIC || vno > VectorPIC+MaxIrqPIC)
114 * tell the 8259 that we're done with the
115 * highest level interrupt (interrupts are still
122 isr |= inb(Int1ctl)<<8;
127 return isr & (1<<irq);
136 * Given an IRQ, enable the corresponding interrupt in the i8259
137 * and return the vector to be used. The i8259 is set to use a fixed
138 * range of vectors starting at VectorPIC.
141 if(irq < 0 || irq > MaxIrqPIC){
142 print("i8259enable: irq %d out of range\n", irq);
148 if(!(i8259mask & irqbit) && !(i8259elcr & irqbit)){
149 print("i8259enable: irq %d shared but not level\n", irq);
153 i8259mask &= ~irqbit;
155 outb(Int0aux, i8259mask & 0xFF);
157 outb(Int1aux, (i8259mask>>8) & 0xFF);
159 if(i8259elcr & irqbit)
165 return VectorPIC+irq;
171 return VectorPIC+irq;
175 i8259disable(int irq)
180 * Given an IRQ, disable the corresponding interrupt
183 if(irq < 0 || irq > MaxIrqPIC){
184 print("i8259disable: irq %d out of range\n", irq);
190 if(!(i8259mask & irqbit)){
193 outb(Int0aux, i8259mask & 0xFF);
195 outb(Int1aux, (i8259mask>>8) & 0xFF);
204 outb(Int0aux, i8259mask&0xFF);
205 outb(Int1aux, (i8259mask>>8)&0xFF);