2 * VIA VT6102 Fast Ethernet Controller (Rhine II).
4 * cache-line size alignments - done
6 * use 2 descriptors on tx for alignment - done
7 * reorganise initialisation/shutdown/reset
8 * adjust Tx FIFO threshold on underflow - untested
9 * why does the link status never cause an interrupt?
10 * use the lproc as a periodic timer for stalls, etc.
13 #include "../port/lib.h"
18 #include "../port/error.h"
19 #include "../port/netif.h"
25 Par0 = 0x00, /* Ethernet Address */
26 Rcr = 0x06, /* Receive Configuration */
27 Tcr = 0x07, /* Transmit Configuration */
28 Cr = 0x08, /* Control */
29 Isr = 0x0C, /* Interrupt Status */
30 Imr = 0x0E, /* Interrupt Mask */
31 Mcfilt0 = 0x10, /* Multicast Filter 0 */
32 Mcfilt1 = 0x14, /* Multicast Filter 1 */
33 Rxdaddr = 0x18, /* Current Rx Descriptor Address */
34 Txdaddr = 0x1C, /* Current Tx Descriptor Address */
35 Phyadr = 0x6C, /* Phy Address */
36 Miisr = 0x6D, /* MII Status */
37 Bcr0 = 0x6E, /* Bus Control */
39 Miicr = 0x70, /* MII Control */
40 Miiadr = 0x71, /* MII Address */
41 Miidata = 0x72, /* MII Data */
42 Eecsr = 0x74, /* EEPROM Control and Status */
43 Stickhw = 0x83, /* Sticky Hardware Control */
50 Sep = 0x01, /* Accept Error Packets */
51 Ar = 0x02, /* Accept Small Packets */
52 Am = 0x04, /* Accept Multicast */
53 Ab = 0x08, /* Accept Broadcast */
54 Prom = 0x10, /* Accept Physical Address Packets */
55 RrftMASK = 0xE0, /* Receive FIFO Threshold */
57 Rrft64 = 0<<RrftSHIFT,
58 Rrft32 = 1<<RrftSHIFT,
59 Rrft128 = 2<<RrftSHIFT,
60 Rrft256 = 3<<RrftSHIFT,
61 Rrft512 = 4<<RrftSHIFT,
62 Rrft768 = 5<<RrftSHIFT,
63 Rrft1024 = 6<<RrftSHIFT,
64 RrftSAF = 7<<RrftSHIFT,
68 Lb0 = 0x02, /* Loopback Mode */
70 Ofset = 0x08, /* Back-off Priority Selection */
71 RtsfMASK = 0xE0, /* Transmit FIFO Threshold */
73 Rtsf128 = 0<<RtsfSHIFT,
74 Rtsf256 = 1<<RtsfSHIFT,
75 Rtsf512 = 2<<RtsfSHIFT,
76 Rtsf1024 = 3<<RtsfSHIFT,
77 RtsfSAF = 7<<RtsfSHIFT,
81 Init = 0x0001, /* INIT Process Begin */
82 Strt = 0x0002, /* Start NIC */
83 Stop = 0x0004, /* Stop NIC */
84 Rxon = 0x0008, /* Turn on Receive Process */
85 Txon = 0x0010, /* Turn on Transmit Process */
86 Tdmd = 0x0020, /* Transmit Poll Demand */
87 Rdmd = 0x0040, /* Receive Poll Demand */
88 Eren = 0x0100, /* Early Receive Enable */
89 Fdx = 0x0400, /* Set MAC to Full Duplex Mode */
90 Dpoll = 0x0800, /* Disable Td/Rd Auto Polling */
91 Tdmd1 = 0x2000, /* Transmit Poll Demand 1 */
92 Rdmd1 = 0x4000, /* Receive Poll Demand 1 */
93 Sfrst = 0x8000, /* Software Reset */
97 Prx = 0x0001, /* Received Packet Successfully */
98 Ptx = 0x0002, /* Transmitted Packet Successfully */
99 Rxe = 0x0004, /* Receive Error */
100 Txe = 0x0008, /* Transmit Error */
101 Tu = 0x0010, /* Transmit Buffer Underflow */
102 Ru = 0x0020, /* Receive Buffer Link Error */
103 Be = 0x0040, /* PCI Bus Error */
104 Cnt = 0x0080, /* Counter Overflow */
105 Eri = 0x0100, /* Early Receive Interrupt */
106 Udfi = 0x0200, /* Tx FIFO Underflow */
107 Ovfi = 0x0400, /* Receive FIFO Overflow */
108 Pktrace = 0x0800, /* Hmmm... */
109 Norbf = 0x1000, /* No Receive Buffers */
110 Abti = 0x2000, /* Transmission Abort */
111 Srci = 0x4000, /* Port State Change */
112 Geni = 0x8000, /* General Purpose Interrupt */
116 PhyadMASK = 0x1F, /* PHY Address */
118 Mfdc = 0x20, /* Accelerate MDC Speed */
119 Mpo0 = 0x40, /* MII Polling Timer Interval */
124 DmaMASK = 0x07, /* DMA Length */
128 Dma128 = 2<<DmaSHIFT,
129 Dma256 = 3<<DmaSHIFT,
130 Dma512 = 4<<DmaSHIFT,
131 Dma1024 = 5<<DmaSHIFT,
132 DmaSAF = 7<<DmaSHIFT,
133 CrftMASK = 0x38, /* Rx FIFO Threshold */
135 Crft64 = 1<<CrftSHIFT,
136 Crft128 = 2<<CrftSHIFT,
137 Crft256 = 3<<CrftSHIFT,
138 Crft512 = 4<<CrftSHIFT,
139 Crft1024 = 5<<CrftSHIFT,
140 CrftSAF = 7<<CrftSHIFT,
141 Extled = 0x40, /* Extra LED Support Control */
142 Med2 = 0x80, /* Medium Select Control */
146 PotMASK = 0x07, /* Polling Timer Interval */
148 CtftMASK = 0x38, /* Tx FIFO Threshold */
150 Ctft64 = 1<<CtftSHIFT,
151 Ctft128 = 2<<CtftSHIFT,
152 Ctft256 = 3<<CtftSHIFT,
153 Ctft512 = 4<<CtftSHIFT,
154 Ctft1024 = 5<<CtftSHIFT,
155 CtftSAF = 7<<CtftSHIFT,
159 Mdc = 0x01, /* Clock */
160 Mdi = 0x02, /* Data In */
161 Mdo = 0x04, /* Data Out */
162 Mout = 0x08, /* Output Enable */
163 Mdpm = 0x10, /* Direct Program Mode Enable */
164 Wcmd = 0x20, /* Write Enable */
165 Rcmd = 0x40, /* Read Enable */
166 Mauto = 0x80, /* Auto Polling Enable */
170 MadMASK = 0x1F, /* MII Port Address */
172 Mdone = 0x20, /* Accelerate MDC Speed */
173 Msrcen = 0x40, /* MII Polling Timer Interval */
178 Edo = 0x01, /* Data Out */
179 Edi = 0x02, /* Data In */
180 Eck = 0x04, /* Clock */
181 Ecs = 0x08, /* Chip Select */
182 Dpm = 0x10, /* Direct Program Mode Enable */
183 Autold = 0x20, /* Dynamic Reload */
184 Embp = 0x40, /* Embedded Program Enable */
185 Eepr = 0x80, /* Programmed */
189 * Ring descriptor. The space allocated for each
190 * of these will be rounded up to a cache-line boundary.
191 * The first 4 elements are known to the hardware.
193 typedef struct Ds Ds;
206 enum { /* Rx Ds status */
207 Rerr = 0x00000001, /* Receiver Error */
208 Crc = 0x00000002, /* CRC Error */
209 Fae = 0x00000004, /* Frame Alignment Error */
210 Fov = 0x00000008, /* FIFO Overflow */
211 Long = 0x00000010, /* A Long Packet */
212 Runt = 0x00000020, /* A Runt Packet */
213 Rxserr = 0x00000040, /* System Error */
214 Buff = 0x00000080, /* Buffer Underflow Error */
215 Rxedp = 0x00000100, /* End of Packet Buffer */
216 Rxstp = 0x00000200, /* Packet Start */
217 Chn = 0x00000400, /* Chain Buffer */
218 Phy = 0x00000800, /* Physical Address Packet */
219 Bar = 0x00001000, /* Broadcast Packet */
220 Mar = 0x00002000, /* Multicast Packet */
221 Rxok = 0x00008000, /* Packet Received Successfully */
222 LengthMASK = 0x07FF0000, /* Received Packet Length */
225 Own = 0x80000000, /* Descriptor Owned by NIC */
228 enum { /* Tx Ds status */
229 NcrMASK = 0x0000000F, /* Collision Retry Count */
231 Cols = 0x00000010, /* Experienced Collisions */
232 Cdh = 0x00000080, /* CD Heartbeat */
233 Abt = 0x00000100, /* Aborted after Excessive Collisions */
234 Owc = 0x00000200, /* Out of Window Collision Seen */
235 Crs = 0x00000400, /* Carrier Sense Lost */
236 Udf = 0x00000800, /* FIFO Underflow */
237 Tbuff = 0x00001000, /* Invalid Td */
238 Txserr = 0x00002000, /* System Error */
239 Terr = 0x00008000, /* Excessive Collisions */
242 enum { /* Tx Ds control */
243 TbsMASK = 0x000007FF, /* Tx Buffer Size */
245 Chain = 0x00008000, /* Chain Buffer */
246 Crcdisable = 0x00010000, /* Disable CRC generation */
247 Stp = 0x00200000, /* Start of Packet */
248 Edp = 0x00400000, /* End of Packet */
249 Ic = 0x00800000, /* Assert Interrupt Immediately */
255 Rdbsz = ROUNDUP(ETHERMAXTU+4, 4),
263 typedef struct Ctlr Ctlr;
264 typedef struct Ctlr {
272 QLock alock; /* attach */
273 void* alloc; /* receive/transmit descriptors */
274 int cls; /* alignment */
290 int tft; /* Tx threshold */
296 uint rxstats[Nrxstats]; /* statistics */
297 uint txstats[Ntxstats];
309 static Ctlr* vt6102ctlrhead;
310 static Ctlr* vt6102ctlrtail;
312 #define csr8r(c, r) (inb((c)->port+(r)))
313 #define csr16r(c, r) (ins((c)->port+(r)))
314 #define csr32r(c, r) (inl((c)->port+(r)))
315 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
316 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
317 #define csr32w(c, r, w) (outl((c)->port+(r), (ulong)(w)))
319 static char* rxstats[Nrxstats] = {
322 "Frame Alignment Error",
327 "Buffer Underflow Error",
329 static char* txstats[Ntxstats] = {
330 "Aborted after Excessive Collisions",
331 "Out of Window Collision Seen",
332 "Carrier Sense Lost",
337 "Excessive Collisions",
341 vt6102ifstat(Ether* edev, void* a, long n, ulong offset)
349 p = smalloc(READSTR);
351 for(i = 0; i < Nrxstats; i++){
352 l += snprint(p+l, READSTR-l, "%s: %ud\n",
353 rxstats[i], ctlr->rxstats[i]);
355 for(i = 0; i < Ntxstats; i++){
356 if(txstats[i] == nil)
358 l += snprint(p+l, READSTR-l, "%s: %ud\n",
359 txstats[i], ctlr->txstats[i]);
361 l += snprint(p+l, READSTR-l, "cls: %ud\n", ctlr->cls);
362 l += snprint(p+l, READSTR-l, "intr: %ud\n", ctlr->intr);
363 l += snprint(p+l, READSTR-l, "lintr: %ud\n", ctlr->lintr);
364 l += snprint(p+l, READSTR-l, "lsleep: %ud\n", ctlr->lsleep);
365 l += snprint(p+l, READSTR-l, "rintr: %ud\n", ctlr->rintr);
366 l += snprint(p+l, READSTR-l, "tintr: %ud\n", ctlr->tintr);
367 l += snprint(p+l, READSTR-l, "taligned: %ud\n", ctlr->taligned);
368 l += snprint(p+l, READSTR-l, "tsplit: %ud\n", ctlr->tsplit);
369 l += snprint(p+l, READSTR-l, "tcopied: %ud\n", ctlr->tcopied);
370 l += snprint(p+l, READSTR-l, "txdw: %ud\n", ctlr->txdw);
371 l += snprint(p+l, READSTR-l, "tft: %ud\n", ctlr->tft);
373 if(ctlr->mii != nil && ctlr->mii->curphy != nil){
374 l += snprint(p+l, READSTR, "phy: ");
375 for(i = 0; i < NMiiPhyr; i++){
376 if(i && ((i & 0x07) == 0))
377 l += snprint(p+l, READSTR-l, "\n ");
378 r = miimir(ctlr->mii, i);
379 l += snprint(p+l, READSTR-l, " %4.4uX", r);
381 snprint(p+l, READSTR-l, "\n");
383 snprint(p+l, READSTR-l, "\n");
385 n = readstr(offset, a, n, p);
392 vt6102promiscuous(void* arg, int on)
400 rcr = csr8r(ctlr, Rcr);
405 csr8w(ctlr, Rcr, rcr);
409 vt6102multicast(void* arg, uchar* addr, int on)
412 * For now Am is set in Rcr.
413 * Will need to interlock with promiscuous
414 * when this gets filled in.
420 vt6102wakeup(void* v)
422 return *((int*)v) != 0;
426 vt6102imr(Ctlr* ctlr, int imr)
430 csr16w(ctlr, Imr, ctlr->imr);
431 iunlock(&ctlr->clock);
435 vt6102lproc(void* arg)
444 if(ctlr->mii == nil || ctlr->mii->curphy == nil)
446 if(miistatus(ctlr->mii) < 0)
449 phy = ctlr->mii->curphy;
455 csr16w(ctlr, Cr, ctlr->cr);
456 iunlock(&ctlr->clock);
459 vt6102imr(ctlr, Srci);
462 sleep(&ctlr->lrendez, vt6102wakeup, &ctlr->lwakeup);
465 pexit("vt6102lproc: done", 1);
469 vt6102attach(Ether* edev)
474 uchar *alloc, *bounce;
479 if(ctlr->alloc != nil){
480 qunlock(&ctlr->alock);
485 * Descriptor and bounce-buffer space.
486 * Must all be aligned on a 4-byte boundary,
487 * but try to align on cache-lines.
491 dsz = ROUNDUP(sizeof(Ds), ctlr->cls);
492 alloc = mallocalign((ctlr->nrd+ctlr->ntd)*dsz + ctlr->ntd*Txcopy, dsz, 0, 0);
494 qunlock(&ctlr->alock);
499 ctlr->rd = (Ds*)alloc;
503 for(i = 0; i < ctlr->nrd; i++){
508 if((ds = ds->next) == nil)
513 qunlock(&ctlr->alock);
517 prev = ctlr->rd + ctlr->nrd-1;
518 for(i = 0; i < ctlr->nrd; i++){
523 ds->branch = PCIWADDR(alloc);
525 ds->bp = iallocb(Rdbsz+3);
527 error("vt6102: can't allocate receive ring\n");
528 ds->bp->rp = (uchar*)ROUNDUP((ulong)ds->bp->rp, 4);
529 ds->addr = PCIWADDR(ds->bp->rp);
531 ds->next = (Ds*)alloc;
538 prev->next = ctlr->rd;
540 ctlr->rdh = ctlr->rd;
542 ctlr->td = (Ds*)alloc;
543 prev = ctlr->td + ctlr->ntd-1;
544 bounce = alloc + ctlr->ntd*dsz;
545 for(i = 0; i < ctlr->ntd; i++){
551 ds->next = (Ds*)alloc;
555 prev->next = ctlr->td;
556 ctlr->tdh = ctlr->tdt = ctlr->td;
559 ctlr->cr = Dpoll|Rdmd|Txon|Rxon|Strt;
560 /*Srci|Abti|Norbf|Pktrace|Ovfi|Udfi|Be|Ru|Tu|Txe|Rxe|Ptx|Prx*/
561 ctlr->imr = Abti|Norbf|Pktrace|Ovfi|Udfi|Be|Ru|Tu|Txe|Rxe|Ptx|Prx;
564 csr32w(ctlr, Rxdaddr, PCIWADDR(ctlr->rd));
565 csr32w(ctlr, Txdaddr, PCIWADDR(ctlr->td));
566 csr16w(ctlr, Isr, ~0);
567 csr16w(ctlr, Imr, ctlr->imr);
568 csr16w(ctlr, Cr, ctlr->cr);
569 iunlock(&ctlr->clock);
571 snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno);
572 kproc(name, vt6102lproc, edev);
574 qunlock(&ctlr->alock);
579 vt6102transmit(Ether* edev)
584 int control, i, o, prefix, size, tdused, timeo;
591 * Free any completed packets
594 for(tdused = ctlr->tdused; tdused > 0; tdused--){
596 * For some errors the chip will turn the Tx engine
597 * off. Wait for that to happen.
598 * Could reset and re-init the chip here if it doesn't
600 * To do: adjust Tx FIFO threshold on underflow.
602 if(ds->status & (Abt|Tbuff|Udf)){
603 for(timeo = 0; timeo < 1000; timeo++){
604 if(!(csr16r(ctlr, Cr) & Txon))
609 csr32w(ctlr, Txdaddr, PCIWADDR(ds));
621 for(i = 0; i < Ntxstats-1; i++){
622 if(ds->status & (1<<i))
625 ctlr->txstats[i] += (ds->status & NcrMASK)>>NcrSHIFT;
632 * Try to fill the ring back up.
635 while(tdused < ctlr->ntd-2){
636 if((bp = qget(edev->oq)) == nil)
643 if(o = (((int)bp->rp) & 0x03)){
647 memmove(ds->bounce, bp->rp, prefix);
648 ds->addr = PCIWADDR(ds->bounce);
654 ds->branch = PCIWADDR(ds->next);
659 next->addr = PCIWADDR(bp->rp);
660 next->branch = PCIWADDR(next->next);
661 next->control = Edp|Chain|((size<<TbsSHIFT) & TbsMASK);
663 control = Stp|Chain|((prefix<<TbsSHIFT) & TbsMASK);
671 ds->addr = PCIWADDR(bp->rp);
672 control = Edp|Stp|((size<<TbsSHIFT) & TbsMASK);
678 control = Edp|Stp|((prefix<<TbsSHIFT) & TbsMASK);
682 ds->control = control;
683 if(tdused >= ctlr->ntd-2){
693 ctlr->tdused = tdused;
695 csr16w(ctlr, Cr, Tdmd|ctlr->cr);
697 iunlock(&ctlr->tlock);
701 vt6102receive(Ether* edev)
711 while(!(ds->status & Own) && ds->status != 0){
712 if(ds->status & Rerr){
713 for(i = 0; i < Nrxstats; i++){
714 if(ds->status & (1<<i))
718 else if(bp = iallocb(Rdbsz+3)){
719 len = ((ds->status & LengthMASK)>>LengthSHIFT)-4;
720 ds->bp->wp = ds->bp->rp+len;
721 etheriq(edev, ds->bp, 1);
722 bp->rp = (uchar*)ROUNDUP((ulong)bp->rp, 4);
723 ds->addr = PCIWADDR(bp->rp);
730 ds->prev->branch = PCIWADDR(ds);
732 ds->prev->status = Own;
738 csr16w(ctlr, Cr, ctlr->cr);
742 vt6102interrupt(Ureg*, void* arg)
746 int imr, isr, r, timeo;
752 csr16w(ctlr, Imr, 0);
756 if((isr = csr16r(ctlr, Isr)) != 0)
757 csr16w(ctlr, Isr, isr);
758 if((isr & ctlr->imr) == 0)
763 ctlr->lwakeup = isr & Srci;
764 wakeup(&ctlr->lrendez);
768 if(isr & (Norbf|Pktrace|Ovfi|Ru|Rxe|Prx)){
770 isr &= ~(Norbf|Pktrace|Ovfi|Ru|Rxe|Prx);
773 if(isr & (Abti|Udfi|Tu|Txe|Ptx)){
774 if(isr & (Abti|Udfi|Tu)){
775 for(timeo = 0; timeo < 1000; timeo++){
776 if(!(csr16r(ctlr, Cr) & Txon))
781 if((isr & Udfi) && ctlr->tft < CtftSAF){
782 ctlr->tft += 1<<CtftSHIFT;
783 r = csr8r(ctlr, Bcr1) & ~CtftMASK;
784 csr8w(ctlr, Bcr1, r|ctlr->tft);
787 vt6102transmit(edev);
788 isr &= ~(Abti|Udfi|Tu|Txe|Ptx);
792 panic("vt6102: isr %4.4uX", isr);
795 csr16w(ctlr, Imr, ctlr->imr);
796 iunlock(&ctlr->clock);
800 vt6102miimicmd(Mii* mii, int pa, int ra, int cmd, int data)
807 csr8w(ctlr, Miicr, 0);
808 r = csr8r(ctlr, Phyadr);
809 csr8w(ctlr, Phyadr, (r & ~PhyadMASK)|pa);
810 csr8w(ctlr, Phyadr, pa);
811 csr8w(ctlr, Miiadr, ra);
813 csr16w(ctlr, Miidata, data);
814 csr8w(ctlr, Miicr, cmd);
816 for(timeo = 0; timeo < 10000; timeo++){
817 if(!(csr8r(ctlr, Miicr) & cmd))
826 return csr16r(ctlr, Miidata);
830 vt6102miimir(Mii* mii, int pa, int ra)
832 return vt6102miimicmd(mii, pa, ra, Rcmd, 0);
836 vt6102miimiw(Mii* mii, int pa, int ra, int data)
838 return vt6102miimicmd(mii, pa, ra, Wcmd, data);
842 vt6102detach(Ctlr* ctlr)
847 * Reset power management registers.
849 revid = pcicfgr8(ctlr->pcidev, PciRID);
851 /* Set power state D0. */
852 csr8w(ctlr, Stickhw, csr8r(ctlr, Stickhw) & 0xFC);
854 /* Disable force PME-enable. */
855 csr8w(ctlr, Wolcgclr, 0x80);
857 /* Clear WOL config and status bits. */
858 csr8w(ctlr, Wolcrclr, 0xFF);
859 csr8w(ctlr, Pwrcsrclr, 0xFF);
863 * Soft reset the controller.
865 csr16w(ctlr, Cr, Stop);
866 csr16w(ctlr, Cr, Stop|Sfrst);
867 for(timeo = 0; timeo < 10000; timeo++){
868 if(!(csr16r(ctlr, Cr) & Sfrst))
879 vt6102reset(Ctlr* ctlr)
884 if(vt6102detach(ctlr) < 0)
888 * Load the MAC address into the PAR[01]
891 r = csr8r(ctlr, Eecsr);
892 csr8w(ctlr, Eecsr, Autold|r);
893 for(timeo = 0; timeo < 100; timeo++){
894 if(!(csr8r(ctlr, Cr) & Autold))
901 for(i = 0; i < Eaddrlen; i++)
902 ctlr->par[i] = csr8r(ctlr, Par0+i);
905 * Configure DMA and Rx/Tx thresholds.
906 * If the Rx/Tx threshold bits in Bcr[01] are 0 then
907 * the thresholds are determined by Rcr/Tcr.
909 r = csr8r(ctlr, Bcr0) & ~(CrftMASK|DmaMASK);
910 csr8w(ctlr, Bcr0, r|Crft64|Dma64);
911 r = csr8r(ctlr, Bcr1) & ~CtftMASK;
912 csr8w(ctlr, Bcr1, r|ctlr->tft);
914 r = csr8r(ctlr, Rcr) & ~(RrftMASK|Prom|Ar|Sep);
915 csr8w(ctlr, Rcr, r|Ab|Am);
916 csr32w(ctlr, Mcfilt0, ~0UL); /* accept all multicast */
917 csr32w(ctlr, Mcfilt1, ~0UL);
919 r = csr8r(ctlr, Tcr) & ~(RtsfMASK|Ofset|Lb1|Lb0);
925 if((ctlr->mii = malloc(sizeof(Mii))) == nil)
927 ctlr->mii->mir = vt6102miimir;
928 ctlr->mii->miw = vt6102miimiw;
929 ctlr->mii->ctlr = ctlr;
931 if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
936 // print("oui %X phyno %d\n", phy->oui, phy->phyno);
939 //miiane(ctlr->mii, ~0, ~0, ~0);
952 while(p = pcimatch(p, 0, 0)){
953 if(p->ccrb != Pcibcnet || p->ccru != Pciscether)
956 switch((p->did<<16)|p->vid){
959 case (0x3065<<16)|0x1106: /* Rhine II */
960 case (0x3106<<16)|0x1106: /* Rhine III */
964 port = p->mem[0].bar & ~0x01;
965 if(ioalloc(port, p->mem[0].size, 0, "vt6102") < 0){
966 print("vt6102: port 0x%uX in use\n", port);
969 ctlr = malloc(sizeof(Ctlr));
971 print("vt6102: can't allocate memory\n");
977 ctlr->id = (p->did<<16)|p->vid;
978 if((cls = pcicfgr8(p, PciCLS)) == 0 || cls == 0xFF)
983 if(vt6102reset(ctlr)){
990 if(vt6102ctlrhead != nil)
991 vt6102ctlrtail->next = ctlr;
993 vt6102ctlrhead = ctlr;
994 vt6102ctlrtail = ctlr;
999 vt6102pnp(Ether* edev)
1003 if(vt6102ctlrhead == nil)
1007 * Any adapter matches if no edev->port is supplied,
1008 * otherwise the ports must match.
1010 for(ctlr = vt6102ctlrhead; ctlr != nil; ctlr = ctlr->next){
1013 if(edev->port == 0 || edev->port == ctlr->port){
1022 edev->port = ctlr->port;
1023 edev->irq = ctlr->pcidev->intl;
1024 edev->tbdf = ctlr->pcidev->tbdf;
1026 memmove(edev->ea, ctlr->par, Eaddrlen);
1029 * Linkage to the generic ethernet driver.
1031 edev->attach = vt6102attach;
1032 edev->transmit = vt6102transmit;
1033 edev->interrupt = vt6102interrupt;
1034 edev->ifstat = vt6102ifstat;
1038 edev->promiscuous = vt6102promiscuous;
1039 edev->multicast = vt6102multicast;
1045 ethervt6102link(void)
1047 addethercard("vt6102", vt6102pnp);
1048 addethercard("rhine", vt6102pnp);