sys/src/9/pc/etheriwl.c

   1 /*
   2  * Intel WiFi Link driver.
   3  *
   4  * Written without any documentation but Damien Bergaminis
   5  * OpenBSD iwn(4) driver sources. Requires intel firmware
   6  * to be present in /lib/firmware/iwn-* on attach.
   7  */
   8
   9 #include "u.h"
  10 #include "../port/lib.h"
  11 #include "mem.h"
  12 #include "dat.h"
  13 #include "fns.h"
  14 #include "io.h"
  15 #include "../port/error.h"
  16 #include "../port/netif.h"
  17
  18 #include "etherif.h"
  19 #include "wifi.h"
  20
  21 enum {
  22         Ntxlog          = 8,
  23         Ntx             = 1<<Ntxlog,
  24         Nrxlog          = 8,
  25         Nrx             = 1<<Nrxlog,
  26
  27         Rstatsize       = 16,
  28         Rbufsize        = 4*1024,
  29         Rdscsize        = 8,
  30
  31         Tbufsize        = 4*1024,
  32         Tdscsize        = 128,
  33         Tcmdsize        = 140,
  34 };
  35
  36 /* registers */
  37 enum {
  38         Cfg             = 0x000,        /* config register */
  39                 MacSi           = 1<<8,
  40                 RadioSi         = 1<<9,
  41                 EepromLocked    = 1<<21,
  42                 NicReady        = 1<<22,
  43                 HapwakeL1A      = 1<<23,
  44                 PrepareDone     = 1<<25,
  45                 Prepare         = 1<<27,
  46
  47         Isr             = 0x008,        /* interrupt status */
  48         Imr             = 0x00c,        /* interrupt mask */
  49                 Ialive          = 1<<0,
  50                 Iwakeup         = 1<<1,
  51                 Iswrx           = 1<<3,
  52                 Ictreached      = 1<<6,
  53                 Irftoggled      = 1<<7,
  54                 Iswerr          = 1<<25,
  55                 Isched          = 1<<26,
  56                 Ifhtx           = 1<<27,
  57                 Irxperiodic     = 1<<28,
  58                 Ihwerr          = 1<<29,
  59                 Ifhrx           = 1<<31,
  60
  61                 Ierr            = Iswerr | Ihwerr,
  62                 Idefmask        = Ierr | Ifhtx | Ifhrx | Ialive | Iwakeup | Iswrx | Ictreached | Irftoggled,
  63
  64         FhIsr           = 0x010,        /* second interrupt status */
  65
  66         Reset           = 0x020,
  67
  68         Rev             = 0x028,        /* hardware revision */
  69
  70         EepromIo        = 0x02c,        /* EEPROM i/o register */
  71         EepromGp        = 0x030,
  72
  73         OtpromGp        = 0x034,
  74                 DevSelOtp       = 1<<16,
  75                 RelativeAccess  = 1<<17,
  76                 EccCorrStts     = 1<<20,
  77                 EccUncorrStts   = 1<<21,
  78
  79         Gpc             = 0x024,        /* gp cntrl */
  80                 MacAccessEna    = 1<<0,
  81                 MacClockReady   = 1<<0,
  82                 InitDone        = 1<<2,
  83                 MacAccessReq    = 1<<3,
  84                 NicSleep        = 1<<4,
  85                 RfKill          = 1<<27,
  86
  87         Gio             = 0x03c,
  88                 EnaL0S          = 1<<1,
  89
  90         Led             = 0x094,
  91                 LedBsmCtrl      = 1<<5,
  92                 LedOn           = 0x38,
  93                 LedOff          = 0x78,
  94
  95         UcodeGp1Clr     = 0x05c,
  96                 UcodeGp1RfKill          = 1<<1,
  97                 UcodeGp1CmdBlocked      = 1<<2,
  98                 UcodeGp1CtempStopRf     = 1<<3,
  99
 100         ShadowRegCtrl   = 0x0a8,
 101
 102         Giochicken      = 0x100,
 103                 L1AnoL0Srx      = 1<<23,
 104                 DisL0Stimer     = 1<<29,
 105
 106         AnaPll          = 0x20c,
 107
 108         Dbghpetmem      = 0x240,
 109         Dbglinkpwrmgmt  = 0x250,
 110
 111         MemRaddr        = 0x40c,
 112         MemWaddr        = 0x410,
 113         MemWdata        = 0x418,
 114         MemRdata        = 0x41c,
 115
 116         PrphWaddr       = 0x444,
 117         PrphRaddr       = 0x448,
 118         PrphWdata       = 0x44c,
 119         PrphRdata       = 0x450,
 120
 121         HbusTargWptr    = 0x460,
 122 };
 123
 124 /*
 125  * Flow-Handler registers.
 126  */
 127 enum {
 128         FhTfbdCtrl0     = 0x1900,       // +q*8
 129         FhTfbdCtrl1     = 0x1904,       // +q*8
 130
 131         FhKwAddr        = 0x197c,
 132
 133         FhSramAddr      = 0x19a4,       // +q*4
 134         FhCbbcQueue     = 0x19d0,       // +q*4
 135         FhStatusWptr    = 0x1bc0,
 136         FhRxBase        = 0x1bc4,
 137         FhRxWptr        = 0x1bc8,
 138         FhRxConfig      = 0x1c00,
 139                 FhRxConfigEna           = 1<<31,
 140                 FhRxConfigRbSize8K      = 1<<16,
 141                 FhRxConfigSingleFrame   = 1<<15,
 142                 FhRxConfigIrqDstHost    = 1<<12,
 143                 FhRxConfigIgnRxfEmpty   = 1<<2,
 144
 145                 FhRxConfigNrbdShift     = 20,
 146                 FhRxConfigRbTimeoutShift= 4,
 147
 148         FhRxStatus      = 0x1c44,
 149
 150         FhTxConfig      = 0x1d00,       // +q*32
 151                 FhTxConfigDmaCreditEna  = 1<<3,
 152                 FhTxConfigDmaEna        = 1<<31,
 153                 FhTxConfigCirqHostEndTfd= 1<<20,
 154
 155         FhTxBufStatus   = 0x1d08,       // +q*32
 156                 FhTxBufStatusTbNumShift = 20,
 157                 FhTxBufStatusTbIdxShift = 12,
 158                 FhTxBufStatusTfbdValid  = 3,
 159
 160         FhTxChicken     = 0x1e98,
 161         FhTxStatus      = 0x1eb0,
 162 };
 163
 164 /*
 165  * NIC internal memory offsets.
 166  */
 167 enum {
 168         ApmgClkCtrl     = 0x3000,
 169         ApmgClkEna      = 0x3004,
 170         ApmgClkDis      = 0x3008,
 171                 DmaClkRqt       = 1<<9,
 172                 BsmClkRqt       = 1<<11,
 173
 174         ApmgPs          = 0x300c,
 175                 EarlyPwroffDis  = 1<<22,
 176                 PwrSrcVMain     = 0<<24,
 177                 PwrSrcVAux      = 2<<24,
 178                 PwrSrcMask      = 3<<24,
 179                 ResetReq        = 1<<26,
 180
 181         ApmgDigitalSvr  = 0x3058,
 182         ApmgAnalogSvr   = 0x306c,
 183         ApmgPciStt      = 0x3010,
 184         BsmWrCtrl       = 0x3400,
 185         BsmWrMemSrc     = 0x3404,
 186         BsmWrMemDst     = 0x3408,
 187         BsmWrDwCount    = 0x340c,
 188         BsmDramTextAddr = 0x3490,
 189         BsmDramTextSize = 0x3494,
 190         BsmDramDataAddr = 0x3498,
 191         BsmDramDataSize = 0x349c,
 192         BsmSramBase     = 0x3800,
 193 };
 194
 195 /*
 196  * TX scheduler registers.
 197  */
 198 enum {
 199         SchedBase               = 0xa02c00,
 200         SchedSramAddr           = SchedBase,
 201
 202         SchedDramAddr4965       = SchedBase+0x010,
 203         SchedTxFact4965         = SchedBase+0x01c,
 204         SchedQueueRdptr4965     = SchedBase+0x064,      // +q*4
 205         SchedQChainSel4965      = SchedBase+0x0d0,
 206         SchedIntrMask4965       = SchedBase+0x0e4,
 207         SchedQueueStatus4965    = SchedBase+0x104,      // +q*4
 208
 209         SchedDramAddr5000       = SchedBase+0x008,
 210         SchedTxFact5000         = SchedBase+0x010,
 211         SchedQueueRdptr5000     = SchedBase+0x068,      // +q*4
 212         SchedQChainSel5000      = SchedBase+0x0e8,
 213         SchedIntrMask5000       = SchedBase+0x108,
 214         SchedQueueStatus5000    = SchedBase+0x10c,      // +q*4
 215         SchedAggrSel5000        = SchedBase+0x248,
 216 };
 217
 218 enum {
 219         SchedCtxOff4965         = 0x380,
 220         SchedCtxLen4965         = 416,
 221
 222         SchedCtxOff5000         = 0x600,
 223         SchedCtxLen5000         = 512,
 224 };
 225
 226 enum {
 227         FilterPromisc           = 1<<0,
 228         FilterCtl               = 1<<1,
 229         FilterMulticast         = 1<<2,
 230         FilterNoDecrypt         = 1<<3,
 231         FilterBSS               = 1<<5,
 232         FilterBeacon            = 1<<6,
 233 };
 234
 235 enum {
 236         RFlag24Ghz              = 1<<0,
 237         RFlagCCK                = 1<<1,
 238         RFlagAuto               = 1<<2,
 239         RFlagShSlot             = 1<<4,
 240         RFlagShPreamble         = 1<<5,
 241         RFlagNoDiversity        = 1<<7,
 242         RFlagAntennaA           = 1<<8,
 243         RFlagAntennaB           = 1<<9,
 244         RFlagTSF                = 1<<15,
 245         RFlagCTSToSelf          = 1<<30,
 246 };
 247
 248 typedef struct FWInfo FWInfo;
 249 typedef struct FWImage FWImage;
 250 typedef struct FWSect FWSect;
 251
 252 typedef struct TXQ TXQ;
 253 typedef struct RXQ RXQ;
 254
 255 typedef struct Ctlr Ctlr;
 256
 257 struct FWSect
 258 {
 259         uchar   *data;
 260         uint    size;
 261 };
 262
 263 struct FWImage
 264 {
 265         struct {
 266                 FWSect  text;
 267                 FWSect  data;
 268         } init, main, boot;
 269
 270         uint    rev;
 271         uint    build;
 272         char    descr[64+1];
 273         uchar   data[];
 274 };
 275
 276 struct FWInfo
 277 {
 278         uchar   major;
 279         uchar   minjor;
 280         uchar   type;
 281         uchar   subtype;
 282
 283         u32int  logptr;
 284         u32int  errptr;
 285         u32int  tstamp;
 286         u32int  valid;
 287 };
 288
 289 struct TXQ
 290 {
 291         uint    n;
 292         uint    i;
 293         Block   **b;
 294         uchar   *d;
 295         uchar   *c;
 296
 297         uint    lastcmd;
 298
 299         Rendez;
 300         QLock;
 301 };
 302
 303 struct RXQ
 304 {
 305         uint    i;
 306         Block   **b;
 307         u32int  *p;
 308         uchar   *s;
 309 };
 310
 311 struct Ctlr {
 312         Lock;
 313         QLock;
 314
 315         Ctlr *link;
 316         Pcidev *pdev;
 317         Wifi *wifi;
 318
 319         int type;
 320         int port;
 321         int power;
 322         int active;
 323         int broken;
 324         int attached;
 325
 326         u32int ie;
 327
 328         u32int *nic;
 329         uchar *kwpage;
 330
 331         /* assigned node ids in hardware node table or -1 if unassigned */
 332         int bcastnodeid;
 333         int bssnodeid;
 334
 335         /* current receiver settings */
 336         uchar bssid[Eaddrlen];
 337         int channel;
 338         int prom;
 339         int aid;
 340
 341         RXQ rx;
 342         TXQ tx[20];
 343
 344         struct {
 345                 Rendez;
 346                 u32int  m;
 347                 u32int  w;
 348                 u32int  r;
 349         } wait;
 350
 351         struct {
 352                 uchar   type;
 353                 uchar   step;
 354                 uchar   dash;
 355                 uchar   txantmask;
 356                 uchar   rxantmask;
 357         } rfcfg;
 358
 359         struct {
 360                 int     otp;
 361                 uint    off;
 362
 363                 uchar   version;
 364                 uchar   type;
 365                 u16int  volt;
 366
 367                 char    regdom[4+1];
 368
 369                 u32int  crystal;
 370         } eeprom;
 371
 372         struct {
 373                 Block   *cmd[21];
 374                 int     done;
 375         } calib;
 376
 377         struct {
 378                 u32int  base;
 379                 uchar   *s;
 380         } sched;
 381
 382         FWInfo fwinfo;
 383         FWImage *fw;
 384 };
 385
 386 /* controller types */
 387 enum {
 388         Type4965        = 0,
 389         Type5300        = 2,
 390         Type5350        = 3,
 391         Type5150        = 4,
 392         Type5100        = 5,
 393         Type1000        = 6,
 394         Type6000        = 7,
 395         Type6050        = 8,
 396         Type6005        = 11,
 397 };
 398
 399 static char *fwname[16] = {
 400         [Type4965] "iwn-4965",
 401         [Type5300] "iwn-5000",
 402         [Type5350] "iwn-5000",
 403         [Type5150] "iwn-5150",
 404         [Type5100] "iwn-5000",
 405         [Type1000] "iwn-1000",
 406         [Type6000] "iwn-6000",
 407         [Type6050] "iwn-6050",
 408         [Type6005] "iwn-6005",
 409 };
 410
 411 static char *qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block);
 412 static char *flushq(Ctlr *ctlr, uint qid);
 413 static char *cmd(Ctlr *ctlr, uint code, uchar *data, int size);
 414
 415 #define csr32r(c, r)    (*((c)->nic+((r)/4)))
 416 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
 417
 418 static uint
 419 get16(uchar *p){
 420         return *((u16int*)p);
 421 }
 422 static uint
 423 get32(uchar *p){
 424         return *((u32int*)p);
 425 }
 426 static void
 427 put32(uchar *p, uint v){
 428         *((u32int*)p) = v;
 429 }
 430 static void
 431 put16(uchar *p, uint v){
 432         *((u16int*)p) = v;
 433 };
 434
 435 static char*
 436 niclock(Ctlr *ctlr)
 437 {
 438         int i;
 439
 440         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | MacAccessReq);
 441         for(i=0; i<1000; i++){
 442                 if((csr32r(ctlr, Gpc) & (NicSleep | MacAccessEna)) == MacAccessEna)
 443                         return 0;
 444                 delay(10);
 445         }
 446         return "niclock: timeout";
 447 }
 448
 449 static void
 450 nicunlock(Ctlr *ctlr)
 451 {
 452         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~MacAccessReq);
 453 }
 454
 455 static u32int
 456 prphread(Ctlr *ctlr, uint off)
 457 {
 458         csr32w(ctlr, PrphRaddr, ((sizeof(u32int)-1)<<24) | off);
 459         coherence();
 460         return csr32r(ctlr, PrphRdata);
 461 }
 462 static void
 463 prphwrite(Ctlr *ctlr, uint off, u32int data)
 464 {
 465         csr32w(ctlr, PrphWaddr, ((sizeof(u32int)-1)<<24) | off);
 466         coherence();
 467         csr32w(ctlr, PrphWdata, data);
 468 }
 469
 470 static u32int
 471 memread(Ctlr *ctlr, uint off)
 472 {
 473         csr32w(ctlr, MemRaddr, off);
 474         coherence();
 475         return csr32r(ctlr, MemRdata);
 476 }
 477 static void
 478 memwrite(Ctlr *ctlr, uint off, u32int data)
 479 {
 480         csr32w(ctlr, MemWaddr, off);
 481         coherence();
 482         csr32w(ctlr, MemWdata, data);
 483 }
 484
 485 static void
 486 setfwinfo(Ctlr *ctlr, uchar *d, int len)
 487 {
 488         FWInfo *i;
 489
 490         if(len < 32)
 491                 return;
 492         i = &ctlr->fwinfo;
 493         i->minjor = *d++;
 494         i->major = *d++;
 495         d += 2+8;
 496         i->type = *d++;
 497         i->subtype = *d++;
 498         d += 2;
 499         i->logptr = get32(d); d += 4;
 500         i->errptr = get32(d); d += 4;
 501         i->tstamp = get32(d); d += 4;
 502         i->valid = get32(d);
 503 };
 504
 505 static void
 506 dumpctlr(Ctlr *ctlr)
 507 {
 508         u32int dump[13];
 509         int i;
 510
 511         print("lastcmd: %ud (0x%ux)\n", ctlr->tx[4].lastcmd,  ctlr->tx[4].lastcmd);
 512         if(ctlr->fwinfo.errptr == 0){
 513                 print("no error pointer\n");
 514                 return;
 515         }
 516         for(i=0; i<nelem(dump); i++)
 517                 dump[i] = memread(ctlr, ctlr->fwinfo.errptr + i*4);
 518         print(  "error:\tid %ux, pc %ux,\n"
 519                 "\tbranchlink %.8ux %.8ux, interruptlink %.8ux %.8ux,\n"
 520                 "\terrordata %.8ux %.8ux, srcline %ud, tsf %ux, time %ux\n",
 521                 dump[1], dump[2],
 522                 dump[4], dump[3], dump[6], dump[5],
 523                 dump[7], dump[8], dump[9], dump[10], dump[11]);
 524 }
 525
 526 static char*
 527 eepromlock(Ctlr *ctlr)
 528 {
 529         int i, j;
 530
 531         for(i=0; i<100; i++){
 532                 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | EepromLocked);
 533                 for(j=0; j<100; j++){
 534                         if(csr32r(ctlr, Cfg) & EepromLocked)
 535                                 return 0;
 536                         delay(10);
 537                 }
 538         }
 539         return "eepromlock: timeout";
 540 }
 541 static void
 542 eepromunlock(Ctlr *ctlr)
 543 {
 544         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) & ~EepromLocked);
 545 }
 546 static char*
 547 eepromread(Ctlr *ctlr, void *data, int count, uint off)
 548 {
 549         uchar *out = data;
 550         u32int w, s;
 551         int i;
 552
 553         w = 0;
 554         off += ctlr->eeprom.off;
 555         for(; count > 0; count -= 2, off++){
 556                 csr32w(ctlr, EepromIo, off << 2);
 557                 for(i=0; i<10; i++){
 558                         w = csr32r(ctlr, EepromIo);
 559                         if(w & 1)
 560                                 break;
 561                         delay(5);
 562                 }
 563                 if(i == 10)
 564                         return "eepromread: timeout";
 565                 if(ctlr->eeprom.otp){
 566                         s = csr32r(ctlr, OtpromGp);
 567                         if(s & EccUncorrStts)
 568                                 return "eepromread: otprom ecc error";
 569                         if(s & EccCorrStts)
 570                                 csr32w(ctlr, OtpromGp, s);
 571                 }
 572                 *out++ = w >> 16;
 573                 if(count > 1)
 574                         *out++ = w >> 24;
 575         }
 576         return 0;
 577 }
 578
 579 static char*
 580 handover(Ctlr *ctlr)
 581 {
 582         int i;
 583
 584         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
 585         for(i=0; i<5; i++){
 586                 if(csr32r(ctlr, Cfg) & NicReady)
 587                         return 0;
 588                 delay(10);
 589         }
 590         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | Prepare);
 591         for(i=0; i<15000; i++){
 592                 if((csr32r(ctlr, Cfg) & PrepareDone) == 0)
 593                         break;
 594                 delay(10);
 595         }
 596         if(i >= 15000)
 597                 return "handover: timeout";
 598         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
 599         for(i=0; i<5; i++){
 600                 if(csr32r(ctlr, Cfg) & NicReady)
 601                         return 0;
 602                 delay(10);
 603         }
 604         return "handover: timeout";
 605 }
 606
 607 static char*
 608 clockwait(Ctlr *ctlr)
 609 {
 610         int i;
 611
 612         /* Set "initialization complete" bit. */
 613         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | InitDone);
 614         for(i=0; i<2500; i++){
 615                 if(csr32r(ctlr, Gpc) & MacClockReady)
 616                         return 0;
 617                 delay(10);
 618         }
 619         return "clockwait: timeout";
 620 }
 621
 622 static char*
 623 poweron(Ctlr *ctlr)
 624 {
 625         int capoff;
 626         char *err;
 627
 628         /* Disable L0s exit timer (NMI bug workaround). */
 629         csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | DisL0Stimer);
 630
 631         /* Don't wait for ICH L0s (ICH bug workaround). */
 632         csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | L1AnoL0Srx);
 633
 634         /* Set FH wait threshold to max (HW bug under stress workaround). */
 635         csr32w(ctlr, Dbghpetmem, csr32r(ctlr, Dbghpetmem) | 0xffff0000);
 636
 637         /* Enable HAP INTA to move adapter from L1a to L0s. */
 638         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | HapwakeL1A);
 639
 640         capoff = pcicap(ctlr->pdev, PciCapPCIe);
 641         if(capoff != -1){
 642                 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
 643                 if(pcicfgr16(ctlr->pdev, capoff + 0x10) & 0x2)  /* LCSR -> L1 Entry enabled. */
 644                         csr32w(ctlr, Gio, csr32r(ctlr, Gio) | EnaL0S);
 645                 else
 646                         csr32w(ctlr, Gio, csr32r(ctlr, Gio) & ~EnaL0S);
 647         }
 648
 649         if(ctlr->type != Type4965 && ctlr->type <= Type1000)
 650                 csr32w(ctlr, AnaPll, csr32r(ctlr, AnaPll) | 0x00880300);
 651
 652         /* Wait for clock stabilization before accessing prph. */
 653         if((err = clockwait(ctlr)) != nil)
 654                 return err;
 655
 656         if((err = niclock(ctlr)) != nil)
 657                 return err;
 658
 659         /* Enable DMA and BSM (Bootstrap State Machine). */
 660         if(ctlr->type == Type4965)
 661                 prphwrite(ctlr, ApmgClkEna, DmaClkRqt | BsmClkRqt);
 662         else
 663                 prphwrite(ctlr, ApmgClkEna, DmaClkRqt);
 664         delay(20);
 665
 666         /* Disable L1-Active. */
 667         prphwrite(ctlr, ApmgPciStt, prphread(ctlr, ApmgPciStt) | (1<<11));
 668
 669         nicunlock(ctlr);
 670
 671         ctlr->power = 1;
 672
 673         return 0;
 674 }
 675
 676 static void
 677 poweroff(Ctlr *ctlr)
 678 {
 679         int i, j;
 680
 681         csr32w(ctlr, Reset, 1);
 682
 683         /* Disable interrupts */
 684         ctlr->ie = 0;
 685         csr32w(ctlr, Imr, 0);
 686         csr32w(ctlr, Isr, ~0);
 687         csr32w(ctlr, FhIsr, ~0);
 688
 689         /* Stop scheduler */
 690         if(ctlr->type != Type4965)
 691                 prphwrite(ctlr, SchedTxFact5000, 0);
 692         else
 693                 prphwrite(ctlr, SchedTxFact4965, 0);
 694
 695         /* Stop TX ring */
 696         if(niclock(ctlr) == nil){
 697                 for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--){
 698                         csr32w(ctlr, FhTxConfig + i*32, 0);
 699                         for(j = 0; j < 200; j++){
 700                                 if(csr32r(ctlr, FhTxStatus) & (0x10000<<i))
 701                                         break;
 702                                 delay(10);
 703                         }
 704                 }
 705                 nicunlock(ctlr);
 706         }
 707
 708         /* Stop RX ring */
 709         if(niclock(ctlr) == nil){
 710                 csr32w(ctlr, FhRxConfig, 0);
 711                 for(j = 0; j < 200; j++){
 712                         if(csr32r(ctlr, FhRxStatus) & 0x1000000)
 713                                 break;
 714                         delay(10);
 715                 }
 716                 nicunlock(ctlr);
 717         }
 718
 719         /* Disable DMA */
 720         if(niclock(ctlr) == nil){
 721                 prphwrite(ctlr, ApmgClkDis, DmaClkRqt);
 722                 nicunlock(ctlr);
 723         }
 724         delay(5);
 725
 726         /* Stop busmaster DMA activity. */
 727         csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<9));
 728         for(j = 0; j < 100; j++){
 729                 if(csr32r(ctlr, Reset) & (1<<8))
 730                         break;
 731                 delay(10);
 732         }
 733
 734         /* Reset the entire device. */
 735         csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<7));
 736         delay(10);
 737
 738         /* Clear "initialization complete" bit. */
 739         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~InitDone);
 740
 741         ctlr->power = 0;
 742 }
 743
 744 static char*
 745 rominit(Ctlr *ctlr)
 746 {
 747         uchar buf[2];
 748         char *err;
 749         uint off;
 750         int i;
 751
 752         ctlr->eeprom.otp = 0;
 753         ctlr->eeprom.off = 0;
 754         if(ctlr->type < Type1000 || (csr32r(ctlr, OtpromGp) & DevSelOtp) == 0)
 755                 return nil;
 756
 757         /* Wait for clock stabilization before accessing prph. */
 758         if((err = clockwait(ctlr)) != nil)
 759                 return err;
 760
 761         if((err = niclock(ctlr)) != nil)
 762                 return err;
 763         prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | ResetReq);
 764         delay(5);
 765         prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) & ~ResetReq);
 766         nicunlock(ctlr);
 767
 768         /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
 769         if(ctlr->type != Type1000)
 770                 csr32w(ctlr, Dbglinkpwrmgmt, csr32r(ctlr, Dbglinkpwrmgmt) | (1<<31));
 771
 772         csr32w(ctlr, EepromGp, csr32r(ctlr, EepromGp) & ~0x00000180);
 773
 774         /* Clear ECC status. */
 775         csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) | (EccCorrStts | EccUncorrStts));
 776
 777         ctlr->eeprom.otp = 1;
 778         if(ctlr->type != Type1000)
 779                 return nil;
 780
 781         /* Switch to absolute addressing mode. */
 782         csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) & ~RelativeAccess);
 783
 784         /*
 785          * Find the block before last block (contains the EEPROM image)
 786          * for HW without OTP shadow RAM.
 787          */
 788         off = 0;
 789         for(i=0; i<3; i++){
 790                 if((err = eepromread(ctlr, buf, 2, off)) != nil)
 791                         return err;
 792                 if(get16(buf) == 0)
 793                         break;
 794                 off = get16(buf);
 795         }
 796         if(i == 0 || i >= 3)
 797                 return "rominit: missing eeprom image";
 798
 799         ctlr->eeprom.off = off+1;
 800         return nil;
 801 }
 802
 803 static int
 804 iwlinit(Ether *edev)
 805 {
 806         Ctlr *ctlr;
 807         char *err;
 808         uchar b[4];
 809         uint u, caloff, regoff;
 810
 811         ctlr = edev->ctlr;
 812         if((err = handover(ctlr)) != nil)
 813                 goto Err;
 814         if((err = poweron(ctlr)) != nil)
 815                 goto Err;
 816         if((csr32r(ctlr, EepromGp) & 0x7) == 0){
 817                 err = "bad rom signature";
 818                 goto Err;
 819         }
 820         if((err = eepromlock(ctlr)) != nil)
 821                 goto Err;
 822         if((err = rominit(ctlr)) != nil)
 823                 goto Err2;
 824         if((err = eepromread(ctlr, edev->ea, sizeof(edev->ea), 0x15)) != nil){
 825                 eepromunlock(ctlr);
 826                 goto Err;
 827         }
 828         if((err = eepromread(ctlr, b, 2, 0x048)) != nil){
 829         Err2:
 830                 eepromunlock(ctlr);
 831                 goto Err;
 832         }
 833         u = get16(b);
 834         ctlr->rfcfg.type = u & 3;       u >>= 2;
 835         ctlr->rfcfg.step = u & 3;       u >>= 2;
 836         ctlr->rfcfg.dash = u & 3;       u >>= 4;
 837         ctlr->rfcfg.txantmask = u & 15; u >>= 4;
 838         ctlr->rfcfg.rxantmask = u & 15;
 839         if((err = eepromread(ctlr, b, 2, 0x66)) != nil)
 840                 goto Err2;
 841         regoff = get16(b);
 842         if((err = eepromread(ctlr, b, 4, regoff+1)) != nil)
 843                 goto Err2;
 844         strncpy(ctlr->eeprom.regdom, (char*)b, 4);
 845         ctlr->eeprom.regdom[4] = 0;
 846         if((err = eepromread(ctlr, b, 2, 0x67)) != nil)
 847                 goto Err2;
 848         caloff = get16(b);
 849         if((err = eepromread(ctlr, b, 4, caloff)) != nil)
 850                 goto Err2;
 851         ctlr->eeprom.version = b[0];
 852         ctlr->eeprom.type = b[1];
 853         ctlr->eeprom.volt = get16(b+2);
 854         if(ctlr->type != Type4965 && ctlr->type != Type5150){
 855                 if((err = eepromread(ctlr, b, 4, caloff + 0x128)) != nil)
 856                         goto Err2;
 857                 ctlr->eeprom.crystal = get32(b);
 858         }
 859         eepromunlock(ctlr);
 860
 861         switch(ctlr->type){
 862         case Type4965:
 863                 ctlr->rfcfg.txantmask = 3;
 864                 ctlr->rfcfg.rxantmask = 7;
 865                 break;
 866         case Type5100:
 867                 ctlr->rfcfg.txantmask = 2;
 868                 ctlr->rfcfg.rxantmask = 3;
 869                 break;
 870         case Type6000:
 871                 if(ctlr->pdev->did == 0x422c || ctlr->pdev->did == 0x4230){
 872                         ctlr->rfcfg.txantmask = 6;
 873                         ctlr->rfcfg.rxantmask = 6;
 874                 }
 875                 break;
 876         }
 877         poweroff(ctlr);
 878         return 0;
 879 Err:
 880         print("iwlinit: %s\n", err);
 881         poweroff(ctlr);
 882         return -1;
 883 }
 884
 885 static char*
 886 crackfw(FWImage *i, uchar *data, uint size, int alt)
 887 {
 888         uchar *p, *e;
 889         FWSect *s;
 890
 891         memset(i, 0, sizeof(*i));
 892         if(size < 4){
 893 Tooshort:
 894                 return "firmware image too short";
 895         }
 896         p = data;
 897         e = p + size;
 898         i->rev = get32(p); p += 4;
 899         if(i->rev == 0){
 900                 uvlong altmask;
 901
 902                 if(size < (4+64+4+4+8))
 903                         goto Tooshort;
 904                 if(memcmp(p, "IWL\n", 4) != 0)
 905                         return "bad firmware signature";
 906                 p += 4;
 907                 strncpy(i->descr, (char*)p, 64);
 908                 i->descr[64] = 0;
 909                 p += 64;
 910                 i->rev = get32(p); p += 4;
 911                 i->build = get32(p); p += 4;
 912                 altmask = get32(p); p += 4;
 913                 altmask |= (uvlong)get32(p) << 32; p += 4;
 914                 while(alt > 0 && (altmask & (1ULL<<alt)) == 0)
 915                         alt--;
 916                 while(p < e){
 917                         FWSect dummy;
 918
 919                         if((p + 2+2+4) > e)
 920                                 goto Tooshort;
 921                         switch(get16(p)){
 922                         case 1: s = &i->main.text; break;
 923                         case 2: s = &i->main.data; break;
 924                         case 3: s = &i->init.text; break;
 925                         case 4: s = &i->init.data; break;
 926                         case 5: s = &i->boot.text; break;
 927                         default:s = &dummy;
 928                         }
 929                         p += 2;
 930                         if(get16(p) != 0 && get16(p) != alt)
 931                                 s = &dummy;
 932                         p += 2;
 933                         s->size = get32(p); p += 4;
 934                         s->data = p;
 935                         if((p + s->size) > e)
 936                                 goto Tooshort;
 937                         p += (s->size + 3) & ~3;
 938                 }
 939         } else {
 940                 if(((i->rev>>8) & 0xFF) < 2)
 941                         return "need firmware api >= 2";
 942                 if(((i->rev>>8) & 0xFF) >= 3){
 943                         i->build = get32(p); p += 4;
 944                 }
 945                 if((p + 5*4) > e)
 946                         goto Tooshort;
 947                 i->main.text.size = get32(p); p += 4;
 948                 i->main.data.size = get32(p); p += 4;
 949                 i->init.text.size = get32(p); p += 4;
 950                 i->init.data.size = get32(p); p += 4;
 951                 i->boot.text.size = get32(p); p += 4;
 952                 i->main.text.data = p; p += i->main.text.size;
 953                 i->main.data.data = p; p += i->main.data.size;
 954                 i->init.text.data = p; p += i->init.text.size;
 955                 i->init.data.data = p; p += i->init.data.size;
 956                 i->boot.text.data = p; p += i->boot.text.size;
 957                 if(p > e)
 958                         goto Tooshort;
 959         }
 960         return 0;
 961 }
 962
 963 static FWImage*
 964 readfirmware(char *name)
 965 {
 966         uchar dirbuf[sizeof(Dir)+100], *data;
 967         char buf[128], *err;
 968         FWImage *fw;
 969         int n, r;
 970         Chan *c;
 971         Dir d;
 972
 973         if(!iseve())
 974                 error(Eperm);
 975         if(!waserror()){
 976                 snprint(buf, sizeof buf, "/boot/%s", name);
 977                 c = namec(buf, Aopen, OREAD, 0);
 978                 poperror();
 979         } else {
 980                 snprint(buf, sizeof buf, "/lib/firmware/%s", name);
 981                 c = namec(buf, Aopen, OREAD, 0);
 982         }
 983         if(waserror()){
 984                 cclose(c);
 985                 nexterror();
 986         }
 987         n = devtab[c->type]->stat(c, dirbuf, sizeof dirbuf);
 988         if(n <= 0)
 989                 error("can't stat firmware");
 990         convM2D(dirbuf, n, &d, nil);
 991         fw = smalloc(sizeof(*fw) + 16 + d.length);
 992         data = (uchar*)(fw+1);
 993         if(waserror()){
 994                 free(fw);
 995                 nexterror();
 996         }
 997         r = 0;
 998         while(r < d.length){
 999                 n = devtab[c->type]->read(c, data+r, d.length-r, (vlong)r);
1000                 if(n <= 0)
1001                         break;
1002                 r += n;
1003         }
1004         if((err = crackfw(fw, data, r, 1)) != nil)
1005                 error(err);
1006         poperror();
1007         poperror();
1008         cclose(c);
1009         return fw;
1010 }
1011
1012 typedef struct Irqwait Irqwait;
1013 struct Irqwait {
1014         Ctlr    *ctlr;
1015         u32int  mask;
1016 };
1017
1018 static int
1019 gotirq(void *arg)
1020 {
1021         Irqwait *w;
1022         Ctlr *ctlr;
1023
1024         w = arg;
1025         ctlr = w->ctlr;
1026         ctlr->wait.r = ctlr->wait.m & w->mask;
1027         if(ctlr->wait.r){
1028                 ctlr->wait.m &= ~ctlr->wait.r;
1029                 return 1;
1030         }
1031         ctlr->wait.w = w->mask;
1032         return 0;
1033 }
1034
1035 static u32int
1036 irqwait(Ctlr *ctlr, u32int mask, int timeout)
1037 {
1038         Irqwait w;
1039
1040         w.ctlr = ctlr;
1041         w.mask = mask;
1042         tsleep(&ctlr->wait, gotirq, &w, timeout);
1043         ctlr->wait.w = 0;
1044         return ctlr->wait.r & mask;
1045 }
1046
1047 static int
1048 rbplant(Ctlr *ctlr, int i)
1049 {
1050         Block *b;
1051
1052         b = iallocb(Rbufsize + 256);
1053         if(b == nil)
1054                 return -1;
1055         b->rp = b->wp = (uchar*)ROUND((uintptr)b->base, 256);
1056         memset(b->rp, 0, Rdscsize);
1057         ctlr->rx.b[i] = b;
1058         ctlr->rx.p[i] = PCIWADDR(b->rp) >> 8;
1059         return 0;
1060 }
1061
1062 static char*
1063 initring(Ctlr *ctlr)
1064 {
1065         RXQ *rx;
1066         TXQ *tx;
1067         int i, q;
1068
1069         rx = &ctlr->rx;
1070         if(rx->b == nil)
1071                 rx->b = malloc(sizeof(Block*) * Nrx);
1072         if(rx->p == nil)
1073                 rx->p = mallocalign(sizeof(u32int) * Nrx, 256, 0, 0);
1074         if(rx->s == nil)
1075                 rx->s = mallocalign(Rstatsize, 16, 0, 0);
1076         if(rx->b == nil || rx->p == nil || rx->s == nil)
1077                 return "no memory for rx ring";
1078         memset(ctlr->rx.s, 0, Rstatsize);
1079         for(i=0; i<Nrx; i++){
1080                 rx->p[i] = 0;
1081                 if(rx->b[i] != nil){
1082                         freeb(rx->b[i]);
1083                         rx->b[i] = nil;
1084                 }
1085                 if(rbplant(ctlr, i) < 0)
1086                         return "no memory for rx descriptors";
1087         }
1088         rx->i = 0;
1089
1090         if(ctlr->sched.s == nil)
1091                 ctlr->sched.s = mallocalign(512 * nelem(ctlr->tx) * 2, 1024, 0, 0);
1092         if(ctlr->sched.s == nil)
1093                 return "no memory for sched buffer";
1094         memset(ctlr->sched.s, 0, 512 * nelem(ctlr->tx));
1095
1096         for(q=0; q<nelem(ctlr->tx); q++){
1097                 tx = &ctlr->tx[q];
1098                 if(tx->b == nil)
1099                         tx->b = malloc(sizeof(Block*) * Ntx);
1100                 if(tx->d == nil)
1101                         tx->d = mallocalign(Tdscsize * Ntx, 256, 0, 0);
1102                 if(tx->c == nil)
1103                         tx->c = mallocalign(Tcmdsize * Ntx, 4, 0, 0);
1104                 if(tx->b == nil || tx->d == nil || tx->c == nil)
1105                         return "no memory for tx ring";
1106                 memset(tx->d, 0, Tdscsize * Ntx);
1107                 memset(tx->c, 0, Tcmdsize * Ntx);
1108                 for(i=0; i<Ntx; i++){
1109                         if(tx->b[i] != nil){
1110                                 freeb(tx->b[i]);
1111                                 tx->b[i] = nil;
1112                         }
1113                 }
1114                 tx->i = 0;
1115                 tx->n = 0;
1116                 tx->lastcmd = 0;
1117         }
1118
1119         if(ctlr->kwpage == nil)
1120                 ctlr->kwpage = mallocalign(4096, 4096, 0, 0);
1121         if(ctlr->kwpage == nil)
1122                 return "no memory for kwpage";
1123         memset(ctlr->kwpage, 0, 4096);
1124
1125         return nil;
1126 }
1127
1128 static char*
1129 reset(Ctlr *ctlr)
1130 {
1131         char *err;
1132         int i, q;
1133
1134         if(ctlr->power)
1135                 poweroff(ctlr);
1136         if((err = initring(ctlr)) != nil)
1137                 return err;
1138         if((err = poweron(ctlr)) != nil)
1139                 return err;
1140
1141         if((err = niclock(ctlr)) != nil)
1142                 return err;
1143         prphwrite(ctlr, ApmgPs, (prphread(ctlr, ApmgPs) & ~PwrSrcMask) | PwrSrcVMain);
1144         nicunlock(ctlr);
1145
1146         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | RadioSi | MacSi);
1147
1148         if((err = niclock(ctlr)) != nil)
1149                 return err;
1150         if(ctlr->type != Type4965)
1151                 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | EarlyPwroffDis);
1152         if(ctlr->type == Type1000){
1153                 /*
1154                  * Select first Switching Voltage Regulator (1.32V) to
1155                  * solve a stability issue related to noisy DC2DC line
1156                  * in the silicon of 1000 Series.
1157                  */
1158                 prphwrite(ctlr, ApmgDigitalSvr,
1159                         (prphread(ctlr, ApmgDigitalSvr) & ~(0xf<<5)) | (3<<5));
1160         }
1161         nicunlock(ctlr);
1162
1163         if((err = niclock(ctlr)) != nil)
1164                 return err;
1165         csr32w(ctlr, FhRxConfig, 0);
1166         csr32w(ctlr, FhRxWptr, 0);
1167         csr32w(ctlr, FhRxBase, PCIWADDR(ctlr->rx.p) >> 8);
1168         csr32w(ctlr, FhStatusWptr, PCIWADDR(ctlr->rx.s) >> 4);
1169         csr32w(ctlr, FhRxConfig,
1170                 FhRxConfigEna |
1171                 FhRxConfigIgnRxfEmpty |
1172                 FhRxConfigIrqDstHost |
1173                 FhRxConfigSingleFrame |
1174                 (Nrxlog << FhRxConfigNrbdShift));
1175         csr32w(ctlr, FhRxWptr, (Nrx-1) & ~7);
1176         nicunlock(ctlr);
1177
1178         if((err = niclock(ctlr)) != nil)
1179                 return err;
1180         if(ctlr->type != Type4965)
1181                 prphwrite(ctlr, SchedTxFact5000, 0);
1182         else
1183                 prphwrite(ctlr, SchedTxFact4965, 0);
1184         csr32w(ctlr, FhKwAddr, PCIWADDR(ctlr->kwpage) >> 4);
1185         for(q = (ctlr->type != Type4965) ? 19 : 15; q >= 0; q--)
1186                 csr32w(ctlr, FhCbbcQueue + q*4, PCIWADDR(ctlr->tx[q].d) >> 8);
1187         nicunlock(ctlr);
1188
1189         for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--)
1190                 csr32w(ctlr, FhTxConfig + i*32, FhTxConfigDmaEna | FhTxConfigDmaCreditEna);
1191
1192         csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
1193         csr32w(ctlr, UcodeGp1Clr, UcodeGp1CmdBlocked);
1194
1195         ctlr->broken = 0;
1196         ctlr->wait.r = 0;
1197         ctlr->wait.w = 0;
1198
1199         ctlr->ie = Idefmask;
1200         csr32w(ctlr, Imr, ctlr->ie);
1201         csr32w(ctlr, Isr, ~0);
1202
1203         if(ctlr->type >= Type6000)
1204                 csr32w(ctlr, ShadowRegCtrl, csr32r(ctlr, ShadowRegCtrl) | 0x800fffff);
1205
1206         return nil;
1207 }
1208
1209 static char*
1210 postboot(Ctlr *ctlr)
1211 {
1212         uint ctxoff, ctxlen, dramaddr;
1213         char *err;
1214         int i, q;
1215
1216         if((err = niclock(ctlr)) != nil)
1217                 return err;
1218
1219         if(ctlr->type != Type4965){
1220                 dramaddr = SchedDramAddr5000;
1221                 ctxoff = SchedCtxOff5000;
1222                 ctxlen = SchedCtxLen5000;
1223         } else {
1224                 dramaddr = SchedDramAddr4965;
1225                 ctxoff = SchedCtxOff4965;
1226                 ctxlen = SchedCtxLen4965;
1227         }
1228
1229         ctlr->sched.base = prphread(ctlr, SchedSramAddr);
1230         for(i=0; i < ctxlen; i += 4)
1231                 memwrite(ctlr, ctlr->sched.base + ctxoff + i, 0);
1232
1233         prphwrite(ctlr, dramaddr, PCIWADDR(ctlr->sched.s)>>10);
1234
1235         csr32w(ctlr, FhTxChicken, csr32r(ctlr, FhTxChicken) | 2);
1236
1237         if(ctlr->type != Type4965){
1238                 /* Enable chain mode for all queues, except command queue 4. */
1239                 prphwrite(ctlr, SchedQChainSel5000, 0xfffef);
1240                 prphwrite(ctlr, SchedAggrSel5000, 0);
1241
1242                 for(q=0; q<20; q++){
1243                         prphwrite(ctlr, SchedQueueRdptr5000 + q*4, 0);
1244                         csr32w(ctlr, HbusTargWptr, q << 8);
1245
1246                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 0);
1247                         /* Set scheduler window size and frame limit. */
1248                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16 | 64);
1249                 }
1250                 /* Enable interrupts for all our 20 queues. */
1251                 prphwrite(ctlr, SchedIntrMask5000, 0xfffff);
1252
1253                 /* Identify TX FIFO rings (0-7). */
1254                 prphwrite(ctlr, SchedTxFact5000, 0xff);
1255         } else {
1256                 /* Disable chain mode for all our 16 queues. */
1257                 prphwrite(ctlr, SchedQChainSel4965, 0);
1258
1259                 for(q=0; q<16; q++) {
1260                         prphwrite(ctlr, SchedQueueRdptr4965 + q*4, 0);
1261                         csr32w(ctlr, HbusTargWptr, q << 8);
1262
1263                         /* Set scheduler window size. */
1264                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 64);
1265                         /* Set scheduler window size and frame limit. */
1266                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16);
1267                 }
1268                 /* Enable interrupts for all our 16 queues. */
1269                 prphwrite(ctlr, SchedIntrMask4965, 0xffff);
1270
1271                 /* Identify TX FIFO rings (0-7). */
1272                 prphwrite(ctlr, SchedTxFact4965, 0xff);
1273         }
1274
1275         /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
1276         for(q=0; q<7; q++){
1277                 if(ctlr->type != Type4965){
1278                         static uchar qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
1279                         prphwrite(ctlr, SchedQueueStatus5000 + q*4, 0x00ff0018 | qid2fifo[q]);
1280                 } else {
1281                         static uchar qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
1282                         prphwrite(ctlr, SchedQueueStatus4965 + q*4, 0x0007fc01 | qid2fifo[q]<<1);
1283                 }
1284         }
1285         nicunlock(ctlr);
1286
1287         if(ctlr->type != Type4965){
1288                 uchar c[Tcmdsize];
1289
1290                 /* disable wimax coexistance */
1291                 memset(c, 0, sizeof(c));
1292                 if((err = cmd(ctlr, 90, c, 4+4*16)) != nil)
1293                         return err;
1294
1295                 if(ctlr->type != Type5150){
1296                         /* calibrate crystal */
1297                         memset(c, 0, sizeof(c));
1298                         c[0] = 15;      /* code */
1299                         c[1] = 0;       /* group */
1300                         c[2] = 1;       /* ngroup */
1301                         c[3] = 1;       /* isvalid */
1302                         c[4] = ctlr->eeprom.crystal;
1303                         c[5] = ctlr->eeprom.crystal>>16;
1304                         if((err = cmd(ctlr, 176, c, 8)) != nil)
1305                                 return err;
1306                 }
1307
1308                 if(ctlr->calib.done == 0){
1309                         /* query calibration (init firmware) */
1310                         memset(c, 0, sizeof(c));
1311                         put32(c + 0*(5*4) + 0, 0xffffffff);
1312                         put32(c + 0*(5*4) + 4, 0xffffffff);
1313                         put32(c + 0*(5*4) + 8, 0xffffffff);
1314                         put32(c + 2*(5*4) + 0, 0xffffffff);
1315                         if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1316                                 return err;
1317
1318                         /* wait to collect calibration records */
1319                         if(irqwait(ctlr, Ierr, 2000))
1320                                 return "calibration failed";
1321
1322                         if(ctlr->calib.done == 0){
1323                                 print("iwl: no calibration results\n");
1324                                 ctlr->calib.done = 1;
1325                         }
1326                 } else {
1327                         static uchar cmds[] = {8, 9, 11, 17, 16};
1328
1329                         /* send calibration records (runtime firmware) */
1330                         for(q=0; q<nelem(cmds); q++){
1331                                 Block *b;
1332
1333                                 i = cmds[q];
1334                                 if(i == 8 && ctlr->type != Type5150)
1335                                         continue;
1336                                 if(i == 17 && (ctlr->type >= Type6000 || ctlr->type == Type5150))
1337                                         continue;
1338                                 if((b = ctlr->calib.cmd[i]) == nil)
1339                                         continue;
1340                                 b->ref++;       /* dont free on command completion */
1341                                 if((err = qcmd(ctlr, 4, 176, nil, 0, b)) != nil){
1342                                         freeb(b);
1343                                         return err;
1344                                 }
1345                                 if((err = flushq(ctlr, 4)) != nil)
1346                                         return err;
1347                         }
1348
1349                         if(ctlr->type == Type6005 || ctlr->type == Type6050){
1350                                 /* runtime DC calibration */
1351                                 memset(c, 0, sizeof(c));
1352                                 put32(c + 0*(5*4) + 0, 0xffffffff);
1353                                 put32(c + 0*(5*4) + 4, 1<<1);
1354                                 if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1355                                         return err;
1356                         }
1357
1358                         /* set tx antenna config */
1359                         put32(c, ctlr->rfcfg.txantmask & 7);
1360                         if((err = cmd(ctlr, 152, c, 4)) != nil)
1361                                 return err;
1362                 }
1363         }
1364
1365         return nil;
1366 }
1367
1368 static char*
1369 loadfirmware1(Ctlr *ctlr, u32int dst, uchar *data, int size)
1370 {
1371         uchar *dma;
1372         char *err;
1373
1374         dma = mallocalign(size, 16, 0, 0);
1375         if(dma == nil)
1376                 return "no memory for dma";
1377         memmove(dma, data, size);
1378         coherence();
1379         if((err = niclock(ctlr)) != 0){
1380                 free(dma);
1381                 return err;
1382         }
1383         csr32w(ctlr, FhTxConfig + 9*32, 0);
1384         csr32w(ctlr, FhSramAddr + 9*4, dst);
1385         csr32w(ctlr, FhTfbdCtrl0 + 9*8, PCIWADDR(dma));
1386         csr32w(ctlr, FhTfbdCtrl1 + 9*8, size);
1387         csr32w(ctlr, FhTxBufStatus + 9*32,
1388                 (1<<FhTxBufStatusTbNumShift) |
1389                 (1<<FhTxBufStatusTbIdxShift) |
1390                 FhTxBufStatusTfbdValid);
1391         csr32w(ctlr, FhTxConfig + 9*32, FhTxConfigDmaEna | FhTxConfigCirqHostEndTfd);
1392         nicunlock(ctlr);
1393         if(irqwait(ctlr, Ifhtx|Ierr, 5000) != Ifhtx){
1394                 free(dma);
1395                 return "dma error / timeout";
1396         }
1397         free(dma);
1398         return 0;
1399 }
1400
1401 static char*
1402 boot(Ctlr *ctlr)
1403 {
1404         int i, n, size;
1405         uchar *p, *dma;
1406         FWImage *fw;
1407         char *err;
1408
1409         fw = ctlr->fw;
1410
1411         if(fw->boot.text.size == 0){
1412                 if(ctlr->calib.done == 0){
1413                         if((err = loadfirmware1(ctlr, 0x00000000, fw->init.text.data, fw->init.text.size)) != nil)
1414                                 return err;
1415                         if((err = loadfirmware1(ctlr, 0x00800000, fw->init.data.data, fw->init.data.size)) != nil)
1416                                 return err;
1417                         csr32w(ctlr, Reset, 0);
1418                         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1419                                 return "init firmware boot failed";
1420                         if((err = postboot(ctlr)) != nil)
1421                                 return err;
1422                         if((err = reset(ctlr)) != nil)
1423                                 return err;
1424                 }
1425                 if((err = loadfirmware1(ctlr, 0x00000000, fw->main.text.data, fw->main.text.size)) != nil)
1426                         return err;
1427                 if((err = loadfirmware1(ctlr, 0x00800000, fw->main.data.data, fw->main.data.size)) != nil)
1428                         return err;
1429                 csr32w(ctlr, Reset, 0);
1430                 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1431                         return "main firmware boot failed";
1432                 return postboot(ctlr);
1433         }
1434
1435         size = ROUND(fw->init.data.size, 16) + ROUND(fw->init.text.size, 16);
1436         dma = mallocalign(size, 16, 0, 0);
1437         if(dma == nil)
1438                 return "no memory for dma";
1439
1440         if((err = niclock(ctlr)) != nil){
1441                 free(dma);
1442                 return err;
1443         }
1444
1445         p = dma;
1446         memmove(p, fw->init.data.data, fw->init.data.size);
1447         coherence();
1448         prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1449         prphwrite(ctlr, BsmDramDataSize, fw->init.data.size);
1450         p += ROUND(fw->init.data.size, 16);
1451         memmove(p, fw->init.text.data, fw->init.text.size);
1452         coherence();
1453         prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1454         prphwrite(ctlr, BsmDramTextSize, fw->init.text.size);
1455
1456         nicunlock(ctlr);
1457         if((err = niclock(ctlr)) != nil){
1458                 free(dma);
1459                 return err;
1460         }
1461
1462         p = fw->boot.text.data;
1463         n = fw->boot.text.size/4;
1464         for(i=0; i<n; i++, p += 4)
1465                 prphwrite(ctlr, BsmSramBase+i*4, get32(p));
1466
1467         prphwrite(ctlr, BsmWrMemSrc, 0);
1468         prphwrite(ctlr, BsmWrMemDst, 0);
1469         prphwrite(ctlr, BsmWrDwCount, n);
1470
1471         prphwrite(ctlr, BsmWrCtrl, 1<<31);
1472
1473         for(i=0; i<1000; i++){
1474                 if((prphread(ctlr, BsmWrCtrl) & (1<<31)) == 0)
1475                         break;
1476                 delay(10);
1477         }
1478         if(i == 1000){
1479                 nicunlock(ctlr);
1480                 free(dma);
1481                 return "bootcode timeout";
1482         }
1483
1484         prphwrite(ctlr, BsmWrCtrl, 1<<30);
1485         nicunlock(ctlr);
1486
1487         csr32w(ctlr, Reset, 0);
1488         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1489                 free(dma);
1490                 return "init firmware boot failed";
1491         }
1492         free(dma);
1493
1494         size = ROUND(fw->main.data.size, 16) + ROUND(fw->main.text.size, 16);
1495         dma = mallocalign(size, 16, 0, 0);
1496         if(dma == nil)
1497                 return "no memory for dma";
1498         if((err = niclock(ctlr)) != nil){
1499                 free(dma);
1500                 return err;
1501         }
1502         p = dma;
1503         memmove(p, fw->main.data.data, fw->main.data.size);
1504         coherence();
1505         prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1506         prphwrite(ctlr, BsmDramDataSize, fw->main.data.size);
1507         p += ROUND(fw->main.data.size, 16);
1508         memmove(p, fw->main.text.data, fw->main.text.size);
1509         coherence();
1510         prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1511         prphwrite(ctlr, BsmDramTextSize, fw->main.text.size | (1<<31));
1512         nicunlock(ctlr);
1513
1514         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1515                 free(dma);
1516                 return "main firmware boot failed";
1517         }
1518         free(dma);
1519         return postboot(ctlr);
1520 }
1521
1522 static int
1523 txqready(void *arg)
1524 {
1525         TXQ *q = arg;
1526         return q->n < Ntx;
1527 }
1528
1529 static char*
1530 qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block)
1531 {
1532         uchar *d, *c;
1533         TXQ *q;
1534
1535         assert(qid < nelem(ctlr->tx));
1536         assert(size <= Tcmdsize-4);
1537
1538         ilock(ctlr);
1539         q = &ctlr->tx[qid];
1540         while(q->n >= Ntx && !ctlr->broken){
1541                 iunlock(ctlr);
1542                 qlock(q);
1543                 if(!waserror()){
1544                         tsleep(q, txqready, q, 10);
1545                         poperror();
1546                 }
1547                 qunlock(q);
1548                 ilock(ctlr);
1549         }
1550         if(ctlr->broken){
1551                 iunlock(ctlr);
1552                 return "qcmd: broken";
1553         }
1554         q->n++;
1555
1556         q->lastcmd = code;
1557         q->b[q->i] = block;
1558         c = q->c + q->i * Tcmdsize;
1559         d = q->d + q->i * Tdscsize;
1560
1561         /* build command */
1562         c[0] = code;
1563         c[1] = 0;       /* flags */
1564         c[2] = q->i;
1565         c[3] = qid;
1566
1567         if(size > 0)
1568                 memmove(c+4, data, size);
1569
1570         size += 4;
1571
1572         /* build descriptor */
1573         *d++ = 0;
1574         *d++ = 0;
1575         *d++ = 0;
1576         *d++ = 1 + (block != nil); /* nsegs */
1577         put32(d, PCIWADDR(c));  d += 4;
1578         put16(d, size << 4); d += 2;
1579         if(block != nil){
1580                 put32(d, PCIWADDR(block->rp)); d += 4;
1581                 put16(d, BLEN(block) << 4);
1582         }
1583
1584         coherence();
1585
1586         q->i = (q->i+1) % Ntx;
1587         csr32w(ctlr, HbusTargWptr, (qid<<8) | q->i);
1588
1589         iunlock(ctlr);
1590
1591         return nil;
1592 }
1593
1594 static int
1595 txqempty(void *arg)
1596 {
1597         TXQ *q = arg;
1598         return q->n == 0;
1599 }
1600
1601 static char*
1602 flushq(Ctlr *ctlr, uint qid)
1603 {
1604         TXQ *q;
1605         int i;
1606
1607         q = &ctlr->tx[qid];
1608         qlock(q);
1609         for(i = 0; i < 200 && !ctlr->broken; i++){
1610                 if(txqempty(q)){
1611                         qunlock(q);
1612                         return nil;
1613                 }
1614                 if(!waserror()){
1615                         tsleep(q, txqempty, q, 10);
1616                         poperror();
1617                 }
1618         }
1619         qunlock(q);
1620         if(ctlr->broken)
1621                 return "flushq: broken";
1622         return "flushq: timeout";
1623 }
1624
1625 static char*
1626 cmd(Ctlr *ctlr, uint code, uchar *data, int size)
1627 {
1628         char *err;
1629
1630         if(0) print("cmd %ud\n", code);
1631         if((err = qcmd(ctlr, 4, code, data, size, nil)) != nil)
1632                 return err;
1633         return flushq(ctlr, 4);
1634 }
1635
1636 static void
1637 setled(Ctlr *ctlr, int which, int on, int off)
1638 {
1639         uchar c[8];
1640
1641         csr32w(ctlr, Led, csr32r(ctlr, Led) & ~LedBsmCtrl);
1642
1643         memset(c, 0, sizeof(c));
1644         put32(c, 10000);
1645         c[4] = which;
1646         c[5] = on;
1647         c[6] = off;
1648         cmd(ctlr, 72, c, sizeof(c));
1649 }
1650
1651 static void
1652 addnode(Ctlr *ctlr, uchar id, uchar *addr)
1653 {
1654         uchar c[Tcmdsize], *p;
1655
1656         memset(p = c, 0, sizeof(c));
1657         *p++ = 0;       /* control (1 = update) */
1658         p += 3;         /* reserved */
1659         memmove(p, addr, 6);
1660         p += 6;
1661         p += 2;         /* reserved */
1662         *p++ = id;      /* node id */
1663         p++;            /* flags */
1664         p += 2;         /* reserved */
1665         p += 2;         /* kflags */
1666         p++;            /* tcs2 */
1667         p++;            /* reserved */
1668         p += 5*2;       /* ttak */
1669         p++;            /* kid */
1670         p++;            /* reserved */
1671         p += 16;        /* key */
1672         if(ctlr->type != Type4965){
1673                 p += 8;         /* tcs */
1674                 p += 8;         /* rxmic */
1675                 p += 8;         /* txmic */
1676         }
1677         p += 4;         /* htflags */
1678         p += 4;         /* mask */
1679         p += 2;         /* disable tid */
1680         p += 2;         /* reserved */
1681         p++;            /* add ba tid */
1682         p++;            /* del ba tid */
1683         p += 2;         /* add ba ssn */
1684         p += 4;         /* reserved */
1685         cmd(ctlr, 24, c, p - c);
1686 }
1687
1688 void
1689 rxon(Ether *edev, Wnode *bss)
1690 {
1691         uchar c[Tcmdsize], *p;
1692         int filter, flags;
1693         Ctlr *ctlr;
1694         char *err;
1695
1696         ctlr = edev->ctlr;
1697         filter = FilterMulticast | FilterBeacon;
1698         if(ctlr->prom){
1699                 filter |= FilterPromisc;
1700                 bss = nil;
1701         }
1702         if(bss != nil){
1703                 ctlr->channel = bss->channel;
1704                 memmove(ctlr->bssid, bss->bssid, Eaddrlen);
1705                 ctlr->aid = bss->aid;
1706                 if(ctlr->aid != 0){
1707                         filter |= FilterBSS;
1708                         filter &= ~FilterBeacon;
1709                         ctlr->bssnodeid = -1;
1710                 } else
1711                         ctlr->bcastnodeid = -1;
1712         } else {
1713                 memmove(ctlr->bssid, edev->bcast, Eaddrlen);
1714                 ctlr->aid = 0;
1715                 ctlr->bcastnodeid = -1;
1716                 ctlr->bssnodeid = -1;
1717         }
1718         flags = RFlagTSF | RFlagCTSToSelf | RFlag24Ghz | RFlagAuto;
1719
1720         if(0) print("rxon: bssid %E, aid %x, channel %d, filter %x, flags %x\n",
1721                 ctlr->bssid, ctlr->aid, ctlr->channel, filter, flags);
1722
1723         memset(p = c, 0, sizeof(c));
1724         memmove(p, edev->ea, 6); p += 8;        /* myaddr */
1725         memmove(p, ctlr->bssid, 6); p += 8;     /* bssid */
1726         memmove(p, edev->ea, 6); p += 8;        /* wlap */
1727         *p++ = 3;                               /* mode (STA) */
1728         *p++ = 0;                               /* air (?) */
1729         /* rxchain */
1730         put16(p, ((ctlr->rfcfg.rxantmask & 7)<<1) | (2<<10) | (2<<12));
1731         p += 2;
1732         *p++ = 0xff;                            /* ofdm mask (not yet negotiated) */
1733         *p++ = 0x0f;                            /* cck mask (not yet negotiated) */
1734         put16(p, ctlr->aid & 0x3fff);
1735         p += 2;                                 /* aid */
1736         put32(p, flags);
1737         p += 4;
1738         put32(p, filter);
1739         p += 4;
1740         *p++ = ctlr->channel;
1741         p++;                                    /* reserved */
1742         *p++ = 0xff;                            /* ht single mask */
1743         *p++ = 0xff;                            /* ht dual mask */
1744         if(ctlr->type != Type4965){
1745                 *p++ = 0xff;                    /* ht triple mask */
1746                 p++;                            /* reserved */
1747                 put16(p, 0); p += 2;            /* acquisition */
1748                 p += 2;                         /* reserved */
1749         }
1750         if((err = cmd(ctlr, 16, c, p - c)) != nil){
1751                 print("rxon: %s\n", err);
1752                 return;
1753         }
1754
1755         if(ctlr->bcastnodeid == -1){
1756                 ctlr->bcastnodeid = (ctlr->type != Type4965) ? 15 : 31;
1757                 addnode(ctlr, ctlr->bcastnodeid, edev->bcast);
1758         }
1759         if(ctlr->bssnodeid == -1 && bss != nil && ctlr->aid != 0){
1760                 ctlr->bssnodeid = 0;
1761                 addnode(ctlr, ctlr->bssnodeid, bss->bssid);
1762         }
1763 }
1764
1765 static struct ratetab {
1766         uchar   rate;
1767         uchar   plcp;
1768         uchar   flags;
1769 } ratetab[] = {
1770         {   2,  10, RFlagCCK },
1771         {   4,  20, RFlagCCK },
1772         {  11,  55, RFlagCCK },
1773         {  22, 110, RFlagCCK },
1774         {  12, 0xd, 0 },
1775         {  18, 0xf, 0 },
1776         {  24, 0x5, 0 },
1777         {  36, 0x7, 0 },
1778         {  48, 0x9, 0 },
1779         {  72, 0xb, 0 },
1780         {  96, 0x1, 0 },
1781         { 108, 0x3, 0 },
1782         { 120, 0x3, 0 }
1783 };
1784
1785 enum {
1786         TFlagNeedProtection     = 1<<0,
1787         TFlagNeedRTS            = 1<<1,
1788         TFlagNeedCTS            = 1<<2,
1789         TFlagNeedACK            = 1<<3,
1790         TFlagLinkq              = 1<<4,
1791         TFlagImmBa              = 1<<6,
1792         TFlagFullTxOp           = 1<<7,
1793         TFlagBtDis              = 1<<12,
1794         TFlagAutoSeq            = 1<<13,
1795         TFlagMoreFrag           = 1<<14,
1796         TFlagInsertTs           = 1<<16,
1797         TFlagNeedPadding        = 1<<20,
1798 };
1799
1800 static void
1801 transmit(Wifi *wifi, Wnode *wn, Block *b)
1802 {
1803         int flags, nodeid, rate, ant;
1804         uchar c[Tcmdsize], *p;
1805         Ether *edev;
1806         Ctlr *ctlr;
1807         Wifipkt *w;
1808         char *err;
1809
1810         w = (Wifipkt*)b->rp;
1811         edev = wifi->ether;
1812         ctlr = edev->ctlr;
1813
1814         qlock(ctlr);
1815         if(ctlr->attached == 0 || ctlr->broken){
1816                 qunlock(ctlr);
1817                 freeb(b);
1818                 return;
1819         }
1820
1821         if(ctlr->prom == 0)
1822         if(wn->aid != ctlr->aid
1823         || wn->channel != ctlr->channel
1824         || memcmp(wn->bssid, ctlr->bssid, Eaddrlen) != 0)
1825                 rxon(edev, wn);
1826
1827         rate = 0;
1828         flags = 0;
1829         nodeid = ctlr->bcastnodeid;
1830         if((w->a1[0] & 1) == 0){
1831                 flags |= TFlagNeedACK;
1832
1833                 if(BLEN(b) > 512-4)
1834                         flags |= TFlagNeedRTS;
1835
1836                 if((w->fc[0] & 0x0c) == 0x08 && ctlr->bssnodeid != -1){
1837                         nodeid = ctlr->bssnodeid;
1838                         rate = 2; /* BUG: hardcode 11Mbit */
1839                 }
1840
1841                 if(flags & (TFlagNeedRTS|TFlagNeedCTS)){
1842                         if(ctlr->type != Type4965){
1843                                 flags &= ~(TFlagNeedRTS|TFlagNeedCTS);
1844                                 flags |= TFlagNeedProtection;
1845                         } else
1846                                 flags |= TFlagFullTxOp;
1847                 }
1848         }
1849         qunlock(ctlr);
1850
1851         /* select first available antenna */
1852         ant = ctlr->rfcfg.txantmask & 7;
1853         ant |= (ant == 0);
1854         ant = ((ant - 1) & ant) ^ ant;
1855
1856         memset(p = c, 0, sizeof(c));
1857         put16(p, BLEN(b));
1858         p += 2;
1859         p += 2;         /* lnext */
1860         put32(p, flags);
1861         p += 4;
1862         put32(p, 0);
1863         p += 4;         /* scratch */
1864
1865         *p++ = ratetab[rate].plcp;
1866         *p++ = ratetab[rate].flags | (ant<<6);
1867
1868         p += 2;         /* xflags */
1869         *p++ = nodeid;
1870         *p++ = 0;       /* security */
1871         *p++ = 0;       /* linkq */
1872         p++;            /* reserved */
1873         p += 16;        /* key */
1874         p += 2;         /* fnext */
1875         p += 2;         /* reserved */
1876         put32(p, ~0);   /* lifetime */
1877         p += 4;
1878
1879         /* BUG: scratch ptr? not clear what this is for */
1880         put32(p, PCIWADDR(ctlr->kwpage));
1881         p += 5;
1882
1883         *p++ = 60;      /* rts ntries */
1884         *p++ = 15;      /* data ntries */
1885         *p++ = 0;       /* tid */
1886         put16(p, 0);    /* timeout */
1887         p += 2;
1888         p += 2;         /* txop */
1889         if((err = qcmd(ctlr, 0, 28, c, p - c, b)) != nil){
1890                 print("transmit: %s\n", err);
1891                 freeb(b);
1892         }
1893 }
1894
1895 static long
1896 iwlctl(Ether *edev, void *buf, long n)
1897 {
1898         Ctlr *ctlr;
1899
1900         ctlr = edev->ctlr;
1901         if(ctlr->wifi)
1902                 return wifictl(ctlr->wifi, buf, n);
1903         return 0;
1904 }
1905
1906 static long
1907 iwlifstat(Ether *edev, void *buf, long n, ulong off)
1908 {
1909         Ctlr *ctlr;
1910
1911         ctlr = edev->ctlr;
1912         if(ctlr->wifi)
1913                 return wifistat(ctlr->wifi, buf, n, off);
1914         return 0;
1915 }
1916
1917 static void
1918 setoptions(Ether *edev)
1919 {
1920         Ctlr *ctlr;
1921         char buf[64];
1922         int i;
1923
1924         ctlr = edev->ctlr;
1925         for(i = 0; i < edev->nopt; i++){
1926                 if(strncmp(edev->opt[i], "essid=", 6) == 0){
1927                         snprint(buf, sizeof(buf), "essid %s", edev->opt[i]+6);
1928                         if(!waserror()){
1929                                 wifictl(ctlr->wifi, buf, strlen(buf));
1930                                 poperror();
1931                         }
1932                 }
1933         }
1934 }
1935
1936 static void
1937 iwlpromiscuous(void *arg, int on)
1938 {
1939         Ether *edev;
1940         Ctlr *ctlr;
1941
1942         edev = arg;
1943         ctlr = edev->ctlr;
1944         qlock(ctlr);
1945         ctlr->prom = on;
1946         rxon(edev, ctlr->wifi->bss);
1947         qunlock(ctlr);
1948 }
1949
1950 static void
1951 iwlproc(void *arg)
1952 {
1953         Ether *edev;
1954         Ctlr *ctlr;
1955         Wifi *wifi;
1956         Wnode *bss;
1957
1958         edev = arg;
1959         ctlr = edev->ctlr;
1960         wifi = ctlr->wifi;
1961
1962         for(;;){
1963                 /* hop channels for catching beacons */
1964                 setled(ctlr, 2, 5, 5);
1965                 while(wifi->bss == nil){
1966                         qlock(ctlr);
1967                         if(wifi->bss != nil){
1968                                 qunlock(ctlr);
1969                                 break;
1970                         }
1971                         ctlr->channel = 1 + ctlr->channel % 11;
1972                         ctlr->aid = 0;
1973                         rxon(edev, nil);
1974                         qunlock(ctlr);
1975                         tsleep(&up->sleep, return0, 0, 1000);
1976                 }
1977
1978                 /* wait for association */
1979                 setled(ctlr, 2, 10, 10);
1980                 while((bss = wifi->bss) != nil){
1981                         if(bss->aid != 0)
1982                                 break;
1983                         tsleep(&up->sleep, return0, 0, 1000);
1984                 }
1985
1986                 if(bss == nil)
1987                         continue;
1988
1989                 /* wait for disassociation */
1990                 edev->link = 1;
1991                 setled(ctlr, 2, 0, 1);
1992                 while((bss = wifi->bss) != nil){
1993                         if(bss->aid == 0)
1994                                 break;
1995                         tsleep(&up->sleep, return0, 0, 1000);
1996                 }
1997                 edev->link = 0;
1998         }
1999 }
2000
2001 static void
2002 iwlattach(Ether *edev)
2003 {
2004         char name[32];
2005         FWImage *fw;
2006         Ctlr *ctlr;
2007         char *err;
2008
2009         ctlr = edev->ctlr;
2010         eqlock(ctlr);
2011         if(waserror()){
2012                 print("#l%d: %s\n", edev->ctlrno, up->errstr);
2013                 if(ctlr->power)
2014                         poweroff(ctlr);
2015                 qunlock(ctlr);
2016                 nexterror();
2017         }
2018         if(ctlr->attached == 0){
2019                 if((csr32r(ctlr, Gpc) & RfKill) == 0)
2020                         error("wifi disabled by switch");
2021
2022                 if(ctlr->wifi == nil)
2023                         ctlr->wifi = wifiattach(edev, transmit);
2024
2025                 if(ctlr->fw == nil){
2026                         fw = readfirmware(fwname[ctlr->type]);
2027                         print("#l%d: firmware: %s, rev %ux, build %ud, size %ux+%ux+%ux+%ux+%ux\n",
2028                                 edev->ctlrno,
2029                                 fwname[ctlr->type],
2030                                 fw->rev, fw->build,
2031                                 fw->main.text.size, fw->main.data.size,
2032                                 fw->init.text.size, fw->init.data.size,
2033                                 fw->boot.text.size);
2034                         ctlr->fw = fw;
2035                 }
2036
2037                 if((err = reset(ctlr)) != nil)
2038                         error(err);
2039                 if((err = boot(ctlr)) != nil)
2040                         error(err);
2041
2042                 ctlr->bcastnodeid = -1;
2043                 ctlr->bssnodeid = -1;
2044                 ctlr->channel = 1;
2045                 ctlr->aid = 0;
2046
2047                 setoptions(edev);
2048
2049                 snprint(name, sizeof(name), "#l%diwl", edev->ctlrno);
2050                 kproc(name, iwlproc, edev);
2051
2052                 ctlr->attached = 1;
2053         }
2054         qunlock(ctlr);
2055         poperror();
2056 }
2057
2058 static void
2059 receive(Ctlr *ctlr)
2060 {
2061         Block *b, *bb;
2062         uchar *d, *dd, *cc;
2063         RXQ *rx;
2064         TXQ *tx;
2065         uint hw;
2066
2067         rx = &ctlr->rx;
2068         if(ctlr->broken || rx->s == nil || rx->b == nil)
2069                 return;
2070         for(hw = get16(rx->s) % Nrx; rx->i != hw; rx->i = (rx->i + 1) % Nrx){
2071                 uchar type, flags, idx, qid;
2072                 u32int len;
2073
2074                 b = rx->b[rx->i];
2075                 if(b == nil)
2076                         continue;
2077
2078                 d = b->rp;
2079                 len = get32(d); d += 4;
2080                 type = *d++;
2081                 flags = *d++;
2082                 USED(flags);
2083                 idx = *d++;
2084                 qid = *d++;
2085
2086                 if((qid & 0x80) == 0 && qid < nelem(ctlr->tx)){
2087                         tx = &ctlr->tx[qid];
2088                         if(tx->n > 0){
2089                                 bb = tx->b[idx];
2090                                 if(bb != nil){
2091                                         tx->b[idx] = nil;
2092                                         freeb(bb);
2093                                 }
2094                                 /* paranoia: clear tx descriptors */
2095                                 dd = tx->d + idx*Tdscsize;
2096                                 cc = tx->c + idx*Tcmdsize;
2097                                 memset(dd, 0, Tdscsize);
2098                                 memset(cc, 0, Tcmdsize);
2099                                 tx->n--;
2100
2101                                 wakeup(tx);
2102                         }
2103                 }
2104
2105                 len &= 0x3fff;
2106                 if(len < 4 || type == 0)
2107                         continue;
2108
2109                 len -= 4;
2110                 switch(type){
2111                 case 1:         /* microcontroller ready */
2112                         setfwinfo(ctlr, d, len);
2113                         break;
2114                 case 24:        /* add node done */
2115                         break;
2116                 case 28:        /* tx done */
2117                         break;
2118                 case 102:       /* calibration result (Type5000 only) */
2119                         if(len < 4)
2120                                 break;
2121                         idx = d[0];
2122                         if(idx >= nelem(ctlr->calib.cmd))
2123                                 break;
2124                         if(rbplant(ctlr, rx->i) < 0)
2125                                 break;
2126                         if(ctlr->calib.cmd[idx] != nil)
2127                                 freeb(ctlr->calib.cmd[idx]);
2128                         b->rp = d;
2129                         b->wp = d + len;
2130                         ctlr->calib.cmd[idx] = b;
2131                         continue;
2132                 case 103:       /* calibration done (Type5000 only) */
2133                         ctlr->calib.done = 1;
2134                         break;
2135                 case 130:       /* start scan */
2136                         break;
2137                 case 132:       /* stop scan */
2138                         break;
2139                 case 156:       /* rx statistics */
2140                         break;
2141                 case 157:       /* beacon statistics */
2142                         break;
2143                 case 161:       /* state changed */
2144                         break;
2145                 case 162:       /* beacon missed */
2146                         break;
2147                 case 192:       /* rx phy */
2148                         break;
2149                 case 195:       /* rx done */
2150                         if(d + 2 > b->lim)
2151                                 break;
2152                         d += d[1];
2153                         d += 56;
2154                 case 193:       /* mpdu rx done */
2155                         if(d + 4 > b->lim)
2156                                 break;
2157                         len = get16(d); d += 4;
2158                         if(d + len + 4 > b->lim)
2159                                 break;
2160                         if((get32(d + len) & 3) != 3)
2161                                 break;
2162                         if(ctlr->wifi == nil)
2163                                 break;
2164                         if(rbplant(ctlr, rx->i) < 0)
2165                                 break;
2166                         b->rp = d;
2167                         b->wp = d + len;
2168                         wifiiq(ctlr->wifi, b);
2169                         continue;
2170                 case 197:       /* rx compressed ba */
2171                         break;
2172                 }
2173                 /* paranoia: clear the descriptor */
2174                 memset(b->rp, 0, Rdscsize);
2175         }
2176         csr32w(ctlr, FhRxWptr, ((hw+Nrx-1) % Nrx) & ~7);
2177 }
2178
2179 static void
2180 iwlinterrupt(Ureg*, void *arg)
2181 {
2182         u32int isr, fhisr;
2183         Ether *edev;
2184         Ctlr *ctlr;
2185
2186         edev = arg;
2187         ctlr = edev->ctlr;
2188         ilock(ctlr);
2189         csr32w(ctlr, Imr, 0);
2190         isr = csr32r(ctlr, Isr);
2191         fhisr = csr32r(ctlr, FhIsr);
2192         if(isr == 0xffffffff || (isr & 0xfffffff0) == 0xa5a5a5a0){
2193                 iunlock(ctlr);
2194                 return;
2195         }
2196         if(isr == 0 && fhisr == 0)
2197                 goto done;
2198         csr32w(ctlr, Isr, isr);
2199         csr32w(ctlr, FhIsr, fhisr);
2200         if((isr & (Iswrx | Ifhrx | Irxperiodic)) || (fhisr & Ifhrx))
2201                 receive(ctlr);
2202         if(isr & Ierr){
2203                 ctlr->broken = 1;
2204                 iprint("#l%d: fatal firmware error\n", edev->ctlrno);
2205                 dumpctlr(ctlr);
2206         }
2207         ctlr->wait.m |= isr;
2208         if(ctlr->wait.m & ctlr->wait.w){
2209                 ctlr->wait.r = ctlr->wait.m & ctlr->wait.w;
2210                 ctlr->wait.m &= ~ctlr->wait.r;
2211                 wakeup(&ctlr->wait);
2212         }
2213 done:
2214         csr32w(ctlr, Imr, ctlr->ie);
2215         iunlock(ctlr);
2216 }
2217
2218 static Ctlr *iwlhead, *iwltail;
2219
2220 static void
2221 iwlpci(void)
2222 {
2223         Pcidev *pdev;
2224
2225         pdev = nil;
2226         while(pdev = pcimatch(pdev, 0, 0)) {
2227                 Ctlr *ctlr;
2228                 void *mem;
2229
2230                 if(pdev->ccrb != 2 || pdev->ccru != 0x80)
2231                         continue;
2232                 if(pdev->vid != 0x8086)
2233                         continue;
2234
2235                 switch(pdev->did){
2236                 default:
2237                         continue;
2238                 case 0x0084:  /* WiFi Link 1000 */
2239                 case 0x4229:    /* WiFi Link 4965 */
2240                 case 0x4230:    /* WiFi Link 4965 */
2241                 case 0x4236:    /* WiFi Link 5300 AGN */
2242                 case 0x4237:    /* Wifi Link 5100 AGN */
2243                 case 0x0085:    /* Centrino Advanced-N 6205 */
2244                 case 0x422b:    /* Centrino Ultimate-N 6300 */
2245                         break;
2246                 }
2247
2248                 /* Clear device-specific "PCI retry timeout" register (41h). */
2249                 if(pcicfgr8(pdev, 0x41) != 0)
2250                         pcicfgw8(pdev, 0x41, 0);
2251
2252                 /* Clear interrupt disable bit. Hardware bug workaround. */
2253                 if(pdev->pcr & 0x400){
2254                         pdev->pcr &= ~0x400;
2255                         pcicfgw16(pdev, PciPCR, pdev->pcr);
2256                 }
2257
2258                 pcisetbme(pdev);
2259                 pcisetpms(pdev, 0);
2260
2261                 ctlr = malloc(sizeof(Ctlr));
2262                 if(ctlr == nil) {
2263                         print("iwl: unable to alloc Ctlr\n");
2264                         continue;
2265                 }
2266                 ctlr->port = pdev->mem[0].bar & ~0x0F;
2267                 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
2268                 if(mem == nil) {
2269                         print("iwl: can't map %8.8luX\n", pdev->mem[0].bar);
2270                         free(ctlr);
2271                         continue;
2272                 }
2273                 ctlr->nic = mem;
2274                 ctlr->pdev = pdev;
2275                 ctlr->type = (csr32r(ctlr, Rev) >> 4) & 0xF;
2276
2277                 if(fwname[ctlr->type] == nil){
2278                         print("iwl: unsupported controller type %d\n", ctlr->type);
2279                         vunmap(mem, pdev->mem[0].size);
2280                         free(ctlr);
2281                         continue;
2282                 }
2283
2284                 if(iwlhead != nil)
2285                         iwltail->link = ctlr;
2286                 else
2287                         iwlhead = ctlr;
2288                 iwltail = ctlr;
2289         }
2290 }
2291
2292 static int
2293 iwlpnp(Ether* edev)
2294 {
2295         Ctlr *ctlr;
2296
2297         if(iwlhead == nil)
2298                 iwlpci();
2299 again:
2300         for(ctlr = iwlhead; ctlr != nil; ctlr = ctlr->link){
2301                 if(ctlr->active)
2302                         continue;
2303                 if(edev->port == 0 || edev->port == ctlr->port){
2304                         ctlr->active = 1;
2305                         break;
2306                 }
2307         }
2308
2309         if(ctlr == nil)
2310                 return -1;
2311
2312         edev->ctlr = ctlr;
2313         edev->port = ctlr->port;
2314         edev->irq = ctlr->pdev->intl;
2315         edev->tbdf = ctlr->pdev->tbdf;
2316         edev->arg = edev;
2317         edev->interrupt = iwlinterrupt;
2318         edev->attach = iwlattach;
2319         edev->ifstat = iwlifstat;
2320         edev->ctl = iwlctl;
2321         edev->promiscuous = iwlpromiscuous;
2322         edev->multicast = nil;
2323         edev->mbps = 10;
2324
2325         if(iwlinit(edev) < 0){
2326                 edev->ctlr = nil;
2327                 goto again;
2328         }
2329
2330         return 0;
2331 }
2332
2333 void
2334 etheriwllink(void)
2335 {
2336         addethercard("iwl", iwlpnp);
2337 }