sys/src/9/pc/etheriwl.c

   1 /*
   2  * Intel WiFi Link driver.
   3  *
   4  * Written without any documentation but Damien Bergaminis
   5  * OpenBSD iwn(4) driver sources. Requires intel firmware
   6  * to be present in /lib/firmware/iwn-* on attach.
   7  */
   8
   9 #include "u.h"
  10 #include "../port/lib.h"
  11 #include "mem.h"
  12 #include "dat.h"
  13 #include "fns.h"
  14 #include "io.h"
  15 #include "../port/error.h"
  16 #include "../port/netif.h"
  17
  18 #include "etherif.h"
  19 #include "wifi.h"
  20
  21 enum {
  22         Ntxlog          = 8,
  23         Ntx             = 1<<Ntxlog,
  24         Nrxlog          = 8,
  25         Nrx             = 1<<Nrxlog,
  26
  27         Rstatsize       = 16,
  28         Rbufsize        = 4*1024,
  29         Rdscsize        = 8,
  30
  31         Tbufsize        = 4*1024,
  32         Tdscsize        = 128,
  33         Tcmdsize        = 140,
  34 };
  35
  36 /* registers */
  37 enum {
  38         Cfg             = 0x000,        /* config register */
  39                 MacSi           = 1<<8,
  40                 RadioSi         = 1<<9,
  41                 EepromLocked    = 1<<21,
  42                 NicReady        = 1<<22,
  43                 HapwakeL1A      = 1<<23,
  44                 PrepareDone     = 1<<25,
  45                 Prepare         = 1<<27,
  46
  47         Isr             = 0x008,        /* interrupt status */
  48         Imr             = 0x00c,        /* interrupt mask */
  49                 Ialive          = 1<<0,
  50                 Iwakeup         = 1<<1,
  51                 Iswrx           = 1<<3,
  52                 Ictreached      = 1<<6,
  53                 Irftoggled      = 1<<7,
  54                 Iswerr          = 1<<25,
  55                 Isched          = 1<<26,
  56                 Ifhtx           = 1<<27,
  57                 Irxperiodic     = 1<<28,
  58                 Ihwerr          = 1<<29,
  59                 Ifhrx           = 1<<31,
  60
  61                 Ierr            = Iswerr | Ihwerr,
  62                 Idefmask        = Ierr | Ifhtx | Ifhrx | Ialive | Iwakeup | Iswrx | Ictreached | Irftoggled,
  63
  64         FhIsr           = 0x010,        /* second interrupt status */
  65
  66         Reset           = 0x020,
  67
  68         Rev             = 0x028,        /* hardware revision */
  69
  70         EepromIo        = 0x02c,        /* EEPROM i/o register */
  71         EepromGp        = 0x030,
  72
  73         OtpromGp        = 0x034,
  74                 DevSelOtp       = 1<<16,
  75                 RelativeAccess  = 1<<17,
  76                 EccCorrStts     = 1<<20,
  77                 EccUncorrStts   = 1<<21,
  78
  79         Gpc             = 0x024,        /* gp cntrl */
  80                 MacAccessEna    = 1<<0,
  81                 MacClockReady   = 1<<0,
  82                 InitDone        = 1<<2,
  83                 MacAccessReq    = 1<<3,
  84                 NicSleep        = 1<<4,
  85                 RfKill          = 1<<27,
  86
  87         Gio             = 0x03c,
  88                 EnaL0S          = 1<<1,
  89
  90         Led             = 0x094,
  91                 LedBsmCtrl      = 1<<5,
  92                 LedOn           = 0x38,
  93                 LedOff          = 0x78,
  94
  95         UcodeGp1Clr     = 0x05c,
  96                 UcodeGp1RfKill          = 1<<1,
  97                 UcodeGp1CmdBlocked      = 1<<2,
  98                 UcodeGp1CtempStopRf     = 1<<3,
  99
 100         ShadowRegCtrl   = 0x0a8,
 101
 102         Giochicken      = 0x100,
 103                 L1AnoL0Srx      = 1<<23,
 104                 DisL0Stimer     = 1<<29,
 105
 106         AnaPll          = 0x20c,
 107
 108         Dbghpetmem      = 0x240,
 109         Dbglinkpwrmgmt  = 0x250,
 110
 111         MemRaddr        = 0x40c,
 112         MemWaddr        = 0x410,
 113         MemWdata        = 0x418,
 114         MemRdata        = 0x41c,
 115
 116         PrphWaddr       = 0x444,
 117         PrphRaddr       = 0x448,
 118         PrphWdata       = 0x44c,
 119         PrphRdata       = 0x450,
 120
 121         HbusTargWptr    = 0x460,
 122 };
 123
 124 /*
 125  * Flow-Handler registers.
 126  */
 127 enum {
 128         FhTfbdCtrl0     = 0x1900,       // +q*8
 129         FhTfbdCtrl1     = 0x1904,       // +q*8
 130
 131         FhKwAddr        = 0x197c,
 132
 133         FhSramAddr      = 0x19a4,       // +q*4
 134         FhCbbcQueue     = 0x19d0,       // +q*4
 135         FhStatusWptr    = 0x1bc0,
 136         FhRxBase        = 0x1bc4,
 137         FhRxWptr        = 0x1bc8,
 138         FhRxConfig      = 0x1c00,
 139                 FhRxConfigEna           = 1<<31,
 140                 FhRxConfigRbSize8K      = 1<<16,
 141                 FhRxConfigSingleFrame   = 1<<15,
 142                 FhRxConfigIrqDstHost    = 1<<12,
 143                 FhRxConfigIgnRxfEmpty   = 1<<2,
 144
 145                 FhRxConfigNrbdShift     = 20,
 146                 FhRxConfigRbTimeoutShift= 4,
 147
 148         FhRxStatus      = 0x1c44,
 149
 150         FhTxConfig      = 0x1d00,       // +q*32
 151                 FhTxConfigDmaCreditEna  = 1<<3,
 152                 FhTxConfigDmaEna        = 1<<31,
 153                 FhTxConfigCirqHostEndTfd= 1<<20,
 154
 155         FhTxBufStatus   = 0x1d08,       // +q*32
 156                 FhTxBufStatusTbNumShift = 20,
 157                 FhTxBufStatusTbIdxShift = 12,
 158                 FhTxBufStatusTfbdValid  = 3,
 159
 160         FhTxChicken     = 0x1e98,
 161         FhTxStatus      = 0x1eb0,
 162 };
 163
 164 /*
 165  * NIC internal memory offsets.
 166  */
 167 enum {
 168         ApmgClkCtrl     = 0x3000,
 169         ApmgClkEna      = 0x3004,
 170         ApmgClkDis      = 0x3008,
 171                 DmaClkRqt       = 1<<9,
 172                 BsmClkRqt       = 1<<11,
 173
 174         ApmgPs          = 0x300c,
 175                 EarlyPwroffDis  = 1<<22,
 176                 PwrSrcVMain     = 0<<24,
 177                 PwrSrcVAux      = 2<<24,
 178                 PwrSrcMask      = 3<<24,
 179                 ResetReq        = 1<<26,
 180
 181         ApmgDigitalSvr  = 0x3058,
 182         ApmgAnalogSvr   = 0x306c,
 183         ApmgPciStt      = 0x3010,
 184         BsmWrCtrl       = 0x3400,
 185         BsmWrMemSrc     = 0x3404,
 186         BsmWrMemDst     = 0x3408,
 187         BsmWrDwCount    = 0x340c,
 188         BsmDramTextAddr = 0x3490,
 189         BsmDramTextSize = 0x3494,
 190         BsmDramDataAddr = 0x3498,
 191         BsmDramDataSize = 0x349c,
 192         BsmSramBase     = 0x3800,
 193 };
 194
 195 /*
 196  * TX scheduler registers.
 197  */
 198 enum {
 199         SchedBase               = 0xa02c00,
 200         SchedSramAddr           = SchedBase,
 201
 202         SchedDramAddr4965       = SchedBase+0x010,
 203         SchedTxFact4965         = SchedBase+0x01c,
 204         SchedQueueRdptr4965     = SchedBase+0x064,      // +q*4
 205         SchedQChainSel4965      = SchedBase+0x0d0,
 206         SchedIntrMask4965       = SchedBase+0x0e4,
 207         SchedQueueStatus4965    = SchedBase+0x104,      // +q*4
 208
 209         SchedDramAddr5000       = SchedBase+0x008,
 210         SchedTxFact5000         = SchedBase+0x010,
 211         SchedQueueRdptr5000     = SchedBase+0x068,      // +q*4
 212         SchedQChainSel5000      = SchedBase+0x0e8,
 213         SchedIntrMask5000       = SchedBase+0x108,
 214         SchedQueueStatus5000    = SchedBase+0x10c,      // +q*4
 215         SchedAggrSel5000        = SchedBase+0x248,
 216 };
 217
 218 enum {
 219         SchedCtxOff4965         = 0x380,
 220         SchedCtxLen4965         = 416,
 221
 222         SchedCtxOff5000         = 0x600,
 223         SchedCtxLen5000         = 512,
 224 };
 225
 226 enum {
 227         FilterPromisc           = 1<<0,
 228         FilterCtl               = 1<<1,
 229         FilterMulticast         = 1<<2,
 230         FilterNoDecrypt         = 1<<3,
 231         FilterBSS               = 1<<5,
 232         FilterBeacon            = 1<<6,
 233 };
 234
 235 enum {
 236         RFlag24Ghz              = 1<<0,
 237         RFlagCCK                = 1<<1,
 238         RFlagAuto               = 1<<2,
 239         RFlagShSlot             = 1<<4,
 240         RFlagShPreamble         = 1<<5,
 241         RFlagNoDiversity        = 1<<7,
 242         RFlagAntennaA           = 1<<8,
 243         RFlagAntennaB           = 1<<9,
 244         RFlagTSF                = 1<<15,
 245         RFlagCTSToSelf          = 1<<30,
 246 };
 247
 248 typedef struct FWInfo FWInfo;
 249 typedef struct FWImage FWImage;
 250 typedef struct FWSect FWSect;
 251
 252 typedef struct TXQ TXQ;
 253 typedef struct RXQ RXQ;
 254
 255 typedef struct Ctlr Ctlr;
 256
 257 struct FWSect
 258 {
 259         uchar   *data;
 260         uint    size;
 261 };
 262
 263 struct FWImage
 264 {
 265         struct {
 266                 FWSect  text;
 267                 FWSect  data;
 268         } init, main, boot;
 269
 270         uint    rev;
 271         uint    build;
 272         char    descr[64+1];
 273         uchar   data[];
 274 };
 275
 276 struct FWInfo
 277 {
 278         uchar   major;
 279         uchar   minjor;
 280         uchar   type;
 281         uchar   subtype;
 282
 283         u32int  logptr;
 284         u32int  errptr;
 285         u32int  tstamp;
 286         u32int  valid;
 287 };
 288
 289 struct TXQ
 290 {
 291         uint    n;
 292         uint    i;
 293         Block   **b;
 294         uchar   *d;
 295         uchar   *c;
 296
 297         uint    lastcmd;
 298
 299         Rendez;
 300         QLock;
 301 };
 302
 303 struct RXQ
 304 {
 305         uint    i;
 306         Block   **b;
 307         u32int  *p;
 308         uchar   *s;
 309 };
 310
 311 struct Ctlr {
 312         Lock;
 313         QLock;
 314
 315         Ctlr *link;
 316         Pcidev *pdev;
 317         Wifi *wifi;
 318
 319         int type;
 320         int port;
 321         int power;
 322         int active;
 323         int broken;
 324         int attached;
 325
 326         u32int ie;
 327
 328         u32int *nic;
 329         uchar *kwpage;
 330
 331         /* assigned node ids in hardware node table or -1 if unassigned */
 332         int bcastnodeid;
 333         int bssnodeid;
 334
 335         /* current receiver settings */
 336         uchar bssid[Eaddrlen];
 337         int channel;
 338         int prom;
 339         int aid;
 340
 341         RXQ rx;
 342         TXQ tx[20];
 343
 344         struct {
 345                 Rendez;
 346                 u32int  m;
 347                 u32int  w;
 348                 u32int  r;
 349         } wait;
 350
 351         struct {
 352                 uchar   type;
 353                 uchar   step;
 354                 uchar   dash;
 355                 uchar   txantmask;
 356                 uchar   rxantmask;
 357         } rfcfg;
 358
 359         struct {
 360                 int     otp;
 361                 uint    off;
 362
 363                 uchar   version;
 364                 uchar   type;
 365                 u16int  volt;
 366
 367                 char    regdom[4+1];
 368
 369                 u32int  crystal;
 370         } eeprom;
 371
 372         struct {
 373                 Block   *cmd[21];
 374                 int     done;
 375         } calib;
 376
 377         struct {
 378                 u32int  base;
 379                 uchar   *s;
 380         } sched;
 381
 382         FWInfo fwinfo;
 383         FWImage *fw;
 384 };
 385
 386 /* controller types */
 387 enum {
 388         Type4965        = 0,
 389         Type5300        = 2,
 390         Type5350        = 3,
 391         Type5150        = 4,
 392         Type5100        = 5,
 393         Type1000        = 6,
 394         Type6000        = 7,
 395         Type6050        = 8,
 396         Type6005        = 11,
 397 };
 398
 399 static char *fwname[16] = {
 400         [Type4965] "iwn-4965",
 401         [Type5300] "iwn-5000",
 402         [Type5350] "iwn-5000",
 403         [Type5150] "iwn-5150",
 404         [Type5100] "iwn-5000",
 405         [Type1000] "iwn-1000",
 406         [Type6000] "iwn-6000",
 407         [Type6050] "iwn-6050",
 408         [Type6005] "iwn-6005",
 409 };
 410
 411 static char *qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block);
 412 static char *flushq(Ctlr *ctlr, uint qid);
 413 static char *cmd(Ctlr *ctlr, uint code, uchar *data, int size);
 414
 415 #define csr32r(c, r)    (*((c)->nic+((r)/4)))
 416 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
 417
 418 static uint
 419 get16(uchar *p){
 420         return *((u16int*)p);
 421 }
 422 static uint
 423 get32(uchar *p){
 424         return *((u32int*)p);
 425 }
 426 static void
 427 put32(uchar *p, uint v){
 428         *((u32int*)p) = v;
 429 }
 430 static void
 431 put16(uchar *p, uint v){
 432         *((u16int*)p) = v;
 433 };
 434
 435 static char*
 436 niclock(Ctlr *ctlr)
 437 {
 438         int i;
 439
 440         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | MacAccessReq);
 441         for(i=0; i<1000; i++){
 442                 if((csr32r(ctlr, Gpc) & (NicSleep | MacAccessEna)) == MacAccessEna)
 443                         return 0;
 444                 delay(10);
 445         }
 446         return "niclock: timeout";
 447 }
 448
 449 static void
 450 nicunlock(Ctlr *ctlr)
 451 {
 452         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~MacAccessReq);
 453 }
 454
 455 static u32int
 456 prphread(Ctlr *ctlr, uint off)
 457 {
 458         csr32w(ctlr, PrphRaddr, ((sizeof(u32int)-1)<<24) | off);
 459         coherence();
 460         return csr32r(ctlr, PrphRdata);
 461 }
 462 static void
 463 prphwrite(Ctlr *ctlr, uint off, u32int data)
 464 {
 465         csr32w(ctlr, PrphWaddr, ((sizeof(u32int)-1)<<24) | off);
 466         coherence();
 467         csr32w(ctlr, PrphWdata, data);
 468 }
 469
 470 static u32int
 471 memread(Ctlr *ctlr, uint off)
 472 {
 473         csr32w(ctlr, MemRaddr, off);
 474         coherence();
 475         return csr32r(ctlr, MemRdata);
 476 }
 477 static void
 478 memwrite(Ctlr *ctlr, uint off, u32int data)
 479 {
 480         csr32w(ctlr, MemWaddr, off);
 481         coherence();
 482         csr32w(ctlr, MemWdata, data);
 483 }
 484
 485 static void
 486 setfwinfo(Ctlr *ctlr, uchar *d, int len)
 487 {
 488         FWInfo *i;
 489
 490         if(len < 32)
 491                 return;
 492         i = &ctlr->fwinfo;
 493         i->minjor = *d++;
 494         i->major = *d++;
 495         d += 2+8;
 496         i->type = *d++;
 497         i->subtype = *d++;
 498         d += 2;
 499         i->logptr = get32(d); d += 4;
 500         i->errptr = get32(d); d += 4;
 501         i->tstamp = get32(d); d += 4;
 502         i->valid = get32(d);
 503 };
 504
 505 static void
 506 dumpctlr(Ctlr *ctlr)
 507 {
 508         u32int dump[13];
 509         int i;
 510
 511         print("lastcmd: %ud (0x%ux)\n", ctlr->tx[4].lastcmd,  ctlr->tx[4].lastcmd);
 512         if(ctlr->fwinfo.errptr == 0){
 513                 print("no error pointer\n");
 514                 return;
 515         }
 516         for(i=0; i<nelem(dump); i++)
 517                 dump[i] = memread(ctlr, ctlr->fwinfo.errptr + i*4);
 518         print(  "error:\tid %ux, pc %ux,\n"
 519                 "\tbranchlink %.8ux %.8ux, interruptlink %.8ux %.8ux,\n"
 520                 "\terrordata %.8ux %.8ux, srcline %ud, tsf %ux, time %ux\n",
 521                 dump[1], dump[2],
 522                 dump[4], dump[3], dump[6], dump[5],
 523                 dump[7], dump[8], dump[9], dump[10], dump[11]);
 524 }
 525
 526 static char*
 527 eepromlock(Ctlr *ctlr)
 528 {
 529         int i, j;
 530
 531         for(i=0; i<100; i++){
 532                 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | EepromLocked);
 533                 for(j=0; j<100; j++){
 534                         if(csr32r(ctlr, Cfg) & EepromLocked)
 535                                 return 0;
 536                         delay(10);
 537                 }
 538         }
 539         return "eepromlock: timeout";
 540 }
 541 static void
 542 eepromunlock(Ctlr *ctlr)
 543 {
 544         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) & ~EepromLocked);
 545 }
 546 static char*
 547 eepromread(Ctlr *ctlr, void *data, int count, uint off)
 548 {
 549         uchar *out = data;
 550         u32int w, s;
 551         int i;
 552
 553         w = 0;
 554         off += ctlr->eeprom.off;
 555         for(; count > 0; count -= 2, off++){
 556                 csr32w(ctlr, EepromIo, off << 2);
 557                 for(i=0; i<10; i++){
 558                         w = csr32r(ctlr, EepromIo);
 559                         if(w & 1)
 560                                 break;
 561                         delay(5);
 562                 }
 563                 if(i == 10)
 564                         return "eepromread: timeout";
 565                 if(ctlr->eeprom.otp){
 566                         s = csr32r(ctlr, OtpromGp);
 567                         if(s & EccUncorrStts)
 568                                 return "eepromread: otprom ecc error";
 569                         if(s & EccCorrStts)
 570                                 csr32w(ctlr, OtpromGp, s);
 571                 }
 572                 *out++ = w >> 16;
 573                 if(count > 1)
 574                         *out++ = w >> 24;
 575         }
 576         return 0;
 577 }
 578
 579 static char*
 580 handover(Ctlr *ctlr)
 581 {
 582         int i;
 583
 584         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
 585         for(i=0; i<5; i++){
 586                 if(csr32r(ctlr, Cfg) & NicReady)
 587                         return 0;
 588                 delay(10);
 589         }
 590         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | Prepare);
 591         for(i=0; i<15000; i++){
 592                 if((csr32r(ctlr, Cfg) & PrepareDone) == 0)
 593                         break;
 594                 delay(10);
 595         }
 596         if(i >= 15000)
 597                 return "handover: timeout";
 598         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
 599         for(i=0; i<5; i++){
 600                 if(csr32r(ctlr, Cfg) & NicReady)
 601                         return 0;
 602                 delay(10);
 603         }
 604         return "handover: timeout";
 605 }
 606
 607 static char*
 608 clockwait(Ctlr *ctlr)
 609 {
 610         int i;
 611
 612         /* Set "initialization complete" bit. */
 613         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | InitDone);
 614         for(i=0; i<2500; i++){
 615                 if(csr32r(ctlr, Gpc) & MacClockReady)
 616                         return 0;
 617                 delay(10);
 618         }
 619         return "clockwait: timeout";
 620 }
 621
 622 static char*
 623 poweron(Ctlr *ctlr)
 624 {
 625         int capoff;
 626         char *err;
 627
 628         /* Disable L0s exit timer (NMI bug workaround). */
 629         csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | DisL0Stimer);
 630
 631         /* Don't wait for ICH L0s (ICH bug workaround). */
 632         csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | L1AnoL0Srx);
 633
 634         /* Set FH wait threshold to max (HW bug under stress workaround). */
 635         csr32w(ctlr, Dbghpetmem, csr32r(ctlr, Dbghpetmem) | 0xffff0000);
 636
 637         /* Enable HAP INTA to move adapter from L1a to L0s. */
 638         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | HapwakeL1A);
 639
 640         capoff = pcicap(ctlr->pdev, PciCapPCIe);
 641         if(capoff != -1){
 642                 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
 643                 if(pcicfgr16(ctlr->pdev, capoff + 0x10) & 0x2)  /* LCSR -> L1 Entry enabled. */
 644                         csr32w(ctlr, Gio, csr32r(ctlr, Gio) | EnaL0S);
 645                 else
 646                         csr32w(ctlr, Gio, csr32r(ctlr, Gio) & ~EnaL0S);
 647         }
 648
 649         if(ctlr->type != Type4965 && ctlr->type <= Type1000)
 650                 csr32w(ctlr, AnaPll, csr32r(ctlr, AnaPll) | 0x00880300);
 651
 652         /* Wait for clock stabilization before accessing prph. */
 653         if((err = clockwait(ctlr)) != nil)
 654                 return err;
 655
 656         if((err = niclock(ctlr)) != nil)
 657                 return err;
 658
 659         /* Enable DMA and BSM (Bootstrap State Machine). */
 660         if(ctlr->type == Type4965)
 661                 prphwrite(ctlr, ApmgClkEna, DmaClkRqt | BsmClkRqt);
 662         else
 663                 prphwrite(ctlr, ApmgClkEna, DmaClkRqt);
 664         delay(20);
 665
 666         /* Disable L1-Active. */
 667         prphwrite(ctlr, ApmgPciStt, prphread(ctlr, ApmgPciStt) | (1<<11));
 668
 669         nicunlock(ctlr);
 670
 671         ctlr->power = 1;
 672
 673         return 0;
 674 }
 675
 676 static void
 677 poweroff(Ctlr *ctlr)
 678 {
 679         int i, j;
 680
 681         csr32w(ctlr, Reset, 1);
 682
 683         /* Disable interrupts */
 684         ctlr->ie = 0;
 685         csr32w(ctlr, Imr, 0);
 686         csr32w(ctlr, Isr, ~0);
 687         csr32w(ctlr, FhIsr, ~0);
 688
 689         /* Stop scheduler */
 690         if(ctlr->type != Type4965)
 691                 prphwrite(ctlr, SchedTxFact5000, 0);
 692         else
 693                 prphwrite(ctlr, SchedTxFact4965, 0);
 694
 695         /* Stop TX ring */
 696         if(niclock(ctlr) == nil){
 697                 for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--){
 698                         csr32w(ctlr, FhTxConfig + i*32, 0);
 699                         for(j = 0; j < 200; j++){
 700                                 if(csr32r(ctlr, FhTxStatus) & (0x10000<<i))
 701                                         break;
 702                                 delay(10);
 703                         }
 704                 }
 705                 nicunlock(ctlr);
 706         }
 707
 708         /* Stop RX ring */
 709         if(niclock(ctlr) == nil){
 710                 csr32w(ctlr, FhRxConfig, 0);
 711                 for(j = 0; j < 200; j++){
 712                         if(csr32r(ctlr, FhRxStatus) & 0x1000000)
 713                                 break;
 714                         delay(10);
 715                 }
 716                 nicunlock(ctlr);
 717         }
 718
 719         /* Disable DMA */
 720         if(niclock(ctlr) == nil){
 721                 prphwrite(ctlr, ApmgClkDis, DmaClkRqt);
 722                 nicunlock(ctlr);
 723         }
 724         delay(5);
 725
 726         /* Stop busmaster DMA activity. */
 727         csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<9));
 728         for(j = 0; j < 100; j++){
 729                 if(csr32r(ctlr, Reset) & (1<<8))
 730                         break;
 731                 delay(10);
 732         }
 733
 734         /* Reset the entire device. */
 735         csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<7));
 736         delay(10);
 737
 738         /* Clear "initialization complete" bit. */
 739         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~InitDone);
 740
 741         ctlr->power = 0;
 742 }
 743
 744 static char*
 745 rominit(Ctlr *ctlr)
 746 {
 747         uchar buf[2];
 748         char *err;
 749         uint off;
 750         int i;
 751
 752         ctlr->eeprom.otp = 0;
 753         ctlr->eeprom.off = 0;
 754         if(ctlr->type < Type1000 || (csr32r(ctlr, OtpromGp) & DevSelOtp) == 0)
 755                 return nil;
 756
 757         /* Wait for clock stabilization before accessing prph. */
 758         if((err = clockwait(ctlr)) != nil)
 759                 return err;
 760
 761         if((err = niclock(ctlr)) != nil)
 762                 return err;
 763         prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | ResetReq);
 764         delay(5);
 765         prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) & ~ResetReq);
 766         nicunlock(ctlr);
 767
 768         /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
 769         if(ctlr->type != Type1000)
 770                 csr32w(ctlr, Dbglinkpwrmgmt, csr32r(ctlr, Dbglinkpwrmgmt) | (1<<31));
 771
 772         csr32w(ctlr, EepromGp, csr32r(ctlr, EepromGp) & ~0x00000180);
 773
 774         /* Clear ECC status. */
 775         csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) | (EccCorrStts | EccUncorrStts));
 776
 777         ctlr->eeprom.otp = 1;
 778         if(ctlr->type != Type1000)
 779                 return nil;
 780
 781         /* Switch to absolute addressing mode. */
 782         csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) & ~RelativeAccess);
 783
 784         /*
 785          * Find the block before last block (contains the EEPROM image)
 786          * for HW without OTP shadow RAM.
 787          */
 788         off = 0;
 789         for(i=0; i<3; i++){
 790                 if((err = eepromread(ctlr, buf, 2, off)) != nil)
 791                         return err;
 792                 if(get16(buf) == 0)
 793                         break;
 794                 off = get16(buf);
 795         }
 796         if(i == 0 || i >= 3)
 797                 return "rominit: missing eeprom image";
 798
 799         ctlr->eeprom.off = off+1;
 800         return nil;
 801 }
 802
 803 static int
 804 iwlinit(Ether *edev)
 805 {
 806         Ctlr *ctlr;
 807         char *err;
 808         uchar b[4];
 809         uint u, caloff, regoff;
 810
 811         ctlr = edev->ctlr;
 812         if((err = handover(ctlr)) != nil)
 813                 goto Err;
 814         if((err = poweron(ctlr)) != nil)
 815                 goto Err;
 816         if((csr32r(ctlr, EepromGp) & 0x7) == 0){
 817                 err = "bad rom signature";
 818                 goto Err;
 819         }
 820         if((err = eepromlock(ctlr)) != nil)
 821                 goto Err;
 822         if((err = rominit(ctlr)) != nil)
 823                 goto Err2;
 824         if((err = eepromread(ctlr, edev->ea, sizeof(edev->ea), 0x15)) != nil){
 825                 eepromunlock(ctlr);
 826                 goto Err;
 827         }
 828         if((err = eepromread(ctlr, b, 2, 0x048)) != nil){
 829         Err2:
 830                 eepromunlock(ctlr);
 831                 goto Err;
 832         }
 833         u = get16(b);
 834         ctlr->rfcfg.type = u & 3;       u >>= 2;
 835         ctlr->rfcfg.step = u & 3;       u >>= 2;
 836         ctlr->rfcfg.dash = u & 3;       u >>= 4;
 837         ctlr->rfcfg.txantmask = u & 15; u >>= 4;
 838         ctlr->rfcfg.rxantmask = u & 15;
 839         if((err = eepromread(ctlr, b, 2, 0x66)) != nil)
 840                 goto Err2;
 841         regoff = get16(b);
 842         if((err = eepromread(ctlr, b, 4, regoff+1)) != nil)
 843                 goto Err2;
 844         strncpy(ctlr->eeprom.regdom, (char*)b, 4);
 845         ctlr->eeprom.regdom[4] = 0;
 846         if((err = eepromread(ctlr, b, 2, 0x67)) != nil)
 847                 goto Err2;
 848         caloff = get16(b);
 849         if((err = eepromread(ctlr, b, 4, caloff)) != nil)
 850                 goto Err2;
 851         ctlr->eeprom.version = b[0];
 852         ctlr->eeprom.type = b[1];
 853         ctlr->eeprom.volt = get16(b+2);
 854         if(ctlr->type != Type4965 && ctlr->type != Type5150){
 855                 if((err = eepromread(ctlr, b, 4, caloff + 0x128)) != nil)
 856                         goto Err2;
 857                 ctlr->eeprom.crystal = get32(b);
 858         }
 859         eepromunlock(ctlr);
 860
 861         switch(ctlr->type){
 862         case Type4965:
 863                 ctlr->rfcfg.txantmask = 3;
 864                 ctlr->rfcfg.rxantmask = 7;
 865                 break;
 866         case Type5100:
 867                 ctlr->rfcfg.txantmask = 2;
 868                 ctlr->rfcfg.rxantmask = 3;
 869                 break;
 870         case Type6000:
 871                 if(ctlr->pdev->did == 0x422c || ctlr->pdev->did == 0x4230){
 872                         ctlr->rfcfg.txantmask = 6;
 873                         ctlr->rfcfg.rxantmask = 6;
 874                 }
 875                 break;
 876         }
 877         poweroff(ctlr);
 878         return 0;
 879 Err:
 880         print("iwlinit: %s\n", err);
 881         poweroff(ctlr);
 882         return -1;
 883 }
 884
 885 static char*
 886 crackfw(FWImage *i, uchar *data, uint size, int alt)
 887 {
 888         uchar *p, *e;
 889         FWSect *s;
 890
 891         memset(i, 0, sizeof(*i));
 892         if(size < 4){
 893 Tooshort:
 894                 return "firmware image too short";
 895         }
 896         p = data;
 897         e = p + size;
 898         i->rev = get32(p); p += 4;
 899         if(i->rev == 0){
 900                 uvlong altmask;
 901
 902                 if(size < (4+64+4+4+8))
 903                         goto Tooshort;
 904                 if(memcmp(p, "IWL\n", 4) != 0)
 905                         return "bad firmware signature";
 906                 p += 4;
 907                 strncpy(i->descr, (char*)p, 64);
 908                 i->descr[64] = 0;
 909                 p += 64;
 910                 i->rev = get32(p); p += 4;
 911                 i->build = get32(p); p += 4;
 912                 altmask = get32(p); p += 4;
 913                 altmask |= (uvlong)get32(p) << 32; p += 4;
 914                 while(alt > 0 && (altmask & (1ULL<<alt)) == 0)
 915                         alt--;
 916                 while(p < e){
 917                         FWSect dummy;
 918
 919                         if((p + 2+2+4) > e)
 920                                 goto Tooshort;
 921                         switch(get16(p)){
 922                         case 1: s = &i->main.text; break;
 923                         case 2: s = &i->main.data; break;
 924                         case 3: s = &i->init.text; break;
 925                         case 4: s = &i->init.data; break;
 926                         case 5: s = &i->boot.text; break;
 927                         default:s = &dummy;
 928                         }
 929                         p += 2;
 930                         if(get16(p) != 0 && get16(p) != alt)
 931                                 s = &dummy;
 932                         p += 2;
 933                         s->size = get32(p); p += 4;
 934                         s->data = p;
 935                         if((p + s->size) > e)
 936                                 goto Tooshort;
 937                         p += (s->size + 3) & ~3;
 938                 }
 939         } else {
 940                 if(((i->rev>>8) & 0xFF) < 2)
 941                         return "need firmware api >= 2";
 942                 if(((i->rev>>8) & 0xFF) >= 3){
 943                         i->build = get32(p); p += 4;
 944                 }
 945                 if((p + 5*4) > e)
 946                         goto Tooshort;
 947                 i->main.text.size = get32(p); p += 4;
 948                 i->main.data.size = get32(p); p += 4;
 949                 i->init.text.size = get32(p); p += 4;
 950                 i->init.data.size = get32(p); p += 4;
 951                 i->boot.text.size = get32(p); p += 4;
 952                 i->main.text.data = p; p += i->main.text.size;
 953                 i->main.data.data = p; p += i->main.data.size;
 954                 i->init.text.data = p; p += i->init.text.size;
 955                 i->init.data.data = p; p += i->init.data.size;
 956                 i->boot.text.data = p; p += i->boot.text.size;
 957                 if(p > e)
 958                         goto Tooshort;
 959         }
 960         return 0;
 961 }
 962
 963 static FWImage*
 964 readfirmware(char *name)
 965 {
 966         uchar dirbuf[sizeof(Dir)+100], *data;
 967         char buf[128], *err;
 968         FWImage *fw;
 969         int n, r;
 970         Chan *c;
 971         Dir d;
 972
 973         if(!iseve())
 974                 error(Eperm);
 975         if(!waserror()){
 976                 snprint(buf, sizeof buf, "/boot/%s", name);
 977                 c = namec(buf, Aopen, OREAD, 0);
 978                 poperror();
 979         } else {
 980                 snprint(buf, sizeof buf, "/lib/firmware/%s", name);
 981                 c = namec(buf, Aopen, OREAD, 0);
 982         }
 983         if(waserror()){
 984                 cclose(c);
 985                 nexterror();
 986         }
 987         n = devtab[c->type]->stat(c, dirbuf, sizeof dirbuf);
 988         if(n <= 0)
 989                 error("can't stat firmware");
 990         convM2D(dirbuf, n, &d, nil);
 991         fw = smalloc(sizeof(*fw) + 16 + d.length);
 992         data = (uchar*)(fw+1);
 993         if(waserror()){
 994                 free(fw);
 995                 nexterror();
 996         }
 997         r = 0;
 998         while(r < d.length){
 999                 n = devtab[c->type]->read(c, data+r, d.length-r, (vlong)r);
1000                 if(n <= 0)
1001                         break;
1002                 r += n;
1003         }
1004         if((err = crackfw(fw, data, r, 1)) != nil)
1005                 error(err);
1006         poperror();
1007         poperror();
1008         cclose(c);
1009         return fw;
1010 }
1011
1012 typedef struct Irqwait Irqwait;
1013 struct Irqwait {
1014         Ctlr    *ctlr;
1015         u32int  mask;
1016 };
1017
1018 static int
1019 gotirq(void *arg)
1020 {
1021         Irqwait *w;
1022         Ctlr *ctlr;
1023
1024         w = arg;
1025         ctlr = w->ctlr;
1026         ctlr->wait.r = ctlr->wait.m & w->mask;
1027         if(ctlr->wait.r){
1028                 ctlr->wait.m &= ~ctlr->wait.r;
1029                 return 1;
1030         }
1031         ctlr->wait.w = w->mask;
1032         return 0;
1033 }
1034
1035 static u32int
1036 irqwait(Ctlr *ctlr, u32int mask, int timeout)
1037 {
1038         Irqwait w;
1039
1040         w.ctlr = ctlr;
1041         w.mask = mask;
1042         tsleep(&ctlr->wait, gotirq, &w, timeout);
1043         ctlr->wait.w = 0;
1044         return ctlr->wait.r & mask;
1045 }
1046
1047 static int
1048 rbplant(Ctlr *ctlr, int i)
1049 {
1050         Block *b;
1051
1052         b = iallocb(Rbufsize + 256);
1053         if(b == nil)
1054                 return -1;
1055         b->rp = b->wp = (uchar*)ROUND((uintptr)b->base, 256);
1056         memset(b->rp, 0, Rdscsize);
1057         ctlr->rx.b[i] = b;
1058         ctlr->rx.p[i] = PCIWADDR(b->rp) >> 8;
1059         return 0;
1060 }
1061
1062 static char*
1063 initring(Ctlr *ctlr)
1064 {
1065         RXQ *rx;
1066         TXQ *tx;
1067         int i, q;
1068
1069         rx = &ctlr->rx;
1070         if(rx->b == nil)
1071                 rx->b = malloc(sizeof(Block*) * Nrx);
1072         if(rx->p == nil)
1073                 rx->p = mallocalign(sizeof(u32int) * Nrx, 256, 0, 0);
1074         if(rx->s == nil)
1075                 rx->s = mallocalign(Rstatsize, 16, 0, 0);
1076         if(rx->b == nil || rx->p == nil || rx->s == nil)
1077                 return "no memory for rx ring";
1078         memset(ctlr->rx.s, 0, Rstatsize);
1079         for(i=0; i<Nrx; i++){
1080                 rx->p[i] = 0;
1081                 if(rx->b[i] != nil){
1082                         freeb(rx->b[i]);
1083                         rx->b[i] = nil;
1084                 }
1085                 if(rbplant(ctlr, i) < 0)
1086                         return "no memory for rx descriptors";
1087         }
1088         rx->i = 0;
1089
1090         if(ctlr->sched.s == nil)
1091                 ctlr->sched.s = mallocalign(512 * nelem(ctlr->tx) * 2, 1024, 0, 0);
1092         if(ctlr->sched.s == nil)
1093                 return "no memory for sched buffer";
1094         memset(ctlr->sched.s, 0, 512 * nelem(ctlr->tx));
1095
1096         for(q=0; q<nelem(ctlr->tx); q++){
1097                 tx = &ctlr->tx[q];
1098                 if(tx->b == nil)
1099                         tx->b = malloc(sizeof(Block*) * Ntx);
1100                 if(tx->d == nil)
1101                         tx->d = mallocalign(Tdscsize * Ntx, 256, 0, 0);
1102                 if(tx->c == nil)
1103                         tx->c = mallocalign(Tcmdsize * Ntx, 4, 0, 0);
1104                 if(tx->b == nil || tx->d == nil || tx->c == nil)
1105                         return "no memory for tx ring";
1106                 memset(tx->d, 0, Tdscsize * Ntx);
1107                 memset(tx->c, 0, Tcmdsize * Ntx);
1108                 for(i=0; i<Ntx; i++){
1109                         if(tx->b[i] != nil){
1110                                 freeb(tx->b[i]);
1111                                 tx->b[i] = nil;
1112                         }
1113                 }
1114                 tx->i = 0;
1115                 tx->n = 0;
1116                 tx->lastcmd = 0;
1117         }
1118
1119         if(ctlr->kwpage == nil)
1120                 ctlr->kwpage = mallocalign(4096, 4096, 0, 0);
1121         if(ctlr->kwpage == nil)
1122                 return "no memory for kwpage";
1123         memset(ctlr->kwpage, 0, 4096);
1124
1125         return nil;
1126 }
1127
1128 static char*
1129 reset(Ctlr *ctlr)
1130 {
1131         char *err;
1132         int i, q;
1133
1134         if(ctlr->power)
1135                 poweroff(ctlr);
1136         if((err = initring(ctlr)) != nil)
1137                 return err;
1138         if((err = poweron(ctlr)) != nil)
1139                 return err;
1140
1141         if((err = niclock(ctlr)) != nil)
1142                 return err;
1143         prphwrite(ctlr, ApmgPs, (prphread(ctlr, ApmgPs) & ~PwrSrcMask) | PwrSrcVMain);
1144         nicunlock(ctlr);
1145
1146         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | RadioSi | MacSi);
1147
1148         if((err = niclock(ctlr)) != nil)
1149                 return err;
1150         if(ctlr->type != Type4965)
1151                 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | EarlyPwroffDis);
1152         if(ctlr->type == Type1000){
1153                 /*
1154                  * Select first Switching Voltage Regulator (1.32V) to
1155                  * solve a stability issue related to noisy DC2DC line
1156                  * in the silicon of 1000 Series.
1157                  */
1158                 prphwrite(ctlr, ApmgDigitalSvr,
1159                         (prphread(ctlr, ApmgDigitalSvr) & ~(0xf<<5)) | (3<<5));
1160         }
1161         nicunlock(ctlr);
1162
1163         if((err = niclock(ctlr)) != nil)
1164                 return err;
1165         csr32w(ctlr, FhRxConfig, 0);
1166         csr32w(ctlr, FhRxWptr, 0);
1167         csr32w(ctlr, FhRxBase, PCIWADDR(ctlr->rx.p) >> 8);
1168         csr32w(ctlr, FhStatusWptr, PCIWADDR(ctlr->rx.s) >> 4);
1169         csr32w(ctlr, FhRxConfig,
1170                 FhRxConfigEna |
1171                 FhRxConfigIgnRxfEmpty |
1172                 FhRxConfigIrqDstHost |
1173                 FhRxConfigSingleFrame |
1174                 (Nrxlog << FhRxConfigNrbdShift));
1175         csr32w(ctlr, FhRxWptr, (Nrx-1) & ~7);
1176         nicunlock(ctlr);
1177
1178         if((err = niclock(ctlr)) != nil)
1179                 return err;
1180         if(ctlr->type != Type4965)
1181                 prphwrite(ctlr, SchedTxFact5000, 0);
1182         else
1183                 prphwrite(ctlr, SchedTxFact4965, 0);
1184         csr32w(ctlr, FhKwAddr, PCIWADDR(ctlr->kwpage) >> 4);
1185         for(q = (ctlr->type != Type4965) ? 19 : 15; q >= 0; q--)
1186                 csr32w(ctlr, FhCbbcQueue + q*4, PCIWADDR(ctlr->tx[q].d) >> 8);
1187         nicunlock(ctlr);
1188
1189         for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--)
1190                 csr32w(ctlr, FhTxConfig + i*32, FhTxConfigDmaEna | FhTxConfigDmaCreditEna);
1191
1192         csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
1193         csr32w(ctlr, UcodeGp1Clr, UcodeGp1CmdBlocked);
1194
1195         ctlr->broken = 0;
1196         ctlr->wait.r = 0;
1197         ctlr->wait.w = 0;
1198
1199         ctlr->ie = Idefmask;
1200         csr32w(ctlr, Imr, ctlr->ie);
1201         csr32w(ctlr, Isr, ~0);
1202
1203         if(ctlr->type >= Type6000)
1204                 csr32w(ctlr, ShadowRegCtrl, csr32r(ctlr, ShadowRegCtrl) | 0x800fffff);
1205
1206         return nil;
1207 }
1208
1209 static char*
1210 postboot(Ctlr *ctlr)
1211 {
1212         uint ctxoff, ctxlen, dramaddr, txfact;
1213         char *err;
1214         int i, q;
1215
1216         if((err = niclock(ctlr)) != nil)
1217                 return err;
1218
1219         if(ctlr->type != Type4965){
1220                 dramaddr = SchedDramAddr5000;
1221                 ctxoff = SchedCtxOff5000;
1222                 ctxlen = SchedCtxLen5000;
1223                 txfact = SchedTxFact5000;
1224         } else {
1225                 dramaddr = SchedDramAddr4965;
1226                 ctxoff = SchedCtxOff4965;
1227                 ctxlen = SchedCtxLen4965;
1228                 txfact = SchedTxFact4965;
1229         }
1230
1231         ctlr->sched.base = prphread(ctlr, SchedSramAddr);
1232         for(i=0; i < ctxlen; i += 4)
1233                 memwrite(ctlr, ctlr->sched.base + ctxoff + i, 0);
1234
1235         prphwrite(ctlr, dramaddr, PCIWADDR(ctlr->sched.s)>>10);
1236
1237         csr32w(ctlr, FhTxChicken, csr32r(ctlr, FhTxChicken) | 2);
1238
1239         if(ctlr->type != Type4965){
1240                 /* Enable chain mode for all queues, except command queue 4. */
1241                 prphwrite(ctlr, SchedQChainSel5000, 0xfffef);
1242                 prphwrite(ctlr, SchedAggrSel5000, 0);
1243
1244                 for(q=0; q<20; q++){
1245                         prphwrite(ctlr, SchedQueueRdptr5000 + q*4, 0);
1246                         csr32w(ctlr, HbusTargWptr, q << 8);
1247
1248                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 0);
1249                         /* Set scheduler window size and frame limit. */
1250                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16 | 64);
1251                 }
1252                 /* Enable interrupts for all our 20 queues. */
1253                 prphwrite(ctlr, SchedIntrMask5000, 0xfffff);
1254         } else {
1255                 /* Disable chain mode for all our 16 queues. */
1256                 prphwrite(ctlr, SchedQChainSel4965, 0);
1257
1258                 for(q=0; q<16; q++) {
1259                         prphwrite(ctlr, SchedQueueRdptr4965 + q*4, 0);
1260                         csr32w(ctlr, HbusTargWptr, q << 8);
1261
1262                         /* Set scheduler window size. */
1263                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 64);
1264                         /* Set scheduler window size and frame limit. */
1265                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16);
1266                 }
1267                 /* Enable interrupts for all our 16 queues. */
1268                 prphwrite(ctlr, SchedIntrMask4965, 0xffff);
1269         }
1270
1271         /* Identify TX FIFO rings (0-7). */
1272         prphwrite(ctlr, txfact, 0xff);
1273
1274         /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
1275         for(q=0; q<7; q++){
1276                 if(ctlr->type != Type4965){
1277                         static uchar qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
1278                         prphwrite(ctlr, SchedQueueStatus5000 + q*4, 0x00ff0018 | qid2fifo[q]);
1279                 } else {
1280                         static uchar qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
1281                         prphwrite(ctlr, SchedQueueStatus4965 + q*4, 0x0007fc01 | qid2fifo[q]<<1);
1282                 }
1283         }
1284         nicunlock(ctlr);
1285
1286         if(ctlr->type != Type4965){
1287                 uchar c[Tcmdsize];
1288
1289                 /* disable wimax coexistance */
1290                 memset(c, 0, sizeof(c));
1291                 if((err = cmd(ctlr, 90, c, 4+4*16)) != nil)
1292                         return err;
1293
1294                 if(ctlr->type != Type5150){
1295                         /* calibrate crystal */
1296                         memset(c, 0, sizeof(c));
1297                         c[0] = 15;      /* code */
1298                         c[1] = 0;       /* group */
1299                         c[2] = 1;       /* ngroup */
1300                         c[3] = 1;       /* isvalid */
1301                         c[4] = ctlr->eeprom.crystal;
1302                         c[5] = ctlr->eeprom.crystal>>16;
1303                         if((err = cmd(ctlr, 176, c, 8)) != nil)
1304                                 return err;
1305                 }
1306
1307                 if(ctlr->calib.done == 0){
1308                         /* query calibration (init firmware) */
1309                         memset(c, 0, sizeof(c));
1310                         put32(c + 0*(5*4) + 0, 0xffffffff);
1311                         put32(c + 0*(5*4) + 4, 0xffffffff);
1312                         put32(c + 0*(5*4) + 8, 0xffffffff);
1313                         put32(c + 2*(5*4) + 0, 0xffffffff);
1314                         if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1315                                 return err;
1316
1317                         /* wait to collect calibration records */
1318                         if(irqwait(ctlr, Ierr, 2000))
1319                                 return "calibration failed";
1320
1321                         if(ctlr->calib.done == 0){
1322                                 print("iwl: no calibration results\n");
1323                                 ctlr->calib.done = 1;
1324                         }
1325                 } else {
1326                         static uchar cmds[] = {8, 9, 11, 17, 16};
1327
1328                         /* send calibration records (runtime firmware) */
1329                         for(q=0; q<nelem(cmds); q++){
1330                                 Block *b;
1331
1332                                 i = cmds[q];
1333                                 if(i == 8 && ctlr->type != Type5150)
1334                                         continue;
1335                                 if(i == 17 && (ctlr->type >= Type6000 || ctlr->type == Type5150))
1336                                         continue;
1337                                 if((b = ctlr->calib.cmd[i]) == nil)
1338                                         continue;
1339                                 b->ref++;       /* dont free on command completion */
1340                                 if((err = qcmd(ctlr, 4, 176, nil, 0, b)) != nil){
1341                                         freeb(b);
1342                                         return err;
1343                                 }
1344                                 if((err = flushq(ctlr, 4)) != nil)
1345                                         return err;
1346                         }
1347
1348                         if(ctlr->type == Type6005 || ctlr->type == Type6050){
1349                                 /* runtime DC calibration */
1350                                 memset(c, 0, sizeof(c));
1351                                 put32(c + 0*(5*4) + 0, 0xffffffff);
1352                                 put32(c + 0*(5*4) + 4, 1<<1);
1353                                 if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1354                                         return err;
1355                         }
1356
1357                         /* set tx antenna config */
1358                         put32(c, ctlr->rfcfg.txantmask & 7);
1359                         if((err = cmd(ctlr, 152, c, 4)) != nil)
1360                                 return err;
1361                 }
1362         }
1363
1364         return nil;
1365 }
1366
1367 static char*
1368 loadfirmware1(Ctlr *ctlr, u32int dst, uchar *data, int size)
1369 {
1370         uchar *dma;
1371         char *err;
1372
1373         dma = mallocalign(size, 16, 0, 0);
1374         if(dma == nil)
1375                 return "no memory for dma";
1376         memmove(dma, data, size);
1377         coherence();
1378         if((err = niclock(ctlr)) != 0){
1379                 free(dma);
1380                 return err;
1381         }
1382         csr32w(ctlr, FhTxConfig + 9*32, 0);
1383         csr32w(ctlr, FhSramAddr + 9*4, dst);
1384         csr32w(ctlr, FhTfbdCtrl0 + 9*8, PCIWADDR(dma));
1385         csr32w(ctlr, FhTfbdCtrl1 + 9*8, size);
1386         csr32w(ctlr, FhTxBufStatus + 9*32,
1387                 (1<<FhTxBufStatusTbNumShift) |
1388                 (1<<FhTxBufStatusTbIdxShift) |
1389                 FhTxBufStatusTfbdValid);
1390         csr32w(ctlr, FhTxConfig + 9*32, FhTxConfigDmaEna | FhTxConfigCirqHostEndTfd);
1391         nicunlock(ctlr);
1392         if(irqwait(ctlr, Ifhtx|Ierr, 5000) != Ifhtx){
1393                 free(dma);
1394                 return "dma error / timeout";
1395         }
1396         free(dma);
1397         return 0;
1398 }
1399
1400 static char*
1401 boot(Ctlr *ctlr)
1402 {
1403         int i, n, size;
1404         uchar *p, *dma;
1405         FWImage *fw;
1406         char *err;
1407
1408         fw = ctlr->fw;
1409
1410         if(fw->boot.text.size == 0){
1411                 if(ctlr->calib.done == 0){
1412                         if((err = loadfirmware1(ctlr, 0x00000000, fw->init.text.data, fw->init.text.size)) != nil)
1413                                 return err;
1414                         if((err = loadfirmware1(ctlr, 0x00800000, fw->init.data.data, fw->init.data.size)) != nil)
1415                                 return err;
1416                         csr32w(ctlr, Reset, 0);
1417                         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1418                                 return "init firmware boot failed";
1419                         if((err = postboot(ctlr)) != nil)
1420                                 return err;
1421                         if((err = reset(ctlr)) != nil)
1422                                 return err;
1423                 }
1424                 if((err = loadfirmware1(ctlr, 0x00000000, fw->main.text.data, fw->main.text.size)) != nil)
1425                         return err;
1426                 if((err = loadfirmware1(ctlr, 0x00800000, fw->main.data.data, fw->main.data.size)) != nil)
1427                         return err;
1428                 csr32w(ctlr, Reset, 0);
1429                 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1430                         return "main firmware boot failed";
1431                 return postboot(ctlr);
1432         }
1433
1434         size = ROUND(fw->init.data.size, 16) + ROUND(fw->init.text.size, 16);
1435         dma = mallocalign(size, 16, 0, 0);
1436         if(dma == nil)
1437                 return "no memory for dma";
1438
1439         if((err = niclock(ctlr)) != nil){
1440                 free(dma);
1441                 return err;
1442         }
1443
1444         p = dma;
1445         memmove(p, fw->init.data.data, fw->init.data.size);
1446         coherence();
1447         prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1448         prphwrite(ctlr, BsmDramDataSize, fw->init.data.size);
1449         p += ROUND(fw->init.data.size, 16);
1450         memmove(p, fw->init.text.data, fw->init.text.size);
1451         coherence();
1452         prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1453         prphwrite(ctlr, BsmDramTextSize, fw->init.text.size);
1454
1455         nicunlock(ctlr);
1456         if((err = niclock(ctlr)) != nil){
1457                 free(dma);
1458                 return err;
1459         }
1460
1461         p = fw->boot.text.data;
1462         n = fw->boot.text.size/4;
1463         for(i=0; i<n; i++, p += 4)
1464                 prphwrite(ctlr, BsmSramBase+i*4, get32(p));
1465
1466         prphwrite(ctlr, BsmWrMemSrc, 0);
1467         prphwrite(ctlr, BsmWrMemDst, 0);
1468         prphwrite(ctlr, BsmWrDwCount, n);
1469
1470         prphwrite(ctlr, BsmWrCtrl, 1<<31);
1471
1472         for(i=0; i<1000; i++){
1473                 if((prphread(ctlr, BsmWrCtrl) & (1<<31)) == 0)
1474                         break;
1475                 delay(10);
1476         }
1477         if(i == 1000){
1478                 nicunlock(ctlr);
1479                 free(dma);
1480                 return "bootcode timeout";
1481         }
1482
1483         prphwrite(ctlr, BsmWrCtrl, 1<<30);
1484         nicunlock(ctlr);
1485
1486         csr32w(ctlr, Reset, 0);
1487         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1488                 free(dma);
1489                 return "init firmware boot failed";
1490         }
1491         free(dma);
1492
1493         size = ROUND(fw->main.data.size, 16) + ROUND(fw->main.text.size, 16);
1494         dma = mallocalign(size, 16, 0, 0);
1495         if(dma == nil)
1496                 return "no memory for dma";
1497         if((err = niclock(ctlr)) != nil){
1498                 free(dma);
1499                 return err;
1500         }
1501         p = dma;
1502         memmove(p, fw->main.data.data, fw->main.data.size);
1503         coherence();
1504         prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1505         prphwrite(ctlr, BsmDramDataSize, fw->main.data.size);
1506         p += ROUND(fw->main.data.size, 16);
1507         memmove(p, fw->main.text.data, fw->main.text.size);
1508         coherence();
1509         prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1510         prphwrite(ctlr, BsmDramTextSize, fw->main.text.size | (1<<31));
1511         nicunlock(ctlr);
1512
1513         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1514                 free(dma);
1515                 return "main firmware boot failed";
1516         }
1517         free(dma);
1518         return postboot(ctlr);
1519 }
1520
1521 static int
1522 txqready(void *arg)
1523 {
1524         TXQ *q = arg;
1525         return q->n < Ntx;
1526 }
1527
1528 static char*
1529 qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block)
1530 {
1531         uchar *d, *c;
1532         TXQ *q;
1533
1534         assert(qid < nelem(ctlr->tx));
1535         assert(size <= Tcmdsize-4);
1536
1537         ilock(ctlr);
1538         q = &ctlr->tx[qid];
1539         while(q->n >= Ntx && !ctlr->broken){
1540                 iunlock(ctlr);
1541                 qlock(q);
1542                 if(!waserror()){
1543                         tsleep(q, txqready, q, 10);
1544                         poperror();
1545                 }
1546                 qunlock(q);
1547                 ilock(ctlr);
1548         }
1549         if(ctlr->broken){
1550                 iunlock(ctlr);
1551                 return "qcmd: broken";
1552         }
1553         q->n++;
1554
1555         q->lastcmd = code;
1556         q->b[q->i] = block;
1557         c = q->c + q->i * Tcmdsize;
1558         d = q->d + q->i * Tdscsize;
1559
1560         /* build command */
1561         c[0] = code;
1562         c[1] = 0;       /* flags */
1563         c[2] = q->i;
1564         c[3] = qid;
1565
1566         if(size > 0)
1567                 memmove(c+4, data, size);
1568
1569         size += 4;
1570
1571         /* build descriptor */
1572         *d++ = 0;
1573         *d++ = 0;
1574         *d++ = 0;
1575         *d++ = 1 + (block != nil); /* nsegs */
1576         put32(d, PCIWADDR(c));  d += 4;
1577         put16(d, size << 4); d += 2;
1578         if(block != nil){
1579                 put32(d, PCIWADDR(block->rp)); d += 4;
1580                 put16(d, BLEN(block) << 4);
1581         }
1582
1583         coherence();
1584
1585         q->i = (q->i+1) % Ntx;
1586         csr32w(ctlr, HbusTargWptr, (qid<<8) | q->i);
1587
1588         iunlock(ctlr);
1589
1590         return nil;
1591 }
1592
1593 static int
1594 txqempty(void *arg)
1595 {
1596         TXQ *q = arg;
1597         return q->n == 0;
1598 }
1599
1600 static char*
1601 flushq(Ctlr *ctlr, uint qid)
1602 {
1603         TXQ *q;
1604         int i;
1605
1606         q = &ctlr->tx[qid];
1607         qlock(q);
1608         for(i = 0; i < 200 && !ctlr->broken; i++){
1609                 if(txqempty(q)){
1610                         qunlock(q);
1611                         return nil;
1612                 }
1613                 if(!waserror()){
1614                         tsleep(q, txqempty, q, 10);
1615                         poperror();
1616                 }
1617         }
1618         qunlock(q);
1619         if(ctlr->broken)
1620                 return "flushq: broken";
1621         return "flushq: timeout";
1622 }
1623
1624 static char*
1625 cmd(Ctlr *ctlr, uint code, uchar *data, int size)
1626 {
1627         char *err;
1628
1629         if(0) print("cmd %ud\n", code);
1630         if((err = qcmd(ctlr, 4, code, data, size, nil)) != nil)
1631                 return err;
1632         return flushq(ctlr, 4);
1633 }
1634
1635 static void
1636 setled(Ctlr *ctlr, int which, int on, int off)
1637 {
1638         uchar c[8];
1639
1640         csr32w(ctlr, Led, csr32r(ctlr, Led) & ~LedBsmCtrl);
1641
1642         memset(c, 0, sizeof(c));
1643         put32(c, 10000);
1644         c[4] = which;
1645         c[5] = on;
1646         c[6] = off;
1647         cmd(ctlr, 72, c, sizeof(c));
1648 }
1649
1650 static void
1651 addnode(Ctlr *ctlr, uchar id, uchar *addr)
1652 {
1653         uchar c[Tcmdsize], *p;
1654
1655         memset(p = c, 0, sizeof(c));
1656         *p++ = 0;       /* control (1 = update) */
1657         p += 3;         /* reserved */
1658         memmove(p, addr, 6);
1659         p += 6;
1660         p += 2;         /* reserved */
1661         *p++ = id;      /* node id */
1662         p++;            /* flags */
1663         p += 2;         /* reserved */
1664         p += 2;         /* kflags */
1665         p++;            /* tcs2 */
1666         p++;            /* reserved */
1667         p += 5*2;       /* ttak */
1668         p++;            /* kid */
1669         p++;            /* reserved */
1670         p += 16;        /* key */
1671         if(ctlr->type != Type4965){
1672                 p += 8;         /* tcs */
1673                 p += 8;         /* rxmic */
1674                 p += 8;         /* txmic */
1675         }
1676         p += 4;         /* htflags */
1677         p += 4;         /* mask */
1678         p += 2;         /* disable tid */
1679         p += 2;         /* reserved */
1680         p++;            /* add ba tid */
1681         p++;            /* del ba tid */
1682         p += 2;         /* add ba ssn */
1683         p += 4;         /* reserved */
1684         cmd(ctlr, 24, c, p - c);
1685 }
1686
1687 void
1688 rxon(Ether *edev, Wnode *bss)
1689 {
1690         uchar c[Tcmdsize], *p;
1691         int filter, flags;
1692         Ctlr *ctlr;
1693         char *err;
1694
1695         ctlr = edev->ctlr;
1696         filter = FilterMulticast | FilterBeacon;
1697         if(ctlr->prom){
1698                 filter |= FilterPromisc;
1699                 bss = nil;
1700         }
1701         if(bss != nil){
1702                 ctlr->channel = bss->channel;
1703                 memmove(ctlr->bssid, bss->bssid, Eaddrlen);
1704                 ctlr->aid = bss->aid;
1705                 if(ctlr->aid != 0){
1706                         filter |= FilterBSS;
1707                         filter &= ~FilterBeacon;
1708                         ctlr->bssnodeid = -1;
1709                 } else
1710                         ctlr->bcastnodeid = -1;
1711         } else {
1712                 memmove(ctlr->bssid, edev->bcast, Eaddrlen);
1713                 ctlr->aid = 0;
1714                 ctlr->bcastnodeid = -1;
1715                 ctlr->bssnodeid = -1;
1716         }
1717         flags = RFlagTSF | RFlagCTSToSelf | RFlag24Ghz | RFlagAuto;
1718
1719         if(0) print("rxon: bssid %E, aid %x, channel %d, filter %x, flags %x\n",
1720                 ctlr->bssid, ctlr->aid, ctlr->channel, filter, flags);
1721
1722         memset(p = c, 0, sizeof(c));
1723         memmove(p, edev->ea, 6); p += 8;        /* myaddr */
1724         memmove(p, ctlr->bssid, 6); p += 8;     /* bssid */
1725         memmove(p, edev->ea, 6); p += 8;        /* wlap */
1726         *p++ = 3;                               /* mode (STA) */
1727         *p++ = 0;                               /* air (?) */
1728         /* rxchain */
1729         put16(p, ((ctlr->rfcfg.rxantmask & 7)<<1) | (2<<10) | (2<<12));
1730         p += 2;
1731         *p++ = 0xff;                            /* ofdm mask (not yet negotiated) */
1732         *p++ = 0x0f;                            /* cck mask (not yet negotiated) */
1733         put16(p, ctlr->aid & 0x3fff);
1734         p += 2;                                 /* aid */
1735         put32(p, flags);
1736         p += 4;
1737         put32(p, filter);
1738         p += 4;
1739         *p++ = ctlr->channel;
1740         p++;                                    /* reserved */
1741         *p++ = 0xff;                            /* ht single mask */
1742         *p++ = 0xff;                            /* ht dual mask */
1743         if(ctlr->type != Type4965){
1744                 *p++ = 0xff;                    /* ht triple mask */
1745                 p++;                            /* reserved */
1746                 put16(p, 0); p += 2;            /* acquisition */
1747                 p += 2;                         /* reserved */
1748         }
1749         if((err = cmd(ctlr, 16, c, p - c)) != nil){
1750                 print("rxon: %s\n", err);
1751                 return;
1752         }
1753
1754         if(ctlr->bcastnodeid == -1){
1755                 ctlr->bcastnodeid = (ctlr->type != Type4965) ? 15 : 31;
1756                 addnode(ctlr, ctlr->bcastnodeid, edev->bcast);
1757         }
1758         if(ctlr->bssnodeid == -1 && bss != nil && ctlr->aid != 0){
1759                 ctlr->bssnodeid = 0;
1760                 addnode(ctlr, ctlr->bssnodeid, bss->bssid);
1761         }
1762 }
1763
1764 static struct ratetab {
1765         uchar   rate;
1766         uchar   plcp;
1767         uchar   flags;
1768 } ratetab[] = {
1769         {   2,  10, RFlagCCK },
1770         {   4,  20, RFlagCCK },
1771         {  11,  55, RFlagCCK },
1772         {  22, 110, RFlagCCK },
1773         {  12, 0xd, 0 },
1774         {  18, 0xf, 0 },
1775         {  24, 0x5, 0 },
1776         {  36, 0x7, 0 },
1777         {  48, 0x9, 0 },
1778         {  72, 0xb, 0 },
1779         {  96, 0x1, 0 },
1780         { 108, 0x3, 0 },
1781         { 120, 0x3, 0 }
1782 };
1783
1784 enum {
1785         TFlagNeedProtection     = 1<<0,
1786         TFlagNeedRTS            = 1<<1,
1787         TFlagNeedCTS            = 1<<2,
1788         TFlagNeedACK            = 1<<3,
1789         TFlagLinkq              = 1<<4,
1790         TFlagImmBa              = 1<<6,
1791         TFlagFullTxOp           = 1<<7,
1792         TFlagBtDis              = 1<<12,
1793         TFlagAutoSeq            = 1<<13,
1794         TFlagMoreFrag           = 1<<14,
1795         TFlagInsertTs           = 1<<16,
1796         TFlagNeedPadding        = 1<<20,
1797 };
1798
1799 static void
1800 transmit(Wifi *wifi, Wnode *wn, Block *b)
1801 {
1802         int flags, nodeid, rate, ant;
1803         uchar c[Tcmdsize], *p;
1804         Ether *edev;
1805         Ctlr *ctlr;
1806         Wifipkt *w;
1807         char *err;
1808
1809         w = (Wifipkt*)b->rp;
1810         edev = wifi->ether;
1811         ctlr = edev->ctlr;
1812
1813         qlock(ctlr);
1814         if(ctlr->attached == 0 || ctlr->broken){
1815                 qunlock(ctlr);
1816                 freeb(b);
1817                 return;
1818         }
1819
1820         if(ctlr->prom == 0)
1821         if(wn->aid != ctlr->aid
1822         || wn->channel != ctlr->channel
1823         || memcmp(wn->bssid, ctlr->bssid, Eaddrlen) != 0)
1824                 rxon(edev, wn);
1825
1826         rate = 0;
1827         flags = 0;
1828         nodeid = ctlr->bcastnodeid;
1829         if((w->a1[0] & 1) == 0){
1830                 flags |= TFlagNeedACK;
1831
1832                 if(BLEN(b) > 512-4)
1833                         flags |= TFlagNeedRTS;
1834
1835                 if((w->fc[0] & 0x0c) == 0x08 && ctlr->bssnodeid != -1){
1836                         nodeid = ctlr->bssnodeid;
1837                         rate = 2; /* BUG: hardcode 11Mbit */
1838                 }
1839
1840                 if(flags & (TFlagNeedRTS|TFlagNeedCTS)){
1841                         if(ctlr->type != Type4965){
1842                                 flags &= ~(TFlagNeedRTS|TFlagNeedCTS);
1843                                 flags |= TFlagNeedProtection;
1844                         } else
1845                                 flags |= TFlagFullTxOp;
1846                 }
1847         }
1848         qunlock(ctlr);
1849
1850         /* select first available antenna */
1851         ant = ctlr->rfcfg.txantmask & 7;
1852         ant |= (ant == 0);
1853         ant = ((ant - 1) & ant) ^ ant;
1854
1855         memset(p = c, 0, sizeof(c));
1856         put16(p, BLEN(b));
1857         p += 2;
1858         p += 2;         /* lnext */
1859         put32(p, flags);
1860         p += 4;
1861         put32(p, 0);
1862         p += 4;         /* scratch */
1863
1864         *p++ = ratetab[rate].plcp;
1865         *p++ = ratetab[rate].flags | (ant<<6);
1866
1867         p += 2;         /* xflags */
1868         *p++ = nodeid;
1869         *p++ = 0;       /* security */
1870         *p++ = 0;       /* linkq */
1871         p++;            /* reserved */
1872         p += 16;        /* key */
1873         p += 2;         /* fnext */
1874         p += 2;         /* reserved */
1875         put32(p, ~0);   /* lifetime */
1876         p += 4;
1877
1878         /* BUG: scratch ptr? not clear what this is for */
1879         put32(p, PCIWADDR(ctlr->kwpage));
1880         p += 5;
1881
1882         *p++ = 60;      /* rts ntries */
1883         *p++ = 15;      /* data ntries */
1884         *p++ = 0;       /* tid */
1885         put16(p, 0);    /* timeout */
1886         p += 2;
1887         p += 2;         /* txop */
1888         if((err = qcmd(ctlr, 0, 28, c, p - c, b)) != nil){
1889                 print("transmit: %s\n", err);
1890                 freeb(b);
1891         }
1892 }
1893
1894 static long
1895 iwlctl(Ether *edev, void *buf, long n)
1896 {
1897         Ctlr *ctlr;
1898
1899         ctlr = edev->ctlr;
1900         if(ctlr->wifi)
1901                 return wifictl(ctlr->wifi, buf, n);
1902         return 0;
1903 }
1904
1905 static long
1906 iwlifstat(Ether *edev, void *buf, long n, ulong off)
1907 {
1908         Ctlr *ctlr;
1909
1910         ctlr = edev->ctlr;
1911         if(ctlr->wifi)
1912                 return wifistat(ctlr->wifi, buf, n, off);
1913         return 0;
1914 }
1915
1916 static void
1917 setoptions(Ether *edev)
1918 {
1919         Ctlr *ctlr;
1920         char buf[64];
1921         int i;
1922
1923         ctlr = edev->ctlr;
1924         for(i = 0; i < edev->nopt; i++){
1925                 if(strncmp(edev->opt[i], "essid=", 6) == 0){
1926                         snprint(buf, sizeof(buf), "essid %s", edev->opt[i]+6);
1927                         if(!waserror()){
1928                                 wifictl(ctlr->wifi, buf, strlen(buf));
1929                                 poperror();
1930                         }
1931                 }
1932         }
1933 }
1934
1935 static void
1936 iwlpromiscuous(void *arg, int on)
1937 {
1938         Ether *edev;
1939         Ctlr *ctlr;
1940
1941         edev = arg;
1942         ctlr = edev->ctlr;
1943         qlock(ctlr);
1944         ctlr->prom = on;
1945         rxon(edev, ctlr->wifi->bss);
1946         qunlock(ctlr);
1947 }
1948
1949 static void
1950 iwlproc(void *arg)
1951 {
1952         Ether *edev;
1953         Ctlr *ctlr;
1954         Wifi *wifi;
1955         Wnode *bss;
1956
1957         edev = arg;
1958         ctlr = edev->ctlr;
1959         wifi = ctlr->wifi;
1960
1961         for(;;){
1962                 /* hop channels for catching beacons */
1963                 setled(ctlr, 2, 5, 5);
1964                 while(wifi->bss == nil){
1965                         qlock(ctlr);
1966                         if(wifi->bss != nil){
1967                                 qunlock(ctlr);
1968                                 break;
1969                         }
1970                         ctlr->channel = 1 + ctlr->channel % 11;
1971                         ctlr->aid = 0;
1972                         rxon(edev, nil);
1973                         qunlock(ctlr);
1974                         tsleep(&up->sleep, return0, 0, 1000);
1975                 }
1976
1977                 /* wait for association */
1978                 setled(ctlr, 2, 10, 10);
1979                 while((bss = wifi->bss) != nil){
1980                         if(bss->aid != 0)
1981                                 break;
1982                         tsleep(&up->sleep, return0, 0, 1000);
1983                 }
1984
1985                 if(bss == nil)
1986                         continue;
1987
1988                 /* wait for disassociation */
1989                 edev->link = 1;
1990                 setled(ctlr, 2, 0, 1);
1991                 while((bss = wifi->bss) != nil){
1992                         if(bss->aid == 0)
1993                                 break;
1994                         tsleep(&up->sleep, return0, 0, 1000);
1995                 }
1996                 edev->link = 0;
1997         }
1998 }
1999
2000 static void
2001 iwlattach(Ether *edev)
2002 {
2003         char name[32];
2004         FWImage *fw;
2005         Ctlr *ctlr;
2006         char *err;
2007
2008         ctlr = edev->ctlr;
2009         eqlock(ctlr);
2010         if(waserror()){
2011                 print("#l%d: %s\n", edev->ctlrno, up->errstr);
2012                 if(ctlr->power)
2013                         poweroff(ctlr);
2014                 qunlock(ctlr);
2015                 nexterror();
2016         }
2017         if(ctlr->attached == 0){
2018                 if((csr32r(ctlr, Gpc) & RfKill) == 0)
2019                         error("wifi disabled by switch");
2020
2021                 if(ctlr->wifi == nil)
2022                         ctlr->wifi = wifiattach(edev, transmit);
2023
2024                 if(ctlr->fw == nil){
2025                         fw = readfirmware(fwname[ctlr->type]);
2026                         print("#l%d: firmware: %s, rev %ux, build %ud, size %ux+%ux+%ux+%ux+%ux\n",
2027                                 edev->ctlrno,
2028                                 fwname[ctlr->type],
2029                                 fw->rev, fw->build,
2030                                 fw->main.text.size, fw->main.data.size,
2031                                 fw->init.text.size, fw->init.data.size,
2032                                 fw->boot.text.size);
2033                         ctlr->fw = fw;
2034                 }
2035
2036                 if((err = reset(ctlr)) != nil)
2037                         error(err);
2038                 if((err = boot(ctlr)) != nil)
2039                         error(err);
2040
2041                 ctlr->bcastnodeid = -1;
2042                 ctlr->bssnodeid = -1;
2043                 ctlr->channel = 1;
2044                 ctlr->aid = 0;
2045
2046                 setoptions(edev);
2047
2048                 snprint(name, sizeof(name), "#l%diwl", edev->ctlrno);
2049                 kproc(name, iwlproc, edev);
2050
2051                 ctlr->attached = 1;
2052         }
2053         qunlock(ctlr);
2054         poperror();
2055 }
2056
2057 static void
2058 receive(Ctlr *ctlr)
2059 {
2060         Block *b, *bb;
2061         uchar *d, *dd, *cc;
2062         RXQ *rx;
2063         TXQ *tx;
2064         uint hw;
2065
2066         rx = &ctlr->rx;
2067         if(ctlr->broken || rx->s == nil || rx->b == nil)
2068                 return;
2069         for(hw = get16(rx->s) % Nrx; rx->i != hw; rx->i = (rx->i + 1) % Nrx){
2070                 uchar type, flags, idx, qid;
2071                 u32int len;
2072
2073                 b = rx->b[rx->i];
2074                 if(b == nil)
2075                         continue;
2076
2077                 d = b->rp;
2078                 len = get32(d); d += 4;
2079                 type = *d++;
2080                 flags = *d++;
2081                 USED(flags);
2082                 idx = *d++;
2083                 qid = *d++;
2084
2085                 if((qid & 0x80) == 0 && qid < nelem(ctlr->tx)){
2086                         tx = &ctlr->tx[qid];
2087                         if(tx->n > 0){
2088                                 bb = tx->b[idx];
2089                                 if(bb != nil){
2090                                         tx->b[idx] = nil;
2091                                         freeb(bb);
2092                                 }
2093                                 /* paranoia: clear tx descriptors */
2094                                 dd = tx->d + idx*Tdscsize;
2095                                 cc = tx->c + idx*Tcmdsize;
2096                                 memset(dd, 0, Tdscsize);
2097                                 memset(cc, 0, Tcmdsize);
2098                                 tx->n--;
2099
2100                                 wakeup(tx);
2101                         }
2102                 }
2103
2104                 len &= 0x3fff;
2105                 if(len < 4 || type == 0)
2106                         continue;
2107
2108                 len -= 4;
2109                 switch(type){
2110                 case 1:         /* microcontroller ready */
2111                         setfwinfo(ctlr, d, len);
2112                         break;
2113                 case 24:        /* add node done */
2114                         break;
2115                 case 28:        /* tx done */
2116                         break;
2117                 case 102:       /* calibration result (Type5000 only) */
2118                         if(len < 4)
2119                                 break;
2120                         idx = d[0];
2121                         if(idx >= nelem(ctlr->calib.cmd))
2122                                 break;
2123                         if(rbplant(ctlr, rx->i) < 0)
2124                                 break;
2125                         if(ctlr->calib.cmd[idx] != nil)
2126                                 freeb(ctlr->calib.cmd[idx]);
2127                         b->rp = d;
2128                         b->wp = d + len;
2129                         ctlr->calib.cmd[idx] = b;
2130                         continue;
2131                 case 103:       /* calibration done (Type5000 only) */
2132                         ctlr->calib.done = 1;
2133                         break;
2134                 case 130:       /* start scan */
2135                         break;
2136                 case 132:       /* stop scan */
2137                         break;
2138                 case 156:       /* rx statistics */
2139                         break;
2140                 case 157:       /* beacon statistics */
2141                         break;
2142                 case 161:       /* state changed */
2143                         break;
2144                 case 162:       /* beacon missed */
2145                         break;
2146                 case 192:       /* rx phy */
2147                         break;
2148                 case 195:       /* rx done */
2149                         if(d + 2 > b->lim)
2150                                 break;
2151                         d += d[1];
2152                         d += 56;
2153                 case 193:       /* mpdu rx done */
2154                         if(d + 4 > b->lim)
2155                                 break;
2156                         len = get16(d); d += 4;
2157                         if(d + len + 4 > b->lim)
2158                                 break;
2159                         if((get32(d + len) & 3) != 3)
2160                                 break;
2161                         if(ctlr->wifi == nil)
2162                                 break;
2163                         if(rbplant(ctlr, rx->i) < 0)
2164                                 break;
2165                         b->rp = d;
2166                         b->wp = d + len;
2167                         wifiiq(ctlr->wifi, b);
2168                         continue;
2169                 case 197:       /* rx compressed ba */
2170                         break;
2171                 }
2172                 /* paranoia: clear the descriptor */
2173                 memset(b->rp, 0, Rdscsize);
2174         }
2175         csr32w(ctlr, FhRxWptr, ((hw+Nrx-1) % Nrx) & ~7);
2176 }
2177
2178 static void
2179 iwlinterrupt(Ureg*, void *arg)
2180 {
2181         u32int isr, fhisr;
2182         Ether *edev;
2183         Ctlr *ctlr;
2184
2185         edev = arg;
2186         ctlr = edev->ctlr;
2187         ilock(ctlr);
2188         csr32w(ctlr, Imr, 0);
2189         isr = csr32r(ctlr, Isr);
2190         fhisr = csr32r(ctlr, FhIsr);
2191         if(isr == 0xffffffff || (isr & 0xfffffff0) == 0xa5a5a5a0){
2192                 iunlock(ctlr);
2193                 return;
2194         }
2195         if(isr == 0 && fhisr == 0)
2196                 goto done;
2197         csr32w(ctlr, Isr, isr);
2198         csr32w(ctlr, FhIsr, fhisr);
2199         if((isr & (Iswrx | Ifhrx | Irxperiodic)) || (fhisr & Ifhrx))
2200                 receive(ctlr);
2201         if(isr & Ierr){
2202                 ctlr->broken = 1;
2203                 iprint("#l%d: fatal firmware error\n", edev->ctlrno);
2204                 dumpctlr(ctlr);
2205         }
2206         ctlr->wait.m |= isr;
2207         if(ctlr->wait.m & ctlr->wait.w){
2208                 ctlr->wait.r = ctlr->wait.m & ctlr->wait.w;
2209                 ctlr->wait.m &= ~ctlr->wait.r;
2210                 wakeup(&ctlr->wait);
2211         }
2212 done:
2213         csr32w(ctlr, Imr, ctlr->ie);
2214         iunlock(ctlr);
2215 }
2216
2217 static Ctlr *iwlhead, *iwltail;
2218
2219 static void
2220 iwlpci(void)
2221 {
2222         Pcidev *pdev;
2223
2224         pdev = nil;
2225         while(pdev = pcimatch(pdev, 0, 0)) {
2226                 Ctlr *ctlr;
2227                 void *mem;
2228
2229                 if(pdev->ccrb != 2 || pdev->ccru != 0x80)
2230                         continue;
2231                 if(pdev->vid != 0x8086)
2232                         continue;
2233
2234                 switch(pdev->did){
2235                 default:
2236                         continue;
2237                 case 0x4229:    /* WiFi Link 4965 */
2238                 case 0x4230:    /* WiFi Link 4965 */
2239                 case 0x4236:    /* WiFi Link 5300 AGN */
2240                 case 0x4237:    /* Wifi Link 5100 AGN */
2241                 case 0x0085:    /* Centrino Advanced-N 6205 */
2242                 case 0x422b:    /* Centrino Ultimate-N 6300 */
2243                         break;
2244                 }
2245
2246                 /* Clear device-specific "PCI retry timeout" register (41h). */
2247                 if(pcicfgr8(pdev, 0x41) != 0)
2248                         pcicfgw8(pdev, 0x41, 0);
2249
2250                 /* Clear interrupt disable bit. Hardware bug workaround. */
2251                 if(pdev->pcr & 0x400){
2252                         pdev->pcr &= ~0x400;
2253                         pcicfgw16(pdev, PciPCR, pdev->pcr);
2254                 }
2255
2256                 pcisetbme(pdev);
2257                 pcisetpms(pdev, 0);
2258
2259                 ctlr = malloc(sizeof(Ctlr));
2260                 if(ctlr == nil) {
2261                         print("iwl: unable to alloc Ctlr\n");
2262                         continue;
2263                 }
2264                 ctlr->port = pdev->mem[0].bar & ~0x0F;
2265                 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
2266                 if(mem == nil) {
2267                         print("iwl: can't map %8.8luX\n", pdev->mem[0].bar);
2268                         free(ctlr);
2269                         continue;
2270                 }
2271                 ctlr->nic = mem;
2272                 ctlr->pdev = pdev;
2273                 ctlr->type = (csr32r(ctlr, Rev) >> 4) & 0xF;
2274
2275                 if(fwname[ctlr->type] == nil){
2276                         print("iwl: unsupported controller type %d\n", ctlr->type);
2277                         vunmap(mem, pdev->mem[0].size);
2278                         free(ctlr);
2279                         continue;
2280                 }
2281
2282                 if(iwlhead != nil)
2283                         iwltail->link = ctlr;
2284                 else
2285                         iwlhead = ctlr;
2286                 iwltail = ctlr;
2287         }
2288 }
2289
2290 static int
2291 iwlpnp(Ether* edev)
2292 {
2293         Ctlr *ctlr;
2294
2295         if(iwlhead == nil)
2296                 iwlpci();
2297 again:
2298         for(ctlr = iwlhead; ctlr != nil; ctlr = ctlr->link){
2299                 if(ctlr->active)
2300                         continue;
2301                 if(edev->port == 0 || edev->port == ctlr->port){
2302                         ctlr->active = 1;
2303                         break;
2304                 }
2305         }
2306
2307         if(ctlr == nil)
2308                 return -1;
2309
2310         edev->ctlr = ctlr;
2311         edev->port = ctlr->port;
2312         edev->irq = ctlr->pdev->intl;
2313         edev->tbdf = ctlr->pdev->tbdf;
2314         edev->arg = edev;
2315         edev->interrupt = iwlinterrupt;
2316         edev->attach = iwlattach;
2317         edev->ifstat = iwlifstat;
2318         edev->ctl = iwlctl;
2319         edev->promiscuous = iwlpromiscuous;
2320         edev->multicast = nil;
2321         edev->mbps = 10;
2322
2323         if(iwlinit(edev) < 0){
2324                 edev->ctlr = nil;
2325                 goto again;
2326         }
2327
2328         return 0;
2329 }
2330
2331 void
2332 etheriwllink(void)
2333 {
2334         addethercard("iwl", iwlpnp);
2335 }