sys/src/9/pc/etheriwl.c

   1 /*
   2  * Intel WiFi Link driver.
   3  *
   4  * Written without any documentation but Damien Bergaminis
   5  * OpenBSD iwn(4) driver sources. Requires intel firmware
   6  * to be present in /lib/firmware/iwn-* on attach.
   7  */
   8
   9 #include "u.h"
  10 #include "../port/lib.h"
  11 #include "mem.h"
  12 #include "dat.h"
  13 #include "fns.h"
  14 #include "io.h"
  15 #include "../port/error.h"
  16 #include "../port/netif.h"
  17 #include "../port/etherif.h"
  18 #include "../port/wifi.h"
  19
  20 enum {
  21         MaxQueue        = 24*1024,      /* total buffer is 2*MaxQueue: 48k at 22Mbit ≅ 20ms */
  22
  23         Ntxlog          = 8,
  24         Ntx             = 1<<Ntxlog,
  25         Ntxqmax         = MaxQueue/1500,
  26
  27         Nrxlog          = 8,
  28         Nrx             = 1<<Nrxlog,
  29
  30         Rstatsize       = 16,
  31         Rbufsize        = 4*1024,
  32         Rdscsize        = 8,
  33
  34         Tbufsize        = 4*1024,
  35         Tdscsize        = 128,
  36         Tcmdsize        = 140,
  37 };
  38
  39 /* registers */
  40 enum {
  41         Cfg             = 0x000,        /* config register */
  42                 MacSi           = 1<<8,
  43                 RadioSi         = 1<<9,
  44                 EepromLocked    = 1<<21,
  45                 NicReady        = 1<<22,
  46                 HapwakeL1A      = 1<<23,
  47                 PrepareDone     = 1<<25,
  48                 Prepare         = 1<<27,
  49
  50         Isr             = 0x008,        /* interrupt status */
  51         Imr             = 0x00c,        /* interrupt mask */
  52                 Ialive          = 1<<0,
  53                 Iwakeup         = 1<<1,
  54                 Iswrx           = 1<<3,
  55                 Ictreached      = 1<<6,
  56                 Irftoggled      = 1<<7,
  57                 Iswerr          = 1<<25,
  58                 Isched          = 1<<26,
  59                 Ifhtx           = 1<<27,
  60                 Irxperiodic     = 1<<28,
  61                 Ihwerr          = 1<<29,
  62                 Ifhrx           = 1<<31,
  63
  64                 Ierr            = Iswerr | Ihwerr,
  65                 Idefmask        = Ierr | Ifhtx | Ifhrx | Ialive | Iwakeup | Iswrx | Ictreached | Irftoggled,
  66
  67         FhIsr           = 0x010,        /* second interrupt status */
  68
  69         Reset           = 0x020,
  70
  71         Rev             = 0x028,        /* hardware revision */
  72
  73         EepromIo        = 0x02c,        /* EEPROM i/o register */
  74         EepromGp        = 0x030,
  75
  76         OtpromGp        = 0x034,
  77                 DevSelOtp       = 1<<16,
  78                 RelativeAccess  = 1<<17,
  79                 EccCorrStts     = 1<<20,
  80                 EccUncorrStts   = 1<<21,
  81
  82         Gpc             = 0x024,        /* gp cntrl */
  83                 MacAccessEna    = 1<<0,
  84                 MacClockReady   = 1<<0,
  85                 InitDone        = 1<<2,
  86                 MacAccessReq    = 1<<3,
  87                 NicSleep        = 1<<4,
  88                 RfKill          = 1<<27,
  89
  90         Gio             = 0x03c,
  91                 EnaL0S          = 1<<1,
  92
  93         GpDrv   = 0x050,
  94                 GpDrvCalV6      = 1<<2,
  95                 GpDrv1X2        = 1<<3,
  96                 GpDrvRadioIqInvert      = 1<<7,
  97
  98         Led             = 0x094,
  99                 LedBsmCtrl      = 1<<5,
 100                 LedOn           = 0x38,
 101                 LedOff          = 0x78,
 102
 103         UcodeGp1Clr     = 0x05c,
 104                 UcodeGp1RfKill          = 1<<1,
 105                 UcodeGp1CmdBlocked      = 1<<2,
 106                 UcodeGp1CtempStopRf     = 1<<3,
 107
 108         ShadowRegCtrl   = 0x0a8,
 109
 110         Giochicken      = 0x100,
 111                 L1AnoL0Srx      = 1<<23,
 112                 DisL0Stimer     = 1<<29,
 113
 114         AnaPll          = 0x20c,
 115
 116         Dbghpetmem      = 0x240,
 117         Dbglinkpwrmgmt  = 0x250,
 118
 119         MemRaddr        = 0x40c,
 120         MemWaddr        = 0x410,
 121         MemWdata        = 0x418,
 122         MemRdata        = 0x41c,
 123
 124         PrphWaddr       = 0x444,
 125         PrphRaddr       = 0x448,
 126         PrphWdata       = 0x44c,
 127         PrphRdata       = 0x450,
 128
 129         HbusTargWptr    = 0x460,
 130 };
 131
 132 /*
 133  * Flow-Handler registers.
 134  */
 135 enum {
 136         FhTfbdCtrl0     = 0x1900,       // +q*8
 137         FhTfbdCtrl1     = 0x1904,       // +q*8
 138
 139         FhKwAddr        = 0x197c,
 140
 141         FhSramAddr      = 0x19a4,       // +q*4
 142         FhCbbcQueue     = 0x19d0,       // +q*4
 143         FhStatusWptr    = 0x1bc0,
 144         FhRxBase        = 0x1bc4,
 145         FhRxWptr        = 0x1bc8,
 146         FhRxConfig      = 0x1c00,
 147                 FhRxConfigEna           = 1<<31,
 148                 FhRxConfigRbSize8K      = 1<<16,
 149                 FhRxConfigSingleFrame   = 1<<15,
 150                 FhRxConfigIrqDstHost    = 1<<12,
 151                 FhRxConfigIgnRxfEmpty   = 1<<2,
 152
 153                 FhRxConfigNrbdShift     = 20,
 154                 FhRxConfigRbTimeoutShift= 4,
 155
 156         FhRxStatus      = 0x1c44,
 157
 158         FhTxConfig      = 0x1d00,       // +q*32
 159                 FhTxConfigDmaCreditEna  = 1<<3,
 160                 FhTxConfigDmaEna        = 1<<31,
 161                 FhTxConfigCirqHostEndTfd= 1<<20,
 162
 163         FhTxBufStatus   = 0x1d08,       // +q*32
 164                 FhTxBufStatusTbNumShift = 20,
 165                 FhTxBufStatusTbIdxShift = 12,
 166                 FhTxBufStatusTfbdValid  = 3,
 167
 168         FhTxChicken     = 0x1e98,
 169         FhTxStatus      = 0x1eb0,
 170 };
 171
 172 /*
 173  * NIC internal memory offsets.
 174  */
 175 enum {
 176         ApmgClkCtrl     = 0x3000,
 177         ApmgClkEna      = 0x3004,
 178         ApmgClkDis      = 0x3008,
 179                 DmaClkRqt       = 1<<9,
 180                 BsmClkRqt       = 1<<11,
 181
 182         ApmgPs          = 0x300c,
 183                 EarlyPwroffDis  = 1<<22,
 184                 PwrSrcVMain     = 0<<24,
 185                 PwrSrcVAux      = 2<<24,
 186                 PwrSrcMask      = 3<<24,
 187                 ResetReq        = 1<<26,
 188
 189         ApmgDigitalSvr  = 0x3058,
 190         ApmgAnalogSvr   = 0x306c,
 191         ApmgPciStt      = 0x3010,
 192         BsmWrCtrl       = 0x3400,
 193         BsmWrMemSrc     = 0x3404,
 194         BsmWrMemDst     = 0x3408,
 195         BsmWrDwCount    = 0x340c,
 196         BsmDramTextAddr = 0x3490,
 197         BsmDramTextSize = 0x3494,
 198         BsmDramDataAddr = 0x3498,
 199         BsmDramDataSize = 0x349c,
 200         BsmSramBase     = 0x3800,
 201 };
 202
 203 /*
 204  * TX scheduler registers.
 205  */
 206 enum {
 207         SchedBase               = 0xa02c00,
 208         SchedSramAddr           = SchedBase,
 209
 210         SchedDramAddr4965       = SchedBase+0x010,
 211         SchedTxFact4965         = SchedBase+0x01c,
 212         SchedQueueRdptr4965     = SchedBase+0x064,      // +q*4
 213         SchedQChainSel4965      = SchedBase+0x0d0,
 214         SchedIntrMask4965       = SchedBase+0x0e4,
 215         SchedQueueStatus4965    = SchedBase+0x104,      // +q*4
 216
 217         SchedDramAddr5000       = SchedBase+0x008,
 218         SchedTxFact5000         = SchedBase+0x010,
 219         SchedQueueRdptr5000     = SchedBase+0x068,      // +q*4
 220         SchedQChainSel5000      = SchedBase+0x0e8,
 221         SchedIntrMask5000       = SchedBase+0x108,
 222         SchedQueueStatus5000    = SchedBase+0x10c,      // +q*4
 223         SchedAggrSel5000        = SchedBase+0x248,
 224 };
 225
 226 enum {
 227         SchedCtxOff4965         = 0x380,
 228         SchedCtxLen4965         = 416,
 229
 230         SchedCtxOff5000         = 0x600,
 231         SchedCtxLen5000         = 512,
 232 };
 233
 234 enum {
 235         FilterPromisc           = 1<<0,
 236         FilterCtl               = 1<<1,
 237         FilterMulticast         = 1<<2,
 238         FilterNoDecrypt         = 1<<3,
 239         FilterBSS               = 1<<5,
 240         FilterBeacon            = 1<<6,
 241 };
 242
 243 enum {
 244         RFlag24Ghz              = 1<<0,
 245         RFlagCCK                = 1<<1,
 246         RFlagAuto               = 1<<2,
 247         RFlagShSlot             = 1<<4,
 248         RFlagShPreamble         = 1<<5,
 249         RFlagNoDiversity        = 1<<7,
 250         RFlagAntennaA           = 1<<8,
 251         RFlagAntennaB           = 1<<9,
 252         RFlagTSF                = 1<<15,
 253         RFlagCTSToSelf          = 1<<30,
 254 };
 255
 256 typedef struct FWInfo FWInfo;
 257 typedef struct FWImage FWImage;
 258 typedef struct FWSect FWSect;
 259
 260 typedef struct TXQ TXQ;
 261 typedef struct RXQ RXQ;
 262
 263 typedef struct Ctlr Ctlr;
 264
 265 struct FWSect
 266 {
 267         uchar   *data;
 268         uint    size;
 269 };
 270
 271 struct FWImage
 272 {
 273         struct {
 274                 FWSect  text;
 275                 FWSect  data;
 276         } init, main, boot;
 277
 278         uint    rev;
 279         uint    build;
 280         char    descr[64+1];
 281         uchar   data[];
 282 };
 283
 284 struct FWInfo
 285 {
 286         uchar   major;
 287         uchar   minjor;
 288         uchar   type;
 289         uchar   subtype;
 290
 291         u32int  logptr;
 292         u32int  errptr;
 293         u32int  tstamp;
 294         u32int  valid;
 295 };
 296
 297 struct TXQ
 298 {
 299         uint    n;
 300         uint    i;
 301         Block   **b;
 302         uchar   *d;
 303         uchar   *c;
 304
 305         uint    lastcmd;
 306
 307         Rendez;
 308         QLock;
 309 };
 310
 311 struct RXQ
 312 {
 313         uint    i;
 314         Block   **b;
 315         u32int  *p;
 316         uchar   *s;
 317 };
 318
 319 struct Ctlr {
 320         Lock;
 321         QLock;
 322
 323         Ctlr *link;
 324         Pcidev *pdev;
 325         Wifi *wifi;
 326
 327         int type;
 328         int port;
 329         int power;
 330         int active;
 331         int broken;
 332         int attached;
 333
 334         u32int ie;
 335
 336         u32int *nic;
 337         uchar *kwpage;
 338
 339         /* assigned node ids in hardware node table or -1 if unassigned */
 340         int bcastnodeid;
 341         int bssnodeid;
 342
 343         /* current receiver settings */
 344         uchar bssid[Eaddrlen];
 345         int channel;
 346         int prom;
 347         int aid;
 348
 349         RXQ rx;
 350         TXQ tx[20];
 351
 352         struct {
 353                 Rendez;
 354                 u32int  m;
 355                 u32int  w;
 356         } wait;
 357
 358         struct {
 359                 uchar   type;
 360                 uchar   step;
 361                 uchar   dash;
 362                 uchar   txantmask;
 363                 uchar   rxantmask;
 364         } rfcfg;
 365
 366         struct {
 367                 int     otp;
 368                 uint    off;
 369
 370                 uchar   version;
 371                 uchar   type;
 372                 u16int  volt;
 373                 u16int  temp;
 374                 u16int  rawtemp;
 375
 376                 char    regdom[4+1];
 377
 378                 u32int  crystal;
 379         } eeprom;
 380
 381         struct {
 382                 Block   *cmd[21];
 383                 int     done;
 384         } calib;
 385
 386         struct {
 387                 u32int  base;
 388                 uchar   *s;
 389         } sched;
 390
 391         FWInfo fwinfo;
 392         FWImage *fw;
 393 };
 394
 395 /* controller types */
 396 enum {
 397         Type4965        = 0,
 398         Type5300        = 2,
 399         Type5350        = 3,
 400         Type5150        = 4,
 401         Type5100        = 5,
 402         Type1000        = 6,
 403         Type6000        = 7,
 404         Type6050        = 8,
 405         Type6005        = 11,   /* also Centrino Advanced-N 6030, 6235 */
 406         Type2030        = 12,
 407 };
 408
 409 static char *fwname[32] = {
 410         [Type4965] "iwn-4965",
 411         [Type5300] "iwn-5000",
 412         [Type5350] "iwn-5000",
 413         [Type5150] "iwn-5150",
 414         [Type5100] "iwn-5000",
 415         [Type1000] "iwn-1000",
 416         [Type6000] "iwn-6000",
 417         [Type6050] "iwn-6050",
 418         [Type6005] "iwn-6005", /* see in iwlattach() below */
 419         [Type2030] "iwn-2030",
 420 };
 421
 422 static char *qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block);
 423 static char *flushq(Ctlr *ctlr, uint qid);
 424 static char *cmd(Ctlr *ctlr, uint code, uchar *data, int size);
 425
 426 #define csr32r(c, r)    (*((c)->nic+((r)/4)))
 427 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
 428
 429 static uint
 430 get16(uchar *p){
 431         return *((u16int*)p);
 432 }
 433 static uint
 434 get32(uchar *p){
 435         return *((u32int*)p);
 436 }
 437 static void
 438 put32(uchar *p, uint v){
 439         *((u32int*)p) = v;
 440 }
 441 static void
 442 put16(uchar *p, uint v){
 443         *((u16int*)p) = v;
 444 };
 445
 446 static char*
 447 niclock(Ctlr *ctlr)
 448 {
 449         int i;
 450
 451         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | MacAccessReq);
 452         for(i=0; i<1000; i++){
 453                 if((csr32r(ctlr, Gpc) & (NicSleep | MacAccessEna)) == MacAccessEna)
 454                         return 0;
 455                 delay(10);
 456         }
 457         return "niclock: timeout";
 458 }
 459
 460 static void
 461 nicunlock(Ctlr *ctlr)
 462 {
 463         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~MacAccessReq);
 464 }
 465
 466 static u32int
 467 prphread(Ctlr *ctlr, uint off)
 468 {
 469         csr32w(ctlr, PrphRaddr, ((sizeof(u32int)-1)<<24) | off);
 470         coherence();
 471         return csr32r(ctlr, PrphRdata);
 472 }
 473 static void
 474 prphwrite(Ctlr *ctlr, uint off, u32int data)
 475 {
 476         csr32w(ctlr, PrphWaddr, ((sizeof(u32int)-1)<<24) | off);
 477         coherence();
 478         csr32w(ctlr, PrphWdata, data);
 479 }
 480
 481 static u32int
 482 memread(Ctlr *ctlr, uint off)
 483 {
 484         csr32w(ctlr, MemRaddr, off);
 485         coherence();
 486         return csr32r(ctlr, MemRdata);
 487 }
 488 static void
 489 memwrite(Ctlr *ctlr, uint off, u32int data)
 490 {
 491         csr32w(ctlr, MemWaddr, off);
 492         coherence();
 493         csr32w(ctlr, MemWdata, data);
 494 }
 495
 496 static void
 497 setfwinfo(Ctlr *ctlr, uchar *d, int len)
 498 {
 499         FWInfo *i;
 500
 501         if(len < 32)
 502                 return;
 503         i = &ctlr->fwinfo;
 504         i->minjor = *d++;
 505         i->major = *d++;
 506         d += 2+8;
 507         i->type = *d++;
 508         i->subtype = *d++;
 509         d += 2;
 510         i->logptr = get32(d); d += 4;
 511         i->errptr = get32(d); d += 4;
 512         i->tstamp = get32(d); d += 4;
 513         i->valid = get32(d);
 514 };
 515
 516 static void
 517 dumpctlr(Ctlr *ctlr)
 518 {
 519         u32int dump[13];
 520         int i;
 521
 522         print("lastcmd: %ud (0x%ux)\n", ctlr->tx[4].lastcmd,  ctlr->tx[4].lastcmd);
 523         if(ctlr->fwinfo.errptr == 0){
 524                 print("no error pointer\n");
 525                 return;
 526         }
 527         for(i=0; i<nelem(dump); i++)
 528                 dump[i] = memread(ctlr, ctlr->fwinfo.errptr + i*4);
 529         print(  "error:\tid %ux, pc %ux,\n"
 530                 "\tbranchlink %.8ux %.8ux, interruptlink %.8ux %.8ux,\n"
 531                 "\terrordata %.8ux %.8ux, srcline %ud, tsf %ux, time %ux\n",
 532                 dump[1], dump[2],
 533                 dump[4], dump[3], dump[6], dump[5],
 534                 dump[7], dump[8], dump[9], dump[10], dump[11]);
 535 }
 536
 537 static char*
 538 eepromlock(Ctlr *ctlr)
 539 {
 540         int i, j;
 541
 542         for(i=0; i<100; i++){
 543                 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | EepromLocked);
 544                 for(j=0; j<100; j++){
 545                         if(csr32r(ctlr, Cfg) & EepromLocked)
 546                                 return 0;
 547                         delay(10);
 548                 }
 549         }
 550         return "eepromlock: timeout";
 551 }
 552 static void
 553 eepromunlock(Ctlr *ctlr)
 554 {
 555         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) & ~EepromLocked);
 556 }
 557 static char*
 558 eepromread(Ctlr *ctlr, void *data, int count, uint off)
 559 {
 560         uchar *out = data;
 561         u32int w, s;
 562         int i;
 563
 564         w = 0;
 565         off += ctlr->eeprom.off;
 566         for(; count > 0; count -= 2, off++){
 567                 csr32w(ctlr, EepromIo, off << 2);
 568                 for(i=0; i<10; i++){
 569                         w = csr32r(ctlr, EepromIo);
 570                         if(w & 1)
 571                                 break;
 572                         delay(5);
 573                 }
 574                 if(i == 10)
 575                         return "eepromread: timeout";
 576                 if(ctlr->eeprom.otp){
 577                         s = csr32r(ctlr, OtpromGp);
 578                         if(s & EccUncorrStts)
 579                                 return "eepromread: otprom ecc error";
 580                         if(s & EccCorrStts)
 581                                 csr32w(ctlr, OtpromGp, s);
 582                 }
 583                 *out++ = w >> 16;
 584                 if(count > 1)
 585                         *out++ = w >> 24;
 586         }
 587         return 0;
 588 }
 589
 590 static char*
 591 handover(Ctlr *ctlr)
 592 {
 593         int i;
 594
 595         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
 596         for(i=0; i<5; i++){
 597                 if(csr32r(ctlr, Cfg) & NicReady)
 598                         return 0;
 599                 delay(10);
 600         }
 601         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | Prepare);
 602         for(i=0; i<15000; i++){
 603                 if((csr32r(ctlr, Cfg) & PrepareDone) == 0)
 604                         break;
 605                 delay(10);
 606         }
 607         if(i >= 15000)
 608                 return "handover: timeout";
 609         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
 610         for(i=0; i<5; i++){
 611                 if(csr32r(ctlr, Cfg) & NicReady)
 612                         return 0;
 613                 delay(10);
 614         }
 615         return "handover: timeout";
 616 }
 617
 618 static char*
 619 clockwait(Ctlr *ctlr)
 620 {
 621         int i;
 622
 623         /* Set "initialization complete" bit. */
 624         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | InitDone);
 625         for(i=0; i<2500; i++){
 626                 if(csr32r(ctlr, Gpc) & MacClockReady)
 627                         return 0;
 628                 delay(10);
 629         }
 630         return "clockwait: timeout";
 631 }
 632
 633 static char*
 634 poweron(Ctlr *ctlr)
 635 {
 636         int capoff;
 637         char *err;
 638
 639         /* Disable L0s exit timer (NMI bug workaround). */
 640         csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | DisL0Stimer);
 641
 642         /* Don't wait for ICH L0s (ICH bug workaround). */
 643         csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | L1AnoL0Srx);
 644
 645         /* Set FH wait threshold to max (HW bug under stress workaround). */
 646         csr32w(ctlr, Dbghpetmem, csr32r(ctlr, Dbghpetmem) | 0xffff0000);
 647
 648         /* Enable HAP INTA to move adapter from L1a to L0s. */
 649         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | HapwakeL1A);
 650
 651         capoff = pcicap(ctlr->pdev, PciCapPCIe);
 652         if(capoff != -1){
 653                 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
 654                 if(pcicfgr16(ctlr->pdev, capoff + 0x10) & 0x2)  /* LCSR -> L1 Entry enabled. */
 655                         csr32w(ctlr, Gio, csr32r(ctlr, Gio) | EnaL0S);
 656                 else
 657                         csr32w(ctlr, Gio, csr32r(ctlr, Gio) & ~EnaL0S);
 658         }
 659
 660         if(ctlr->type != Type4965 && ctlr->type <= Type1000)
 661                 csr32w(ctlr, AnaPll, csr32r(ctlr, AnaPll) | 0x00880300);
 662
 663         /* Wait for clock stabilization before accessing prph. */
 664         if((err = clockwait(ctlr)) != nil)
 665                 return err;
 666
 667         if((err = niclock(ctlr)) != nil)
 668                 return err;
 669
 670         /* Enable DMA and BSM (Bootstrap State Machine). */
 671         if(ctlr->type == Type4965)
 672                 prphwrite(ctlr, ApmgClkEna, DmaClkRqt | BsmClkRqt);
 673         else
 674                 prphwrite(ctlr, ApmgClkEna, DmaClkRqt);
 675         delay(20);
 676
 677         /* Disable L1-Active. */
 678         prphwrite(ctlr, ApmgPciStt, prphread(ctlr, ApmgPciStt) | (1<<11));
 679
 680         nicunlock(ctlr);
 681
 682         ctlr->power = 1;
 683
 684         return 0;
 685 }
 686
 687 static void
 688 poweroff(Ctlr *ctlr)
 689 {
 690         int i, j;
 691
 692         csr32w(ctlr, Reset, 1);
 693
 694         /* Disable interrupts */
 695         ctlr->ie = 0;
 696         csr32w(ctlr, Imr, 0);
 697         csr32w(ctlr, Isr, ~0);
 698         csr32w(ctlr, FhIsr, ~0);
 699
 700         /* Stop scheduler */
 701         if(ctlr->type != Type4965)
 702                 prphwrite(ctlr, SchedTxFact5000, 0);
 703         else
 704                 prphwrite(ctlr, SchedTxFact4965, 0);
 705
 706         /* Stop TX ring */
 707         if(niclock(ctlr) == nil){
 708                 for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--){
 709                         csr32w(ctlr, FhTxConfig + i*32, 0);
 710                         for(j = 0; j < 200; j++){
 711                                 if(csr32r(ctlr, FhTxStatus) & (0x10000<<i))
 712                                         break;
 713                                 delay(10);
 714                         }
 715                 }
 716                 nicunlock(ctlr);
 717         }
 718
 719         /* Stop RX ring */
 720         if(niclock(ctlr) == nil){
 721                 csr32w(ctlr, FhRxConfig, 0);
 722                 for(j = 0; j < 200; j++){
 723                         if(csr32r(ctlr, FhRxStatus) & 0x1000000)
 724                                 break;
 725                         delay(10);
 726                 }
 727                 nicunlock(ctlr);
 728         }
 729
 730         /* Disable DMA */
 731         if(niclock(ctlr) == nil){
 732                 prphwrite(ctlr, ApmgClkDis, DmaClkRqt);
 733                 nicunlock(ctlr);
 734         }
 735         delay(5);
 736
 737         /* Stop busmaster DMA activity. */
 738         csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<9));
 739         for(j = 0; j < 100; j++){
 740                 if(csr32r(ctlr, Reset) & (1<<8))
 741                         break;
 742                 delay(10);
 743         }
 744
 745         /* Reset the entire device. */
 746         csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<7));
 747         delay(10);
 748
 749         /* Clear "initialization complete" bit. */
 750         csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~InitDone);
 751
 752         ctlr->power = 0;
 753 }
 754
 755 static char*
 756 rominit(Ctlr *ctlr)
 757 {
 758         uint prev, last;
 759         uchar buf[2];
 760         char *err;
 761         int i;
 762
 763         ctlr->eeprom.otp = 0;
 764         ctlr->eeprom.off = 0;
 765         if(ctlr->type < Type1000 || (csr32r(ctlr, OtpromGp) & DevSelOtp) == 0)
 766                 return nil;
 767
 768         /* Wait for clock stabilization before accessing prph. */
 769         if((err = clockwait(ctlr)) != nil)
 770                 return err;
 771
 772         if((err = niclock(ctlr)) != nil)
 773                 return err;
 774         prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | ResetReq);
 775         delay(5);
 776         prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) & ~ResetReq);
 777         nicunlock(ctlr);
 778
 779         /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
 780         if(ctlr->type != Type1000)
 781                 csr32w(ctlr, Dbglinkpwrmgmt, csr32r(ctlr, Dbglinkpwrmgmt) | (1<<31));
 782
 783         csr32w(ctlr, EepromGp, csr32r(ctlr, EepromGp) & ~0x00000180);
 784
 785         /* Clear ECC status. */
 786         csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) | (EccCorrStts | EccUncorrStts));
 787
 788         ctlr->eeprom.otp = 1;
 789         if(ctlr->type != Type1000)
 790                 return nil;
 791
 792         /* Switch to absolute addressing mode. */
 793         csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) & ~RelativeAccess);
 794
 795         /*
 796          * Find the block before last block (contains the EEPROM image)
 797          * for HW without OTP shadow RAM.
 798          */
 799         prev = last = 0;
 800         for(i=0; i<3; i++){
 801                 if((err = eepromread(ctlr, buf, 2, last)) != nil)
 802                         return err;
 803                 if(get16(buf) == 0)
 804                         break;
 805                 prev = last;
 806                 last = get16(buf);
 807         }
 808         if(i == 0 || i >= 3)
 809                 return "rominit: missing eeprom image";
 810
 811         ctlr->eeprom.off = prev+1;
 812         return nil;
 813 }
 814
 815 static int
 816 iwlinit(Ether *edev)
 817 {
 818         Ctlr *ctlr;
 819         char *err;
 820         uchar b[4];
 821         uint u, caloff, regoff;
 822
 823         ctlr = edev->ctlr;
 824
 825         /* Clear device-specific "PCI retry timeout" register (41h). */
 826         if(pcicfgr8(ctlr->pdev, 0x41) != 0)
 827                 pcicfgw8(ctlr->pdev, 0x41, 0);
 828
 829         /* Clear interrupt disable bit. Hardware bug workaround. */
 830         if(ctlr->pdev->pcr & 0x400){
 831                 ctlr->pdev->pcr &= ~0x400;
 832                 pcicfgw16(ctlr->pdev, PciPCR, ctlr->pdev->pcr);
 833         }
 834
 835         ctlr->type = (csr32r(ctlr, Rev) >> 4) & 0x1F;
 836         if(fwname[ctlr->type] == nil){
 837                 print("iwl: unsupported controller type %d\n", ctlr->type);
 838                 return -1;
 839         }
 840
 841         if((err = handover(ctlr)) != nil)
 842                 goto Err;
 843         if((err = poweron(ctlr)) != nil)
 844                 goto Err;
 845         if((csr32r(ctlr, EepromGp) & 0x7) == 0){
 846                 err = "bad rom signature";
 847                 goto Err;
 848         }
 849         if((err = eepromlock(ctlr)) != nil)
 850                 goto Err;
 851         if((err = rominit(ctlr)) != nil)
 852                 goto Err2;
 853         if((err = eepromread(ctlr, edev->ea, sizeof(edev->ea), 0x15)) != nil){
 854                 eepromunlock(ctlr);
 855                 goto Err;
 856         }
 857         if((err = eepromread(ctlr, b, 2, 0x048)) != nil){
 858         Err2:
 859                 eepromunlock(ctlr);
 860                 goto Err;
 861         }
 862         u = get16(b);
 863         ctlr->rfcfg.type = u & 3;       u >>= 2;
 864         ctlr->rfcfg.step = u & 3;       u >>= 2;
 865         ctlr->rfcfg.dash = u & 3;       u >>= 4;
 866         ctlr->rfcfg.txantmask = u & 15; u >>= 4;
 867         ctlr->rfcfg.rxantmask = u & 15;
 868         if((err = eepromread(ctlr, b, 2, 0x66)) != nil)
 869                 goto Err2;
 870         regoff = get16(b);
 871         if((err = eepromread(ctlr, b, 4, regoff+1)) != nil)
 872                 goto Err2;
 873         strncpy(ctlr->eeprom.regdom, (char*)b, 4);
 874         ctlr->eeprom.regdom[4] = 0;
 875         if((err = eepromread(ctlr, b, 2, 0x67)) != nil)
 876                 goto Err2;
 877         caloff = get16(b);
 878         if((err = eepromread(ctlr, b, 4, caloff)) != nil)
 879                 goto Err2;
 880         ctlr->eeprom.version = b[0];
 881         ctlr->eeprom.type = b[1];
 882         ctlr->eeprom.volt = get16(b+2);
 883
 884         ctlr->eeprom.temp = 0;
 885         ctlr->eeprom.rawtemp = 0;
 886         if(ctlr->type == Type2030){
 887                 if((err = eepromread(ctlr, b, 2, caloff + 0x12a)) != nil)
 888                         goto Err2;
 889                 ctlr->eeprom.temp = get16(b);
 890                 if((err = eepromread(ctlr, b, 2, caloff + 0x12b)) != nil)
 891                         goto Err2;
 892                 ctlr->eeprom.rawtemp = get16(b);
 893         }
 894
 895         if(ctlr->type != Type4965 && ctlr->type != Type5150){
 896                 if((err = eepromread(ctlr, b, 4, caloff + 0x128)) != nil)
 897                         goto Err2;
 898                 ctlr->eeprom.crystal = get32(b);
 899         }
 900         eepromunlock(ctlr);
 901
 902         switch(ctlr->type){
 903         case Type4965:
 904                 ctlr->rfcfg.txantmask = 3;
 905                 ctlr->rfcfg.rxantmask = 7;
 906                 break;
 907         case Type5100:
 908                 ctlr->rfcfg.txantmask = 2;
 909                 ctlr->rfcfg.rxantmask = 3;
 910                 break;
 911         case Type6000:
 912                 if(ctlr->pdev->did == 0x422c || ctlr->pdev->did == 0x4230){
 913                         ctlr->rfcfg.txantmask = 6;
 914                         ctlr->rfcfg.rxantmask = 6;
 915                 }
 916                 break;
 917         }
 918         poweroff(ctlr);
 919         return 0;
 920 Err:
 921         print("iwlinit: %s\n", err);
 922         poweroff(ctlr);
 923         return -1;
 924 }
 925
 926 static char*
 927 crackfw(FWImage *i, uchar *data, uint size, int alt)
 928 {
 929         uchar *p, *e;
 930         FWSect *s;
 931
 932         memset(i, 0, sizeof(*i));
 933         if(size < 4){
 934 Tooshort:
 935                 return "firmware image too short";
 936         }
 937         p = data;
 938         e = p + size;
 939         i->rev = get32(p); p += 4;
 940         if(i->rev == 0){
 941                 uvlong altmask;
 942
 943                 if(size < (4+64+4+4+8))
 944                         goto Tooshort;
 945                 if(memcmp(p, "IWL\n", 4) != 0)
 946                         return "bad firmware signature";
 947                 p += 4;
 948                 strncpy(i->descr, (char*)p, 64);
 949                 i->descr[64] = 0;
 950                 p += 64;
 951                 i->rev = get32(p); p += 4;
 952                 i->build = get32(p); p += 4;
 953                 altmask = get32(p); p += 4;
 954                 altmask |= (uvlong)get32(p) << 32; p += 4;
 955                 while(alt > 0 && (altmask & (1ULL<<alt)) == 0)
 956                         alt--;
 957                 while(p < e){
 958                         FWSect dummy;
 959
 960                         if((p + 2+2+4) > e)
 961                                 goto Tooshort;
 962                         switch(get16(p)){
 963                         case 1: s = &i->main.text; break;
 964                         case 2: s = &i->main.data; break;
 965                         case 3: s = &i->init.text; break;
 966                         case 4: s = &i->init.data; break;
 967                         case 5: s = &i->boot.text; break;
 968                         default:s = &dummy;
 969                         }
 970                         p += 2;
 971                         if(get16(p) != 0 && get16(p) != alt)
 972                                 s = &dummy;
 973                         p += 2;
 974                         s->size = get32(p); p += 4;
 975                         s->data = p;
 976                         if((p + s->size) > e)
 977                                 goto Tooshort;
 978                         p += (s->size + 3) & ~3;
 979                 }
 980         } else {
 981                 if(((i->rev>>8) & 0xFF) < 2)
 982                         return "need firmware api >= 2";
 983                 if(((i->rev>>8) & 0xFF) >= 3){
 984                         i->build = get32(p); p += 4;
 985                 }
 986                 if((p + 5*4) > e)
 987                         goto Tooshort;
 988                 i->main.text.size = get32(p); p += 4;
 989                 i->main.data.size = get32(p); p += 4;
 990                 i->init.text.size = get32(p); p += 4;
 991                 i->init.data.size = get32(p); p += 4;
 992                 i->boot.text.size = get32(p); p += 4;
 993                 i->main.text.data = p; p += i->main.text.size;
 994                 i->main.data.data = p; p += i->main.data.size;
 995                 i->init.text.data = p; p += i->init.text.size;
 996                 i->init.data.data = p; p += i->init.data.size;
 997                 i->boot.text.data = p; p += i->boot.text.size;
 998                 if(p > e)
 999                         goto Tooshort;
1000         }
1001         return 0;
1002 }
1003
1004 static FWImage*
1005 readfirmware(char *name)
1006 {
1007         uchar dirbuf[sizeof(Dir)+100], *data;
1008         char buf[128], *err;
1009         FWImage *fw;
1010         int n, r;
1011         Chan *c;
1012         Dir d;
1013
1014         if(!iseve())
1015                 error(Eperm);
1016         if(!waserror()){
1017                 snprint(buf, sizeof buf, "/boot/%s", name);
1018                 c = namec(buf, Aopen, OREAD, 0);
1019                 poperror();
1020         } else {
1021                 snprint(buf, sizeof buf, "/lib/firmware/%s", name);
1022                 c = namec(buf, Aopen, OREAD, 0);
1023         }
1024         if(waserror()){
1025                 cclose(c);
1026                 nexterror();
1027         }
1028         n = devtab[c->type]->stat(c, dirbuf, sizeof dirbuf);
1029         if(n <= 0)
1030                 error("can't stat firmware");
1031         convM2D(dirbuf, n, &d, nil);
1032         fw = smalloc(sizeof(*fw) + 16 + d.length);
1033         data = (uchar*)(fw+1);
1034         if(waserror()){
1035                 free(fw);
1036                 nexterror();
1037         }
1038         r = 0;
1039         while(r < d.length){
1040                 n = devtab[c->type]->read(c, data+r, d.length-r, (vlong)r);
1041                 if(n <= 0)
1042                         break;
1043                 r += n;
1044         }
1045         if((err = crackfw(fw, data, r, 1)) != nil)
1046                 error(err);
1047         poperror();
1048         poperror();
1049         cclose(c);
1050         return fw;
1051 }
1052
1053
1054 static int
1055 gotirq(void *arg)
1056 {
1057         Ctlr *ctlr = arg;
1058         return (ctlr->wait.m & ctlr->wait.w) != 0;
1059 }
1060
1061 static u32int
1062 irqwait(Ctlr *ctlr, u32int mask, int timeout)
1063 {
1064         u32int r;
1065
1066         ilock(ctlr);
1067         r = ctlr->wait.m & mask;
1068         if(r == 0){
1069                 ctlr->wait.w = mask;
1070                 iunlock(ctlr);
1071                 if(!waserror()){
1072                         tsleep(&ctlr->wait, gotirq, ctlr, timeout);
1073                         poperror();
1074                 }
1075                 ilock(ctlr);
1076                 ctlr->wait.w = 0;
1077                 r = ctlr->wait.m & mask;
1078         }
1079         ctlr->wait.m &= ~r;
1080         iunlock(ctlr);
1081         return r;
1082 }
1083
1084 static int
1085 rbplant(Ctlr *ctlr, int i)
1086 {
1087         Block *b;
1088
1089         b = iallocb(Rbufsize + 256);
1090         if(b == nil)
1091                 return -1;
1092         b->rp = b->wp = (uchar*)ROUND((uintptr)b->base, 256);
1093         memset(b->rp, 0, Rdscsize);
1094         ctlr->rx.b[i] = b;
1095         ctlr->rx.p[i] = PCIWADDR(b->rp) >> 8;
1096         return 0;
1097 }
1098
1099 static char*
1100 initring(Ctlr *ctlr)
1101 {
1102         RXQ *rx;
1103         TXQ *tx;
1104         int i, q;
1105
1106         rx = &ctlr->rx;
1107         if(rx->b == nil)
1108                 rx->b = malloc(sizeof(Block*) * Nrx);
1109         if(rx->p == nil)
1110                 rx->p = mallocalign(sizeof(u32int) * Nrx, 256, 0, 0);
1111         if(rx->s == nil)
1112                 rx->s = mallocalign(Rstatsize, 16, 0, 0);
1113         if(rx->b == nil || rx->p == nil || rx->s == nil)
1114                 return "no memory for rx ring";
1115         memset(ctlr->rx.s, 0, Rstatsize);
1116         for(i=0; i<Nrx; i++){
1117                 rx->p[i] = 0;
1118                 if(rx->b[i] != nil){
1119                         freeb(rx->b[i]);
1120                         rx->b[i] = nil;
1121                 }
1122                 if(rbplant(ctlr, i) < 0)
1123                         return "no memory for rx descriptors";
1124         }
1125         rx->i = 0;
1126
1127         if(ctlr->sched.s == nil)
1128                 ctlr->sched.s = mallocalign(512 * nelem(ctlr->tx) * 2, 1024, 0, 0);
1129         if(ctlr->sched.s == nil)
1130                 return "no memory for sched buffer";
1131         memset(ctlr->sched.s, 0, 512 * nelem(ctlr->tx));
1132
1133         for(q=0; q<nelem(ctlr->tx); q++){
1134                 tx = &ctlr->tx[q];
1135                 if(tx->b == nil)
1136                         tx->b = malloc(sizeof(Block*) * Ntx);
1137                 if(tx->d == nil)
1138                         tx->d = mallocalign(Tdscsize * Ntx, 256, 0, 0);
1139                 if(tx->c == nil)
1140                         tx->c = mallocalign(Tcmdsize * Ntx, 4, 0, 0);
1141                 if(tx->b == nil || tx->d == nil || tx->c == nil)
1142                         return "no memory for tx ring";
1143                 memset(tx->d, 0, Tdscsize * Ntx);
1144                 memset(tx->c, 0, Tcmdsize * Ntx);
1145                 for(i=0; i<Ntx; i++){
1146                         if(tx->b[i] != nil){
1147                                 freeb(tx->b[i]);
1148                                 tx->b[i] = nil;
1149                         }
1150                 }
1151                 tx->i = 0;
1152                 tx->n = 0;
1153                 tx->lastcmd = 0;
1154         }
1155
1156         if(ctlr->kwpage == nil)
1157                 ctlr->kwpage = mallocalign(4096, 4096, 0, 0);
1158         if(ctlr->kwpage == nil)
1159                 return "no memory for kwpage";
1160         memset(ctlr->kwpage, 0, 4096);
1161
1162         return nil;
1163 }
1164
1165 static char*
1166 reset(Ctlr *ctlr)
1167 {
1168         char *err;
1169         int i, q;
1170
1171         if(ctlr->power)
1172                 poweroff(ctlr);
1173         if((err = initring(ctlr)) != nil)
1174                 return err;
1175         if((err = poweron(ctlr)) != nil)
1176                 return err;
1177
1178         if((err = niclock(ctlr)) != nil)
1179                 return err;
1180         prphwrite(ctlr, ApmgPs, (prphread(ctlr, ApmgPs) & ~PwrSrcMask) | PwrSrcVMain);
1181         nicunlock(ctlr);
1182
1183         csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | RadioSi | MacSi);
1184
1185         if((err = niclock(ctlr)) != nil)
1186                 return err;
1187         if(ctlr->type != Type4965)
1188                 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | EarlyPwroffDis);
1189         if(ctlr->type == Type1000){
1190                 /*
1191                  * Select first Switching Voltage Regulator (1.32V) to
1192                  * solve a stability issue related to noisy DC2DC line
1193                  * in the silicon of 1000 Series.
1194                  */
1195                 prphwrite(ctlr, ApmgDigitalSvr,
1196                         (prphread(ctlr, ApmgDigitalSvr) & ~(0xf<<5)) | (3<<5));
1197         }
1198         nicunlock(ctlr);
1199
1200         if((err = niclock(ctlr)) != nil)
1201                 return err;
1202         if((ctlr->type == Type6005 || ctlr->type == Type6050) && ctlr->eeprom.version == 6)
1203                 csr32w(ctlr, GpDrv, csr32r(ctlr, GpDrv) | GpDrvCalV6);
1204         if(ctlr->type == Type6005)
1205                 csr32w(ctlr, GpDrv, csr32r(ctlr, GpDrv) | GpDrv1X2);
1206         if(ctlr->type == Type2030)
1207                 csr32w(ctlr, GpDrv, csr32r(ctlr, GpDrv) | GpDrvRadioIqInvert);
1208         nicunlock(ctlr);
1209
1210         if((err = niclock(ctlr)) != nil)
1211                 return err;
1212         csr32w(ctlr, FhRxConfig, 0);
1213         csr32w(ctlr, FhRxWptr, 0);
1214         csr32w(ctlr, FhRxBase, PCIWADDR(ctlr->rx.p) >> 8);
1215         csr32w(ctlr, FhStatusWptr, PCIWADDR(ctlr->rx.s) >> 4);
1216         csr32w(ctlr, FhRxConfig,
1217                 FhRxConfigEna |
1218                 FhRxConfigIgnRxfEmpty |
1219                 FhRxConfigIrqDstHost |
1220                 FhRxConfigSingleFrame |
1221                 (Nrxlog << FhRxConfigNrbdShift));
1222         csr32w(ctlr, FhRxWptr, (Nrx-1) & ~7);
1223         nicunlock(ctlr);
1224
1225         if((err = niclock(ctlr)) != nil)
1226                 return err;
1227         if(ctlr->type != Type4965)
1228                 prphwrite(ctlr, SchedTxFact5000, 0);
1229         else
1230                 prphwrite(ctlr, SchedTxFact4965, 0);
1231         csr32w(ctlr, FhKwAddr, PCIWADDR(ctlr->kwpage) >> 4);
1232         for(q = (ctlr->type != Type4965) ? 19 : 15; q >= 0; q--)
1233                 csr32w(ctlr, FhCbbcQueue + q*4, PCIWADDR(ctlr->tx[q].d) >> 8);
1234         nicunlock(ctlr);
1235
1236         for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--)
1237                 csr32w(ctlr, FhTxConfig + i*32, FhTxConfigDmaEna | FhTxConfigDmaCreditEna);
1238
1239         csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
1240         csr32w(ctlr, UcodeGp1Clr, UcodeGp1CmdBlocked);
1241
1242         ctlr->broken = 0;
1243         ctlr->wait.m = 0;
1244         ctlr->wait.w = 0;
1245
1246         ctlr->ie = Idefmask;
1247         csr32w(ctlr, Imr, ctlr->ie);
1248         csr32w(ctlr, Isr, ~0);
1249
1250         if(ctlr->type >= Type6000)
1251                 csr32w(ctlr, ShadowRegCtrl, csr32r(ctlr, ShadowRegCtrl) | 0x800fffff);
1252
1253         return nil;
1254 }
1255
1256 static char*
1257 sendbtcoexadv(Ctlr *ctlr)
1258 {
1259         static u32int btcoex3wire[12] = {
1260                 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
1261                 0xcc00ff28,     0x0000aaaa, 0xcc00aaaa, 0x0000aaaa,
1262                 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000,
1263         };
1264
1265         uchar c[Tcmdsize], *p;
1266         char *err;
1267         int i;
1268
1269         /* set BT config */
1270         memset(c, 0, sizeof(c));
1271         p = c;
1272
1273         if(ctlr->type == Type2030){
1274                 *p++ = 145; /* flags */
1275                 p++; /* lead time */
1276                 *p++ = 5; /* max kill */
1277                 *p++ = 1; /* bt3 t7 timer */
1278                 put32(p, 0xffff0000); /* kill ack */
1279                 p += 4;
1280                 put32(p, 0xffff0000); /* kill cts */
1281                 p += 4;
1282                 *p++ = 2; /* sample time */
1283                 *p++ = 0xc; /* bt3 t2 timer */
1284                 p += 2; /* bt4 reaction */
1285                 for (i = 0; i < nelem(btcoex3wire); i++){
1286                         put32(p, btcoex3wire[i]);
1287                         p += 4;
1288                 }
1289                 p += 2; /* bt4 decision */
1290                 put16(p, 0xff); /* valid */
1291                 p += 2;
1292                 put32(p, 0xf0); /* prio boost */
1293                 p += 4;
1294                 p++; /* reserved */
1295                 p++; /* tx prio boost */
1296                 p += 2; /* rx prio boost */
1297         }
1298         if((err = cmd(ctlr, 155, c, p-c)) != nil)
1299                 return err;
1300
1301         /* set BT priority */
1302         memset(c, 0, sizeof(c));
1303         p = c;
1304
1305         *p++ = 0x6; /* init1 */
1306         *p++ = 0x7; /* init2 */
1307         *p++ = 0x2; /* periodic low1 */
1308         *p++ = 0x3; /* periodic low2 */
1309         *p++ = 0x4; /* periodic high1 */
1310         *p++ = 0x5; /* periodic high2 */
1311         *p++ = 0x6; /* dtim */
1312         *p++ = 0x8; /* scan52 */
1313         *p++ = 0xa; /* scan24 */
1314         p += 7; /* reserved */
1315         if((err = cmd(ctlr, 204, c, p-c)) != nil)
1316                 return err;
1317
1318         /* force BT state machine change */
1319         memset(c, 0, sizeof(c));
1320         p = c;
1321
1322         *p++ = 1; /* open */
1323         *p++ = 1; /* type */
1324         p += 2; /* reserved */
1325         if((err = cmd(ctlr, 205, c, p-c)) != nil)
1326                 return err;
1327
1328         c[0] = 0; /* open */
1329         return cmd(ctlr, 205, c, p-c);
1330 }
1331
1332 static char*
1333 postboot(Ctlr *ctlr)
1334 {
1335         uint ctxoff, ctxlen, dramaddr;
1336         char *err;
1337         int i, q;
1338
1339         if((err = niclock(ctlr)) != nil)
1340                 return err;
1341
1342         if(ctlr->type != Type4965){
1343                 dramaddr = SchedDramAddr5000;
1344                 ctxoff = SchedCtxOff5000;
1345                 ctxlen = SchedCtxLen5000;
1346         } else {
1347                 dramaddr = SchedDramAddr4965;
1348                 ctxoff = SchedCtxOff4965;
1349                 ctxlen = SchedCtxLen4965;
1350         }
1351
1352         ctlr->sched.base = prphread(ctlr, SchedSramAddr);
1353         for(i=0; i < ctxlen; i += 4)
1354                 memwrite(ctlr, ctlr->sched.base + ctxoff + i, 0);
1355
1356         prphwrite(ctlr, dramaddr, PCIWADDR(ctlr->sched.s)>>10);
1357
1358         csr32w(ctlr, FhTxChicken, csr32r(ctlr, FhTxChicken) | 2);
1359
1360         if(ctlr->type != Type4965){
1361                 /* Enable chain mode for all queues, except command queue 4. */
1362                 prphwrite(ctlr, SchedQChainSel5000, 0xfffef);
1363                 prphwrite(ctlr, SchedAggrSel5000, 0);
1364
1365                 for(q=0; q<20; q++){
1366                         prphwrite(ctlr, SchedQueueRdptr5000 + q*4, 0);
1367                         csr32w(ctlr, HbusTargWptr, q << 8);
1368
1369                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 0);
1370                         /* Set scheduler window size and frame limit. */
1371                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16 | 64);
1372                 }
1373                 /* Enable interrupts for all our 20 queues. */
1374                 prphwrite(ctlr, SchedIntrMask5000, 0xfffff);
1375
1376                 /* Identify TX FIFO rings (0-7). */
1377                 prphwrite(ctlr, SchedTxFact5000, 0xff);
1378         } else {
1379                 /* Disable chain mode for all our 16 queues. */
1380                 prphwrite(ctlr, SchedQChainSel4965, 0);
1381
1382                 for(q=0; q<16; q++) {
1383                         prphwrite(ctlr, SchedQueueRdptr4965 + q*4, 0);
1384                         csr32w(ctlr, HbusTargWptr, q << 8);
1385
1386                         /* Set scheduler window size. */
1387                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 64);
1388                         /* Set scheduler window size and frame limit. */
1389                         memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16);
1390                 }
1391                 /* Enable interrupts for all our 16 queues. */
1392                 prphwrite(ctlr, SchedIntrMask4965, 0xffff);
1393
1394                 /* Identify TX FIFO rings (0-7). */
1395                 prphwrite(ctlr, SchedTxFact4965, 0xff);
1396         }
1397
1398         /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
1399         for(q=0; q<7; q++){
1400                 if(ctlr->type != Type4965){
1401                         static uchar qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
1402                         prphwrite(ctlr, SchedQueueStatus5000 + q*4, 0x00ff0018 | qid2fifo[q]);
1403                 } else {
1404                         static uchar qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
1405                         prphwrite(ctlr, SchedQueueStatus4965 + q*4, 0x0007fc01 | qid2fifo[q]<<1);
1406                 }
1407         }
1408         nicunlock(ctlr);
1409
1410         if(ctlr->type != Type4965){
1411                 uchar c[Tcmdsize];
1412
1413                 /* disable wimax coexistance */
1414                 memset(c, 0, sizeof(c));
1415                 if((err = cmd(ctlr, 90, c, 4+4*16)) != nil)
1416                         return err;
1417
1418                 if(ctlr->type != Type5150){
1419                         /* calibrate crystal */
1420                         memset(c, 0, sizeof(c));
1421                         c[0] = 15;      /* code */
1422                         c[1] = 0;       /* group */
1423                         c[2] = 1;       /* ngroup */
1424                         c[3] = 1;       /* isvalid */
1425                         c[4] = ctlr->eeprom.crystal;
1426                         c[5] = ctlr->eeprom.crystal>>16;
1427                         /* for some reason 8086:4238 needs a second try */
1428                         if(cmd(ctlr, 176, c, 8) != nil && (err = cmd(ctlr, 176, c, 8)) != nil)
1429                                 return err;
1430                 }
1431
1432                 if(ctlr->calib.done == 0){
1433                         /* query calibration (init firmware) */
1434                         memset(c, 0, sizeof(c));
1435                         put32(c + 0*(5*4) + 0, 0xffffffff);
1436                         put32(c + 0*(5*4) + 4, 0xffffffff);
1437                         put32(c + 0*(5*4) + 8, 0xffffffff);
1438                         put32(c + 2*(5*4) + 0, 0xffffffff);
1439                         if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1440                                 return err;
1441
1442                         /* wait to collect calibration records */
1443                         if(irqwait(ctlr, Ierr, 2000))
1444                                 return "calibration failed";
1445
1446                         if(ctlr->calib.done == 0){
1447                                 print("iwl: no calibration results\n");
1448                                 ctlr->calib.done = 1;
1449                         }
1450                 } else {
1451                         static uchar cmds[] = {8, 9, 11, 17, 16};
1452
1453                         /* send calibration records (runtime firmware) */
1454                         for(q=0; q<nelem(cmds); q++){
1455                                 Block *b;
1456
1457                                 i = cmds[q];
1458                                 if(i == 8 && ctlr->type != Type5150 && ctlr->type != Type2030)
1459                                         continue;
1460                                 if(i == 17 && (ctlr->type >= Type6000 || ctlr->type == Type5150) &&
1461                                         ctlr->type != Type2030)
1462                                         continue;
1463
1464                                 if((b = ctlr->calib.cmd[i]) == nil)
1465                                         continue;
1466                                 b = copyblock(b, BLEN(b));
1467                                 if((err = qcmd(ctlr, 4, 176, nil, 0, b)) != nil){
1468                                         freeb(b);
1469                                         return err;
1470                                 }
1471                                 if((err = flushq(ctlr, 4)) != nil)
1472                                         return err;
1473                         }
1474
1475                         /* temperature sensor offset */
1476                         switch (ctlr->type){
1477                         case Type6005:
1478                                 memset(c, 0, sizeof(c));
1479                                 c[0] = 18;
1480                                 c[1] = 0;
1481                                 c[2] = 1;
1482                                 c[3] = 1;
1483                                 put16(c + 4, 2700);
1484                                 if((err = cmd(ctlr, 176, c, 4+2+2)) != nil)
1485                                         return err;
1486                                 break;
1487
1488                         case Type2030:
1489                                 memset(c, 0, sizeof(c));
1490                                 c[0] = 18;
1491                                 c[1] = 0;
1492                                 c[2] = 1;
1493                                 c[3] = 1;
1494                                 if(ctlr->eeprom.rawtemp != 0){
1495                                         put16(c + 4, ctlr->eeprom.temp);
1496                                         put16(c + 6, ctlr->eeprom.rawtemp);
1497                                 } else{
1498                                         put16(c + 4, 2700);
1499                                         put16(c + 6, 2700);
1500                                 }
1501                                 put16(c + 8, ctlr->eeprom.volt);
1502                                 if((err = cmd(ctlr, 176, c, 4+2+2+2+2)) != nil)
1503                                         return err;
1504                                 break;
1505                         }
1506
1507                         if(ctlr->type == Type6005 || ctlr->type == Type6050){
1508                                 /* runtime DC calibration */
1509                                 memset(c, 0, sizeof(c));
1510                                 put32(c + 0*(5*4) + 0, 0xffffffff);
1511                                 put32(c + 0*(5*4) + 4, 1<<1);
1512                                 if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1513                                         return err;
1514                         }
1515
1516                         /* set tx antenna config */
1517                         put32(c, ctlr->rfcfg.txantmask & 7);
1518                         if((err = cmd(ctlr, 152, c, 4)) != nil)
1519                                 return err;
1520
1521                         if(ctlr->type == Type2030){
1522                                 if((err = sendbtcoexadv(ctlr)) != nil)
1523                                         return err;
1524                         }
1525                 }
1526         }
1527
1528         return nil;
1529 }
1530
1531 static char*
1532 loadfirmware1(Ctlr *ctlr, u32int dst, uchar *data, int size)
1533 {
1534         uchar *dma;
1535         char *err;
1536
1537         dma = mallocalign(size, 16, 0, 0);
1538         if(dma == nil)
1539                 return "no memory for dma";
1540         memmove(dma, data, size);
1541         coherence();
1542         if((err = niclock(ctlr)) != 0){
1543                 free(dma);
1544                 return err;
1545         }
1546         csr32w(ctlr, FhTxConfig + 9*32, 0);
1547         csr32w(ctlr, FhSramAddr + 9*4, dst);
1548         csr32w(ctlr, FhTfbdCtrl0 + 9*8, PCIWADDR(dma));
1549         csr32w(ctlr, FhTfbdCtrl1 + 9*8, size);
1550         csr32w(ctlr, FhTxBufStatus + 9*32,
1551                 (1<<FhTxBufStatusTbNumShift) |
1552                 (1<<FhTxBufStatusTbIdxShift) |
1553                 FhTxBufStatusTfbdValid);
1554         csr32w(ctlr, FhTxConfig + 9*32, FhTxConfigDmaEna | FhTxConfigCirqHostEndTfd);
1555         nicunlock(ctlr);
1556         if(irqwait(ctlr, Ifhtx|Ierr, 5000) != Ifhtx){
1557                 free(dma);
1558                 return "dma error / timeout";
1559         }
1560         free(dma);
1561         return 0;
1562 }
1563
1564 static char*
1565 boot(Ctlr *ctlr)
1566 {
1567         int i, n, size;
1568         uchar *p, *dma;
1569         FWImage *fw;
1570         char *err;
1571
1572         fw = ctlr->fw;
1573
1574         if(fw->boot.text.size == 0){
1575                 if(ctlr->calib.done == 0){
1576                         if((err = loadfirmware1(ctlr, 0x00000000, fw->init.text.data, fw->init.text.size)) != nil)
1577                                 return err;
1578                         if((err = loadfirmware1(ctlr, 0x00800000, fw->init.data.data, fw->init.data.size)) != nil)
1579                                 return err;
1580                         csr32w(ctlr, Reset, 0);
1581                         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1582                                 return "init firmware boot failed";
1583                         if((err = postboot(ctlr)) != nil)
1584                                 return err;
1585                         if((err = reset(ctlr)) != nil)
1586                                 return err;
1587                 }
1588                 if((err = loadfirmware1(ctlr, 0x00000000, fw->main.text.data, fw->main.text.size)) != nil)
1589                         return err;
1590                 if((err = loadfirmware1(ctlr, 0x00800000, fw->main.data.data, fw->main.data.size)) != nil)
1591                         return err;
1592                 csr32w(ctlr, Reset, 0);
1593                 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1594                         return "main firmware boot failed";
1595                 return postboot(ctlr);
1596         }
1597
1598         size = ROUND(fw->init.data.size, 16) + ROUND(fw->init.text.size, 16);
1599         dma = mallocalign(size, 16, 0, 0);
1600         if(dma == nil)
1601                 return "no memory for dma";
1602
1603         if((err = niclock(ctlr)) != nil){
1604                 free(dma);
1605                 return err;
1606         }
1607
1608         p = dma;
1609         memmove(p, fw->init.data.data, fw->init.data.size);
1610         coherence();
1611         prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1612         prphwrite(ctlr, BsmDramDataSize, fw->init.data.size);
1613         p += ROUND(fw->init.data.size, 16);
1614         memmove(p, fw->init.text.data, fw->init.text.size);
1615         coherence();
1616         prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1617         prphwrite(ctlr, BsmDramTextSize, fw->init.text.size);
1618
1619         nicunlock(ctlr);
1620         if((err = niclock(ctlr)) != nil){
1621                 free(dma);
1622                 return err;
1623         }
1624
1625         p = fw->boot.text.data;
1626         n = fw->boot.text.size/4;
1627         for(i=0; i<n; i++, p += 4)
1628                 prphwrite(ctlr, BsmSramBase+i*4, get32(p));
1629
1630         prphwrite(ctlr, BsmWrMemSrc, 0);
1631         prphwrite(ctlr, BsmWrMemDst, 0);
1632         prphwrite(ctlr, BsmWrDwCount, n);
1633
1634         prphwrite(ctlr, BsmWrCtrl, 1<<31);
1635
1636         for(i=0; i<1000; i++){
1637                 if((prphread(ctlr, BsmWrCtrl) & (1<<31)) == 0)
1638                         break;
1639                 delay(10);
1640         }
1641         if(i == 1000){
1642                 nicunlock(ctlr);
1643                 free(dma);
1644                 return "bootcode timeout";
1645         }
1646
1647         prphwrite(ctlr, BsmWrCtrl, 1<<30);
1648         nicunlock(ctlr);
1649
1650         csr32w(ctlr, Reset, 0);
1651         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1652                 free(dma);
1653                 return "init firmware boot failed";
1654         }
1655         free(dma);
1656
1657         size = ROUND(fw->main.data.size, 16) + ROUND(fw->main.text.size, 16);
1658         dma = mallocalign(size, 16, 0, 0);
1659         if(dma == nil)
1660                 return "no memory for dma";
1661         if((err = niclock(ctlr)) != nil){
1662                 free(dma);
1663                 return err;
1664         }
1665         p = dma;
1666         memmove(p, fw->main.data.data, fw->main.data.size);
1667         coherence();
1668         prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1669         prphwrite(ctlr, BsmDramDataSize, fw->main.data.size);
1670         p += ROUND(fw->main.data.size, 16);
1671         memmove(p, fw->main.text.data, fw->main.text.size);
1672         coherence();
1673         prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1674         prphwrite(ctlr, BsmDramTextSize, fw->main.text.size | (1<<31));
1675         nicunlock(ctlr);
1676
1677         if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1678                 free(dma);
1679                 return "main firmware boot failed";
1680         }
1681         free(dma);
1682         return postboot(ctlr);
1683 }
1684
1685 static int
1686 txqready(void *arg)
1687 {
1688         TXQ *q = arg;
1689         return q->n < Ntxqmax;
1690 }
1691
1692 static char*
1693 qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block)
1694 {
1695         uchar *d, *c;
1696         TXQ *q;
1697
1698         assert(qid < nelem(ctlr->tx));
1699         assert(size <= Tcmdsize-4);
1700
1701         ilock(ctlr);
1702         q = &ctlr->tx[qid];
1703         while(q->n >= Ntxqmax && !ctlr->broken){
1704                 iunlock(ctlr);
1705                 qlock(q);
1706                 if(!waserror()){
1707                         tsleep(q, txqready, q, 5);
1708                         poperror();
1709                 }
1710                 qunlock(q);
1711                 ilock(ctlr);
1712         }
1713         if(ctlr->broken){
1714                 iunlock(ctlr);
1715                 return "qcmd: broken";
1716         }
1717         q->n++;
1718
1719         q->lastcmd = code;
1720         q->b[q->i] = block;
1721         c = q->c + q->i * Tcmdsize;
1722         d = q->d + q->i * Tdscsize;
1723
1724         /* build command */
1725         c[0] = code;
1726         c[1] = 0;       /* flags */
1727         c[2] = q->i;
1728         c[3] = qid;
1729
1730         if(size > 0)
1731                 memmove(c+4, data, size);
1732
1733         size += 4;
1734
1735         /* build descriptor */
1736         *d++ = 0;
1737         *d++ = 0;
1738         *d++ = 0;
1739         *d++ = 1 + (block != nil); /* nsegs */
1740         put32(d, PCIWADDR(c));  d += 4;
1741         put16(d, size << 4); d += 2;
1742         if(block != nil){
1743                 size = BLEN(block);
1744                 put32(d, PCIWADDR(block->rp)); d += 4;
1745                 put16(d, size << 4);
1746         }
1747
1748         coherence();
1749
1750         q->i = (q->i+1) % Ntx;
1751         csr32w(ctlr, HbusTargWptr, (qid<<8) | q->i);
1752
1753         iunlock(ctlr);
1754
1755         return nil;
1756 }
1757
1758 static int
1759 txqempty(void *arg)
1760 {
1761         TXQ *q = arg;
1762         return q->n == 0;
1763 }
1764
1765 static char*
1766 flushq(Ctlr *ctlr, uint qid)
1767 {
1768         TXQ *q;
1769         int i;
1770
1771         q = &ctlr->tx[qid];
1772         qlock(q);
1773         for(i = 0; i < 200 && !ctlr->broken; i++){
1774                 if(txqempty(q)){
1775                         qunlock(q);
1776                         return nil;
1777                 }
1778                 if(!waserror()){
1779                         tsleep(q, txqempty, q, 10);
1780                         poperror();
1781                 }
1782         }
1783         qunlock(q);
1784         if(ctlr->broken)
1785                 return "flushq: broken";
1786         return "flushq: timeout";
1787 }
1788
1789 static char*
1790 cmd(Ctlr *ctlr, uint code, uchar *data, int size)
1791 {
1792         char *err;
1793
1794         if(0) print("cmd %ud\n", code);
1795         if((err = qcmd(ctlr, 4, code, data, size, nil)) != nil)
1796                 return err;
1797         return flushq(ctlr, 4);
1798 }
1799
1800 static void
1801 setled(Ctlr *ctlr, int which, int on, int off)
1802 {
1803         uchar c[8];
1804
1805         csr32w(ctlr, Led, csr32r(ctlr, Led) & ~LedBsmCtrl);
1806
1807         memset(c, 0, sizeof(c));
1808         put32(c, 10000);
1809         c[4] = which;
1810         c[5] = on;
1811         c[6] = off;
1812         cmd(ctlr, 72, c, sizeof(c));
1813 }
1814
1815 static void
1816 addnode(Ctlr *ctlr, uchar id, uchar *addr)
1817 {
1818         uchar c[Tcmdsize], *p;
1819
1820         memset(p = c, 0, sizeof(c));
1821         *p++ = 0;       /* control (1 = update) */
1822         p += 3;         /* reserved */
1823         memmove(p, addr, 6);
1824         p += 6;
1825         p += 2;         /* reserved */
1826         *p++ = id;      /* node id */
1827         p++;            /* flags */
1828         p += 2;         /* reserved */
1829         p += 2;         /* kflags */
1830         p++;            /* tcs2 */
1831         p++;            /* reserved */
1832         p += 5*2;       /* ttak */
1833         p++;            /* kid */
1834         p++;            /* reserved */
1835         p += 16;        /* key */
1836         if(ctlr->type != Type4965){
1837                 p += 8;         /* tcs */
1838                 p += 8;         /* rxmic */
1839                 p += 8;         /* txmic */
1840         }
1841         p += 4;         /* htflags */
1842         p += 4;         /* mask */
1843         p += 2;         /* disable tid */
1844         p += 2;         /* reserved */
1845         p++;            /* add ba tid */
1846         p++;            /* del ba tid */
1847         p += 2;         /* add ba ssn */
1848         p += 4;         /* reserved */
1849         cmd(ctlr, 24, c, p - c);
1850 }
1851
1852 static void
1853 rxon(Ether *edev, Wnode *bss)
1854 {
1855         uchar c[Tcmdsize], *p;
1856         int filter, flags;
1857         Ctlr *ctlr;
1858         char *err;
1859
1860         ctlr = edev->ctlr;
1861         filter = FilterNoDecrypt | FilterMulticast | FilterBeacon;
1862         if(ctlr->prom){
1863                 filter |= FilterPromisc;
1864                 if(bss != nil)
1865                         ctlr->channel = bss->channel;
1866                 bss = nil;
1867         }
1868         flags = RFlagTSF | RFlagCTSToSelf | RFlag24Ghz | RFlagAuto;
1869         if(bss != nil){
1870                 if(bss->cap & (1<<5))
1871                         flags |= RFlagShPreamble;
1872                 if(bss->cap & (1<<10))
1873                         flags |= RFlagShSlot;
1874                 ctlr->channel = bss->channel;
1875                 memmove(ctlr->bssid, bss->bssid, Eaddrlen);
1876                 ctlr->aid = bss->aid;
1877                 if(ctlr->aid != 0){
1878                         filter |= FilterBSS;
1879                         filter &= ~FilterBeacon;
1880                         ctlr->bssnodeid = -1;
1881                 } else
1882                         ctlr->bcastnodeid = -1;
1883         } else {
1884                 memmove(ctlr->bssid, edev->bcast, Eaddrlen);
1885                 ctlr->aid = 0;
1886                 ctlr->bcastnodeid = -1;
1887                 ctlr->bssnodeid = -1;
1888         }
1889
1890         if(ctlr->aid != 0)
1891                 setled(ctlr, 2, 0, 1);          /* on when associated */
1892         else if(memcmp(ctlr->bssid, edev->bcast, Eaddrlen) != 0)
1893                 setled(ctlr, 2, 10, 10);        /* slow blink when connecting */
1894         else
1895                 setled(ctlr, 2, 5, 5);          /* fast blink when scanning */
1896
1897         if(ctlr->wifi->debug)
1898                 print("#l%d: rxon: bssid %E, aid %x, channel %d, filter %x, flags %x\n",
1899                         edev->ctlrno, ctlr->bssid, ctlr->aid, ctlr->channel, filter, flags);
1900
1901         memset(p = c, 0, sizeof(c));
1902         memmove(p, edev->ea, 6); p += 8;        /* myaddr */
1903         memmove(p, ctlr->bssid, 6); p += 8;     /* bssid */
1904         memmove(p, edev->ea, 6); p += 8;        /* wlap */
1905         *p++ = 3;                               /* mode (STA) */
1906         *p++ = 0;                               /* air (?) */
1907         /* rxchain */
1908         put16(p, ((ctlr->rfcfg.rxantmask & 7)<<1) | (2<<10) | (2<<12));
1909         p += 2;
1910         *p++ = 0xff;                            /* ofdm mask (not yet negotiated) */
1911         *p++ = 0x0f;                            /* cck mask (not yet negotiated) */
1912         put16(p, ctlr->aid & 0x3fff);
1913         p += 2;                                 /* aid */
1914         put32(p, flags);
1915         p += 4;
1916         put32(p, filter);
1917         p += 4;
1918         *p++ = ctlr->channel;
1919         p++;                                    /* reserved */
1920         *p++ = 0xff;                            /* ht single mask */
1921         *p++ = 0xff;                            /* ht dual mask */
1922         if(ctlr->type != Type4965){
1923                 *p++ = 0xff;                    /* ht triple mask */
1924                 p++;                            /* reserved */
1925                 put16(p, 0); p += 2;            /* acquisition */
1926                 p += 2;                         /* reserved */
1927         }
1928         if((err = cmd(ctlr, 16, c, p - c)) != nil){
1929                 print("rxon: %s\n", err);
1930                 return;
1931         }
1932
1933         if(ctlr->bcastnodeid == -1){
1934                 ctlr->bcastnodeid = (ctlr->type != Type4965) ? 15 : 31;
1935                 addnode(ctlr, ctlr->bcastnodeid, edev->bcast);
1936         }
1937         if(ctlr->bssnodeid == -1 && bss != nil && ctlr->aid != 0){
1938                 ctlr->bssnodeid = 0;
1939                 addnode(ctlr, ctlr->bssnodeid, bss->bssid);
1940         }
1941 }
1942
1943 static struct ratetab {
1944         uchar   rate;
1945         uchar   plcp;
1946         uchar   flags;
1947 } ratetab[] = {
1948         {   2,  10, RFlagCCK },
1949         {   4,  20, RFlagCCK },
1950         {  11,  55, RFlagCCK },
1951         {  22, 110, RFlagCCK },
1952
1953         {  12, 0xd, 0 },
1954         {  18, 0xf, 0 },
1955         {  24, 0x5, 0 },
1956         {  36, 0x7, 0 },
1957         {  48, 0x9, 0 },
1958         {  72, 0xb, 0 },
1959         {  96, 0x1, 0 },
1960         { 108, 0x3, 0 },
1961         { 120, 0x3, 0 }
1962 };
1963
1964 static uchar iwlrates[] = {
1965         0x80 | 2,
1966         0x80 | 4,
1967         0x80 | 11,
1968         0x80 | 22,
1969
1970         0x80 | 12,
1971         0x80 | 18,
1972         0x80 | 24,
1973         0x80 | 36,
1974         0x80 | 48,
1975         0x80 | 72,
1976         0x80 | 96,
1977         0x80 | 108,
1978         0x80 | 120,
1979
1980         0
1981 };
1982
1983 enum {
1984         TFlagNeedProtection     = 1<<0,
1985         TFlagNeedRTS            = 1<<1,
1986         TFlagNeedCTS            = 1<<2,
1987         TFlagNeedACK            = 1<<3,
1988         TFlagLinkq              = 1<<4,
1989         TFlagImmBa              = 1<<6,
1990         TFlagFullTxOp           = 1<<7,
1991         TFlagBtDis              = 1<<12,
1992         TFlagAutoSeq            = 1<<13,
1993         TFlagMoreFrag           = 1<<14,
1994         TFlagInsertTs           = 1<<16,
1995         TFlagNeedPadding        = 1<<20,
1996 };
1997
1998 static void
1999 transmit(Wifi *wifi, Wnode *wn, Block *b)
2000 {
2001         int flags, nodeid, rate, ant;
2002         uchar c[Tcmdsize], *p;
2003         Ether *edev;
2004         Ctlr *ctlr;
2005         Wifipkt *w;
2006         char *err;
2007
2008         edev = wifi->ether;
2009         ctlr = edev->ctlr;
2010
2011         qlock(ctlr);
2012         if(ctlr->attached == 0 || ctlr->broken){
2013                 qunlock(ctlr);
2014                 freeb(b);
2015                 return;
2016         }
2017
2018         if((wn->channel != ctlr->channel)
2019         || (!ctlr->prom && (wn->aid != ctlr->aid || memcmp(wn->bssid, ctlr->bssid, Eaddrlen) != 0)))
2020                 rxon(edev, wn);
2021
2022         if(b == nil){
2023                 /* association note has no data to transmit */
2024                 qunlock(ctlr);
2025                 return;
2026         }
2027
2028         flags = 0;
2029         nodeid = ctlr->bcastnodeid;
2030         p = wn->minrate;
2031         w = (Wifipkt*)b->rp;
2032         if((w->a1[0] & 1) == 0){
2033                 flags |= TFlagNeedACK;
2034
2035                 if(BLEN(b) > 512-4)
2036                         flags |= TFlagNeedRTS;
2037
2038                 if((w->fc[0] & 0x0c) == 0x08 && ctlr->bssnodeid != -1){
2039                         nodeid = ctlr->bssnodeid;
2040                         p = wn->actrate;
2041                 }
2042
2043                 if(flags & (TFlagNeedRTS|TFlagNeedCTS)){
2044                         if(ctlr->type != Type4965){
2045                                 flags &= ~(TFlagNeedRTS|TFlagNeedCTS);
2046                                 flags |= TFlagNeedProtection;
2047                         } else
2048                                 flags |= TFlagFullTxOp;
2049                 }
2050         }
2051         if(p >= wifi->rates)
2052                 rate = p - wifi->rates;
2053         else
2054                 rate = 0;
2055         qunlock(ctlr);
2056
2057         /* select first available antenna */
2058         ant = ctlr->rfcfg.txantmask & 7;
2059         ant |= (ant == 0);
2060         ant = ((ant - 1) & ant) ^ ant;
2061
2062         memset(p = c, 0, sizeof(c));
2063         put16(p, BLEN(b));
2064         p += 2;
2065         p += 2;         /* lnext */
2066         put32(p, flags);
2067         p += 4;
2068         put32(p, 0);
2069         p += 4;         /* scratch */
2070
2071         *p++ = ratetab[rate].plcp;
2072         *p++ = ratetab[rate].flags | (ant<<6);
2073
2074         p += 2;         /* xflags */
2075         *p++ = nodeid;
2076         *p++ = 0;       /* security */
2077         *p++ = 0;       /* linkq */
2078         p++;            /* reserved */
2079         p += 16;        /* key */
2080         p += 2;         /* fnext */
2081         p += 2;         /* reserved */
2082         put32(p, ~0);   /* lifetime */
2083         p += 4;
2084
2085         /* BUG: scratch ptr? not clear what this is for */
2086         put32(p, PCIWADDR(ctlr->kwpage));
2087         p += 5;
2088
2089         *p++ = 60;      /* rts ntries */
2090         *p++ = 15;      /* data ntries */
2091         *p++ = 0;       /* tid */
2092         put16(p, 0);    /* timeout */
2093         p += 2;
2094         p += 2;         /* txop */
2095         if((err = qcmd(ctlr, 0, 28, c, p - c, b)) != nil){
2096                 print("transmit: %s\n", err);
2097                 freeb(b);
2098         }
2099 }
2100
2101 static long
2102 iwlctl(Ether *edev, void *buf, long n)
2103 {
2104         Ctlr *ctlr;
2105
2106         ctlr = edev->ctlr;
2107         if(n >= 5 && memcmp(buf, "reset", 5) == 0){
2108                 ctlr->broken = 1;
2109                 return n;
2110         }
2111         if(ctlr->wifi)
2112                 return wifictl(ctlr->wifi, buf, n);
2113         return 0;
2114 }
2115
2116 static long
2117 iwlifstat(Ether *edev, void *buf, long n, ulong off)
2118 {
2119         Ctlr *ctlr;
2120
2121         ctlr = edev->ctlr;
2122         if(ctlr->wifi)
2123                 return wifistat(ctlr->wifi, buf, n, off);
2124         return 0;
2125 }
2126
2127 static void
2128 setoptions(Ether *edev)
2129 {
2130         Ctlr *ctlr;
2131         int i;
2132
2133         ctlr = edev->ctlr;
2134         for(i = 0; i < edev->nopt; i++)
2135                 wificfg(ctlr->wifi, edev->opt[i]);
2136 }
2137
2138 static void
2139 iwlpromiscuous(void *arg, int on)
2140 {
2141         Ether *edev;
2142         Ctlr *ctlr;
2143
2144         edev = arg;
2145         ctlr = edev->ctlr;
2146         qlock(ctlr);
2147         ctlr->prom = on;
2148         rxon(edev, ctlr->wifi->bss);
2149         qunlock(ctlr);
2150 }
2151
2152 static void
2153 iwlmulticast(void *, uchar*, int)
2154 {
2155 }
2156
2157 static void
2158 iwlrecover(void *arg)
2159 {
2160         Ether *edev;
2161         Ctlr *ctlr;
2162
2163         edev = arg;
2164         ctlr = edev->ctlr;
2165         while(waserror())
2166                 ;
2167         for(;;){
2168                 tsleep(&up->sleep, return0, 0, 4000);
2169
2170                 qlock(ctlr);
2171                 for(;;){
2172                         if(ctlr->broken == 0)
2173                                 break;
2174
2175                         if(ctlr->power)
2176                                 poweroff(ctlr);
2177
2178                         if((csr32r(ctlr, Gpc) & RfKill) == 0)
2179                                 break;
2180
2181                         if(reset(ctlr) != nil)
2182                                 break;
2183                         if(boot(ctlr) != nil)
2184                                 break;
2185
2186                         ctlr->bcastnodeid = -1;
2187                         ctlr->bssnodeid = -1;
2188                         ctlr->aid = 0;
2189                         rxon(edev, ctlr->wifi->bss);
2190                         break;
2191                 }
2192                 qunlock(ctlr);
2193         }
2194 }
2195
2196 static void
2197 iwlattach(Ether *edev)
2198 {
2199         FWImage *fw;
2200         Ctlr *ctlr;
2201         char *err;
2202
2203         ctlr = edev->ctlr;
2204         eqlock(ctlr);
2205         if(waserror()){
2206                 print("#l%d: %s\n", edev->ctlrno, up->errstr);
2207                 if(ctlr->power)
2208                         poweroff(ctlr);
2209                 qunlock(ctlr);
2210                 nexterror();
2211         }
2212         if(ctlr->attached == 0){
2213                 if((csr32r(ctlr, Gpc) & RfKill) == 0)
2214                         error("wifi disabled by switch");
2215
2216                 if(ctlr->wifi == nil){
2217                         qsetlimit(edev->oq, MaxQueue);
2218
2219                         ctlr->wifi = wifiattach(edev, transmit);
2220                         /* tested with 2230, it has transmit issues using higher bit rates */
2221                         if(ctlr->type != Type2030)
2222                                 ctlr->wifi->rates = iwlrates;
2223                 }
2224
2225                 if(ctlr->fw == nil){
2226                         char *fn = fwname[ctlr->type];
2227                         if(ctlr->type == Type6005){
2228                                 switch(ctlr->pdev->did){
2229                                 case 0x0082:    /* Centrino Advanced-N 6205 */
2230                                 case 0x0085:    /* Centrino Advanced-N 6205 */
2231                                         break;
2232                                 default:        /* Centrino Advanced-N 6030, 6235 */
2233                                         fn = "iwn-6030";
2234                                 }
2235                         }
2236                         fw = readfirmware(fn);
2237                         print("#l%d: firmware: %s, rev %ux, build %ud, size %ux+%ux+%ux+%ux+%ux\n",
2238                                 edev->ctlrno, fn,
2239                                 fw->rev, fw->build,
2240                                 fw->main.text.size, fw->main.data.size,
2241                                 fw->init.text.size, fw->init.data.size,
2242                                 fw->boot.text.size);
2243                         ctlr->fw = fw;
2244                 }
2245
2246                 if((err = reset(ctlr)) != nil)
2247                         error(err);
2248                 if((err = boot(ctlr)) != nil)
2249                         error(err);
2250
2251                 ctlr->bcastnodeid = -1;
2252                 ctlr->bssnodeid = -1;
2253                 ctlr->channel = 1;
2254                 ctlr->aid = 0;
2255
2256                 setoptions(edev);
2257
2258                 ctlr->attached = 1;
2259
2260                 kproc("iwlrecover", iwlrecover, edev);
2261         }
2262         qunlock(ctlr);
2263         poperror();
2264 }
2265
2266 static void
2267 receive(Ctlr *ctlr)
2268 {
2269         Block *b, *bb;
2270         uchar *d;
2271         RXQ *rx;
2272         TXQ *tx;
2273         uint hw;
2274
2275         rx = &ctlr->rx;
2276         if(ctlr->broken || rx->s == nil || rx->b == nil)
2277                 return;
2278
2279         bb = nil;
2280         for(hw = get16(rx->s) % Nrx; rx->i != hw; rx->i = (rx->i + 1) % Nrx){
2281                 uchar type, flags, idx, qid;
2282                 u32int len;
2283
2284                 b = rx->b[rx->i];
2285                 if(b == nil)
2286                         continue;
2287
2288                 d = b->rp;
2289                 len = get32(d); d += 4;
2290                 type = *d++;
2291                 flags = *d++;
2292                 USED(flags);
2293                 idx = *d++;
2294                 qid = *d++;
2295
2296                 if(bb != nil){
2297                         freeb(bb);
2298                         bb = nil;
2299                 }
2300                 if((qid & 0x80) == 0 && qid < nelem(ctlr->tx)){
2301                         tx = &ctlr->tx[qid];
2302                         if(tx->n > 0){
2303                                 bb = tx->b[idx];
2304                                 tx->b[idx] = nil;
2305                                 tx->n--;
2306
2307                                 wakeup(tx);
2308                         }
2309                 }
2310
2311                 len &= 0x3fff;
2312                 if(len < 4 || type == 0)
2313                         continue;
2314
2315                 len -= 4;
2316                 switch(type){
2317                 case 1:         /* microcontroller ready */
2318                         setfwinfo(ctlr, d, len);
2319                         break;
2320                 case 24:        /* add node done */
2321                         break;
2322                 case 28:        /* tx done */
2323                         if(ctlr->type == Type4965){
2324                                 if(len <= 20 || d[20] == 1 || d[20] == 2)
2325                                         break;
2326                         } else {
2327                                 if(len <= 32 || d[32] == 1 || d[32] == 2)
2328                                         break;
2329                         }
2330                         wifitxfail(ctlr->wifi, bb);
2331                         break;
2332                 case 102:       /* calibration result (Type5000 only) */
2333                         if(len < 4)
2334                                 break;
2335                         idx = d[0];
2336                         if(idx >= nelem(ctlr->calib.cmd))
2337                                 break;
2338                         if(rbplant(ctlr, rx->i) < 0)
2339                                 break;
2340                         if(ctlr->calib.cmd[idx] != nil)
2341                                 freeb(ctlr->calib.cmd[idx]);
2342                         b->rp = d;
2343                         b->wp = d + len;
2344                         ctlr->calib.cmd[idx] = b;
2345                         continue;
2346                 case 103:       /* calibration done (Type5000 only) */
2347                         ctlr->calib.done = 1;
2348                         break;
2349                 case 130:       /* start scan */
2350                         break;
2351                 case 132:       /* stop scan */
2352                         break;
2353                 case 156:       /* rx statistics */
2354                         break;
2355                 case 157:       /* beacon statistics */
2356                         break;
2357                 case 161:       /* state changed */
2358                         break;
2359                 case 162:       /* beacon missed */
2360                         break;
2361                 case 192:       /* rx phy */
2362                         break;
2363                 case 195:       /* rx done */
2364                         if(d + 2 > b->lim)
2365                                 break;
2366                         d += d[1];
2367                         d += 56;
2368                 case 193:       /* mpdu rx done */
2369                         if(d + 4 > b->lim)
2370                                 break;
2371                         len = get16(d); d += 4;
2372                         if(d + len + 4 > b->lim)
2373                                 break;
2374                         if((get32(d + len) & 3) != 3)
2375                                 break;
2376                         if(ctlr->wifi == nil)
2377                                 break;
2378                         if(rbplant(ctlr, rx->i) < 0)
2379                                 break;
2380                         b->rp = d;
2381                         b->wp = d + len;
2382                         wifiiq(ctlr->wifi, b);
2383                         continue;
2384                 case 197:       /* rx compressed ba */
2385                         break;
2386                 }
2387         }
2388         csr32w(ctlr, FhRxWptr, ((hw+Nrx-1) % Nrx) & ~7);
2389         if(bb != nil)
2390                 freeb(bb);
2391 }
2392
2393 static void
2394 iwlinterrupt(Ureg*, void *arg)
2395 {
2396         u32int isr, fhisr;
2397         Ether *edev;
2398         Ctlr *ctlr;
2399
2400         edev = arg;
2401         ctlr = edev->ctlr;
2402         ilock(ctlr);
2403         csr32w(ctlr, Imr, 0);
2404         isr = csr32r(ctlr, Isr);
2405         fhisr = csr32r(ctlr, FhIsr);
2406         if(isr == 0xffffffff || (isr & 0xfffffff0) == 0xa5a5a5a0){
2407                 iunlock(ctlr);
2408                 return;
2409         }
2410         if(isr == 0 && fhisr == 0)
2411                 goto done;
2412         csr32w(ctlr, Isr, isr);
2413         csr32w(ctlr, FhIsr, fhisr);
2414         if((isr & (Iswrx | Ifhrx | Irxperiodic)) || (fhisr & Ifhrx))
2415                 receive(ctlr);
2416         if(isr & Ierr){
2417                 ctlr->broken = 1;
2418                 print("#l%d: fatal firmware error\n", edev->ctlrno);
2419                 dumpctlr(ctlr);
2420         }
2421         ctlr->wait.m |= isr;
2422         if(ctlr->wait.m & ctlr->wait.w)
2423                 wakeup(&ctlr->wait);
2424 done:
2425         csr32w(ctlr, Imr, ctlr->ie);
2426         iunlock(ctlr);
2427 }
2428
2429 static void
2430 iwlshutdown(Ether *edev)
2431 {
2432         Ctlr *ctlr;
2433
2434         ctlr = edev->ctlr;
2435         if(ctlr->power)
2436                 poweroff(ctlr);
2437         ctlr->broken = 0;
2438 }
2439
2440 static Ctlr *iwlhead, *iwltail;
2441
2442 static void
2443 iwlpci(void)
2444 {
2445         Pcidev *pdev;
2446
2447         pdev = nil;
2448         while(pdev = pcimatch(pdev, 0, 0)) {
2449                 Ctlr *ctlr;
2450                 void *mem;
2451
2452                 if(pdev->ccrb != 2 || pdev->ccru != 0x80)
2453                         continue;
2454                 if(pdev->vid != 0x8086)
2455                         continue;
2456
2457                 switch(pdev->did){
2458                 default:
2459                         continue;
2460                 case 0x0084:    /* WiFi Link 1000 */
2461                 case 0x4229:    /* WiFi Link 4965 */
2462                 case 0x4230:    /* WiFi Link 4965 */
2463                 case 0x4232:    /* Wifi Link 5100 */
2464                 case 0x4235:    /* Intel Corporation Ultimate N WiFi Link 5300 */
2465                 case 0x4236:    /* WiFi Link 5300 AGN */
2466                 case 0x4237:    /* Wifi Link 5100 AGN */
2467                 case 0x4239:    /* Centrino Advanced-N 6200 */
2468                 case 0x423d:    /* Wifi Link 5150 */
2469                 case 0x423b:    /* PRO/Wireless 5350 AGN */
2470                 case 0x0082:    /* Centrino Advanced-N 6205 */
2471                 case 0x0085:    /* Centrino Advanced-N 6205 */
2472                 case 0x422b:    /* Centrino Ultimate-N 6300 variant 1 */
2473                 case 0x4238:    /* Centrino Ultimate-N 6300 variant 2 */
2474                 case 0x08ae:    /* Centrino Wireless-N 100 */
2475                 case 0x0083:    /* Centrino Wireless-N 1000 */
2476                 case 0x0887:    /* Centrino Wireless-N 2230 */
2477                 case 0x0888:    /* Centrino Wireless-N 2230 */
2478                 case 0x0090:    /* Centrino Advanced-N 6030 */
2479                 case 0x0091:    /* Centrino Advanced-N 6030 */
2480                 case 0x088e:    /* Centrino Advanced-N 6235 */
2481                 case 0x088f:    /* Centrino Advanced-N 6235 */
2482                         break;
2483                 }
2484
2485                 ctlr = malloc(sizeof(Ctlr));
2486                 if(ctlr == nil) {
2487                         print("iwl: unable to alloc Ctlr\n");
2488                         continue;
2489                 }
2490                 ctlr->port = pdev->mem[0].bar & ~0x0F;
2491                 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
2492                 if(mem == nil) {
2493                         print("iwl: can't map %8.8luX\n", pdev->mem[0].bar);
2494                         free(ctlr);
2495                         continue;
2496                 }
2497                 ctlr->nic = mem;
2498                 ctlr->pdev = pdev;
2499
2500                 if(iwlhead != nil)
2501                         iwltail->link = ctlr;
2502                 else
2503                         iwlhead = ctlr;
2504                 iwltail = ctlr;
2505         }
2506 }
2507
2508 static int
2509 iwlpnp(Ether* edev)
2510 {
2511         Ctlr *ctlr;
2512
2513         if(iwlhead == nil)
2514                 iwlpci();
2515 again:
2516         for(ctlr = iwlhead; ctlr != nil; ctlr = ctlr->link){
2517                 if(ctlr->active)
2518                         continue;
2519                 if(edev->port == 0 || edev->port == ctlr->port){
2520                         ctlr->active = 1;
2521                         break;
2522                 }
2523         }
2524
2525         if(ctlr == nil)
2526                 return -1;
2527
2528         edev->ctlr = ctlr;
2529         edev->port = ctlr->port;
2530         edev->irq = ctlr->pdev->intl;
2531         edev->tbdf = ctlr->pdev->tbdf;
2532         edev->arg = edev;
2533         edev->attach = iwlattach;
2534         edev->ifstat = iwlifstat;
2535         edev->ctl = iwlctl;
2536         edev->shutdown = iwlshutdown;
2537         edev->promiscuous = iwlpromiscuous;
2538         edev->multicast = iwlmulticast;
2539         edev->mbps = 54;
2540
2541         pcienable(ctlr->pdev);
2542         if(iwlinit(edev) < 0){
2543                 pcidisable(ctlr->pdev);
2544                 edev->ctlr = nil;
2545                 goto again;
2546         }
2547
2548         pcisetbme(ctlr->pdev);
2549         intrenable(edev->irq, iwlinterrupt, edev, edev->tbdf, edev->name);
2550
2551         return 0;
2552 }
2553
2554 void
2555 etheriwllink(void)
2556 {
2557         addethercard("iwl", iwlpnp);
2558 }