2 * Intel WiFi Link driver.
4 * Written without any documentation but Damien Bergaminis
5 * OpenBSD iwn(4) driver sources. Requires intel firmware
6 * to be present in /lib/firmware/iwn-* on attach.
10 #include "../port/lib.h"
15 #include "../port/error.h"
16 #include "../port/netif.h"
38 Cfg = 0x000, /* config register */
47 Isr = 0x008, /* interrupt status */
48 Imr = 0x00c, /* interrupt mask */
61 Ierr = Iswerr | Ihwerr,
62 Idefmask = Ierr | Ifhtx | Ifhrx | Ialive | Iwakeup | Iswrx | Ictreached | Irftoggled,
64 FhIsr = 0x010, /* second interrupt status */
68 Rev = 0x028, /* hardware revision */
70 EepromIo = 0x02c, /* EEPROM i/o register */
75 RelativeAccess = 1<<17,
77 EccUncorrStts = 1<<21,
79 Gpc = 0x024, /* gp cntrl */
100 UcodeGp1RfKill = 1<<1,
101 UcodeGp1CmdBlocked = 1<<2,
102 UcodeGp1CtempStopRf = 1<<3,
104 ShadowRegCtrl = 0x0a8,
113 Dbglinkpwrmgmt = 0x250,
125 HbusTargWptr = 0x460,
129 * Flow-Handler registers.
132 FhTfbdCtrl0 = 0x1900, // +q*8
133 FhTfbdCtrl1 = 0x1904, // +q*8
137 FhSramAddr = 0x19a4, // +q*4
138 FhCbbcQueue = 0x19d0, // +q*4
139 FhStatusWptr = 0x1bc0,
143 FhRxConfigEna = 1<<31,
144 FhRxConfigRbSize8K = 1<<16,
145 FhRxConfigSingleFrame = 1<<15,
146 FhRxConfigIrqDstHost = 1<<12,
147 FhRxConfigIgnRxfEmpty = 1<<2,
149 FhRxConfigNrbdShift = 20,
150 FhRxConfigRbTimeoutShift= 4,
154 FhTxConfig = 0x1d00, // +q*32
155 FhTxConfigDmaCreditEna = 1<<3,
156 FhTxConfigDmaEna = 1<<31,
157 FhTxConfigCirqHostEndTfd= 1<<20,
159 FhTxBufStatus = 0x1d08, // +q*32
160 FhTxBufStatusTbNumShift = 20,
161 FhTxBufStatusTbIdxShift = 12,
162 FhTxBufStatusTfbdValid = 3,
164 FhTxChicken = 0x1e98,
169 * NIC internal memory offsets.
172 ApmgClkCtrl = 0x3000,
179 EarlyPwroffDis = 1<<22,
185 ApmgDigitalSvr = 0x3058,
186 ApmgAnalogSvr = 0x306c,
189 BsmWrMemSrc = 0x3404,
190 BsmWrMemDst = 0x3408,
191 BsmWrDwCount = 0x340c,
192 BsmDramTextAddr = 0x3490,
193 BsmDramTextSize = 0x3494,
194 BsmDramDataAddr = 0x3498,
195 BsmDramDataSize = 0x349c,
196 BsmSramBase = 0x3800,
200 * TX scheduler registers.
203 SchedBase = 0xa02c00,
204 SchedSramAddr = SchedBase,
206 SchedDramAddr4965 = SchedBase+0x010,
207 SchedTxFact4965 = SchedBase+0x01c,
208 SchedQueueRdptr4965 = SchedBase+0x064, // +q*4
209 SchedQChainSel4965 = SchedBase+0x0d0,
210 SchedIntrMask4965 = SchedBase+0x0e4,
211 SchedQueueStatus4965 = SchedBase+0x104, // +q*4
213 SchedDramAddr5000 = SchedBase+0x008,
214 SchedTxFact5000 = SchedBase+0x010,
215 SchedQueueRdptr5000 = SchedBase+0x068, // +q*4
216 SchedQChainSel5000 = SchedBase+0x0e8,
217 SchedIntrMask5000 = SchedBase+0x108,
218 SchedQueueStatus5000 = SchedBase+0x10c, // +q*4
219 SchedAggrSel5000 = SchedBase+0x248,
223 SchedCtxOff4965 = 0x380,
224 SchedCtxLen4965 = 416,
226 SchedCtxOff5000 = 0x600,
227 SchedCtxLen5000 = 512,
231 FilterPromisc = 1<<0,
233 FilterMulticast = 1<<2,
234 FilterNoDecrypt = 1<<3,
244 RFlagShPreamble = 1<<5,
245 RFlagNoDiversity = 1<<7,
246 RFlagAntennaA = 1<<8,
247 RFlagAntennaB = 1<<9,
249 RFlagCTSToSelf = 1<<30,
252 typedef struct FWInfo FWInfo;
253 typedef struct FWImage FWImage;
254 typedef struct FWSect FWSect;
256 typedef struct TXQ TXQ;
257 typedef struct RXQ RXQ;
259 typedef struct Ctlr Ctlr;
335 /* assigned node ids in hardware node table or -1 if unassigned */
339 /* current receiver settings */
340 uchar bssid[Eaddrlen];
390 /* controller types */
403 static char *fwname[16] = {
404 [Type4965] "iwn-4965",
405 [Type5300] "iwn-5000",
406 [Type5350] "iwn-5000",
407 [Type5150] "iwn-5150",
408 [Type5100] "iwn-5000",
409 [Type1000] "iwn-1000",
410 [Type6000] "iwn-6000",
411 [Type6050] "iwn-6050",
412 [Type6005] "iwn-6005",
415 static char *qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block);
416 static char *flushq(Ctlr *ctlr, uint qid);
417 static char *cmd(Ctlr *ctlr, uint code, uchar *data, int size);
419 #define csr32r(c, r) (*((c)->nic+((r)/4)))
420 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
424 return *((u16int*)p);
428 return *((u32int*)p);
431 put32(uchar *p, uint v){
435 put16(uchar *p, uint v){
444 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | MacAccessReq);
445 for(i=0; i<1000; i++){
446 if((csr32r(ctlr, Gpc) & (NicSleep | MacAccessEna)) == MacAccessEna)
450 return "niclock: timeout";
454 nicunlock(Ctlr *ctlr)
456 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~MacAccessReq);
460 prphread(Ctlr *ctlr, uint off)
462 csr32w(ctlr, PrphRaddr, ((sizeof(u32int)-1)<<24) | off);
464 return csr32r(ctlr, PrphRdata);
467 prphwrite(Ctlr *ctlr, uint off, u32int data)
469 csr32w(ctlr, PrphWaddr, ((sizeof(u32int)-1)<<24) | off);
471 csr32w(ctlr, PrphWdata, data);
475 memread(Ctlr *ctlr, uint off)
477 csr32w(ctlr, MemRaddr, off);
479 return csr32r(ctlr, MemRdata);
482 memwrite(Ctlr *ctlr, uint off, u32int data)
484 csr32w(ctlr, MemWaddr, off);
486 csr32w(ctlr, MemWdata, data);
490 setfwinfo(Ctlr *ctlr, uchar *d, int len)
503 i->logptr = get32(d); d += 4;
504 i->errptr = get32(d); d += 4;
505 i->tstamp = get32(d); d += 4;
515 print("lastcmd: %ud (0x%ux)\n", ctlr->tx[4].lastcmd, ctlr->tx[4].lastcmd);
516 if(ctlr->fwinfo.errptr == 0){
517 print("no error pointer\n");
520 for(i=0; i<nelem(dump); i++)
521 dump[i] = memread(ctlr, ctlr->fwinfo.errptr + i*4);
522 print( "error:\tid %ux, pc %ux,\n"
523 "\tbranchlink %.8ux %.8ux, interruptlink %.8ux %.8ux,\n"
524 "\terrordata %.8ux %.8ux, srcline %ud, tsf %ux, time %ux\n",
526 dump[4], dump[3], dump[6], dump[5],
527 dump[7], dump[8], dump[9], dump[10], dump[11]);
531 eepromlock(Ctlr *ctlr)
535 for(i=0; i<100; i++){
536 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | EepromLocked);
537 for(j=0; j<100; j++){
538 if(csr32r(ctlr, Cfg) & EepromLocked)
543 return "eepromlock: timeout";
546 eepromunlock(Ctlr *ctlr)
548 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) & ~EepromLocked);
551 eepromread(Ctlr *ctlr, void *data, int count, uint off)
558 off += ctlr->eeprom.off;
559 for(; count > 0; count -= 2, off++){
560 csr32w(ctlr, EepromIo, off << 2);
562 w = csr32r(ctlr, EepromIo);
568 return "eepromread: timeout";
569 if(ctlr->eeprom.otp){
570 s = csr32r(ctlr, OtpromGp);
571 if(s & EccUncorrStts)
572 return "eepromread: otprom ecc error";
574 csr32w(ctlr, OtpromGp, s);
588 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
590 if(csr32r(ctlr, Cfg) & NicReady)
594 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | Prepare);
595 for(i=0; i<15000; i++){
596 if((csr32r(ctlr, Cfg) & PrepareDone) == 0)
601 return "handover: timeout";
602 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
604 if(csr32r(ctlr, Cfg) & NicReady)
608 return "handover: timeout";
612 clockwait(Ctlr *ctlr)
616 /* Set "initialization complete" bit. */
617 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | InitDone);
618 for(i=0; i<2500; i++){
619 if(csr32r(ctlr, Gpc) & MacClockReady)
623 return "clockwait: timeout";
632 /* Disable L0s exit timer (NMI bug workaround). */
633 csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | DisL0Stimer);
635 /* Don't wait for ICH L0s (ICH bug workaround). */
636 csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | L1AnoL0Srx);
638 /* Set FH wait threshold to max (HW bug under stress workaround). */
639 csr32w(ctlr, Dbghpetmem, csr32r(ctlr, Dbghpetmem) | 0xffff0000);
641 /* Enable HAP INTA to move adapter from L1a to L0s. */
642 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | HapwakeL1A);
644 capoff = pcicap(ctlr->pdev, PciCapPCIe);
646 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
647 if(pcicfgr16(ctlr->pdev, capoff + 0x10) & 0x2) /* LCSR -> L1 Entry enabled. */
648 csr32w(ctlr, Gio, csr32r(ctlr, Gio) | EnaL0S);
650 csr32w(ctlr, Gio, csr32r(ctlr, Gio) & ~EnaL0S);
653 if(ctlr->type != Type4965 && ctlr->type <= Type1000)
654 csr32w(ctlr, AnaPll, csr32r(ctlr, AnaPll) | 0x00880300);
656 /* Wait for clock stabilization before accessing prph. */
657 if((err = clockwait(ctlr)) != nil)
660 if((err = niclock(ctlr)) != nil)
663 /* Enable DMA and BSM (Bootstrap State Machine). */
664 if(ctlr->type == Type4965)
665 prphwrite(ctlr, ApmgClkEna, DmaClkRqt | BsmClkRqt);
667 prphwrite(ctlr, ApmgClkEna, DmaClkRqt);
670 /* Disable L1-Active. */
671 prphwrite(ctlr, ApmgPciStt, prphread(ctlr, ApmgPciStt) | (1<<11));
685 csr32w(ctlr, Reset, 1);
687 /* Disable interrupts */
689 csr32w(ctlr, Imr, 0);
690 csr32w(ctlr, Isr, ~0);
691 csr32w(ctlr, FhIsr, ~0);
694 if(ctlr->type != Type4965)
695 prphwrite(ctlr, SchedTxFact5000, 0);
697 prphwrite(ctlr, SchedTxFact4965, 0);
700 if(niclock(ctlr) == nil){
701 for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--){
702 csr32w(ctlr, FhTxConfig + i*32, 0);
703 for(j = 0; j < 200; j++){
704 if(csr32r(ctlr, FhTxStatus) & (0x10000<<i))
713 if(niclock(ctlr) == nil){
714 csr32w(ctlr, FhRxConfig, 0);
715 for(j = 0; j < 200; j++){
716 if(csr32r(ctlr, FhRxStatus) & 0x1000000)
724 if(niclock(ctlr) == nil){
725 prphwrite(ctlr, ApmgClkDis, DmaClkRqt);
730 /* Stop busmaster DMA activity. */
731 csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<9));
732 for(j = 0; j < 100; j++){
733 if(csr32r(ctlr, Reset) & (1<<8))
738 /* Reset the entire device. */
739 csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<7));
742 /* Clear "initialization complete" bit. */
743 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~InitDone);
756 ctlr->eeprom.otp = 0;
757 ctlr->eeprom.off = 0;
758 if(ctlr->type < Type1000 || (csr32r(ctlr, OtpromGp) & DevSelOtp) == 0)
761 /* Wait for clock stabilization before accessing prph. */
762 if((err = clockwait(ctlr)) != nil)
765 if((err = niclock(ctlr)) != nil)
767 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | ResetReq);
769 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) & ~ResetReq);
772 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
773 if(ctlr->type != Type1000)
774 csr32w(ctlr, Dbglinkpwrmgmt, csr32r(ctlr, Dbglinkpwrmgmt) | (1<<31));
776 csr32w(ctlr, EepromGp, csr32r(ctlr, EepromGp) & ~0x00000180);
778 /* Clear ECC status. */
779 csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) | (EccCorrStts | EccUncorrStts));
781 ctlr->eeprom.otp = 1;
782 if(ctlr->type != Type1000)
785 /* Switch to absolute addressing mode. */
786 csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) & ~RelativeAccess);
789 * Find the block before last block (contains the EEPROM image)
790 * for HW without OTP shadow RAM.
794 if((err = eepromread(ctlr, buf, 2, last)) != nil)
802 return "rominit: missing eeprom image";
804 ctlr->eeprom.off = prev+1;
814 uint u, caloff, regoff;
817 if((err = handover(ctlr)) != nil)
819 if((err = poweron(ctlr)) != nil)
821 if((csr32r(ctlr, EepromGp) & 0x7) == 0){
822 err = "bad rom signature";
825 if((err = eepromlock(ctlr)) != nil)
827 if((err = rominit(ctlr)) != nil)
829 if((err = eepromread(ctlr, edev->ea, sizeof(edev->ea), 0x15)) != nil){
833 if((err = eepromread(ctlr, b, 2, 0x048)) != nil){
839 ctlr->rfcfg.type = u & 3; u >>= 2;
840 ctlr->rfcfg.step = u & 3; u >>= 2;
841 ctlr->rfcfg.dash = u & 3; u >>= 4;
842 ctlr->rfcfg.txantmask = u & 15; u >>= 4;
843 ctlr->rfcfg.rxantmask = u & 15;
844 if((err = eepromread(ctlr, b, 2, 0x66)) != nil)
847 if((err = eepromread(ctlr, b, 4, regoff+1)) != nil)
849 strncpy(ctlr->eeprom.regdom, (char*)b, 4);
850 ctlr->eeprom.regdom[4] = 0;
851 if((err = eepromread(ctlr, b, 2, 0x67)) != nil)
854 if((err = eepromread(ctlr, b, 4, caloff)) != nil)
856 ctlr->eeprom.version = b[0];
857 ctlr->eeprom.type = b[1];
858 ctlr->eeprom.volt = get16(b+2);
859 if(ctlr->type != Type4965 && ctlr->type != Type5150){
860 if((err = eepromread(ctlr, b, 4, caloff + 0x128)) != nil)
862 ctlr->eeprom.crystal = get32(b);
868 ctlr->rfcfg.txantmask = 3;
869 ctlr->rfcfg.rxantmask = 7;
872 ctlr->rfcfg.txantmask = 2;
873 ctlr->rfcfg.rxantmask = 3;
876 if(ctlr->pdev->did == 0x422c || ctlr->pdev->did == 0x4230){
877 ctlr->rfcfg.txantmask = 6;
878 ctlr->rfcfg.rxantmask = 6;
885 print("iwlinit: %s\n", err);
891 crackfw(FWImage *i, uchar *data, uint size, int alt)
896 memset(i, 0, sizeof(*i));
899 return "firmware image too short";
903 i->rev = get32(p); p += 4;
907 if(size < (4+64+4+4+8))
909 if(memcmp(p, "IWL\n", 4) != 0)
910 return "bad firmware signature";
912 strncpy(i->descr, (char*)p, 64);
915 i->rev = get32(p); p += 4;
916 i->build = get32(p); p += 4;
917 altmask = get32(p); p += 4;
918 altmask |= (uvlong)get32(p) << 32; p += 4;
919 while(alt > 0 && (altmask & (1ULL<<alt)) == 0)
927 case 1: s = &i->main.text; break;
928 case 2: s = &i->main.data; break;
929 case 3: s = &i->init.text; break;
930 case 4: s = &i->init.data; break;
931 case 5: s = &i->boot.text; break;
935 if(get16(p) != 0 && get16(p) != alt)
938 s->size = get32(p); p += 4;
940 if((p + s->size) > e)
942 p += (s->size + 3) & ~3;
945 if(((i->rev>>8) & 0xFF) < 2)
946 return "need firmware api >= 2";
947 if(((i->rev>>8) & 0xFF) >= 3){
948 i->build = get32(p); p += 4;
952 i->main.text.size = get32(p); p += 4;
953 i->main.data.size = get32(p); p += 4;
954 i->init.text.size = get32(p); p += 4;
955 i->init.data.size = get32(p); p += 4;
956 i->boot.text.size = get32(p); p += 4;
957 i->main.text.data = p; p += i->main.text.size;
958 i->main.data.data = p; p += i->main.data.size;
959 i->init.text.data = p; p += i->init.text.size;
960 i->init.data.data = p; p += i->init.data.size;
961 i->boot.text.data = p; p += i->boot.text.size;
969 readfirmware(char *name)
971 uchar dirbuf[sizeof(Dir)+100], *data;
981 snprint(buf, sizeof buf, "/boot/%s", name);
982 c = namec(buf, Aopen, OREAD, 0);
985 snprint(buf, sizeof buf, "/lib/firmware/%s", name);
986 c = namec(buf, Aopen, OREAD, 0);
992 n = devtab[c->type]->stat(c, dirbuf, sizeof dirbuf);
994 error("can't stat firmware");
995 convM2D(dirbuf, n, &d, nil);
996 fw = smalloc(sizeof(*fw) + 16 + d.length);
997 data = (uchar*)(fw+1);
1003 while(r < d.length){
1004 n = devtab[c->type]->read(c, data+r, d.length-r, (vlong)r);
1009 if((err = crackfw(fw, data, r, 1)) != nil)
1017 typedef struct Irqwait Irqwait;
1031 ctlr->wait.r = ctlr->wait.m & w->mask;
1033 ctlr->wait.m &= ~ctlr->wait.r;
1036 ctlr->wait.w = w->mask;
1041 irqwait(Ctlr *ctlr, u32int mask, int timeout)
1047 tsleep(&ctlr->wait, gotirq, &w, timeout);
1049 return ctlr->wait.r & mask;
1053 rbplant(Ctlr *ctlr, int i)
1057 b = iallocb(Rbufsize + 256);
1060 b->rp = b->wp = (uchar*)ROUND((uintptr)b->base, 256);
1061 memset(b->rp, 0, Rdscsize);
1063 ctlr->rx.p[i] = PCIWADDR(b->rp) >> 8;
1068 initring(Ctlr *ctlr)
1076 rx->b = malloc(sizeof(Block*) * Nrx);
1078 rx->p = mallocalign(sizeof(u32int) * Nrx, 256, 0, 0);
1080 rx->s = mallocalign(Rstatsize, 16, 0, 0);
1081 if(rx->b == nil || rx->p == nil || rx->s == nil)
1082 return "no memory for rx ring";
1083 memset(ctlr->rx.s, 0, Rstatsize);
1084 for(i=0; i<Nrx; i++){
1086 if(rx->b[i] != nil){
1090 if(rbplant(ctlr, i) < 0)
1091 return "no memory for rx descriptors";
1095 if(ctlr->sched.s == nil)
1096 ctlr->sched.s = mallocalign(512 * nelem(ctlr->tx) * 2, 1024, 0, 0);
1097 if(ctlr->sched.s == nil)
1098 return "no memory for sched buffer";
1099 memset(ctlr->sched.s, 0, 512 * nelem(ctlr->tx));
1101 for(q=0; q<nelem(ctlr->tx); q++){
1104 tx->b = malloc(sizeof(Block*) * Ntx);
1106 tx->d = mallocalign(Tdscsize * Ntx, 256, 0, 0);
1108 tx->c = mallocalign(Tcmdsize * Ntx, 4, 0, 0);
1109 if(tx->b == nil || tx->d == nil || tx->c == nil)
1110 return "no memory for tx ring";
1111 memset(tx->d, 0, Tdscsize * Ntx);
1112 memset(tx->c, 0, Tcmdsize * Ntx);
1113 for(i=0; i<Ntx; i++){
1114 if(tx->b[i] != nil){
1124 if(ctlr->kwpage == nil)
1125 ctlr->kwpage = mallocalign(4096, 4096, 0, 0);
1126 if(ctlr->kwpage == nil)
1127 return "no memory for kwpage";
1128 memset(ctlr->kwpage, 0, 4096);
1141 if((err = initring(ctlr)) != nil)
1143 if((err = poweron(ctlr)) != nil)
1146 if((err = niclock(ctlr)) != nil)
1148 prphwrite(ctlr, ApmgPs, (prphread(ctlr, ApmgPs) & ~PwrSrcMask) | PwrSrcVMain);
1151 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | RadioSi | MacSi);
1153 if((err = niclock(ctlr)) != nil)
1155 if(ctlr->type != Type4965)
1156 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | EarlyPwroffDis);
1157 if(ctlr->type == Type1000){
1159 * Select first Switching Voltage Regulator (1.32V) to
1160 * solve a stability issue related to noisy DC2DC line
1161 * in the silicon of 1000 Series.
1163 prphwrite(ctlr, ApmgDigitalSvr,
1164 (prphread(ctlr, ApmgDigitalSvr) & ~(0xf<<5)) | (3<<5));
1168 if((err = niclock(ctlr)) != nil)
1170 if((ctlr->type == Type6005 || ctlr->type == Type6050) && ctlr->eeprom.version == 6)
1171 csr32w(ctlr, GpDrv, csr32r(ctlr, GpDrv) | GpDrvCalV6);
1172 if(ctlr->type == Type6005)
1173 csr32w(ctlr, GpDrv, csr32r(ctlr, GpDrv) | GpDrv1X2);
1176 if((err = niclock(ctlr)) != nil)
1178 csr32w(ctlr, FhRxConfig, 0);
1179 csr32w(ctlr, FhRxWptr, 0);
1180 csr32w(ctlr, FhRxBase, PCIWADDR(ctlr->rx.p) >> 8);
1181 csr32w(ctlr, FhStatusWptr, PCIWADDR(ctlr->rx.s) >> 4);
1182 csr32w(ctlr, FhRxConfig,
1184 FhRxConfigIgnRxfEmpty |
1185 FhRxConfigIrqDstHost |
1186 FhRxConfigSingleFrame |
1187 (Nrxlog << FhRxConfigNrbdShift));
1188 csr32w(ctlr, FhRxWptr, (Nrx-1) & ~7);
1191 if((err = niclock(ctlr)) != nil)
1193 if(ctlr->type != Type4965)
1194 prphwrite(ctlr, SchedTxFact5000, 0);
1196 prphwrite(ctlr, SchedTxFact4965, 0);
1197 csr32w(ctlr, FhKwAddr, PCIWADDR(ctlr->kwpage) >> 4);
1198 for(q = (ctlr->type != Type4965) ? 19 : 15; q >= 0; q--)
1199 csr32w(ctlr, FhCbbcQueue + q*4, PCIWADDR(ctlr->tx[q].d) >> 8);
1202 for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--)
1203 csr32w(ctlr, FhTxConfig + i*32, FhTxConfigDmaEna | FhTxConfigDmaCreditEna);
1205 csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
1206 csr32w(ctlr, UcodeGp1Clr, UcodeGp1CmdBlocked);
1212 ctlr->ie = Idefmask;
1213 csr32w(ctlr, Imr, ctlr->ie);
1214 csr32w(ctlr, Isr, ~0);
1216 if(ctlr->type >= Type6000)
1217 csr32w(ctlr, ShadowRegCtrl, csr32r(ctlr, ShadowRegCtrl) | 0x800fffff);
1223 postboot(Ctlr *ctlr)
1225 uint ctxoff, ctxlen, dramaddr;
1229 if((err = niclock(ctlr)) != nil)
1232 if(ctlr->type != Type4965){
1233 dramaddr = SchedDramAddr5000;
1234 ctxoff = SchedCtxOff5000;
1235 ctxlen = SchedCtxLen5000;
1237 dramaddr = SchedDramAddr4965;
1238 ctxoff = SchedCtxOff4965;
1239 ctxlen = SchedCtxLen4965;
1242 ctlr->sched.base = prphread(ctlr, SchedSramAddr);
1243 for(i=0; i < ctxlen; i += 4)
1244 memwrite(ctlr, ctlr->sched.base + ctxoff + i, 0);
1246 prphwrite(ctlr, dramaddr, PCIWADDR(ctlr->sched.s)>>10);
1248 csr32w(ctlr, FhTxChicken, csr32r(ctlr, FhTxChicken) | 2);
1250 if(ctlr->type != Type4965){
1251 /* Enable chain mode for all queues, except command queue 4. */
1252 prphwrite(ctlr, SchedQChainSel5000, 0xfffef);
1253 prphwrite(ctlr, SchedAggrSel5000, 0);
1255 for(q=0; q<20; q++){
1256 prphwrite(ctlr, SchedQueueRdptr5000 + q*4, 0);
1257 csr32w(ctlr, HbusTargWptr, q << 8);
1259 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 0);
1260 /* Set scheduler window size and frame limit. */
1261 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16 | 64);
1263 /* Enable interrupts for all our 20 queues. */
1264 prphwrite(ctlr, SchedIntrMask5000, 0xfffff);
1266 /* Identify TX FIFO rings (0-7). */
1267 prphwrite(ctlr, SchedTxFact5000, 0xff);
1269 /* Disable chain mode for all our 16 queues. */
1270 prphwrite(ctlr, SchedQChainSel4965, 0);
1272 for(q=0; q<16; q++) {
1273 prphwrite(ctlr, SchedQueueRdptr4965 + q*4, 0);
1274 csr32w(ctlr, HbusTargWptr, q << 8);
1276 /* Set scheduler window size. */
1277 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 64);
1278 /* Set scheduler window size and frame limit. */
1279 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16);
1281 /* Enable interrupts for all our 16 queues. */
1282 prphwrite(ctlr, SchedIntrMask4965, 0xffff);
1284 /* Identify TX FIFO rings (0-7). */
1285 prphwrite(ctlr, SchedTxFact4965, 0xff);
1288 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
1290 if(ctlr->type != Type4965){
1291 static uchar qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
1292 prphwrite(ctlr, SchedQueueStatus5000 + q*4, 0x00ff0018 | qid2fifo[q]);
1294 static uchar qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
1295 prphwrite(ctlr, SchedQueueStatus4965 + q*4, 0x0007fc01 | qid2fifo[q]<<1);
1300 if(ctlr->type != Type4965){
1303 /* disable wimax coexistance */
1304 memset(c, 0, sizeof(c));
1305 if((err = cmd(ctlr, 90, c, 4+4*16)) != nil)
1308 if(ctlr->type != Type5150){
1309 /* calibrate crystal */
1310 memset(c, 0, sizeof(c));
1311 c[0] = 15; /* code */
1312 c[1] = 0; /* group */
1313 c[2] = 1; /* ngroup */
1314 c[3] = 1; /* isvalid */
1315 c[4] = ctlr->eeprom.crystal;
1316 c[5] = ctlr->eeprom.crystal>>16;
1317 if((err = cmd(ctlr, 176, c, 8)) != nil)
1321 if(ctlr->calib.done == 0){
1322 /* query calibration (init firmware) */
1323 memset(c, 0, sizeof(c));
1324 put32(c + 0*(5*4) + 0, 0xffffffff);
1325 put32(c + 0*(5*4) + 4, 0xffffffff);
1326 put32(c + 0*(5*4) + 8, 0xffffffff);
1327 put32(c + 2*(5*4) + 0, 0xffffffff);
1328 if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1331 /* wait to collect calibration records */
1332 if(irqwait(ctlr, Ierr, 2000))
1333 return "calibration failed";
1335 if(ctlr->calib.done == 0){
1336 print("iwl: no calibration results\n");
1337 ctlr->calib.done = 1;
1340 static uchar cmds[] = {8, 9, 11, 17, 16};
1342 /* send calibration records (runtime firmware) */
1343 for(q=0; q<nelem(cmds); q++){
1347 if(i == 8 && ctlr->type != Type5150)
1349 if(i == 17 && (ctlr->type >= Type6000 || ctlr->type == Type5150))
1351 if((b = ctlr->calib.cmd[i]) == nil)
1353 b->ref++; /* dont free on command completion */
1354 if((err = qcmd(ctlr, 4, 176, nil, 0, b)) != nil){
1358 if((err = flushq(ctlr, 4)) != nil)
1362 if(ctlr->type == Type6005){
1363 /* temperature sensor offset */
1364 memset(c, 0, sizeof(c));
1370 if((err = cmd(ctlr, 176, c, 4+2+2)) != nil)
1374 if(ctlr->type == Type6005 || ctlr->type == Type6050){
1375 /* runtime DC calibration */
1376 memset(c, 0, sizeof(c));
1377 put32(c + 0*(5*4) + 0, 0xffffffff);
1378 put32(c + 0*(5*4) + 4, 1<<1);
1379 if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1383 /* set tx antenna config */
1384 put32(c, ctlr->rfcfg.txantmask & 7);
1385 if((err = cmd(ctlr, 152, c, 4)) != nil)
1394 loadfirmware1(Ctlr *ctlr, u32int dst, uchar *data, int size)
1399 dma = mallocalign(size, 16, 0, 0);
1401 return "no memory for dma";
1402 memmove(dma, data, size);
1404 if((err = niclock(ctlr)) != 0){
1408 csr32w(ctlr, FhTxConfig + 9*32, 0);
1409 csr32w(ctlr, FhSramAddr + 9*4, dst);
1410 csr32w(ctlr, FhTfbdCtrl0 + 9*8, PCIWADDR(dma));
1411 csr32w(ctlr, FhTfbdCtrl1 + 9*8, size);
1412 csr32w(ctlr, FhTxBufStatus + 9*32,
1413 (1<<FhTxBufStatusTbNumShift) |
1414 (1<<FhTxBufStatusTbIdxShift) |
1415 FhTxBufStatusTfbdValid);
1416 csr32w(ctlr, FhTxConfig + 9*32, FhTxConfigDmaEna | FhTxConfigCirqHostEndTfd);
1418 if(irqwait(ctlr, Ifhtx|Ierr, 5000) != Ifhtx){
1420 return "dma error / timeout";
1436 if(fw->boot.text.size == 0){
1437 if(ctlr->calib.done == 0){
1438 if((err = loadfirmware1(ctlr, 0x00000000, fw->init.text.data, fw->init.text.size)) != nil)
1440 if((err = loadfirmware1(ctlr, 0x00800000, fw->init.data.data, fw->init.data.size)) != nil)
1442 csr32w(ctlr, Reset, 0);
1443 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1444 return "init firmware boot failed";
1445 if((err = postboot(ctlr)) != nil)
1447 if((err = reset(ctlr)) != nil)
1450 if((err = loadfirmware1(ctlr, 0x00000000, fw->main.text.data, fw->main.text.size)) != nil)
1452 if((err = loadfirmware1(ctlr, 0x00800000, fw->main.data.data, fw->main.data.size)) != nil)
1454 csr32w(ctlr, Reset, 0);
1455 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1456 return "main firmware boot failed";
1457 return postboot(ctlr);
1460 size = ROUND(fw->init.data.size, 16) + ROUND(fw->init.text.size, 16);
1461 dma = mallocalign(size, 16, 0, 0);
1463 return "no memory for dma";
1465 if((err = niclock(ctlr)) != nil){
1471 memmove(p, fw->init.data.data, fw->init.data.size);
1473 prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1474 prphwrite(ctlr, BsmDramDataSize, fw->init.data.size);
1475 p += ROUND(fw->init.data.size, 16);
1476 memmove(p, fw->init.text.data, fw->init.text.size);
1478 prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1479 prphwrite(ctlr, BsmDramTextSize, fw->init.text.size);
1482 if((err = niclock(ctlr)) != nil){
1487 p = fw->boot.text.data;
1488 n = fw->boot.text.size/4;
1489 for(i=0; i<n; i++, p += 4)
1490 prphwrite(ctlr, BsmSramBase+i*4, get32(p));
1492 prphwrite(ctlr, BsmWrMemSrc, 0);
1493 prphwrite(ctlr, BsmWrMemDst, 0);
1494 prphwrite(ctlr, BsmWrDwCount, n);
1496 prphwrite(ctlr, BsmWrCtrl, 1<<31);
1498 for(i=0; i<1000; i++){
1499 if((prphread(ctlr, BsmWrCtrl) & (1<<31)) == 0)
1506 return "bootcode timeout";
1509 prphwrite(ctlr, BsmWrCtrl, 1<<30);
1512 csr32w(ctlr, Reset, 0);
1513 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1515 return "init firmware boot failed";
1519 size = ROUND(fw->main.data.size, 16) + ROUND(fw->main.text.size, 16);
1520 dma = mallocalign(size, 16, 0, 0);
1522 return "no memory for dma";
1523 if((err = niclock(ctlr)) != nil){
1528 memmove(p, fw->main.data.data, fw->main.data.size);
1530 prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1531 prphwrite(ctlr, BsmDramDataSize, fw->main.data.size);
1532 p += ROUND(fw->main.data.size, 16);
1533 memmove(p, fw->main.text.data, fw->main.text.size);
1535 prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1536 prphwrite(ctlr, BsmDramTextSize, fw->main.text.size | (1<<31));
1539 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1541 return "main firmware boot failed";
1544 return postboot(ctlr);
1555 qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block)
1560 assert(qid < nelem(ctlr->tx));
1561 assert(size <= Tcmdsize-4);
1565 while(q->n >= Ntx && !ctlr->broken){
1569 tsleep(q, txqready, q, 10);
1577 return "qcmd: broken";
1583 c = q->c + q->i * Tcmdsize;
1584 d = q->d + q->i * Tdscsize;
1588 c[1] = 0; /* flags */
1593 memmove(c+4, data, size);
1597 /* build descriptor */
1601 *d++ = 1 + (block != nil); /* nsegs */
1602 put32(d, PCIWADDR(c)); d += 4;
1603 put16(d, size << 4); d += 2;
1606 put32(d, PCIWADDR(block->rp)); d += 4;
1607 put16(d, size << 4);
1612 q->i = (q->i+1) % Ntx;
1613 csr32w(ctlr, HbusTargWptr, (qid<<8) | q->i);
1628 flushq(Ctlr *ctlr, uint qid)
1635 for(i = 0; i < 200 && !ctlr->broken; i++){
1641 tsleep(q, txqempty, q, 10);
1647 return "flushq: broken";
1648 return "flushq: timeout";
1652 cmd(Ctlr *ctlr, uint code, uchar *data, int size)
1656 if(0) print("cmd %ud\n", code);
1657 if((err = qcmd(ctlr, 4, code, data, size, nil)) != nil)
1659 return flushq(ctlr, 4);
1663 setled(Ctlr *ctlr, int which, int on, int off)
1667 csr32w(ctlr, Led, csr32r(ctlr, Led) & ~LedBsmCtrl);
1669 memset(c, 0, sizeof(c));
1674 cmd(ctlr, 72, c, sizeof(c));
1678 addnode(Ctlr *ctlr, uchar id, uchar *addr)
1680 uchar c[Tcmdsize], *p;
1682 memset(p = c, 0, sizeof(c));
1683 *p++ = 0; /* control (1 = update) */
1684 p += 3; /* reserved */
1685 memmove(p, addr, 6);
1687 p += 2; /* reserved */
1688 *p++ = id; /* node id */
1690 p += 2; /* reserved */
1691 p += 2; /* kflags */
1694 p += 5*2; /* ttak */
1698 if(ctlr->type != Type4965){
1703 p += 4; /* htflags */
1705 p += 2; /* disable tid */
1706 p += 2; /* reserved */
1707 p++; /* add ba tid */
1708 p++; /* del ba tid */
1709 p += 2; /* add ba ssn */
1710 p += 4; /* reserved */
1711 cmd(ctlr, 24, c, p - c);
1715 rxon(Ether *edev, Wnode *bss)
1717 uchar c[Tcmdsize], *p;
1723 filter = FilterNoDecrypt | FilterMulticast | FilterBeacon;
1725 filter |= FilterPromisc;
1727 ctlr->channel = bss->channel;
1731 ctlr->channel = bss->channel;
1732 memmove(ctlr->bssid, bss->bssid, Eaddrlen);
1733 ctlr->aid = bss->aid;
1735 filter |= FilterBSS;
1736 filter &= ~FilterBeacon;
1737 ctlr->bssnodeid = -1;
1739 ctlr->bcastnodeid = -1;
1741 memmove(ctlr->bssid, edev->bcast, Eaddrlen);
1743 ctlr->bcastnodeid = -1;
1744 ctlr->bssnodeid = -1;
1746 flags = RFlagTSF | RFlagCTSToSelf | RFlag24Ghz | RFlagAuto;
1748 if(0) print("rxon: bssid %E, aid %x, channel %d, filter %x, flags %x\n",
1749 ctlr->bssid, ctlr->aid, ctlr->channel, filter, flags);
1751 memset(p = c, 0, sizeof(c));
1752 memmove(p, edev->ea, 6); p += 8; /* myaddr */
1753 memmove(p, ctlr->bssid, 6); p += 8; /* bssid */
1754 memmove(p, edev->ea, 6); p += 8; /* wlap */
1755 *p++ = 3; /* mode (STA) */
1756 *p++ = 0; /* air (?) */
1758 put16(p, ((ctlr->rfcfg.rxantmask & 7)<<1) | (2<<10) | (2<<12));
1760 *p++ = 0xff; /* ofdm mask (not yet negotiated) */
1761 *p++ = 0x0f; /* cck mask (not yet negotiated) */
1762 put16(p, ctlr->aid & 0x3fff);
1768 *p++ = ctlr->channel;
1770 *p++ = 0xff; /* ht single mask */
1771 *p++ = 0xff; /* ht dual mask */
1772 if(ctlr->type != Type4965){
1773 *p++ = 0xff; /* ht triple mask */
1775 put16(p, 0); p += 2; /* acquisition */
1776 p += 2; /* reserved */
1778 if((err = cmd(ctlr, 16, c, p - c)) != nil){
1779 print("rxon: %s\n", err);
1783 if(ctlr->bcastnodeid == -1){
1784 ctlr->bcastnodeid = (ctlr->type != Type4965) ? 15 : 31;
1785 addnode(ctlr, ctlr->bcastnodeid, edev->bcast);
1787 if(ctlr->bssnodeid == -1 && bss != nil && ctlr->aid != 0){
1788 ctlr->bssnodeid = 0;
1789 addnode(ctlr, ctlr->bssnodeid, bss->bssid);
1793 static struct ratetab {
1798 { 2, 10, RFlagCCK },
1799 { 4, 20, RFlagCCK },
1800 { 11, 55, RFlagCCK },
1801 { 22, 110, RFlagCCK },
1814 TFlagNeedProtection = 1<<0,
1815 TFlagNeedRTS = 1<<1,
1816 TFlagNeedCTS = 1<<2,
1817 TFlagNeedACK = 1<<3,
1820 TFlagFullTxOp = 1<<7,
1822 TFlagAutoSeq = 1<<13,
1823 TFlagMoreFrag = 1<<14,
1824 TFlagInsertTs = 1<<16,
1825 TFlagNeedPadding = 1<<20,
1829 transmit(Wifi *wifi, Wnode *wn, Block *b)
1831 int flags, nodeid, rate, ant;
1832 uchar c[Tcmdsize], *p;
1842 if(ctlr->attached == 0 || ctlr->broken){
1848 if((wn->channel != ctlr->channel)
1849 || (!ctlr->prom && (wn->aid != ctlr->aid || memcmp(wn->bssid, ctlr->bssid, Eaddrlen) != 0)))
1853 /* association note has no data to transmit */
1860 nodeid = ctlr->bcastnodeid;
1861 w = (Wifipkt*)b->rp;
1862 if((w->a1[0] & 1) == 0){
1863 flags |= TFlagNeedACK;
1866 flags |= TFlagNeedRTS;
1868 if((w->fc[0] & 0x0c) == 0x08 && ctlr->bssnodeid != -1){
1869 nodeid = ctlr->bssnodeid;
1870 rate = 2; /* BUG: hardcode 11Mbit */
1873 if(flags & (TFlagNeedRTS|TFlagNeedCTS)){
1874 if(ctlr->type != Type4965){
1875 flags &= ~(TFlagNeedRTS|TFlagNeedCTS);
1876 flags |= TFlagNeedProtection;
1878 flags |= TFlagFullTxOp;
1883 /* select first available antenna */
1884 ant = ctlr->rfcfg.txantmask & 7;
1886 ant = ((ant - 1) & ant) ^ ant;
1888 memset(p = c, 0, sizeof(c));
1895 p += 4; /* scratch */
1897 *p++ = ratetab[rate].plcp;
1898 *p++ = ratetab[rate].flags | (ant<<6);
1900 p += 2; /* xflags */
1902 *p++ = 0; /* security */
1903 *p++ = 0; /* linkq */
1907 p += 2; /* reserved */
1908 put32(p, ~0); /* lifetime */
1911 /* BUG: scratch ptr? not clear what this is for */
1912 put32(p, PCIWADDR(ctlr->kwpage));
1915 *p++ = 60; /* rts ntries */
1916 *p++ = 15; /* data ntries */
1918 put16(p, 0); /* timeout */
1921 if((err = qcmd(ctlr, 0, 28, c, p - c, b)) != nil){
1922 print("transmit: %s\n", err);
1928 iwlctl(Ether *edev, void *buf, long n)
1934 return wifictl(ctlr->wifi, buf, n);
1939 iwlifstat(Ether *edev, void *buf, long n, ulong off)
1945 return wifistat(ctlr->wifi, buf, n, off);
1950 setoptions(Ether *edev)
1957 for(i = 0; i < edev->nopt; i++){
1958 snprint(buf, sizeof(buf), "%s", edev->opt[i]);
1959 p = strchr(buf, '=');
1962 if(strcmp(buf, "debug") == 0
1963 || strcmp(buf, "essid") == 0
1964 || strcmp(buf, "bssid") == 0){
1968 wifictl(ctlr->wifi, buf, strlen(buf));
1976 iwlpromiscuous(void *arg, int on)
1985 rxon(edev, ctlr->wifi->bss);
2002 /* hop channels for catching beacons */
2003 setled(ctlr, 2, 5, 5);
2004 while(wifi->bss == nil){
2006 if(wifi->bss != nil){
2010 ctlr->channel = 1 + ctlr->channel % 11;
2014 tsleep(&up->sleep, return0, 0, 1000);
2017 /* wait for association */
2018 setled(ctlr, 2, 10, 10);
2019 while((bss = wifi->bss) != nil){
2022 tsleep(&up->sleep, return0, 0, 1000);
2028 /* wait for disassociation */
2030 setled(ctlr, 2, 0, 1);
2031 while((bss = wifi->bss) != nil){
2034 tsleep(&up->sleep, return0, 0, 1000);
2041 iwlattach(Ether *edev)
2051 print("#l%d: %s\n", edev->ctlrno, up->errstr);
2057 if(ctlr->attached == 0){
2058 if((csr32r(ctlr, Gpc) & RfKill) == 0)
2059 error("wifi disabled by switch");
2061 if(ctlr->wifi == nil)
2062 ctlr->wifi = wifiattach(edev, transmit);
2064 if(ctlr->fw == nil){
2065 fw = readfirmware(fwname[ctlr->type]);
2066 print("#l%d: firmware: %s, rev %ux, build %ud, size %ux+%ux+%ux+%ux+%ux\n",
2070 fw->main.text.size, fw->main.data.size,
2071 fw->init.text.size, fw->init.data.size,
2072 fw->boot.text.size);
2076 if((err = reset(ctlr)) != nil)
2078 if((err = boot(ctlr)) != nil)
2081 ctlr->bcastnodeid = -1;
2082 ctlr->bssnodeid = -1;
2088 snprint(name, sizeof(name), "#l%diwl", edev->ctlrno);
2089 kproc(name, iwlproc, edev);
2107 if(ctlr->broken || rx->s == nil || rx->b == nil)
2109 for(hw = get16(rx->s) % Nrx; rx->i != hw; rx->i = (rx->i + 1) % Nrx){
2110 uchar type, flags, idx, qid;
2118 len = get32(d); d += 4;
2125 if((qid & 0x80) == 0 && qid < nelem(ctlr->tx)){
2126 tx = &ctlr->tx[qid];
2133 /* paranoia: clear tx descriptors */
2134 dd = tx->d + idx*Tdscsize;
2135 cc = tx->c + idx*Tcmdsize;
2136 memset(dd, 0, Tdscsize);
2137 memset(cc, 0, Tcmdsize);
2145 if(len < 4 || type == 0)
2150 case 1: /* microcontroller ready */
2151 setfwinfo(ctlr, d, len);
2153 case 24: /* add node done */
2155 case 28: /* tx done */
2157 case 102: /* calibration result (Type5000 only) */
2161 if(idx >= nelem(ctlr->calib.cmd))
2163 if(rbplant(ctlr, rx->i) < 0)
2165 if(ctlr->calib.cmd[idx] != nil)
2166 freeb(ctlr->calib.cmd[idx]);
2169 ctlr->calib.cmd[idx] = b;
2171 case 103: /* calibration done (Type5000 only) */
2172 ctlr->calib.done = 1;
2174 case 130: /* start scan */
2176 case 132: /* stop scan */
2178 case 156: /* rx statistics */
2180 case 157: /* beacon statistics */
2182 case 161: /* state changed */
2184 case 162: /* beacon missed */
2186 case 192: /* rx phy */
2188 case 195: /* rx done */
2193 case 193: /* mpdu rx done */
2196 len = get16(d); d += 4;
2197 if(d + len + 4 > b->lim)
2199 if((get32(d + len) & 3) != 3)
2201 if(ctlr->wifi == nil)
2203 if(rbplant(ctlr, rx->i) < 0)
2207 wifiiq(ctlr->wifi, b);
2209 case 197: /* rx compressed ba */
2212 /* paranoia: clear the descriptor */
2213 memset(b->rp, 0, Rdscsize);
2215 csr32w(ctlr, FhRxWptr, ((hw+Nrx-1) % Nrx) & ~7);
2219 iwlinterrupt(Ureg*, void *arg)
2228 csr32w(ctlr, Imr, 0);
2229 isr = csr32r(ctlr, Isr);
2230 fhisr = csr32r(ctlr, FhIsr);
2231 if(isr == 0xffffffff || (isr & 0xfffffff0) == 0xa5a5a5a0){
2235 if(isr == 0 && fhisr == 0)
2237 csr32w(ctlr, Isr, isr);
2238 csr32w(ctlr, FhIsr, fhisr);
2239 if((isr & (Iswrx | Ifhrx | Irxperiodic)) || (fhisr & Ifhrx))
2243 iprint("#l%d: fatal firmware error\n", edev->ctlrno);
2246 ctlr->wait.m |= isr;
2247 if(ctlr->wait.m & ctlr->wait.w){
2248 ctlr->wait.r = ctlr->wait.m & ctlr->wait.w;
2249 ctlr->wait.m &= ~ctlr->wait.r;
2250 wakeup(&ctlr->wait);
2253 csr32w(ctlr, Imr, ctlr->ie);
2257 static Ctlr *iwlhead, *iwltail;
2265 while(pdev = pcimatch(pdev, 0, 0)) {
2269 if(pdev->ccrb != 2 || pdev->ccru != 0x80)
2271 if(pdev->vid != 0x8086)
2277 case 0x0084: /* WiFi Link 1000 */
2278 case 0x4229: /* WiFi Link 4965 */
2279 case 0x4230: /* WiFi Link 4965 */
2280 case 0x4236: /* WiFi Link 5300 AGN */
2281 case 0x4237: /* Wifi Link 5100 AGN */
2282 case 0x0085: /* Centrino Advanced-N 6205 */
2283 case 0x422b: /* Centrino Ultimate-N 6300 */
2284 case 0x08ae: /* Centrino Wireless-N 100 */
2288 /* Clear device-specific "PCI retry timeout" register (41h). */
2289 if(pcicfgr8(pdev, 0x41) != 0)
2290 pcicfgw8(pdev, 0x41, 0);
2292 /* Clear interrupt disable bit. Hardware bug workaround. */
2293 if(pdev->pcr & 0x400){
2294 pdev->pcr &= ~0x400;
2295 pcicfgw16(pdev, PciPCR, pdev->pcr);
2301 ctlr = malloc(sizeof(Ctlr));
2303 print("iwl: unable to alloc Ctlr\n");
2306 ctlr->port = pdev->mem[0].bar & ~0x0F;
2307 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
2309 print("iwl: can't map %8.8luX\n", pdev->mem[0].bar);
2315 ctlr->type = (csr32r(ctlr, Rev) >> 4) & 0xF;
2317 if(fwname[ctlr->type] == nil){
2318 print("iwl: unsupported controller type %d\n", ctlr->type);
2319 vunmap(mem, pdev->mem[0].size);
2325 iwltail->link = ctlr;
2340 for(ctlr = iwlhead; ctlr != nil; ctlr = ctlr->link){
2343 if(edev->port == 0 || edev->port == ctlr->port){
2353 edev->port = ctlr->port;
2354 edev->irq = ctlr->pdev->intl;
2355 edev->tbdf = ctlr->pdev->tbdf;
2357 edev->interrupt = iwlinterrupt;
2358 edev->attach = iwlattach;
2359 edev->ifstat = iwlifstat;
2361 edev->promiscuous = iwlpromiscuous;
2362 edev->multicast = nil;
2365 if(iwlinit(edev) < 0){
2376 addethercard("iwl", iwlpnp);