2 * Intel WiFi Link driver.
4 * Written without any documentation but Damien Bergaminis
5 * OpenBSD iwn(4) driver sources. Requires intel firmware
6 * to be present in /lib/firmware/iwn-* on attach.
10 #include "../port/lib.h"
15 #include "../port/error.h"
16 #include "../port/netif.h"
38 Cfg = 0x000, /* config register */
47 Isr = 0x008, /* interrupt status */
48 Imr = 0x00c, /* interrupt mask */
61 Ierr = Iswerr | Ihwerr,
62 Idefmask = Ierr | Ifhtx | Ifhrx | Ialive | Iwakeup | Iswrx | Ictreached | Irftoggled,
64 FhIsr = 0x010, /* second interrupt status */
68 Rev = 0x028, /* hardware revision */
70 EepromIo = 0x02c, /* EEPROM i/o register */
75 RelativeAccess = 1<<17,
77 EccUncorrStts = 1<<21,
79 Gpc = 0x024, /* gp cntrl */
96 UcodeGp1RfKill = 1<<1,
97 UcodeGp1CmdBlocked = 1<<2,
98 UcodeGp1CtempStopRf = 1<<3,
100 ShadowRegCtrl = 0x0a8,
109 Dbglinkpwrmgmt = 0x250,
121 HbusTargWptr = 0x460,
125 * Flow-Handler registers.
128 FhTfbdCtrl0 = 0x1900, // +q*8
129 FhTfbdCtrl1 = 0x1904, // +q*8
133 FhSramAddr = 0x19a4, // +q*4
134 FhCbbcQueue = 0x19d0, // +q*4
135 FhStatusWptr = 0x1bc0,
139 FhRxConfigEna = 1<<31,
140 FhRxConfigRbSize8K = 1<<16,
141 FhRxConfigSingleFrame = 1<<15,
142 FhRxConfigIrqDstHost = 1<<12,
143 FhRxConfigIgnRxfEmpty = 1<<2,
145 FhRxConfigNrbdShift = 20,
146 FhRxConfigRbTimeoutShift= 4,
150 FhTxConfig = 0x1d00, // +q*32
151 FhTxConfigDmaCreditEna = 1<<3,
152 FhTxConfigDmaEna = 1<<31,
153 FhTxConfigCirqHostEndTfd= 1<<20,
155 FhTxBufStatus = 0x1d08, // +q*32
156 FhTxBufStatusTbNumShift = 20,
157 FhTxBufStatusTbIdxShift = 12,
158 FhTxBufStatusTfbdValid = 3,
160 FhTxChicken = 0x1e98,
165 * NIC internal memory offsets.
168 ApmgClkCtrl = 0x3000,
175 EarlyPwroffDis = 1<<22,
181 ApmgDigitalSvr = 0x3058,
182 ApmgAnalogSvr = 0x306c,
185 BsmWrMemSrc = 0x3404,
186 BsmWrMemDst = 0x3408,
187 BsmWrDwCount = 0x340c,
188 BsmDramTextAddr = 0x3490,
189 BsmDramTextSize = 0x3494,
190 BsmDramDataAddr = 0x3498,
191 BsmDramDataSize = 0x349c,
192 BsmSramBase = 0x3800,
196 * TX scheduler registers.
199 SchedBase = 0xa02c00,
200 SchedSramAddr = SchedBase,
202 SchedDramAddr4965 = SchedBase+0x010,
203 SchedTxFact4965 = SchedBase+0x01c,
204 SchedQueueRdptr4965 = SchedBase+0x064, // +q*4
205 SchedQChainSel4965 = SchedBase+0x0d0,
206 SchedIntrMask4965 = SchedBase+0x0e4,
207 SchedQueueStatus4965 = SchedBase+0x104, // +q*4
209 SchedDramAddr5000 = SchedBase+0x008,
210 SchedTxFact5000 = SchedBase+0x010,
211 SchedQueueRdptr5000 = SchedBase+0x068, // +q*4
212 SchedQChainSel5000 = SchedBase+0x0e8,
213 SchedIntrMask5000 = SchedBase+0x108,
214 SchedQueueStatus5000 = SchedBase+0x10c, // +q*4
215 SchedAggrSel5000 = SchedBase+0x248,
219 SchedCtxOff4965 = 0x380,
220 SchedCtxLen4965 = 416,
222 SchedCtxOff5000 = 0x600,
223 SchedCtxLen5000 = 512,
227 FilterPromisc = 1<<0,
229 FilterMulticast = 1<<2,
230 FilterNoDecrypt = 1<<3,
240 RFlagShPreamble = 1<<5,
241 RFlagNoDiversity = 1<<7,
242 RFlagAntennaA = 1<<8,
243 RFlagAntennaB = 1<<9,
245 RFlagCTSToSelf = 1<<30,
248 typedef struct FWInfo FWInfo;
249 typedef struct FWImage FWImage;
250 typedef struct FWSect FWSect;
252 typedef struct TXQ TXQ;
253 typedef struct RXQ RXQ;
255 typedef struct Ctlr Ctlr;
331 /* assigned node ids in hardware node table or -1 if unassigned */
335 /* current receiver settings */
336 uchar bssid[Eaddrlen];
386 /* controller types */
399 static char *fwname[16] = {
400 [Type4965] "iwn-4965",
401 [Type5300] "iwn-5000",
402 [Type5350] "iwn-5000",
403 [Type5150] "iwn-5150",
404 [Type5100] "iwn-5000",
405 [Type1000] "iwn-1000",
406 [Type6000] "iwn-6000",
407 [Type6050] "iwn-6050",
408 [Type6005] "iwn-6005",
411 static char *qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block);
412 static char *flushq(Ctlr *ctlr, uint qid);
413 static char *cmd(Ctlr *ctlr, uint code, uchar *data, int size);
415 #define csr32r(c, r) (*((c)->nic+((r)/4)))
416 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
420 return *((u16int*)p);
424 return *((u32int*)p);
427 put32(uchar *p, uint v){
431 put16(uchar *p, uint v){
440 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | MacAccessReq);
441 for(i=0; i<1000; i++){
442 if((csr32r(ctlr, Gpc) & (NicSleep | MacAccessEna)) == MacAccessEna)
446 return "niclock: timeout";
450 nicunlock(Ctlr *ctlr)
452 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~MacAccessReq);
456 prphread(Ctlr *ctlr, uint off)
458 csr32w(ctlr, PrphRaddr, ((sizeof(u32int)-1)<<24) | off);
460 return csr32r(ctlr, PrphRdata);
463 prphwrite(Ctlr *ctlr, uint off, u32int data)
465 csr32w(ctlr, PrphWaddr, ((sizeof(u32int)-1)<<24) | off);
467 csr32w(ctlr, PrphWdata, data);
471 memread(Ctlr *ctlr, uint off)
473 csr32w(ctlr, MemRaddr, off);
475 return csr32r(ctlr, MemRdata);
478 memwrite(Ctlr *ctlr, uint off, u32int data)
480 csr32w(ctlr, MemWaddr, off);
482 csr32w(ctlr, MemWdata, data);
486 setfwinfo(Ctlr *ctlr, uchar *d, int len)
499 i->logptr = get32(d); d += 4;
500 i->errptr = get32(d); d += 4;
501 i->tstamp = get32(d); d += 4;
511 print("lastcmd: %ud (0x%ux)\n", ctlr->tx[4].lastcmd, ctlr->tx[4].lastcmd);
512 if(ctlr->fwinfo.errptr == 0){
513 print("no error pointer\n");
516 for(i=0; i<nelem(dump); i++)
517 dump[i] = memread(ctlr, ctlr->fwinfo.errptr + i*4);
518 print( "error:\tid %ux, pc %ux,\n"
519 "\tbranchlink %.8ux %.8ux, interruptlink %.8ux %.8ux,\n"
520 "\terrordata %.8ux %.8ux, srcline %ud, tsf %ux, time %ux\n",
522 dump[4], dump[3], dump[6], dump[5],
523 dump[7], dump[8], dump[9], dump[10], dump[11]);
527 eepromlock(Ctlr *ctlr)
531 for(i=0; i<100; i++){
532 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | EepromLocked);
533 for(j=0; j<100; j++){
534 if(csr32r(ctlr, Cfg) & EepromLocked)
539 return "eepromlock: timeout";
542 eepromunlock(Ctlr *ctlr)
544 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) & ~EepromLocked);
547 eepromread(Ctlr *ctlr, void *data, int count, uint off)
554 off += ctlr->eeprom.off;
555 for(; count > 0; count -= 2, off++){
556 csr32w(ctlr, EepromIo, off << 2);
558 w = csr32r(ctlr, EepromIo);
564 return "eepromread: timeout";
565 if(ctlr->eeprom.otp){
566 s = csr32r(ctlr, OtpromGp);
567 if(s & EccUncorrStts)
568 return "eepromread: otprom ecc error";
570 csr32w(ctlr, OtpromGp, s);
584 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
586 if(csr32r(ctlr, Cfg) & NicReady)
590 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | Prepare);
591 for(i=0; i<15000; i++){
592 if((csr32r(ctlr, Cfg) & PrepareDone) == 0)
597 return "handover: timeout";
598 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady);
600 if(csr32r(ctlr, Cfg) & NicReady)
604 return "handover: timeout";
608 clockwait(Ctlr *ctlr)
612 /* Set "initialization complete" bit. */
613 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | InitDone);
614 for(i=0; i<2500; i++){
615 if(csr32r(ctlr, Gpc) & MacClockReady)
619 return "clockwait: timeout";
628 /* Disable L0s exit timer (NMI bug workaround). */
629 csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | DisL0Stimer);
631 /* Don't wait for ICH L0s (ICH bug workaround). */
632 csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | L1AnoL0Srx);
634 /* Set FH wait threshold to max (HW bug under stress workaround). */
635 csr32w(ctlr, Dbghpetmem, csr32r(ctlr, Dbghpetmem) | 0xffff0000);
637 /* Enable HAP INTA to move adapter from L1a to L0s. */
638 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | HapwakeL1A);
640 capoff = pcicap(ctlr->pdev, PciCapPCIe);
642 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
643 if(pcicfgr16(ctlr->pdev, capoff + 0x10) & 0x2) /* LCSR -> L1 Entry enabled. */
644 csr32w(ctlr, Gio, csr32r(ctlr, Gio) | EnaL0S);
646 csr32w(ctlr, Gio, csr32r(ctlr, Gio) & ~EnaL0S);
649 if(ctlr->type != Type4965 && ctlr->type <= Type1000)
650 csr32w(ctlr, AnaPll, csr32r(ctlr, AnaPll) | 0x00880300);
652 /* Wait for clock stabilization before accessing prph. */
653 if((err = clockwait(ctlr)) != nil)
656 if((err = niclock(ctlr)) != nil)
659 /* Enable DMA and BSM (Bootstrap State Machine). */
660 if(ctlr->type == Type4965)
661 prphwrite(ctlr, ApmgClkEna, DmaClkRqt | BsmClkRqt);
663 prphwrite(ctlr, ApmgClkEna, DmaClkRqt);
666 /* Disable L1-Active. */
667 prphwrite(ctlr, ApmgPciStt, prphread(ctlr, ApmgPciStt) | (1<<11));
681 csr32w(ctlr, Reset, 1);
683 /* Disable interrupts */
685 csr32w(ctlr, Imr, 0);
686 csr32w(ctlr, Isr, ~0);
687 csr32w(ctlr, FhIsr, ~0);
690 if(ctlr->type != Type4965)
691 prphwrite(ctlr, SchedTxFact5000, 0);
693 prphwrite(ctlr, SchedTxFact4965, 0);
696 if(niclock(ctlr) == nil){
697 for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--){
698 csr32w(ctlr, FhTxConfig + i*32, 0);
699 for(j = 0; j < 200; j++){
700 if(csr32r(ctlr, FhTxStatus) & (0x10000<<i))
709 if(niclock(ctlr) == nil){
710 csr32w(ctlr, FhRxConfig, 0);
711 for(j = 0; j < 200; j++){
712 if(csr32r(ctlr, FhRxStatus) & 0x1000000)
720 if(niclock(ctlr) == nil){
721 prphwrite(ctlr, ApmgClkDis, DmaClkRqt);
726 /* Stop busmaster DMA activity. */
727 csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<9));
728 for(j = 0; j < 100; j++){
729 if(csr32r(ctlr, Reset) & (1<<8))
734 /* Reset the entire device. */
735 csr32w(ctlr, Reset, csr32r(ctlr, Reset) | (1<<7));
738 /* Clear "initialization complete" bit. */
739 csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~InitDone);
752 ctlr->eeprom.otp = 0;
753 ctlr->eeprom.off = 0;
754 if(ctlr->type < Type1000 || (csr32r(ctlr, OtpromGp) & DevSelOtp) == 0)
757 /* Wait for clock stabilization before accessing prph. */
758 if((err = clockwait(ctlr)) != nil)
761 if((err = niclock(ctlr)) != nil)
763 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | ResetReq);
765 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) & ~ResetReq);
768 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
769 if(ctlr->type != Type1000)
770 csr32w(ctlr, Dbglinkpwrmgmt, csr32r(ctlr, Dbglinkpwrmgmt) | (1<<31));
772 csr32w(ctlr, EepromGp, csr32r(ctlr, EepromGp) & ~0x00000180);
774 /* Clear ECC status. */
775 csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) | (EccCorrStts | EccUncorrStts));
777 ctlr->eeprom.otp = 1;
778 if(ctlr->type != Type1000)
781 /* Switch to absolute addressing mode. */
782 csr32w(ctlr, OtpromGp, csr32r(ctlr, OtpromGp) & ~RelativeAccess);
785 * Find the block before last block (contains the EEPROM image)
786 * for HW without OTP shadow RAM.
790 if((err = eepromread(ctlr, buf, 2, last)) != nil)
798 return "rominit: missing eeprom image";
800 ctlr->eeprom.off = prev+1;
810 uint u, caloff, regoff;
813 if((err = handover(ctlr)) != nil)
815 if((err = poweron(ctlr)) != nil)
817 if((csr32r(ctlr, EepromGp) & 0x7) == 0){
818 err = "bad rom signature";
821 if((err = eepromlock(ctlr)) != nil)
823 if((err = rominit(ctlr)) != nil)
825 if((err = eepromread(ctlr, edev->ea, sizeof(edev->ea), 0x15)) != nil){
829 if((err = eepromread(ctlr, b, 2, 0x048)) != nil){
835 ctlr->rfcfg.type = u & 3; u >>= 2;
836 ctlr->rfcfg.step = u & 3; u >>= 2;
837 ctlr->rfcfg.dash = u & 3; u >>= 4;
838 ctlr->rfcfg.txantmask = u & 15; u >>= 4;
839 ctlr->rfcfg.rxantmask = u & 15;
840 if((err = eepromread(ctlr, b, 2, 0x66)) != nil)
843 if((err = eepromread(ctlr, b, 4, regoff+1)) != nil)
845 strncpy(ctlr->eeprom.regdom, (char*)b, 4);
846 ctlr->eeprom.regdom[4] = 0;
847 if((err = eepromread(ctlr, b, 2, 0x67)) != nil)
850 if((err = eepromread(ctlr, b, 4, caloff)) != nil)
852 ctlr->eeprom.version = b[0];
853 ctlr->eeprom.type = b[1];
854 ctlr->eeprom.volt = get16(b+2);
855 if(ctlr->type != Type4965 && ctlr->type != Type5150){
856 if((err = eepromread(ctlr, b, 4, caloff + 0x128)) != nil)
858 ctlr->eeprom.crystal = get32(b);
864 ctlr->rfcfg.txantmask = 3;
865 ctlr->rfcfg.rxantmask = 7;
868 ctlr->rfcfg.txantmask = 2;
869 ctlr->rfcfg.rxantmask = 3;
872 if(ctlr->pdev->did == 0x422c || ctlr->pdev->did == 0x4230){
873 ctlr->rfcfg.txantmask = 6;
874 ctlr->rfcfg.rxantmask = 6;
881 print("iwlinit: %s\n", err);
887 crackfw(FWImage *i, uchar *data, uint size, int alt)
892 memset(i, 0, sizeof(*i));
895 return "firmware image too short";
899 i->rev = get32(p); p += 4;
903 if(size < (4+64+4+4+8))
905 if(memcmp(p, "IWL\n", 4) != 0)
906 return "bad firmware signature";
908 strncpy(i->descr, (char*)p, 64);
911 i->rev = get32(p); p += 4;
912 i->build = get32(p); p += 4;
913 altmask = get32(p); p += 4;
914 altmask |= (uvlong)get32(p) << 32; p += 4;
915 while(alt > 0 && (altmask & (1ULL<<alt)) == 0)
923 case 1: s = &i->main.text; break;
924 case 2: s = &i->main.data; break;
925 case 3: s = &i->init.text; break;
926 case 4: s = &i->init.data; break;
927 case 5: s = &i->boot.text; break;
931 if(get16(p) != 0 && get16(p) != alt)
934 s->size = get32(p); p += 4;
936 if((p + s->size) > e)
938 p += (s->size + 3) & ~3;
941 if(((i->rev>>8) & 0xFF) < 2)
942 return "need firmware api >= 2";
943 if(((i->rev>>8) & 0xFF) >= 3){
944 i->build = get32(p); p += 4;
948 i->main.text.size = get32(p); p += 4;
949 i->main.data.size = get32(p); p += 4;
950 i->init.text.size = get32(p); p += 4;
951 i->init.data.size = get32(p); p += 4;
952 i->boot.text.size = get32(p); p += 4;
953 i->main.text.data = p; p += i->main.text.size;
954 i->main.data.data = p; p += i->main.data.size;
955 i->init.text.data = p; p += i->init.text.size;
956 i->init.data.data = p; p += i->init.data.size;
957 i->boot.text.data = p; p += i->boot.text.size;
965 readfirmware(char *name)
967 uchar dirbuf[sizeof(Dir)+100], *data;
977 snprint(buf, sizeof buf, "/boot/%s", name);
978 c = namec(buf, Aopen, OREAD, 0);
981 snprint(buf, sizeof buf, "/lib/firmware/%s", name);
982 c = namec(buf, Aopen, OREAD, 0);
988 n = devtab[c->type]->stat(c, dirbuf, sizeof dirbuf);
990 error("can't stat firmware");
991 convM2D(dirbuf, n, &d, nil);
992 fw = smalloc(sizeof(*fw) + 16 + d.length);
993 data = (uchar*)(fw+1);
1000 n = devtab[c->type]->read(c, data+r, d.length-r, (vlong)r);
1005 if((err = crackfw(fw, data, r, 1)) != nil)
1013 typedef struct Irqwait Irqwait;
1027 ctlr->wait.r = ctlr->wait.m & w->mask;
1029 ctlr->wait.m &= ~ctlr->wait.r;
1032 ctlr->wait.w = w->mask;
1037 irqwait(Ctlr *ctlr, u32int mask, int timeout)
1043 tsleep(&ctlr->wait, gotirq, &w, timeout);
1045 return ctlr->wait.r & mask;
1049 rbplant(Ctlr *ctlr, int i)
1053 b = iallocb(Rbufsize + 256);
1056 b->rp = b->wp = (uchar*)ROUND((uintptr)b->base, 256);
1057 memset(b->rp, 0, Rdscsize);
1059 ctlr->rx.p[i] = PCIWADDR(b->rp) >> 8;
1064 initring(Ctlr *ctlr)
1072 rx->b = malloc(sizeof(Block*) * Nrx);
1074 rx->p = mallocalign(sizeof(u32int) * Nrx, 256, 0, 0);
1076 rx->s = mallocalign(Rstatsize, 16, 0, 0);
1077 if(rx->b == nil || rx->p == nil || rx->s == nil)
1078 return "no memory for rx ring";
1079 memset(ctlr->rx.s, 0, Rstatsize);
1080 for(i=0; i<Nrx; i++){
1082 if(rx->b[i] != nil){
1086 if(rbplant(ctlr, i) < 0)
1087 return "no memory for rx descriptors";
1091 if(ctlr->sched.s == nil)
1092 ctlr->sched.s = mallocalign(512 * nelem(ctlr->tx) * 2, 1024, 0, 0);
1093 if(ctlr->sched.s == nil)
1094 return "no memory for sched buffer";
1095 memset(ctlr->sched.s, 0, 512 * nelem(ctlr->tx));
1097 for(q=0; q<nelem(ctlr->tx); q++){
1100 tx->b = malloc(sizeof(Block*) * Ntx);
1102 tx->d = mallocalign(Tdscsize * Ntx, 256, 0, 0);
1104 tx->c = mallocalign(Tcmdsize * Ntx, 4, 0, 0);
1105 if(tx->b == nil || tx->d == nil || tx->c == nil)
1106 return "no memory for tx ring";
1107 memset(tx->d, 0, Tdscsize * Ntx);
1108 memset(tx->c, 0, Tcmdsize * Ntx);
1109 for(i=0; i<Ntx; i++){
1110 if(tx->b[i] != nil){
1120 if(ctlr->kwpage == nil)
1121 ctlr->kwpage = mallocalign(4096, 4096, 0, 0);
1122 if(ctlr->kwpage == nil)
1123 return "no memory for kwpage";
1124 memset(ctlr->kwpage, 0, 4096);
1137 if((err = initring(ctlr)) != nil)
1139 if((err = poweron(ctlr)) != nil)
1142 if((err = niclock(ctlr)) != nil)
1144 prphwrite(ctlr, ApmgPs, (prphread(ctlr, ApmgPs) & ~PwrSrcMask) | PwrSrcVMain);
1147 csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | RadioSi | MacSi);
1149 if((err = niclock(ctlr)) != nil)
1151 if(ctlr->type != Type4965)
1152 prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | EarlyPwroffDis);
1153 if(ctlr->type == Type1000){
1155 * Select first Switching Voltage Regulator (1.32V) to
1156 * solve a stability issue related to noisy DC2DC line
1157 * in the silicon of 1000 Series.
1159 prphwrite(ctlr, ApmgDigitalSvr,
1160 (prphread(ctlr, ApmgDigitalSvr) & ~(0xf<<5)) | (3<<5));
1164 if((err = niclock(ctlr)) != nil)
1166 csr32w(ctlr, FhRxConfig, 0);
1167 csr32w(ctlr, FhRxWptr, 0);
1168 csr32w(ctlr, FhRxBase, PCIWADDR(ctlr->rx.p) >> 8);
1169 csr32w(ctlr, FhStatusWptr, PCIWADDR(ctlr->rx.s) >> 4);
1170 csr32w(ctlr, FhRxConfig,
1172 FhRxConfigIgnRxfEmpty |
1173 FhRxConfigIrqDstHost |
1174 FhRxConfigSingleFrame |
1175 (Nrxlog << FhRxConfigNrbdShift));
1176 csr32w(ctlr, FhRxWptr, (Nrx-1) & ~7);
1179 if((err = niclock(ctlr)) != nil)
1181 if(ctlr->type != Type4965)
1182 prphwrite(ctlr, SchedTxFact5000, 0);
1184 prphwrite(ctlr, SchedTxFact4965, 0);
1185 csr32w(ctlr, FhKwAddr, PCIWADDR(ctlr->kwpage) >> 4);
1186 for(q = (ctlr->type != Type4965) ? 19 : 15; q >= 0; q--)
1187 csr32w(ctlr, FhCbbcQueue + q*4, PCIWADDR(ctlr->tx[q].d) >> 8);
1190 for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--)
1191 csr32w(ctlr, FhTxConfig + i*32, FhTxConfigDmaEna | FhTxConfigDmaCreditEna);
1193 csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
1194 csr32w(ctlr, UcodeGp1Clr, UcodeGp1CmdBlocked);
1200 ctlr->ie = Idefmask;
1201 csr32w(ctlr, Imr, ctlr->ie);
1202 csr32w(ctlr, Isr, ~0);
1204 if(ctlr->type >= Type6000)
1205 csr32w(ctlr, ShadowRegCtrl, csr32r(ctlr, ShadowRegCtrl) | 0x800fffff);
1211 postboot(Ctlr *ctlr)
1213 uint ctxoff, ctxlen, dramaddr;
1217 if((err = niclock(ctlr)) != nil)
1220 if(ctlr->type != Type4965){
1221 dramaddr = SchedDramAddr5000;
1222 ctxoff = SchedCtxOff5000;
1223 ctxlen = SchedCtxLen5000;
1225 dramaddr = SchedDramAddr4965;
1226 ctxoff = SchedCtxOff4965;
1227 ctxlen = SchedCtxLen4965;
1230 ctlr->sched.base = prphread(ctlr, SchedSramAddr);
1231 for(i=0; i < ctxlen; i += 4)
1232 memwrite(ctlr, ctlr->sched.base + ctxoff + i, 0);
1234 prphwrite(ctlr, dramaddr, PCIWADDR(ctlr->sched.s)>>10);
1236 csr32w(ctlr, FhTxChicken, csr32r(ctlr, FhTxChicken) | 2);
1238 if(ctlr->type != Type4965){
1239 /* Enable chain mode for all queues, except command queue 4. */
1240 prphwrite(ctlr, SchedQChainSel5000, 0xfffef);
1241 prphwrite(ctlr, SchedAggrSel5000, 0);
1243 for(q=0; q<20; q++){
1244 prphwrite(ctlr, SchedQueueRdptr5000 + q*4, 0);
1245 csr32w(ctlr, HbusTargWptr, q << 8);
1247 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 0);
1248 /* Set scheduler window size and frame limit. */
1249 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16 | 64);
1251 /* Enable interrupts for all our 20 queues. */
1252 prphwrite(ctlr, SchedIntrMask5000, 0xfffff);
1254 /* Identify TX FIFO rings (0-7). */
1255 prphwrite(ctlr, SchedTxFact5000, 0xff);
1257 /* Disable chain mode for all our 16 queues. */
1258 prphwrite(ctlr, SchedQChainSel4965, 0);
1260 for(q=0; q<16; q++) {
1261 prphwrite(ctlr, SchedQueueRdptr4965 + q*4, 0);
1262 csr32w(ctlr, HbusTargWptr, q << 8);
1264 /* Set scheduler window size. */
1265 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 64);
1266 /* Set scheduler window size and frame limit. */
1267 memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16);
1269 /* Enable interrupts for all our 16 queues. */
1270 prphwrite(ctlr, SchedIntrMask4965, 0xffff);
1272 /* Identify TX FIFO rings (0-7). */
1273 prphwrite(ctlr, SchedTxFact4965, 0xff);
1276 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
1278 if(ctlr->type != Type4965){
1279 static uchar qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
1280 prphwrite(ctlr, SchedQueueStatus5000 + q*4, 0x00ff0018 | qid2fifo[q]);
1282 static uchar qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
1283 prphwrite(ctlr, SchedQueueStatus4965 + q*4, 0x0007fc01 | qid2fifo[q]<<1);
1288 if(ctlr->type != Type4965){
1291 /* disable wimax coexistance */
1292 memset(c, 0, sizeof(c));
1293 if((err = cmd(ctlr, 90, c, 4+4*16)) != nil)
1296 if(ctlr->type != Type5150){
1297 /* calibrate crystal */
1298 memset(c, 0, sizeof(c));
1299 c[0] = 15; /* code */
1300 c[1] = 0; /* group */
1301 c[2] = 1; /* ngroup */
1302 c[3] = 1; /* isvalid */
1303 c[4] = ctlr->eeprom.crystal;
1304 c[5] = ctlr->eeprom.crystal>>16;
1305 if((err = cmd(ctlr, 176, c, 8)) != nil)
1309 if(ctlr->calib.done == 0){
1310 /* query calibration (init firmware) */
1311 memset(c, 0, sizeof(c));
1312 put32(c + 0*(5*4) + 0, 0xffffffff);
1313 put32(c + 0*(5*4) + 4, 0xffffffff);
1314 put32(c + 0*(5*4) + 8, 0xffffffff);
1315 put32(c + 2*(5*4) + 0, 0xffffffff);
1316 if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1319 /* wait to collect calibration records */
1320 if(irqwait(ctlr, Ierr, 2000))
1321 return "calibration failed";
1323 if(ctlr->calib.done == 0){
1324 print("iwl: no calibration results\n");
1325 ctlr->calib.done = 1;
1328 static uchar cmds[] = {8, 9, 11, 17, 16};
1330 /* send calibration records (runtime firmware) */
1331 for(q=0; q<nelem(cmds); q++){
1335 if(i == 8 && ctlr->type != Type5150)
1337 if(i == 17 && (ctlr->type >= Type6000 || ctlr->type == Type5150))
1339 if((b = ctlr->calib.cmd[i]) == nil)
1341 b->ref++; /* dont free on command completion */
1342 if((err = qcmd(ctlr, 4, 176, nil, 0, b)) != nil){
1346 if((err = flushq(ctlr, 4)) != nil)
1350 if(ctlr->type == Type6005 || ctlr->type == Type6050){
1351 /* runtime DC calibration */
1352 memset(c, 0, sizeof(c));
1353 put32(c + 0*(5*4) + 0, 0xffffffff);
1354 put32(c + 0*(5*4) + 4, 1<<1);
1355 if((err = cmd(ctlr, 101, c, (((2*(5*4))+4)*2)+4)) != nil)
1359 /* set tx antenna config */
1360 put32(c, ctlr->rfcfg.txantmask & 7);
1361 if((err = cmd(ctlr, 152, c, 4)) != nil)
1370 loadfirmware1(Ctlr *ctlr, u32int dst, uchar *data, int size)
1375 dma = mallocalign(size, 16, 0, 0);
1377 return "no memory for dma";
1378 memmove(dma, data, size);
1380 if((err = niclock(ctlr)) != 0){
1384 csr32w(ctlr, FhTxConfig + 9*32, 0);
1385 csr32w(ctlr, FhSramAddr + 9*4, dst);
1386 csr32w(ctlr, FhTfbdCtrl0 + 9*8, PCIWADDR(dma));
1387 csr32w(ctlr, FhTfbdCtrl1 + 9*8, size);
1388 csr32w(ctlr, FhTxBufStatus + 9*32,
1389 (1<<FhTxBufStatusTbNumShift) |
1390 (1<<FhTxBufStatusTbIdxShift) |
1391 FhTxBufStatusTfbdValid);
1392 csr32w(ctlr, FhTxConfig + 9*32, FhTxConfigDmaEna | FhTxConfigCirqHostEndTfd);
1394 if(irqwait(ctlr, Ifhtx|Ierr, 5000) != Ifhtx){
1396 return "dma error / timeout";
1412 if(fw->boot.text.size == 0){
1413 if(ctlr->calib.done == 0){
1414 if((err = loadfirmware1(ctlr, 0x00000000, fw->init.text.data, fw->init.text.size)) != nil)
1416 if((err = loadfirmware1(ctlr, 0x00800000, fw->init.data.data, fw->init.data.size)) != nil)
1418 csr32w(ctlr, Reset, 0);
1419 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1420 return "init firmware boot failed";
1421 if((err = postboot(ctlr)) != nil)
1423 if((err = reset(ctlr)) != nil)
1426 if((err = loadfirmware1(ctlr, 0x00000000, fw->main.text.data, fw->main.text.size)) != nil)
1428 if((err = loadfirmware1(ctlr, 0x00800000, fw->main.data.data, fw->main.data.size)) != nil)
1430 csr32w(ctlr, Reset, 0);
1431 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive)
1432 return "main firmware boot failed";
1433 return postboot(ctlr);
1436 size = ROUND(fw->init.data.size, 16) + ROUND(fw->init.text.size, 16);
1437 dma = mallocalign(size, 16, 0, 0);
1439 return "no memory for dma";
1441 if((err = niclock(ctlr)) != nil){
1447 memmove(p, fw->init.data.data, fw->init.data.size);
1449 prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1450 prphwrite(ctlr, BsmDramDataSize, fw->init.data.size);
1451 p += ROUND(fw->init.data.size, 16);
1452 memmove(p, fw->init.text.data, fw->init.text.size);
1454 prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1455 prphwrite(ctlr, BsmDramTextSize, fw->init.text.size);
1458 if((err = niclock(ctlr)) != nil){
1463 p = fw->boot.text.data;
1464 n = fw->boot.text.size/4;
1465 for(i=0; i<n; i++, p += 4)
1466 prphwrite(ctlr, BsmSramBase+i*4, get32(p));
1468 prphwrite(ctlr, BsmWrMemSrc, 0);
1469 prphwrite(ctlr, BsmWrMemDst, 0);
1470 prphwrite(ctlr, BsmWrDwCount, n);
1472 prphwrite(ctlr, BsmWrCtrl, 1<<31);
1474 for(i=0; i<1000; i++){
1475 if((prphread(ctlr, BsmWrCtrl) & (1<<31)) == 0)
1482 return "bootcode timeout";
1485 prphwrite(ctlr, BsmWrCtrl, 1<<30);
1488 csr32w(ctlr, Reset, 0);
1489 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1491 return "init firmware boot failed";
1495 size = ROUND(fw->main.data.size, 16) + ROUND(fw->main.text.size, 16);
1496 dma = mallocalign(size, 16, 0, 0);
1498 return "no memory for dma";
1499 if((err = niclock(ctlr)) != nil){
1504 memmove(p, fw->main.data.data, fw->main.data.size);
1506 prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4);
1507 prphwrite(ctlr, BsmDramDataSize, fw->main.data.size);
1508 p += ROUND(fw->main.data.size, 16);
1509 memmove(p, fw->main.text.data, fw->main.text.size);
1511 prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4);
1512 prphwrite(ctlr, BsmDramTextSize, fw->main.text.size | (1<<31));
1515 if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){
1517 return "main firmware boot failed";
1520 return postboot(ctlr);
1531 qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block)
1536 assert(qid < nelem(ctlr->tx));
1537 assert(size <= Tcmdsize-4);
1541 while(q->n >= Ntx && !ctlr->broken){
1545 tsleep(q, txqready, q, 10);
1553 return "qcmd: broken";
1559 c = q->c + q->i * Tcmdsize;
1560 d = q->d + q->i * Tdscsize;
1564 c[1] = 0; /* flags */
1569 memmove(c+4, data, size);
1573 /* build descriptor */
1577 *d++ = 1 + (block != nil); /* nsegs */
1578 put32(d, PCIWADDR(c)); d += 4;
1579 put16(d, size << 4); d += 2;
1581 put32(d, PCIWADDR(block->rp)); d += 4;
1582 put16(d, BLEN(block) << 4);
1587 q->i = (q->i+1) % Ntx;
1588 csr32w(ctlr, HbusTargWptr, (qid<<8) | q->i);
1603 flushq(Ctlr *ctlr, uint qid)
1610 for(i = 0; i < 200 && !ctlr->broken; i++){
1616 tsleep(q, txqempty, q, 10);
1622 return "flushq: broken";
1623 return "flushq: timeout";
1627 cmd(Ctlr *ctlr, uint code, uchar *data, int size)
1631 if(0) print("cmd %ud\n", code);
1632 if((err = qcmd(ctlr, 4, code, data, size, nil)) != nil)
1634 return flushq(ctlr, 4);
1638 setled(Ctlr *ctlr, int which, int on, int off)
1642 csr32w(ctlr, Led, csr32r(ctlr, Led) & ~LedBsmCtrl);
1644 memset(c, 0, sizeof(c));
1649 cmd(ctlr, 72, c, sizeof(c));
1653 addnode(Ctlr *ctlr, uchar id, uchar *addr)
1655 uchar c[Tcmdsize], *p;
1657 memset(p = c, 0, sizeof(c));
1658 *p++ = 0; /* control (1 = update) */
1659 p += 3; /* reserved */
1660 memmove(p, addr, 6);
1662 p += 2; /* reserved */
1663 *p++ = id; /* node id */
1665 p += 2; /* reserved */
1666 p += 2; /* kflags */
1669 p += 5*2; /* ttak */
1673 if(ctlr->type != Type4965){
1678 p += 4; /* htflags */
1680 p += 2; /* disable tid */
1681 p += 2; /* reserved */
1682 p++; /* add ba tid */
1683 p++; /* del ba tid */
1684 p += 2; /* add ba ssn */
1685 p += 4; /* reserved */
1686 cmd(ctlr, 24, c, p - c);
1690 rxon(Ether *edev, Wnode *bss)
1692 uchar c[Tcmdsize], *p;
1698 filter = FilterMulticast | FilterBeacon;
1700 filter |= FilterPromisc;
1704 ctlr->channel = bss->channel;
1705 memmove(ctlr->bssid, bss->bssid, Eaddrlen);
1706 ctlr->aid = bss->aid;
1708 filter |= FilterBSS;
1709 filter &= ~FilterBeacon;
1710 ctlr->bssnodeid = -1;
1712 ctlr->bcastnodeid = -1;
1714 memmove(ctlr->bssid, edev->bcast, Eaddrlen);
1716 ctlr->bcastnodeid = -1;
1717 ctlr->bssnodeid = -1;
1719 flags = RFlagTSF | RFlagCTSToSelf | RFlag24Ghz | RFlagAuto;
1721 if(0) print("rxon: bssid %E, aid %x, channel %d, filter %x, flags %x\n",
1722 ctlr->bssid, ctlr->aid, ctlr->channel, filter, flags);
1724 memset(p = c, 0, sizeof(c));
1725 memmove(p, edev->ea, 6); p += 8; /* myaddr */
1726 memmove(p, ctlr->bssid, 6); p += 8; /* bssid */
1727 memmove(p, edev->ea, 6); p += 8; /* wlap */
1728 *p++ = 3; /* mode (STA) */
1729 *p++ = 0; /* air (?) */
1731 put16(p, ((ctlr->rfcfg.rxantmask & 7)<<1) | (2<<10) | (2<<12));
1733 *p++ = 0xff; /* ofdm mask (not yet negotiated) */
1734 *p++ = 0x0f; /* cck mask (not yet negotiated) */
1735 put16(p, ctlr->aid & 0x3fff);
1741 *p++ = ctlr->channel;
1743 *p++ = 0xff; /* ht single mask */
1744 *p++ = 0xff; /* ht dual mask */
1745 if(ctlr->type != Type4965){
1746 *p++ = 0xff; /* ht triple mask */
1748 put16(p, 0); p += 2; /* acquisition */
1749 p += 2; /* reserved */
1751 if((err = cmd(ctlr, 16, c, p - c)) != nil){
1752 print("rxon: %s\n", err);
1756 if(ctlr->bcastnodeid == -1){
1757 ctlr->bcastnodeid = (ctlr->type != Type4965) ? 15 : 31;
1758 addnode(ctlr, ctlr->bcastnodeid, edev->bcast);
1760 if(ctlr->bssnodeid == -1 && bss != nil && ctlr->aid != 0){
1761 ctlr->bssnodeid = 0;
1762 addnode(ctlr, ctlr->bssnodeid, bss->bssid);
1766 static struct ratetab {
1771 { 2, 10, RFlagCCK },
1772 { 4, 20, RFlagCCK },
1773 { 11, 55, RFlagCCK },
1774 { 22, 110, RFlagCCK },
1787 TFlagNeedProtection = 1<<0,
1788 TFlagNeedRTS = 1<<1,
1789 TFlagNeedCTS = 1<<2,
1790 TFlagNeedACK = 1<<3,
1793 TFlagFullTxOp = 1<<7,
1795 TFlagAutoSeq = 1<<13,
1796 TFlagMoreFrag = 1<<14,
1797 TFlagInsertTs = 1<<16,
1798 TFlagNeedPadding = 1<<20,
1802 transmit(Wifi *wifi, Wnode *wn, Block *b)
1804 int flags, nodeid, rate, ant;
1805 uchar c[Tcmdsize], *p;
1811 w = (Wifipkt*)b->rp;
1816 if(ctlr->attached == 0 || ctlr->broken){
1823 if(wn->aid != ctlr->aid
1824 || wn->channel != ctlr->channel
1825 || memcmp(wn->bssid, ctlr->bssid, Eaddrlen) != 0)
1830 nodeid = ctlr->bcastnodeid;
1831 if((w->a1[0] & 1) == 0){
1832 flags |= TFlagNeedACK;
1835 flags |= TFlagNeedRTS;
1837 if((w->fc[0] & 0x0c) == 0x08 && ctlr->bssnodeid != -1){
1838 nodeid = ctlr->bssnodeid;
1839 rate = 2; /* BUG: hardcode 11Mbit */
1842 if(flags & (TFlagNeedRTS|TFlagNeedCTS)){
1843 if(ctlr->type != Type4965){
1844 flags &= ~(TFlagNeedRTS|TFlagNeedCTS);
1845 flags |= TFlagNeedProtection;
1847 flags |= TFlagFullTxOp;
1852 /* select first available antenna */
1853 ant = ctlr->rfcfg.txantmask & 7;
1855 ant = ((ant - 1) & ant) ^ ant;
1857 memset(p = c, 0, sizeof(c));
1864 p += 4; /* scratch */
1866 *p++ = ratetab[rate].plcp;
1867 *p++ = ratetab[rate].flags | (ant<<6);
1869 p += 2; /* xflags */
1871 *p++ = 0; /* security */
1872 *p++ = 0; /* linkq */
1876 p += 2; /* reserved */
1877 put32(p, ~0); /* lifetime */
1880 /* BUG: scratch ptr? not clear what this is for */
1881 put32(p, PCIWADDR(ctlr->kwpage));
1884 *p++ = 60; /* rts ntries */
1885 *p++ = 15; /* data ntries */
1887 put16(p, 0); /* timeout */
1890 if((err = qcmd(ctlr, 0, 28, c, p - c, b)) != nil){
1891 print("transmit: %s\n", err);
1897 iwlctl(Ether *edev, void *buf, long n)
1903 return wifictl(ctlr->wifi, buf, n);
1908 iwlifstat(Ether *edev, void *buf, long n, ulong off)
1914 return wifistat(ctlr->wifi, buf, n, off);
1919 setoptions(Ether *edev)
1926 for(i = 0; i < edev->nopt; i++){
1927 if(strncmp(edev->opt[i], "essid=", 6) == 0){
1928 snprint(buf, sizeof(buf), "essid %s", edev->opt[i]+6);
1930 wifictl(ctlr->wifi, buf, strlen(buf));
1938 iwlpromiscuous(void *arg, int on)
1947 rxon(edev, ctlr->wifi->bss);
1964 /* hop channels for catching beacons */
1965 setled(ctlr, 2, 5, 5);
1966 while(wifi->bss == nil){
1968 if(wifi->bss != nil){
1972 ctlr->channel = 1 + ctlr->channel % 11;
1976 tsleep(&up->sleep, return0, 0, 1000);
1979 /* wait for association */
1980 setled(ctlr, 2, 10, 10);
1981 while((bss = wifi->bss) != nil){
1984 tsleep(&up->sleep, return0, 0, 1000);
1990 /* wait for disassociation */
1992 setled(ctlr, 2, 0, 1);
1993 while((bss = wifi->bss) != nil){
1996 tsleep(&up->sleep, return0, 0, 1000);
2003 iwlattach(Ether *edev)
2013 print("#l%d: %s\n", edev->ctlrno, up->errstr);
2019 if(ctlr->attached == 0){
2020 if((csr32r(ctlr, Gpc) & RfKill) == 0)
2021 error("wifi disabled by switch");
2023 if(ctlr->wifi == nil)
2024 ctlr->wifi = wifiattach(edev, transmit);
2026 if(ctlr->fw == nil){
2027 fw = readfirmware(fwname[ctlr->type]);
2028 print("#l%d: firmware: %s, rev %ux, build %ud, size %ux+%ux+%ux+%ux+%ux\n",
2032 fw->main.text.size, fw->main.data.size,
2033 fw->init.text.size, fw->init.data.size,
2034 fw->boot.text.size);
2038 if((err = reset(ctlr)) != nil)
2040 if((err = boot(ctlr)) != nil)
2043 ctlr->bcastnodeid = -1;
2044 ctlr->bssnodeid = -1;
2050 snprint(name, sizeof(name), "#l%diwl", edev->ctlrno);
2051 kproc(name, iwlproc, edev);
2069 if(ctlr->broken || rx->s == nil || rx->b == nil)
2071 for(hw = get16(rx->s) % Nrx; rx->i != hw; rx->i = (rx->i + 1) % Nrx){
2072 uchar type, flags, idx, qid;
2080 len = get32(d); d += 4;
2087 if((qid & 0x80) == 0 && qid < nelem(ctlr->tx)){
2088 tx = &ctlr->tx[qid];
2095 /* paranoia: clear tx descriptors */
2096 dd = tx->d + idx*Tdscsize;
2097 cc = tx->c + idx*Tcmdsize;
2098 memset(dd, 0, Tdscsize);
2099 memset(cc, 0, Tcmdsize);
2107 if(len < 4 || type == 0)
2112 case 1: /* microcontroller ready */
2113 setfwinfo(ctlr, d, len);
2115 case 24: /* add node done */
2117 case 28: /* tx done */
2119 case 102: /* calibration result (Type5000 only) */
2123 if(idx >= nelem(ctlr->calib.cmd))
2125 if(rbplant(ctlr, rx->i) < 0)
2127 if(ctlr->calib.cmd[idx] != nil)
2128 freeb(ctlr->calib.cmd[idx]);
2131 ctlr->calib.cmd[idx] = b;
2133 case 103: /* calibration done (Type5000 only) */
2134 ctlr->calib.done = 1;
2136 case 130: /* start scan */
2138 case 132: /* stop scan */
2140 case 156: /* rx statistics */
2142 case 157: /* beacon statistics */
2144 case 161: /* state changed */
2146 case 162: /* beacon missed */
2148 case 192: /* rx phy */
2150 case 195: /* rx done */
2155 case 193: /* mpdu rx done */
2158 len = get16(d); d += 4;
2159 if(d + len + 4 > b->lim)
2161 if((get32(d + len) & 3) != 3)
2163 if(ctlr->wifi == nil)
2165 if(rbplant(ctlr, rx->i) < 0)
2169 wifiiq(ctlr->wifi, b);
2171 case 197: /* rx compressed ba */
2174 /* paranoia: clear the descriptor */
2175 memset(b->rp, 0, Rdscsize);
2177 csr32w(ctlr, FhRxWptr, ((hw+Nrx-1) % Nrx) & ~7);
2181 iwlinterrupt(Ureg*, void *arg)
2190 csr32w(ctlr, Imr, 0);
2191 isr = csr32r(ctlr, Isr);
2192 fhisr = csr32r(ctlr, FhIsr);
2193 if(isr == 0xffffffff || (isr & 0xfffffff0) == 0xa5a5a5a0){
2197 if(isr == 0 && fhisr == 0)
2199 csr32w(ctlr, Isr, isr);
2200 csr32w(ctlr, FhIsr, fhisr);
2201 if((isr & (Iswrx | Ifhrx | Irxperiodic)) || (fhisr & Ifhrx))
2205 iprint("#l%d: fatal firmware error\n", edev->ctlrno);
2208 ctlr->wait.m |= isr;
2209 if(ctlr->wait.m & ctlr->wait.w){
2210 ctlr->wait.r = ctlr->wait.m & ctlr->wait.w;
2211 ctlr->wait.m &= ~ctlr->wait.r;
2212 wakeup(&ctlr->wait);
2215 csr32w(ctlr, Imr, ctlr->ie);
2219 static Ctlr *iwlhead, *iwltail;
2227 while(pdev = pcimatch(pdev, 0, 0)) {
2231 if(pdev->ccrb != 2 || pdev->ccru != 0x80)
2233 if(pdev->vid != 0x8086)
2239 case 0x0084: /* WiFi Link 1000 */
2240 case 0x4229: /* WiFi Link 4965 */
2241 case 0x4230: /* WiFi Link 4965 */
2242 case 0x4236: /* WiFi Link 5300 AGN */
2243 case 0x4237: /* Wifi Link 5100 AGN */
2244 case 0x0085: /* Centrino Advanced-N 6205 */
2245 case 0x422b: /* Centrino Ultimate-N 6300 */
2249 /* Clear device-specific "PCI retry timeout" register (41h). */
2250 if(pcicfgr8(pdev, 0x41) != 0)
2251 pcicfgw8(pdev, 0x41, 0);
2253 /* Clear interrupt disable bit. Hardware bug workaround. */
2254 if(pdev->pcr & 0x400){
2255 pdev->pcr &= ~0x400;
2256 pcicfgw16(pdev, PciPCR, pdev->pcr);
2262 ctlr = malloc(sizeof(Ctlr));
2264 print("iwl: unable to alloc Ctlr\n");
2267 ctlr->port = pdev->mem[0].bar & ~0x0F;
2268 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
2270 print("iwl: can't map %8.8luX\n", pdev->mem[0].bar);
2276 ctlr->type = (csr32r(ctlr, Rev) >> 4) & 0xF;
2278 if(fwname[ctlr->type] == nil){
2279 print("iwl: unsupported controller type %d\n", ctlr->type);
2280 vunmap(mem, pdev->mem[0].size);
2286 iwltail->link = ctlr;
2301 for(ctlr = iwlhead; ctlr != nil; ctlr = ctlr->link){
2304 if(edev->port == 0 || edev->port == ctlr->port){
2314 edev->port = ctlr->port;
2315 edev->irq = ctlr->pdev->intl;
2316 edev->tbdf = ctlr->pdev->tbdf;
2318 edev->interrupt = iwlinterrupt;
2319 edev->attach = iwlattach;
2320 edev->ifstat = iwlifstat;
2322 edev->promiscuous = iwlpromiscuous;
2323 edev->multicast = nil;
2326 if(iwlinit(edev) < 0){
2337 addethercard("iwl", iwlpnp);