2 * Intel 8254[340]NN Gigabit Ethernet PCI Controllers
3 * as found on the Intel PRO/1000 series of adapters:
4 * 82543GC Intel PRO/1000 T
5 * 82544EI Intel PRO/1000 XT
6 * 82540EM Intel PRO/1000 MT
12 * finish autonegotiation code;
13 * integrate fiber stuff back in (this ONLY handles
14 * the CAT5 cards at the moment);
15 * add checksum-offload;
16 * add tuning control via ctl file;
17 * this driver is little-endian specific.
20 #include "../port/lib.h"
25 #include "../port/error.h"
26 #include "../port/netif.h"
27 #include "../port/etherif.h"
28 #include "../port/ethermii.h"
31 i82542 = (0x1000<<16)|0x8086,
32 i82543gc = (0x1004<<16)|0x8086,
33 i82544ei = (0x1008<<16)|0x8086,
34 i82544eif = (0x1009<<16)|0x8086,
35 i82544gc = (0x100d<<16)|0x8086,
36 i82540em = (0x100E<<16)|0x8086,
37 i82540eplp = (0x101E<<16)|0x8086,
38 i82545em = (0x100F<<16)|0x8086,
39 i82545gmc = (0x1026<<16)|0x8086,
40 i82547ei = (0x1019<<16)|0x8086,
41 i82547gi = (0x1075<<16)|0x8086,
42 i82541ei = (0x1013<<16)|0x8086,
43 i82541gi = (0x1076<<16)|0x8086,
44 i82541gi2 = (0x1077<<16)|0x8086,
45 i82541pi = (0x107c<<16)|0x8086,
46 i82546gb = (0x1079<<16)|0x8086,
47 i82546eb = (0x1010<<16)|0x8086,
51 Ctrl = 0x00000000, /* Device Control */
52 Ctrldup = 0x00000004, /* Device Control Duplicate */
53 Status = 0x00000008, /* Device Status */
54 Eecd = 0x00000010, /* EEPROM/Flash Control/Data */
55 Ctrlext = 0x00000018, /* Extended Device Control */
56 Mdic = 0x00000020, /* MDI Control */
57 Fcal = 0x00000028, /* Flow Control Address Low */
58 Fcah = 0x0000002C, /* Flow Control Address High */
59 Fct = 0x00000030, /* Flow Control Type */
60 Icr = 0x000000C0, /* Interrupt Cause Read */
61 Ics = 0x000000C8, /* Interrupt Cause Set */
62 Ims = 0x000000D0, /* Interrupt Mask Set/Read */
63 Imc = 0x000000D8, /* Interrupt mask Clear */
64 Rctl = 0x00000100, /* Receive Control */
65 Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
66 Txcw = 0x00000178, /* Transmit Configuration Word */
67 Rxcw = 0x00000180, /* Receive Configuration Word */
68 /* on the oldest cards (8254[23]), the Mta register is at 0x200 */
69 Tctl = 0x00000400, /* Transmit Control */
70 Tipg = 0x00000410, /* Transmit IPG */
71 Tbt = 0x00000448, /* Transmit Burst Timer */
72 Ait = 0x00000458, /* Adaptive IFS Throttle */
73 Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
74 Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
75 Rdfh = 0x00002410, /* Receive data fifo head */
76 Rdft = 0x00002418, /* Receive data fifo tail */
77 Rdfhs = 0x00002420, /* Receive data fifo head saved */
78 Rdfts = 0x00002428, /* Receive data fifo tail saved */
79 Rdfpc = 0x00002430, /* Receive data fifo packet count */
80 Rdbal = 0x00002800, /* Rd Base Address Low */
81 Rdbah = 0x00002804, /* Rd Base Address High */
82 Rdlen = 0x00002808, /* Receive Descriptor Length */
83 Rdh = 0x00002810, /* Receive Descriptor Head */
84 Rdt = 0x00002818, /* Receive Descriptor Tail */
85 Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
86 Rxdctl = 0x00002828, /* Receive Descriptor Control */
87 Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
88 Txdmac = 0x00003000, /* Transfer DMA Control */
89 Ett = 0x00003008, /* Early Transmit Control */
90 Tdfh = 0x00003410, /* Transmit data fifo head */
91 Tdft = 0x00003418, /* Transmit data fifo tail */
92 Tdfhs = 0x00003420, /* Transmit data Fifo Head saved */
93 Tdfts = 0x00003428, /* Transmit data fifo tail saved */
94 Tdfpc = 0x00003430, /* Trasnmit data Fifo packet count */
95 Tdbal = 0x00003800, /* Td Base Address Low */
96 Tdbah = 0x00003804, /* Td Base Address High */
97 Tdlen = 0x00003808, /* Transmit Descriptor Length */
98 Tdh = 0x00003810, /* Transmit Descriptor Head */
99 Tdt = 0x00003818, /* Transmit Descriptor Tail */
100 Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
101 Txdctl = 0x00003828, /* Transmit Descriptor Control */
102 Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
104 Statistics = 0x00004000, /* Start of Statistics Area */
105 Gorcl = 0x88/4, /* Good Octets Received Count */
106 Gotcl = 0x90/4, /* Good Octets Transmitted Count */
107 Torl = 0xC0/4, /* Total Octets Received */
108 Totl = 0xC8/4, /* Total Octets Transmitted */
111 Rxcsum = 0x00005000, /* Receive Checksum Control */
112 Mta = 0x00005200, /* Multicast Table Array */
113 Ral = 0x00005400, /* Receive Address Low */
114 Rah = 0x00005404, /* Receive Address High */
115 Manc = 0x00005820, /* Management Control */
119 Bem = 0x00000002, /* Big Endian Mode */
120 Prior = 0x00000004, /* Priority on the PCI bus */
121 Lrst = 0x00000008, /* Link Reset */
122 Asde = 0x00000020, /* Auto-Speed Detection Enable */
123 Slu = 0x00000040, /* Set Link Up */
124 Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */
125 SspeedMASK = 0x00000300, /* Speed Selection */
127 Sspeed10 = 0x00000000, /* 10Mb/s */
128 Sspeed100 = 0x00000100, /* 100Mb/s */
129 Sspeed1000 = 0x00000200, /* 1000Mb/s */
130 Frcspd = 0x00000800, /* Force Speed */
131 Frcdplx = 0x00001000, /* Force Duplex */
132 SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
134 SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
136 Devrst = 0x04000000, /* Device Reset */
137 Rfce = 0x08000000, /* Receive Flow Control Enable */
138 Tfce = 0x10000000, /* Transmit Flow Control Enable */
139 Vme = 0x40000000, /* VLAN Mode Enable */
143 * can't find Tckok nor Rbcok in any Intel docs,
144 * but even 82543gc docs define Lanid.
147 Lu = 0x00000002, /* Link Up */
148 Lanid = 0x0000000C, /* mask for Lan ID. (function id) */
149 // Tckok = 0x00000004, /* Transmit clock is running */
150 // Rbcok = 0x00000008, /* Receive clock is running */
151 Txoff = 0x00000010, /* Transmission Paused */
152 Tbimode = 0x00000020, /* TBI Mode Indication */
153 LspeedMASK = 0x000000C0, /* Link Speed Setting */
155 Lspeed10 = 0x00000000, /* 10Mb/s */
156 Lspeed100 = 0x00000040, /* 100Mb/s */
157 Lspeed1000 = 0x00000080, /* 1000Mb/s */
158 Mtxckok = 0x00000400, /* MTX clock is running */
159 Pci66 = 0x00000800, /* PCI Bus speed indication */
160 Bus64 = 0x00001000, /* PCI Bus width indication */
161 Pcixmode = 0x00002000, /* PCI-X mode */
162 PcixspeedMASK = 0x0000C000, /* PCI-X bus speed */
164 Pcix66 = 0x00000000, /* 50-66MHz */
165 Pcix100 = 0x00004000, /* 66-100MHz */
166 Pcix133 = 0x00008000, /* 100-133MHz */
169 enum { /* Ctrl and Status */
170 Fd = 0x00000001, /* Full-Duplex */
171 AsdvMASK = 0x00000300,
173 Asdv10 = 0x00000000, /* 10Mb/s */
174 Asdv100 = 0x00000100, /* 100Mb/s */
175 Asdv1000 = 0x00000200, /* 1000Mb/s */
179 Sk = 0x00000001, /* Clock input to the EEPROM */
180 Cs = 0x00000002, /* Chip Select */
181 Di = 0x00000004, /* Data Input to the EEPROM */
182 Do = 0x00000008, /* Data Output from the EEPROM */
183 Areq = 0x00000040, /* EEPROM Access Request */
184 Agnt = 0x00000080, /* EEPROM Access Grant */
185 Eepresent = 0x00000100, /* EEPROM Present */
186 Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */
187 Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */
188 Spi = 0x00002000, /* EEPROM is SPI not Microwire */
192 Gpien = 0x0000000F, /* General Purpose Interrupt Enables */
193 SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */
195 SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */
197 Asdchk = 0x00001000, /* ASD Check */
198 Eerst = 0x00002000, /* EEPROM Reset */
199 Ips = 0x00004000, /* Invert Power State */
200 Spdbyps = 0x00008000, /* Speed Select Bypass */
203 enum { /* EEPROM content offsets */
204 Ea = 0x00, /* Ethernet Address */
205 Cf = 0x03, /* Compatibility Field */
206 Pba = 0x08, /* Printed Board Assembly number */
207 Icw1 = 0x0A, /* Initialization Control Word 1 */
208 Sid = 0x0B, /* Subsystem ID */
209 Svid = 0x0C, /* Subsystem Vendor ID */
210 Did = 0x0D, /* Device ID */
211 Vid = 0x0E, /* Vendor ID */
212 Icw2 = 0x0F, /* Initialization Control Word 2 */
216 MDIdMASK = 0x0000FFFF, /* Data */
218 MDIrMASK = 0x001F0000, /* PHY Register Address */
220 MDIpMASK = 0x03E00000, /* PHY Address */
222 MDIwop = 0x04000000, /* Write Operation */
223 MDIrop = 0x08000000, /* Read Operation */
224 MDIready = 0x10000000, /* End of Transaction */
225 MDIie = 0x20000000, /* Interrupt Enable */
226 MDIe = 0x40000000, /* Error */
229 enum { /* Icr, Ics, Ims, Imc */
230 Txdw = 0x00000001, /* Transmit Descriptor Written Back */
231 Txqe = 0x00000002, /* Transmit Queue Empty */
232 Lsc = 0x00000004, /* Link Status Change */
233 Rxseq = 0x00000008, /* Receive Sequence Error */
234 Rxdmt0 = 0x00000010, /* Rd Minimum Threshold Reached */
235 Rxo = 0x00000040, /* Receiver Overrun */
236 Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
237 Mdac = 0x00000200, /* MDIO Access Completed */
238 Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
239 Gpi0 = 0x00000800, /* General Purpose Interrupts */
246 * The Mdic register isn't implemented on the 82543GC,
247 * the software defined pins are used instead.
248 * These definitions work for the Intel PRO/1000 T Server Adapter.
249 * The direction pin bits are read from the EEPROM.
252 Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */
253 Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */
254 Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */
255 Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */
256 Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */
257 Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */
261 TxcwFd = 0x00000020, /* Full Duplex */
262 TxcwHd = 0x00000040, /* Half Duplex */
263 TxcwPauseMASK = 0x00000180, /* Pause */
265 TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
266 TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
267 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
269 TxcwNpr = 0x00008000, /* Next Page Request */
270 TxcwConfig = 0x40000000, /* Transmit COnfig Control */
271 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
275 Rxword = 0x0000FFFF, /* Data from auto-negotiation process */
276 Rxnocarrier = 0x04000000, /* Carrier Sense indication */
277 Rxinvalid = 0x08000000, /* Invalid Symbol during configuration */
278 Rxchange = 0x10000000, /* Change to the Rxword indication */
279 Rxconfig = 0x20000000, /* /C/ order set reception indication */
280 Rxsync = 0x40000000, /* Lost bit synchronization indication */
281 Anc = 0x80000000, /* Auto Negotiation Complete */
285 Rrst = 0x00000001, /* Receiver Software Reset */
286 Ren = 0x00000002, /* Receiver Enable */
287 Sbp = 0x00000004, /* Store Bad Packets */
288 Upe = 0x00000008, /* Unicast Promiscuous Enable */
289 Mpe = 0x00000010, /* Multicast Promiscuous Enable */
290 Lpe = 0x00000020, /* Long Packet Reception Enable */
291 LbmMASK = 0x000000C0, /* Loopback Mode */
292 LbmOFF = 0x00000000, /* No Loopback */
293 LbmTBI = 0x00000040, /* TBI Loopback */
294 LbmMII = 0x00000080, /* GMII/MII Loopback */
295 LbmXCVR = 0x000000C0, /* Transceiver Loopback */
296 RdtmsMASK = 0x00000300, /* Rd Minimum Threshold Size */
297 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
298 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
299 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
300 MoMASK = 0x00003000, /* Multicast Offset */
301 Mo47b36 = 0x00000000, /* bits [47:36] of received address */
302 Mo46b35 = 0x00001000, /* bits [46:35] of received address */
303 Mo45b34 = 0x00002000, /* bits [45:34] of received address */
304 Mo43b32 = 0x00003000, /* bits [43:32] of received address */
305 Bam = 0x00008000, /* Broadcast Accept Mode */
306 BsizeMASK = 0x00030000, /* Receive Buffer Size */
307 Bsize2048 = 0x00000000, /* Bsex = 0 */
308 Bsize1024 = 0x00010000, /* Bsex = 0 */
309 Bsize512 = 0x00020000, /* Bsex = 0 */
310 Bsize256 = 0x00030000, /* Bsex = 0 */
311 Bsize16384 = 0x00010000, /* Bsex = 1 */
312 Vfe = 0x00040000, /* VLAN Filter Enable */
313 Cfien = 0x00080000, /* Canonical Form Indicator Enable */
314 Cfi = 0x00100000, /* Canonical Form Indicator value */
315 Dpf = 0x00400000, /* Discard Pause Frames */
316 Pmcf = 0x00800000, /* Pass MAC Control Frames */
317 Bsex = 0x02000000, /* Buffer Size Extension */
318 Secrc = 0x04000000, /* Strip CRC from incoming packet */
322 Trst = 0x00000001, /* Transmitter Software Reset */
323 Ten = 0x00000002, /* Transmit Enable */
324 Psp = 0x00000008, /* Pad Short Packets */
325 CtMASK = 0x00000FF0, /* Collision Threshold */
327 ColdMASK = 0x003FF000, /* Collision Distance */
329 Swxoff = 0x00400000, /* Sofware XOFF Transmission */
330 Pbe = 0x00800000, /* Packet Burst Enable */
331 Rtlc = 0x01000000, /* Re-transmit on Late Collision */
332 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
335 enum { /* [RT]xdctl */
336 PthreshMASK = 0x0000003F, /* Prefetch Threshold */
338 HthreshMASK = 0x00003F00, /* Host Threshold */
340 WthreshMASK = 0x003F0000, /* Writeback Threshold */
342 Gran = 0x01000000, /* Granularity */
343 LthreshMASK = 0xFE000000, /* Low Threshold */
348 PcssMASK = 0x000000FF, /* Packet Checksum Start */
350 Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
351 Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
355 Arpen = 0x00002000, /* Enable ARP Request Filtering */
358 enum { /* Receive Delay Timer Ring */
359 DelayMASK = 0x0000FFFF, /* delay timer in 1.024nS increments */
361 Fpd = 0x80000000, /* Flush partial Descriptor Block */
364 typedef struct Rd { /* Receive Descriptor */
373 enum { /* Rd status */
374 Rdd = 0x01, /* Descriptor Done */
375 Reop = 0x02, /* End of Packet */
376 Ixsm = 0x04, /* Ignore Checksum Indication */
377 Vp = 0x08, /* Packet is 802.1Q (matched VET) */
378 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
379 Ipcs = 0x40, /* IP Checksum Calculated on Packet */
380 Pif = 0x80, /* Passed in-exact filter */
383 enum { /* Rd errors */
384 Ce = 0x01, /* CRC Error or Alignment Error */
385 Se = 0x02, /* Symbol Error */
386 Seq = 0x04, /* Sequence Error */
387 Cxe = 0x10, /* Carrier Extension Error */
388 Tcpe = 0x20, /* TCP/UDP Checksum Error */
389 Ipe = 0x40, /* IP Checksum Error */
390 Rxe = 0x80, /* RX Data Error */
393 typedef struct Td Td;
394 struct Td { /* Transmit Descriptor */
396 uint addr[2]; /* Data */
397 struct { /* Context */
410 enum { /* Td control */
411 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
413 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
414 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
415 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
416 Teop = 0x01000000, /* End of Packet (DD) */
417 PtypeIP = 0x02000000, /* IP Packet Type (CD) */
418 Ifcs = 0x02000000, /* Insert FCS (DD) */
419 Tse = 0x04000000, /* TCP Segmentation Enable */
420 Rs = 0x08000000, /* Report Status */
421 Rps = 0x10000000, /* Report Status Sent */
422 Dext = 0x20000000, /* Descriptor Extension */
423 Vle = 0x40000000, /* VLAN Packet Enable */
424 Ide = 0x80000000, /* Interrupt Delay Enable */
427 enum { /* Td status */
428 Tdd = 0x00000001, /* Descriptor Done */
429 Ec = 0x00000002, /* Excess Collisions */
430 Lc = 0x00000004, /* Late Collision */
431 Tu = 0x00000008, /* Transmit Underrun */
432 Iixsm = 0x00000100, /* Insert IP Checksum */
433 Itxsm = 0x00000200, /* Insert TCP/UDP Checksum */
434 HdrlenMASK = 0x0000FF00, /* Header Length (Tse) */
436 VlanMASK = 0x0FFF0000, /* VLAN Identifier */
438 Tcfi = 0x10000000, /* Canonical Form Indicator */
439 PriMASK = 0xE0000000, /* User Priority */
441 MssMASK = 0xFFFF0000, /* Maximum Segment Size (Tse) */
446 Nrd = 256, /* multiple of 8 */
447 Ntd = 64, /* multiple of 8 */
448 Nrb = 1024, /* private receive buffers per Ctlr */
452 typedef struct Ctlr Ctlr;
453 typedef struct Ctlr {
464 QLock alock; /* attach */
465 void* alloc; /* receive/transmit descriptors */
471 int im; /* interrupt mask */
480 uint statistics[Nstatistics];
491 uchar ra[Eaddrlen]; /* receive address */
492 ulong mta[128]; /* multicast table array */
497 Rd* rdba; /* receive descriptor base address */
498 Block** rb; /* receive buffers */
499 int rdh; /* receive descriptor head */
500 int rdt; /* receive descriptor tail */
501 int rdtr; /* receive delay timer ring value */
506 Td* tdba; /* transmit descriptor base address */
507 Block** tb; /* transmit buffers */
508 int tdh; /* transmit descriptor head */
509 int tdt; /* transmit descriptor tail */
516 #define csr32r(c, r) (*((c)->nic+((r)/4)))
517 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
519 static Ctlr* igbectlrhead;
520 static Ctlr* igbectlrtail;
522 static char* statistics[Nstatistics] = {
529 "Excessive Collisions",
530 "Multiple Collision",
538 "Carrier Extension Error",
539 "Receive Error Length",
545 "FC Received Unsupported",
546 "Packets Received (64 Bytes)",
547 "Packets Received (65-127 Bytes)",
548 "Packets Received (128-255 Bytes)",
549 "Packets Received (256-511 Bytes)",
550 "Packets Received (512-1023 Bytes)",
551 "Packets Received (1024-1522 Bytes)",
552 "Good Packets Received",
553 "Broadcast Packets Received",
554 "Multicast Packets Received",
555 "Good Packets Transmitted",
557 "Good Octets Received",
559 "Good Octets Transmitted",
563 "Receive No Buffers",
571 "Total Octets Received",
573 "Total Octets Transmitted",
575 "Total Packets Received",
576 "Total Packets Transmitted",
577 "Packets Transmitted (64 Bytes)",
578 "Packets Transmitted (65-127 Bytes)",
579 "Packets Transmitted (128-255 Bytes)",
580 "Packets Transmitted (256-511 Bytes)",
581 "Packets Transmitted (512-1023 Bytes)",
582 "Packets Transmitted (1024-1522 Bytes)",
583 "Multicast Packets Transmitted",
584 "Broadcast Packets Transmitted",
585 "TCP Segmentation Context Transmitted",
586 "TCP Segmentation Context Fail",
590 igbeifstat(Ether* edev, void* a, long n, ulong offset)
597 p = smalloc(READSTR);
601 for(i = 0; i < Nstatistics; i++){
602 r = csr32r(ctlr, Statistics+i*4);
603 if((s = statistics[i]) == nil)
611 ruvl += ((uvlong)csr32r(ctlr, Statistics+(i+1)*4))<<32;
613 tuvl += ctlr->statistics[i];
614 tuvl += ((uvlong)ctlr->statistics[i+1])<<32;
617 ctlr->statistics[i] = tuvl;
618 ctlr->statistics[i+1] = tuvl>>32;
619 l += snprint(p+l, READSTR-l, "%s: %llud %llud\n",
625 ctlr->statistics[i] += r;
626 if(ctlr->statistics[i] == 0)
628 l += snprint(p+l, READSTR-l, "%s: %ud %ud\n",
629 s, ctlr->statistics[i], r);
634 l += snprint(p+l, READSTR-l, "lintr: %ud %ud\n",
635 ctlr->lintr, ctlr->lsleep);
636 l += snprint(p+l, READSTR-l, "rintr: %ud %ud\n",
637 ctlr->rintr, ctlr->rsleep);
638 l += snprint(p+l, READSTR-l, "tintr: %ud %ud\n",
639 ctlr->tintr, ctlr->txdw);
640 l += snprint(p+l, READSTR-l, "ixcs: %ud %ud %ud\n",
641 ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
642 l += snprint(p+l, READSTR-l, "rdtr: %ud\n", ctlr->rdtr);
643 l += snprint(p+l, READSTR-l, "Ctrlext: %08x\n", csr32r(ctlr, Ctrlext));
645 l += snprint(p+l, READSTR-l, "eeprom:");
646 for(i = 0; i < 0x40; i++){
647 if(i && ((i & 0x07) == 0))
648 l += snprint(p+l, READSTR-l, "\n ");
649 l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
651 l += snprint(p+l, READSTR-l, "\n");
653 if(ctlr->mii != nil && ctlr->mii->curphy != nil){
654 l += snprint(p+l, READSTR-l, "phy: ");
655 for(i = 0; i < NMiiPhyr; i++){
656 if(i && ((i & 0x07) == 0))
657 l += snprint(p+l, READSTR-l, "\n ");
658 r = miimir(ctlr->mii, i);
659 l += snprint(p+l, READSTR-l, " %4.4uX", r);
661 snprint(p+l, READSTR-l, "\n");
663 n = readstr(offset, a, n, p);
665 qunlock(&ctlr->slock);
674 static Cmdtab igbectlmsg[] = {
679 igbectl(Ether* edev, void* buf, long n)
687 if((ctlr = edev->ctlr) == nil)
690 cb = parsecmd(buf, n);
696 ct = lookupcmd(cb, igbectlmsg, nelem(igbectlmsg));
699 v = strtol(cb->f[1], &p, 0);
700 if(v < 0 || p == cb->f[1] || v > 0xFFFF)
703 csr32w(ctlr, Rdtr, Fpd|v);
713 igbepromiscuous(void* arg, int on)
722 rctl = csr32r(ctlr, Rctl);
729 csr32w(ctlr, Rctl, rctl|Mpe); /* temporarily keep Mpe on */
733 igbemulticast(void* arg, uchar* addr, int add)
743 bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
745 * multiple ether addresses can hash to the same filter bit,
746 * so it's never safe to clear a filter bit.
747 * if we want to clear filter bits, we need to keep track of
748 * all the multicast addresses in use, clear all the filter bits,
749 * then set the ones corresponding to in-use addresses.
752 ctlr->mta[x] |= 1<<bit;
754 // ctlr->mta[x] &= ~(1<<bit);
756 csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
760 igbeim(Ctlr* ctlr, int im)
762 ilock(&ctlr->imlock);
764 csr32w(ctlr, Ims, ctlr->im);
765 iunlock(&ctlr->imlock);
771 return ((Ctlr*)ctlr)->lim != 0;
787 if(ctlr->mii == nil || ctlr->mii->curphy == nil)
792 * logic to manage status change,
793 * this is incomplete but should work
794 * one time to set up the hardware.
796 * MiiPhy.speed, etc. should be in Mii.
798 if(miistatus(ctlr->mii) < 0)
802 phy = ctlr->mii->curphy;
803 ctrl = csr32r(ctlr, Ctrl);
811 ctrl &= ~(SspeedMASK|Ilos|Fd);
812 ctrl |= Frcdplx|Frcspd;
813 if(phy->speed == 1000)
815 else if(phy->speed == 100)
832 * Collision Distance.
834 r = csr32r(ctlr, Tctl);
840 csr32w(ctlr, Tctl, r);
849 csr32w(ctlr, Ctrl, ctrl);
856 sleep(&ctlr->lrendez, igbelim, ctlr);
861 igbetxinit(Ctlr* ctlr)
866 csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT));
890 csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
891 csr32w(ctlr, Ait, 0);
892 csr32w(ctlr, Txdmac, 0);
894 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
895 csr32w(ctlr, Tdbah, 0);
896 csr32w(ctlr, Tdlen, ctlr->ntd*sizeof(Td));
897 ctlr->tdh = PREV(0, ctlr->ntd);
898 csr32w(ctlr, Tdh, 0);
900 csr32w(ctlr, Tdt, 0);
902 for(i = 0; i < ctlr->ntd; i++){
903 if((bp = ctlr->tb[i]) != nil){
907 memset(&ctlr->tdba[i], 0, sizeof(Td));
909 ctlr->tdfree = ctlr->ntd;
911 csr32w(ctlr, Tidv, 128);
912 r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
927 r = csr32r(ctlr, Txdctl);
929 r |= Gran|(4<<WthreshSHIFT);
931 csr32w(ctlr, Tadv, 64);
935 csr32w(ctlr, Txdctl, r);
937 r = csr32r(ctlr, Tctl);
939 csr32w(ctlr, Tctl, r);
943 igbetransmit(Ether* edev)
955 * Free any completed packets
958 while(NEXT(tdh, ctlr->ntd) != csr32r(ctlr, Tdh)){
959 if((bp = ctlr->tb[tdh]) != nil){
963 memset(&ctlr->tdba[tdh], 0, sizeof(Td));
964 tdh = NEXT(tdh, ctlr->ntd);
969 * Try to fill the ring back up.
972 while(NEXT(tdt, ctlr->ntd) != tdh){
973 if((bp = qget(edev->oq)) == nil)
975 td = &ctlr->tdba[tdt];
976 td->addr[0] = PCIWADDR(bp->rp);
977 td->control = ((BLEN(bp) & LenMASK)<<LenSHIFT);
978 td->control |= Dext|Ifcs|Teop|DtypeDD;
980 tdt = NEXT(tdt, ctlr->ntd);
981 if(NEXT(tdt, ctlr->ntd) == tdh){
985 csr32w(ctlr, Tdt, tdt);
990 csr32w(ctlr, Tdt, tdt);
993 iunlock(&ctlr->tlock);
997 igbereplenish(Ctlr* ctlr)
1004 while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
1005 rd = &ctlr->rdba[rdt];
1006 if(ctlr->rb[rdt] == nil){
1008 bp->rp = bp->lim - Rbsz;
1011 rd->addr[0] = PCIWADDR(bp->rp);
1016 rdt = NEXT(rdt, ctlr->nrd);
1020 csr32w(ctlr, Rdt, rdt);
1024 igberxinit(Ctlr* ctlr)
1029 /* temporarily keep Mpe on */
1030 csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF|Mpe);
1032 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
1033 csr32w(ctlr, Rdbah, 0);
1034 csr32w(ctlr, Rdlen, ctlr->nrd*sizeof(Rd));
1036 csr32w(ctlr, Rdh, 0);
1038 csr32w(ctlr, Rdt, 0);
1040 csr32w(ctlr, Rdtr, Fpd|0);
1042 for(i = 0; i < ctlr->nrd; i++){
1043 if((bp = ctlr->rb[i]) != nil){
1048 igbereplenish(ctlr);
1061 csr32w(ctlr, Radv, 64);
1064 csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
1067 * Disable checksum offload as it has known bugs.
1069 csr32w(ctlr, Rxcsum, ETHERHDRSIZE<<PcssSHIFT);
1075 return ((Ctlr*)ctlr)->rim != 0;
1079 igberproc(void* arg)
1091 r = csr32r(ctlr, Rctl);
1093 csr32w(ctlr, Rctl, r);
1100 igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
1102 sleep(&ctlr->rrendez, igberim, ctlr);
1106 rd = &ctlr->rdba[rdh];
1108 if(!(rd->status & Rdd))
1112 * Accept eop packets with no errors.
1113 * With no errors and the Ixsm bit set,
1114 * the descriptor status Tpcs and Ipcs bits give
1115 * an indication of whether the checksums were
1116 * calculated and valid.
1118 if((rd->status & Reop) && rd->errors == 0){
1120 ctlr->rb[rdh] = nil;
1121 bp->wp += rd->length;
1123 if(!(rd->status & Ixsm)){
1125 if(rd->status & Ipcs){
1127 * IP checksum calculated
1128 * (and valid as errors == 0).
1133 if(rd->status & Tcpcs){
1135 * TCP/UDP checksum calculated
1136 * (and valid as errors == 0).
1139 bp->flag |= Btcpck|Budpck;
1141 bp->checksum = rd->checksum;
1146 else if(ctlr->rb[rdh] != nil){
1147 freeb(ctlr->rb[rdh]);
1148 ctlr->rb[rdh] = nil;
1151 memset(rd, 0, sizeof(Rd));
1154 rdh = NEXT(rdh, ctlr->nrd);
1158 if(ctlr->rdfree < ctlr->nrd/2 || (ctlr->rim & Rxdmt0))
1159 igbereplenish(ctlr);
1164 igbeattach(Ether* edev)
1167 char name[KNAMELEN];
1170 ctlr->edev = edev; /* point back to Ether* */
1171 qlock(&ctlr->alock);
1172 if(ctlr->alloc != nil){ /* already allocated? */
1173 qunlock(&ctlr->alock);
1177 ctlr->nrd = ROUND(Nrd, 8);
1178 ctlr->ntd = ROUND(Ntd, 8);
1179 ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 127);
1180 if(ctlr->alloc == nil){
1181 print("igbe: can't allocate ctlr->alloc\n");
1182 qunlock(&ctlr->alock);
1185 ctlr->rdba = (Rd*)ROUNDUP((uintptr)ctlr->alloc, 128);
1186 ctlr->tdba = (Td*)(ctlr->rdba+ctlr->nrd);
1188 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
1189 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
1190 if (ctlr->rb == nil || ctlr->tb == nil) {
1191 print("igbe: can't allocate ctlr->rb or ctlr->tb\n");
1192 qunlock(&ctlr->alock);
1203 qunlock(&ctlr->alock);
1207 snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno);
1208 kproc(name, igbelproc, edev);
1210 snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
1211 kproc(name, igberproc, edev);
1215 qunlock(&ctlr->alock);
1220 igbeinterrupt(Ureg*, void* arg)
1229 ilock(&ctlr->imlock);
1230 csr32w(ctlr, Imc, ~0);
1234 while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){
1237 ctlr->lim = icr & Lsc;
1238 wakeup(&ctlr->lrendez);
1241 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq)){
1242 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq);
1243 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq);
1244 wakeup(&ctlr->rrendez);
1255 csr32w(ctlr, Ims, im);
1256 iunlock(&ctlr->imlock);
1263 i82543mdior(Ctlr* ctlr, int n)
1265 int ctrl, data, i, r;
1268 * Read n bits from the Management Data I/O Interface.
1270 ctrl = csr32r(ctlr, Ctrl);
1271 r = (ctrl & ~Mddo)|Mdco;
1273 for(i = n-1; i >= 0; i--){
1274 if(csr32r(ctlr, Ctrl) & Mdd)
1276 csr32w(ctlr, Ctrl, Mdc|r);
1277 csr32w(ctlr, Ctrl, r);
1279 csr32w(ctlr, Ctrl, ctrl);
1285 i82543mdiow(Ctlr* ctlr, int bits, int n)
1290 * Write n bits to the Management Data I/O Interface.
1292 ctrl = csr32r(ctlr, Ctrl);
1294 for(i = n-1; i >= 0; i--){
1299 csr32w(ctlr, Ctrl, Mdc|r);
1300 csr32w(ctlr, Ctrl, r);
1302 csr32w(ctlr, Ctrl, ctrl);
1308 i82543miimir(Mii* mii, int pa, int ra)
1316 * MII Management Interface Read.
1319 * ST+OP+PHYAD+REGAD;
1320 * TA + 16 data bits.
1322 i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1323 i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
1324 data = i82543mdior(ctlr, 18);
1329 return data & 0xFFFF;
1333 i82543miimiw(Mii* mii, int pa, int ra, int data)
1340 * MII Management Interface Write.
1343 * ST+OP+PHYAD+REGAD+TA + 16 data bits;
1346 i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1348 data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
1349 i82543mdiow(ctlr, data, 32);
1355 igbemiimir(Mii* mii, int pa, int ra)
1362 csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
1364 for(timo = 64; timo; timo--){
1365 mdic = csr32r(ctlr, Mdic);
1366 if(mdic & (MDIe|MDIready))
1371 if((mdic & (MDIe|MDIready)) == MDIready)
1372 return mdic & 0xFFFF;
1377 igbemiimiw(Mii* mii, int pa, int ra, int data)
1385 csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
1387 for(timo = 64; timo; timo--){
1388 mdic = csr32r(ctlr, Mdic);
1389 if(mdic & (MDIe|MDIready))
1393 if((mdic & (MDIe|MDIready)) == MDIready)
1404 r = csr32r(ctlr, Status);
1407 if((ctlr->mii = malloc(sizeof(Mii))) == nil)
1409 ctlr->mii->ctlr = ctlr;
1411 ctrl = csr32r(ctlr, Ctrl);
1416 ctrl |= Frcdplx|Frcspd;
1417 csr32w(ctlr, Ctrl, ctrl);
1420 * The reset pin direction (Mdro) should already
1421 * be set from the EEPROM load.
1422 * If it's not set this configuration is unexpected
1425 r = csr32r(ctlr, Ctrlext);
1427 print("igbe: 82543gc Mdro not set\n");
1430 csr32w(ctlr, Ctrlext, r);
1432 r = csr32r(ctlr, Ctrlext);
1434 csr32w(ctlr, Ctrlext, r);
1436 r = csr32r(ctlr, Ctrlext);
1438 csr32w(ctlr, Ctrlext, r);
1441 ctlr->mii->mir = i82543miimir;
1442 ctlr->mii->miw = i82543miimiw;
1459 ctrl &= ~(Frcdplx|Frcspd);
1460 csr32w(ctlr, Ctrl, ctrl);
1461 ctlr->mii->mir = igbemiimir;
1462 ctlr->mii->miw = igbemiimiw;
1470 if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
1476 // print("oui %X phyno %d\n", phy->oui, phy->phyno);
1479 * 8254X-specific PHY registers not in 802.3:
1480 * 0x10 PHY specific control
1481 * 0x14 extended PHY specific control
1482 * Set appropriate values then reset the PHY to have
1496 r = miimir(ctlr->mii, 16);
1497 r |= 0x0800; /* assert CRS on Tx */
1498 r |= 0x0060; /* auto-crossover all speeds */
1499 r |= 0x0002; /* polarity reversal enabled */
1500 miimiw(ctlr->mii, 16, r);
1502 r = miimir(ctlr->mii, 20);
1503 r |= 0x0070; /* +25MHz clock */
1505 r |= 0x0100; /* 1x downshift */
1506 miimiw(ctlr->mii, 20, r);
1508 miireset(ctlr->mii);
1510 if(ctlr->txcw & TxcwPs)
1512 if(ctlr->txcw & TxcwAs)
1514 miiane(ctlr->mii, ~0, p, ~0);
1521 at93c46io(Ctlr* ctlr, char* op, int data)
1524 int i, loop, eecd, r;
1526 eecd = csr32r(ctlr, Eecd);
1531 for(p = op; *p != '\0'; p++){
1537 case ':': /* start of loop */
1538 loop = strtol(p+1, &lp, 0)-1;
1544 case ';': /* end of loop */
1553 case 'C': /* assert clock */
1556 case 'c': /* deassert clock */
1559 case 'D': /* next bit in 'data' byte */
1562 if(data & (1<<loop))
1567 case 'O': /* collect data output */
1568 i = (csr32r(ctlr, Eecd) & Do) != 0;
1580 case 'I': /* assert data input */
1583 case 'i': /* deassert data input */
1586 case 'S': /* enable chip select */
1589 case 's': /* disable chip select */
1593 csr32w(ctlr, Eecd, eecd);
1605 at93c46r(Ctlr* ctlr)
1609 int addr, areq, bits, data, eecd, i;
1612 eecd = csr32r(ctlr, Eecd);
1631 csr32w(ctlr, Eecd, eecd|Areq);
1632 for(i = 0; i < 1000; i++){
1633 if((eecd = csr32r(ctlr, Eecd)) & Agnt)
1638 print("igbe: not granted EEPROM access\n");
1645 for(i = 0; i < 1000; i++){
1646 at93c46io(ctlr, "H :8HDCc;", 0x05);
1647 data = at93c46io(ctlr, "h :8COc;", 0);
1653 at93c46io(ctlr, "Ss", 0);
1656 print("igbe: SPI EEPROM not ready\n");
1660 at93c46io(ctlr, "Ss H :8HDCc;", 0x03);
1666 snprint(rop, sizeof(rop), "H :%dHDCc;", bits);
1667 if(at93c46io(ctlr, rop, 0) != 0){
1668 print("igbe: can't set EEPROM address 0x00\n");
1672 for(addr = 0; addr < 0x40; addr++){
1673 data = at93c46io(ctlr, "h :16COc;", 0);
1674 ctlr->eeprom[addr] = (data >> 8) | (data << 8);
1675 sum += ctlr->eeprom[addr];
1678 if(eecd & (Eeszaddr|Eesz256))
1682 snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
1684 for(addr = 0; addr < 0x40; addr++){
1686 * Read a word at address 'addr' from the Atmel AT93C46
1687 * 3-Wire Serial EEPROM or compatible. The EEPROM access is
1688 * controlled by 4 bits in Eecd. See the AT93C46 datasheet
1689 * for protocol details.
1691 if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
1692 print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
1695 data = at93c46io(ctlr, ":16COc;", 0);
1696 at93c46io(ctlr, "sic", 0);
1697 ctlr->eeprom[addr] = data;
1704 csr32w(ctlr, Eecd, eecd & ~Areq);
1709 igbedetach(Ctlr* ctlr)
1714 * Perform a device reset to get the chip back to the
1715 * power-on state, followed by an EEPROM reset to read
1716 * the defaults for some internal registers.
1718 csr32w(ctlr, Imc, ~0);
1719 csr32w(ctlr, Rctl, 0);
1720 csr32w(ctlr, Tctl, 0);
1724 csr32w(ctlr, Ctrl, Devrst);
1726 for(timeo = 0; timeo < 1000; timeo++){
1727 if(!(csr32r(ctlr, Ctrl) & Devrst))
1731 if(csr32r(ctlr, Ctrl) & Devrst)
1733 r = csr32r(ctlr, Ctrlext);
1734 csr32w(ctlr, Ctrlext, r|Eerst);
1736 for(timeo = 0; timeo < 1000; timeo++){
1737 if(!(csr32r(ctlr, Ctrlext) & Eerst))
1741 if(csr32r(ctlr, Ctrlext) & Eerst)
1757 r = csr32r(ctlr, Manc);
1759 csr32w(ctlr, Manc, r);
1763 csr32w(ctlr, Imc, ~0);
1765 for(timeo = 0; timeo < 1000; timeo++){
1766 if(!csr32r(ctlr, Icr))
1770 if(csr32r(ctlr, Icr))
1777 igbeshutdown(Ether* ether)
1779 igbedetach(ether->ctlr);
1783 igbereset(Ctlr* ctlr)
1785 int ctrl, i, pause, r, swdpio, txcw;
1787 if(igbedetach(ctlr))
1791 * Read the EEPROM, validate the checksum
1792 * then get the device back to a power-on state.
1794 if((r = at93c46r(ctlr)) != 0xBABA){
1795 print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
1800 * Snarf and set up the receive addresses.
1801 * There are 16 addresses. The first should be the MAC address.
1802 * The others are cleared and not marked valid (MS bit of Rah).
1804 if ((ctlr->id == i82546gb || ctlr->id == i82546eb) &&
1805 BUSFNO(ctlr->pcidev->tbdf) == 1)
1806 ctlr->eeprom[Ea+2] += 0x100; /* second interface */
1807 if(ctlr->id == i82541gi && ctlr->eeprom[Ea] == 0xFFFF)
1808 ctlr->eeprom[Ea] = 0xD000;
1809 for(i = Ea; i < Eaddrlen/2; i++){
1810 ctlr->ra[2*i] = ctlr->eeprom[i];
1811 ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
1813 /* lan id seems to vary on 82543gc; don't use it */
1814 if (ctlr->id != i82543gc) {
1815 r = (csr32r(ctlr, Status) & Lanid) >> 2;
1816 ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */
1819 r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
1820 csr32w(ctlr, Ral, r);
1821 r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
1822 csr32w(ctlr, Rah, r);
1823 for(i = 1; i < 16; i++){
1824 csr32w(ctlr, Ral+i*8, 0);
1825 csr32w(ctlr, Rah+i*8, 0);
1829 * Clear the Multicast Table Array.
1830 * It's a 4096 bit vector accessed as 128 32-bit registers.
1832 memset(ctlr->mta, 0, sizeof(ctlr->mta));
1833 for(i = 0; i < 128; i++)
1834 csr32w(ctlr, Mta+i*4, 0);
1837 * Just in case the Eerst didn't load the defaults
1838 * (doesn't appear to fully on the 82543GC), do it manually.
1840 if (ctlr->id == i82543gc) {
1841 txcw = csr32r(ctlr, Txcw);
1842 txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
1843 ctrl = csr32r(ctlr, Ctrl);
1844 ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
1846 if(ctlr->eeprom[Icw1] & 0x0400){
1850 if(ctlr->eeprom[Icw1] & 0x0200)
1852 if(ctlr->eeprom[Icw1] & 0x0010)
1854 if(ctlr->eeprom[Icw1] & 0x0800)
1856 swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
1857 ctrl |= swdpio<<SwdpioloSHIFT;
1858 csr32w(ctlr, Ctrl, ctrl);
1860 ctrl = csr32r(ctlr, Ctrlext);
1861 ctrl &= ~(Ips|SwdpiohiMASK);
1862 swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
1863 if(ctlr->eeprom[Icw1] & 0x1000)
1865 ctrl |= swdpio<<SwdpiohiSHIFT;
1866 csr32w(ctlr, Ctrlext, ctrl);
1868 if(ctlr->eeprom[Icw2] & 0x0800)
1870 pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
1871 txcw |= pause<<TxcwPauseSHIFT;
1874 ctlr->fcrtl = 0x00002000;
1875 ctlr->fcrth = 0x00004000;
1876 txcw |= TxcwAs|TxcwPs;
1879 ctlr->fcrtl = 0x00002000;
1880 ctlr->fcrth = 0x00004000;
1889 csr32w(ctlr, Txcw, txcw);
1894 * Flow control - values from the datasheet.
1896 csr32w(ctlr, Fcal, 0x00C28001);
1897 csr32w(ctlr, Fcah, 0x00000100);
1898 csr32w(ctlr, Fct, 0x00008808);
1899 csr32w(ctlr, Fcttv, 0x00000100);
1901 csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1902 csr32w(ctlr, Fcrth, ctlr->fcrth);
1904 if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0)
1919 while(p = pcimatch(p, 0, 0)){
1920 if(p->ccrb != 0x02 || p->ccru != 0)
1923 switch((p->did<<16)|p->vid){
1945 mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
1947 print("igbe: can't map %8.8luX\n", p->mem[0].bar);
1950 cls = pcicfgr8(p, PciCLS);
1953 print("igbe: p->cls %#ux, setting to 0x10\n", p->cls);
1955 pcicfgw8(p, PciCLS, p->cls);
1961 ctlr = malloc(sizeof(Ctlr));
1963 print("igbe: can't allocate memory\n");
1966 ctlr->port = p->mem[0].bar & ~0x0F;
1969 ctlr->id = (p->did<<16)|p->vid;
1973 if(igbereset(ctlr)){
1975 vunmap(mem, p->mem[0].size);
1980 if(igbectlrhead != nil)
1981 igbectlrtail->next = ctlr;
1983 igbectlrhead = ctlr;
1984 igbectlrtail = ctlr;
1989 igbepnp(Ether* edev)
1993 if(igbectlrhead == nil)
1997 * Any adapter matches if no edev->port is supplied,
1998 * otherwise the ports must match.
2000 for(ctlr = igbectlrhead; ctlr != nil; ctlr = ctlr->next){
2003 if(edev->port == 0 || edev->port == ctlr->port){
2012 edev->port = ctlr->port;
2013 edev->irq = ctlr->pcidev->intl;
2014 edev->tbdf = ctlr->pcidev->tbdf;
2016 memmove(edev->ea, ctlr->ra, Eaddrlen);
2019 * Linkage to the generic ethernet driver.
2021 edev->attach = igbeattach;
2022 edev->transmit = igbetransmit;
2023 edev->ifstat = igbeifstat;
2024 edev->ctl = igbectl;
2027 edev->promiscuous = igbepromiscuous;
2028 edev->shutdown = igbeshutdown;
2029 edev->multicast = igbemulticast;
2031 intrenable(edev->irq, igbeinterrupt, edev, edev->tbdf, edev->name);
2039 addethercard("i82543", igbepnp);
2040 addethercard("igbe", igbepnp);