4 * proper fatal error handling
11 #include "../port/lib.h"
16 #include "../port/error.h"
17 #include "../port/netif.h"
21 #define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
23 typedef struct Ctlr Ctlr;
29 /* One Ring to find them, One Ring to bring them all and in the darkness bind them */
30 ulong *recvret, *recvprod, *sendr;
32 ulong recvreti, recvprodi, sendri, sendcleani;
38 RecvRetRingLen = 0x200,
39 RecvProdRingLen = 0x200,
48 PowerControlStatus = 0x4C,
55 EnablePCIStateRegister = 1<<4,
56 EnableClockControlRegister = 1<<5,
57 IndirectAccessEnable = 1<<7,
61 DMAWatermarkMask = ~(7<<19),
62 DMAWatermarkValue = 3<<19,
65 MemoryWindowData = 0x84,
70 InterruptMailbox = 0x204,
72 RecvProdBDRingIndex = 0x26c,
73 RecvBDRetRingIndex = 0x284,
74 SendBDRingHostIndex = 0x304,
77 MACPortMask = ~((1<<3)|(1<<2)),
80 MACEnable = (1<<23) | (1<<22) | (1<<21) | (1 << 15) | (1 << 14) | (1<<12) | (1<<11),
83 MACEventStatus = 0x404,
84 MACEventEnable = 0x408,
86 EthernetRandomBackoff = 0x438,
91 ReceiveMACMode = 0x468,
92 TransmitMACMode = 0x45C,
93 TransmitMACLengths = 0x464,
97 ReceiveRulesConfiguration = 0x500,
98 LowWatermarkMaximum = 0x504,
99 LowWatermarkMaxMask = ~0xFFFF,
100 LowWatermarkMaxValue = 2,
102 SendDataInitiatorMode = 0xC00,
103 SendInitiatorConfiguration = 0x0C08,
105 SendInitiatorMask = 0x0C0C,
107 SendDataCompletionMode = 0x1000,
108 SendBDSelectorMode = 0x1400,
109 SendBDInitiatorMode = 0x1800,
110 SendBDCompletionMode = 0x1C00,
112 ReceiveListPlacementMode = 0x2000,
113 ReceiveListPlacement = 0x2010,
114 ReceiveListPlacementConfiguration = 0x2014,
116 ReceiveListPlacementMask = 0x2018,
118 ReceiveDataBDInitiatorMode = 0x2400,
119 ReceiveBDHostAddr = 0x2450,
120 ReceiveBDFlags = 0x2458,
121 ReceiveBDNIC = 0x245C,
122 ReceiveDataCompletionMode = 0x2800,
123 ReceiveBDInitiatorMode = 0x2C00,
124 ReceiveBDRepl = 0x2C18,
126 ReceiveBDCompletionMode = 0x3000,
127 HostCoalescingMode = 0x3C00,
128 HostCoalescingRecvTicks = 0x3C08,
129 HostCoalescingSendTicks = 0x3C0C,
130 RecvMaxCoalescedFrames = 0x3C10,
131 SendMaxCoalescedFrames = 0x3C14,
132 RecvMaxCoalescedFramesInt = 0x3C20,
133 SendMaxCoalescedFramesInt = 0x3C24,
134 StatusBlockHostAddr = 0x3C38,
135 FlowAttention = 0x3C48,
137 MemArbiterMode = 0x4000,
139 BufferManMode = 0x4400,
141 MBUFLowWatermark = 0x4414,
142 MBUFHighWatermark = 0x4418,
144 ReadDMAMode = 0x4800,
145 ReadDMAStatus = 0x4804,
146 WriteDMAMode = 0x4C00,
147 WriteDMAStatus = 0x4C04,
153 ModeControl = 0x6800,
154 ByteWordSwap = (1<<4)|(1<<5)|(1<<2),//|(1<<1),
157 InterruptOnMAC = 1<<26,
159 MiscConfiguration = 0x6804,
160 CoreClockBlocksReset = 1<<0,
161 GPHYPowerDownOverride = 1<<26,
162 DisableGRCResetOnPCIE = 1<<29,
165 MiscLocalControl = 0x6808,
166 InterruptOnAttn = 1<<3,
169 SwArbitration = 0x7020,
176 PhyLinkStatus = 1<<2,
177 PhyAutoNegComplete = 1<<5,
178 PhyPartnerStatus = 0x05,
183 PhyGbitStatus = 0x0A,
186 PhyAuxControl = 0x18,
191 LinkStateChange = 1<<1,
281 #define csr32(c, r) ((c)->nic[(r)/4])
282 #define mem32(c, r) csr32(c, (r)+0x8000)
284 static Ctlr *bcmhead, *bcmtail;
293 miir(Ctlr *ctlr, int ra)
295 while(csr32(ctlr, MIComm) & (1<<29));
296 csr32(ctlr, MIComm) = (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
297 while(csr32(ctlr, MIComm) & (1<<29));
298 if(csr32(ctlr, MIComm) & (1<<28)) return -1;
299 return csr32(ctlr, MIComm) & 0xFFFF;
303 miiw(Ctlr *ctlr, int ra, int value)
305 while(csr32(ctlr, MIComm) & (1<<29));
306 csr32(ctlr, MIComm) = (value & 0xFFFF) | (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
307 while(csr32(ctlr, MIComm) & (1<<29));
312 checklink(Ether *edev)
318 miir(ctlr, PhyStatus); /* dummy read necessary */
319 if(!(miir(ctlr, PhyStatus) & PhyLinkStatus)) {
323 print("bcm: no link\n");
327 while((miir(ctlr, PhyStatus) & PhyAutoNegComplete) == 0);
328 i = miir(ctlr, PhyGbitStatus);
329 if(i & (Phy1000FD | Phy1000HD)) {
331 ctlr->duplex = (i & Phy1000FD) != 0;
332 } else if(i = miir(ctlr, PhyPartnerStatus), i & (Phy100FD | Phy100HD)) {
334 ctlr->duplex = (i & Phy100FD) != 0;
335 } else if(i & (Phy10FD | Phy10HD)) {
337 ctlr->duplex = (i & Phy10FD) != 0;
342 print("bcm: link partner supports neither 10/100/1000 Mbps\n");
345 print("bcm: %d Mbps link, %s duplex\n", edev->mbps, ctlr->duplex ? "full" : "half");
347 if(ctlr->duplex) csr32(ctlr, MACMode) &= ~MACHalfDuplex;
348 else csr32(ctlr, MACMode) |= MACHalfDuplex;
349 if(edev->mbps >= 1000)
350 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
352 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortMII;
353 csr32(ctlr, MACEventStatus) |= (1<<4) | (1<<3); /* undocumented bits (sync and config changed) */
357 currentrecvret(Ctlr *ctlr)
359 if(ctlr->recvreti == (ctlr->status[4] & 0xFFFF)) return 0;
360 return ctlr->recvret + ctlr->recvreti * 8;
364 consumerecvret(Ctlr *ctlr)
366 csr32(ctlr, RecvBDRetRingIndex) = ctlr->recvreti = (ctlr->recvreti + 1) & (RecvRetRingLen - 1);
370 replenish(Ctlr *ctlr)
376 incr = (ctlr->recvprodi + 1) & (RecvProdRingLen - 1);
377 if(incr == (ctlr->status[2] >> 16)) return -1;
380 print("bcm: out of memory for receive buffers\n");
383 next = ctlr->recvprod + ctlr->recvprodi * 8;
385 next[1] = PADDR(bp->rp);
387 next[7] = (ulong) bp;
389 csr32(ctlr, RecvProdBDRingIndex) = ctlr->recvprodi = incr;
394 bcmreceive(Ether *edev)
401 for(; pkt = currentrecvret(ctlr); replenish(ctlr), consumerecvret(ctlr)) {
402 bp = (Block*) pkt[7];
403 len = pkt[2] & 0xFFFF;
404 bp->wp = bp->rp + len;
405 if((pkt[3] & PacketEnd) == 0) print("bcm: partial frame received -- shouldn't happen\n");
406 if(pkt[3] & FrameError) {
407 freeb(bp); /* dump erroneous packets */
409 etheriq(edev, bp, 1);
415 bcmtransclean(Ether *edev, int dolock)
421 ilock(&ctlr->txlock);
422 while(ctlr->sendcleani != (ctlr->status[4] >> 16)) {
423 freeb(ctlr->sends[ctlr->sendcleani]);
424 ctlr->sends[ctlr->sendcleani] = 0;
425 ctlr->sendcleani = (ctlr->sendcleani + 1) & (SendRingLen - 1);
428 iunlock(&ctlr->txlock);
432 bcmtransmit(Ether *edev)
440 ilock(&ctlr->txlock);
442 incr = (ctlr->sendri + 1) & (SendRingLen - 1);
443 if(incr == (ctlr->status[4] >> 16)) {
444 print("bcm: send queue full\n");
449 setmalloctag(bp, (ulong)(void*)bcmtransmit);
450 next = ctlr->sendr + ctlr->sendri * 4;
452 next[1] = PADDR(bp->rp);
453 next[2] = (BLEN(bp) << 16) | PacketEnd;
455 if(ctlr->sends[ctlr->sendri] != 0)
456 freeb(ctlr->sends[ctlr->sendri]);
457 ctlr->sends[ctlr->sendri] = bp;
459 csr32(ctlr, SendBDRingHostIndex) = ctlr->sendri = incr;
461 iunlock(&ctlr->txlock);
465 bcmerror(Ether *edev)
470 if(csr32(ctlr, FlowAttention)) {
471 if(csr32(ctlr, FlowAttention) & 0xF8FF8080UL) {
472 panic("bcm: fatal error %#.8ulx", csr32(ctlr, FlowAttention));
474 csr32(ctlr, FlowAttention) = 0;
476 csr32(ctlr, MACEventStatus) = 0; /* worth ignoring */
477 if(csr32(ctlr, ReadDMAStatus) || csr32(ctlr, WriteDMAStatus)) {
478 print("bcm: DMA error\n");
479 csr32(ctlr, ReadDMAStatus) = 0;
480 csr32(ctlr, WriteDMAStatus) = 0;
482 if(csr32(ctlr, RISCState)) {
483 if(csr32(ctlr, RISCState) & 0x78000403) {
484 panic("bcm: RISC halted %#.8ulx", csr32(ctlr, RISCState));
486 csr32(ctlr, RISCState) = 0;
491 bcminterrupt(Ureg*, void *arg)
499 ilock(&ctlr->imlock);
500 dummyread(csr32(ctlr, InterruptMailbox));
501 csr32(ctlr, InterruptMailbox) = 1;
502 status = ctlr->status[0];
503 tag = ctlr->status[1];
505 if(status & Error) bcmerror(edev);
506 if(status & LinkStateChange) checklink(edev);
507 // print("bcm: interrupt %8ulx %8ulx\n", ctlr->status[2], ctlr->status[4]);
509 bcmtransclean(edev, 1);
511 csr32(ctlr, InterruptMailbox) = tag << 24;
512 iunlock(&ctlr->imlock);
522 print("bcm: reset\n");
523 /* initialization procedure according to the datasheet */
524 csr32(ctlr, MiscHostCtl) |= MaskPCIInt | ClearIntA;
525 csr32(ctlr, SwArbitration) |= SwArbitSet1;
526 for(i = 0; i < 10000 && (csr32(ctlr, SwArbitration) & SwArbitWon1) == 0; i++)
529 iprint("bcm: arbiter failed to respond\n");
532 csr32(ctlr, MemArbiterMode) |= Enable;
533 csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister;
534 csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
535 csr32(ctlr, ModeControl) |= ByteWordSwap;
536 csr32(ctlr, MemoryWindow) = 0;
537 mem32(ctlr, 0xB50) = 0x4B657654; /* magic number bullshit */
538 csr32(ctlr, MiscConfiguration) |= GPHYPowerDownOverride | DisableGRCResetOnPCIE;
539 csr32(ctlr, MiscConfiguration) |= CoreClockBlocksReset;
541 ctlr->pdev->pcr |= 1<<1; /* pci memory access enable */
542 pcisetbme(ctlr->pdev);
543 csr32(ctlr, MiscHostCtl) |= MaskPCIInt;
544 csr32(ctlr, MemArbiterMode) |= Enable;
545 csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
546 csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister | TaggedStatus;
547 csr32(ctlr, ModeControl) |= ByteWordSwap;
548 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
550 for(i = 0; i < 100000 && mem32(ctlr, 0xB50) != 0xB49A89AB; i++)
553 iprint("bcm: chip failed to reset\n");
556 switch(ctlr->pdev->did){
560 csr32(ctlr, TLPControl) |= (1<<25) | (1<<29);
563 memset(ctlr->status, 0, 20);
564 csr32(ctlr, DMARWControl) = (csr32(ctlr, DMARWControl) & DMAWatermarkMask) | DMAWatermarkValue;
565 csr32(ctlr, ModeControl) |= HostSendBDs | HostStackUp | InterruptOnMAC;
566 csr32(ctlr, MiscConfiguration) = (csr32(ctlr, MiscConfiguration) & TimerMask) | TimerValue;
567 csr32(ctlr, MBUFLowWatermark) = 0x20;
568 csr32(ctlr, MBUFHighWatermark) = 0x60;
569 csr32(ctlr, LowWatermarkMaximum) = (csr32(ctlr, LowWatermarkMaximum) & LowWatermarkMaxMask) | LowWatermarkMaxValue;
570 csr32(ctlr, BufferManMode) |= Enable | Attn;
571 for(i = 0; i < 100 && (csr32(ctlr, BufferManMode) & Enable) == 0; i++)
574 iprint("bcm: buffer manager failed to start\n");
577 csr32(ctlr, FTQReset) = -1;
578 csr32(ctlr, FTQReset) = 0;
579 for(i = 0; i < 1000 && csr32(ctlr, FTQReset) != 0; i++)
582 iprint("bcm: ftq failed to reset\n");
585 csr32(ctlr, ReceiveBDHostAddr) = 0;
586 csr32(ctlr, ReceiveBDHostAddr + 4) = PADDR(ctlr->recvprod);
587 csr32(ctlr, ReceiveBDFlags) = RecvProdRingLen << 16;
588 csr32(ctlr, ReceiveBDNIC) = 0x6000;
589 csr32(ctlr, ReceiveBDRepl) = 25;
590 csr32(ctlr, SendBDRingHostIndex) = 0;
591 csr32(ctlr, SendBDRingHostIndex+4) = 0;
592 mem32(ctlr, SendRCB) = 0;
593 mem32(ctlr, SendRCB + 4) = PADDR(ctlr->sendr);
594 mem32(ctlr, SendRCB + 8) = SendRingLen << 16;
595 mem32(ctlr, SendRCB + 12) = 0x4000;
597 mem32(ctlr, RecvRetRCB + i * 0x10 + 8) = 2;
598 mem32(ctlr, RecvRetRCB) = 0;
599 mem32(ctlr, RecvRetRCB + 4) = PADDR(ctlr->recvret);
600 mem32(ctlr, RecvRetRCB + 8) = RecvRetRingLen << 16;
601 csr32(ctlr, RecvProdBDRingIndex) = 0;
602 csr32(ctlr, RecvProdBDRingIndex+4) = 0;
603 /* this delay is not in the datasheet, but necessary; Broadcom is fucking with us */
605 i = csr32(ctlr, 0x410);
606 j = edev->ea[0] = i >> 8;
607 j += edev->ea[1] = i;
608 i = csr32(ctlr, MACAddress + 4);
609 j += edev->ea[2] = i >> 24;
610 j += edev->ea[3] = i >> 16;
611 j += edev->ea[4] = i >> 8;
612 j += edev->ea[5] = i;
613 csr32(ctlr, EthernetRandomBackoff) = j & 0x3FF;
614 csr32(ctlr, ReceiveMTU) = Rbsz;
615 csr32(ctlr, TransmitMACLengths) = 0x2620;
616 csr32(ctlr, ReceiveListPlacement) = 1<<3; /* one list */
617 csr32(ctlr, ReceiveListPlacementMask) = 0xFFFFFF;
618 csr32(ctlr, ReceiveListPlacementConfiguration) |= ReceiveStats;
619 csr32(ctlr, SendInitiatorMask) = 0xFFFFFF;
620 csr32(ctlr, SendInitiatorConfiguration) |= SendStats;
621 csr32(ctlr, HostCoalescingMode) = 0;
622 for(i = 0; i < 200 && csr32(ctlr, HostCoalescingMode) != 0; i++)
625 iprint("bcm: host coalescing engine failed to stop\n");
628 csr32(ctlr, HostCoalescingRecvTicks) = 150;
629 csr32(ctlr, HostCoalescingSendTicks) = 150;
630 csr32(ctlr, RecvMaxCoalescedFrames) = 10;
631 csr32(ctlr, SendMaxCoalescedFrames) = 10;
632 csr32(ctlr, RecvMaxCoalescedFramesInt) = 0;
633 csr32(ctlr, SendMaxCoalescedFramesInt) = 0;
634 csr32(ctlr, StatusBlockHostAddr) = 0;
635 csr32(ctlr, StatusBlockHostAddr + 4) = PADDR(ctlr->status);
636 csr32(ctlr, HostCoalescingMode) |= Enable;
637 csr32(ctlr, ReceiveBDCompletionMode) |= Enable | Attn;
638 csr32(ctlr, ReceiveListPlacementMode) |= Enable;
639 csr32(ctlr, MACMode) |= MACEnable;
640 csr32(ctlr, MiscLocalControl) |= InterruptOnAttn | AutoSEEPROM;
641 csr32(ctlr, InterruptMailbox) = 0;
642 csr32(ctlr, WriteDMAMode) |= 0x200003fe; /* pulled out of my nose */
643 csr32(ctlr, ReadDMAMode) |= 0x3fe;
644 csr32(ctlr, ReceiveDataCompletionMode) |= Enable | Attn;
645 csr32(ctlr, SendDataCompletionMode) |= Enable;
646 csr32(ctlr, SendBDCompletionMode) |= Enable | Attn;
647 csr32(ctlr, ReceiveBDInitiatorMode) |= Enable | Attn;
648 csr32(ctlr, ReceiveDataBDInitiatorMode) |= Enable | (1<<4);
649 csr32(ctlr, SendDataInitiatorMode) |= Enable;
650 csr32(ctlr, SendBDInitiatorMode) |= Enable | Attn;
651 csr32(ctlr, SendBDSelectorMode) |= Enable | Attn;
653 while(replenish(ctlr) >= 0);
654 csr32(ctlr, TransmitMACMode) |= Enable;
655 csr32(ctlr, ReceiveMACMode) |= Enable;
656 csr32(ctlr, PowerControlStatus) &= ~3;
657 csr32(ctlr, MIStatus) |= 1<<0;
658 csr32(ctlr, MACEventEnable) = 0;
659 csr32(ctlr, MACEventStatus) |= (1<<12);
660 csr32(ctlr, MIMode) = 0xC0000;
662 miiw(ctlr, PhyControl, 1<<15);
663 for(i = 0; i < 1000 && miir(ctlr, PhyControl) & (1<<15); i++)
666 iprint("bcm: PHY failed to reset\n");
669 miiw(ctlr, PhyAuxControl, 2);
670 miir(ctlr, PhyIntStatus);
671 miir(ctlr, PhyIntStatus);
672 miiw(ctlr, PhyIntMask, ~(1<<1));
674 csr32(ctlr, MACEventEnable) |= 1<<12;
675 csr32(ctlr, MACHash) = -1;
676 csr32(ctlr, MACHash+4) = -1;
677 csr32(ctlr, MACHash+8) = -1;
678 csr32(ctlr, MACHash+12) = -1;
679 for(i = 0; i < 8; i++) csr32(ctlr, ReceiveRules + 8 * i) = 0;
680 csr32(ctlr, ReceiveRulesConfiguration) = 1 << 3;
681 csr32(ctlr, MSIMode) |= Enable;
682 csr32(ctlr, MiscHostCtl) &= ~(MaskPCIInt | ClearIntA);
692 while(pdev = pcimatch(pdev, 0, 0)) {
696 if(pdev->ccrb != 2 || pdev->ccru != 0)
698 if(pdev->vid != 0x14e4)
781 case BCM5906: /* ??? */
782 case BCM5906M: /* ??? */
783 case 0x1670: /* ??? */
789 ctlr = malloc(sizeof(Ctlr));
791 print("bcm: unable to alloc Ctlr\n");
794 ctlr->sends = malloc(sizeof(ctlr->sends[0]) * SendRingLen);
795 if(ctlr->sends == nil){
796 print("bcm: unable to alloc ctlr->sends\n");
800 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
802 print("bcm: can't map %8.8luX\n", pdev->mem[0].bar);
809 ctlr->port = pdev->mem[0].bar & ~0x0F;
810 ctlr->status = xspanalloc(20, 16, 0);
811 ctlr->recvprod = xspanalloc(32 * RecvProdRingLen, 16, 0);
812 ctlr->recvret = xspanalloc(32 * RecvRetRingLen, 16, 0);
813 ctlr->sendr = xspanalloc(16 * SendRingLen, 16, 0);
815 bcmtail->link = ctlr;
823 bcmpromiscuous(void* arg, int on)
827 ctlr = ((Ether*)arg)->ctlr;
829 csr32(ctlr, ReceiveMACMode) |= 1<<8;
831 csr32(ctlr, ReceiveMACMode) &= ~(1<<8);
835 bcmmulticast(void*, uchar*, int)
848 for(ctlr = bcmhead; ctlr != nil; ctlr = ctlr->link) {
852 if(edev->port == 0 || edev->port == ctlr->port) {
862 edev->port = ctlr->port;
863 edev->irq = ctlr->pdev->intl;
864 edev->tbdf = ctlr->pdev->tbdf;
865 edev->interrupt = bcminterrupt;
866 edev->transmit = bcmtransmit;
867 edev->multicast = bcmmulticast;
868 edev->promiscuous = bcmpromiscuous;
872 if(bcminit(edev) < 0){
882 addethercard("bcm", bcmpnp);