4 * proper fatal error handling
11 #include "../port/lib.h"
16 #include "../port/error.h"
17 #include "../port/netif.h"
21 #define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
23 typedef struct Ctlr Ctlr;
29 /* One Ring to find them, One Ring to bring them all and in the darkness bind them */
30 ulong *recvret, *recvprod, *sendr;
32 ulong recvreti, recvprodi, sendri, sendcleani;
33 Block **sends, **recvs;
38 RecvRetRingLen = 0x200,
39 RecvProdRingLen = 0x200,
48 PowerControlStatus = 0x4C,
55 EnablePCIStateRegister = 1<<4,
56 EnableClockControlRegister = 1<<5,
57 IndirectAccessEnable = 1<<7,
61 DMAWatermarkMask = ~(7<<19),
62 DMAWatermarkValue = 3<<19,
65 MemoryWindowData = 0x84,
70 InterruptMailbox = 0x204,
72 RecvProdBDRingIndex = 0x26c,
73 RecvBDRetRingIndex = 0x284,
74 SendBDRingHostIndex = 0x304,
77 MACPortMask = ~((1<<3)|(1<<2)),
80 MACEnable = (1<<23) | (1<<22) | (1<<21) | (1 << 15) | (1 << 14) | (1<<12) | (1<<11),
83 MACEventStatus = 0x404,
84 MACEventEnable = 0x408,
86 EthernetRandomBackoff = 0x438,
91 ReceiveMACMode = 0x468,
92 TransmitMACMode = 0x45C,
93 TransmitMACLengths = 0x464,
97 ReceiveRulesConfiguration = 0x500,
98 LowWatermarkMaximum = 0x504,
99 LowWatermarkMaxMask = ~0xFFFF,
100 LowWatermarkMaxValue = 2,
102 SendDataInitiatorMode = 0xC00,
103 SendInitiatorConfiguration = 0x0C08,
105 SendInitiatorMask = 0x0C0C,
107 SendDataCompletionMode = 0x1000,
108 SendBDSelectorMode = 0x1400,
109 SendBDInitiatorMode = 0x1800,
110 SendBDCompletionMode = 0x1C00,
112 ReceiveListPlacementMode = 0x2000,
113 ReceiveListPlacement = 0x2010,
114 ReceiveListPlacementConfiguration = 0x2014,
116 ReceiveListPlacementMask = 0x2018,
118 ReceiveDataBDInitiatorMode = 0x2400,
119 ReceiveBDHostAddr = 0x2450,
120 ReceiveBDFlags = 0x2458,
121 ReceiveBDNIC = 0x245C,
122 ReceiveDataCompletionMode = 0x2800,
123 ReceiveBDInitiatorMode = 0x2C00,
124 ReceiveBDRepl = 0x2C18,
126 ReceiveBDCompletionMode = 0x3000,
127 HostCoalescingMode = 0x3C00,
128 HostCoalescingRecvTicks = 0x3C08,
129 HostCoalescingSendTicks = 0x3C0C,
130 RecvMaxCoalescedFrames = 0x3C10,
131 SendMaxCoalescedFrames = 0x3C14,
132 RecvMaxCoalescedFramesInt = 0x3C20,
133 SendMaxCoalescedFramesInt = 0x3C24,
134 StatusBlockHostAddr = 0x3C38,
135 FlowAttention = 0x3C48,
137 MemArbiterMode = 0x4000,
139 BufferManMode = 0x4400,
141 MBUFLowWatermark = 0x4414,
142 MBUFHighWatermark = 0x4418,
144 ReadDMAMode = 0x4800,
145 ReadDMAStatus = 0x4804,
146 WriteDMAMode = 0x4C00,
147 WriteDMAStatus = 0x4C04,
153 ModeControl = 0x6800,
154 ByteWordSwap = (1<<4)|(1<<5)|(1<<2),//|(1<<1),
157 InterruptOnMAC = 1<<26,
159 MiscConfiguration = 0x6804,
160 CoreClockBlocksReset = 1<<0,
161 GPHYPowerDownOverride = 1<<26,
162 DisableGRCResetOnPCIE = 1<<29,
165 MiscLocalControl = 0x6808,
166 InterruptOnAttn = 1<<3,
169 SwArbitration = 0x7020,
176 PhyLinkStatus = 1<<2,
177 PhyAutoNegComplete = 1<<5,
178 PhyPartnerStatus = 0x05,
183 PhyGbitStatus = 0x0A,
186 PhyAuxControl = 0x18,
191 LinkStateChange = 1<<1,
281 #define csr32(c, r) ((c)->nic[(r)/4])
282 #define mem32(c, r) csr32(c, (r)+0x8000)
284 static Ctlr *bcmhead, *bcmtail;
293 miir(Ctlr *ctlr, int ra)
295 while(csr32(ctlr, MIComm) & (1<<29));
296 csr32(ctlr, MIComm) = (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
297 while(csr32(ctlr, MIComm) & (1<<29));
298 if(csr32(ctlr, MIComm) & (1<<28)) return -1;
299 return csr32(ctlr, MIComm) & 0xFFFF;
303 miiw(Ctlr *ctlr, int ra, int value)
305 while(csr32(ctlr, MIComm) & (1<<29));
306 csr32(ctlr, MIComm) = (value & 0xFFFF) | (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
307 while(csr32(ctlr, MIComm) & (1<<29));
312 checklink(Ether *edev)
318 miir(ctlr, PhyStatus); /* dummy read necessary */
319 if(!(miir(ctlr, PhyStatus) & PhyLinkStatus)) {
323 print("bcm: no link\n");
327 while((miir(ctlr, PhyStatus) & PhyAutoNegComplete) == 0);
328 i = miir(ctlr, PhyGbitStatus);
329 if(i & (Phy1000FD | Phy1000HD)) {
331 ctlr->duplex = (i & Phy1000FD) != 0;
332 } else if(i = miir(ctlr, PhyPartnerStatus), i & (Phy100FD | Phy100HD)) {
334 ctlr->duplex = (i & Phy100FD) != 0;
335 } else if(i & (Phy10FD | Phy10HD)) {
337 ctlr->duplex = (i & Phy10FD) != 0;
342 print("bcm: link partner supports neither 10/100/1000 Mbps\n");
345 print("bcm: %d Mbps link, %s duplex\n", edev->mbps, ctlr->duplex ? "full" : "half");
347 if(ctlr->duplex) csr32(ctlr, MACMode) &= ~MACHalfDuplex;
348 else csr32(ctlr, MACMode) |= MACHalfDuplex;
349 if(edev->mbps >= 1000)
350 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
352 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortMII;
353 csr32(ctlr, MACEventStatus) |= (1<<4) | (1<<3); /* undocumented bits (sync and config changed) */
357 currentrecvret(Ctlr *ctlr)
359 if(ctlr->recvreti == (ctlr->status[4] & 0xFFFF)) return 0;
360 return ctlr->recvret + ctlr->recvreti * 8;
364 consumerecvret(Ctlr *ctlr)
366 csr32(ctlr, RecvBDRetRingIndex) = ctlr->recvreti = (ctlr->recvreti + 1) & (RecvRetRingLen - 1);
370 replenish(Ctlr *ctlr)
376 idx = ctlr->recvprodi;
377 incr = (idx + 1) & (RecvProdRingLen - 1);
378 if(incr == (ctlr->status[2] >> 16)) return -1;
379 if(ctlr->recvs[idx] != 0) return -1;
382 print("bcm: out of memory for receive buffers\n");
385 ctlr->recvs[idx] = bp;
386 next = ctlr->recvprod + idx * 8;
388 next[1] = PADDR(bp->rp);
392 csr32(ctlr, RecvProdBDRingIndex) = ctlr->recvprodi = incr;
397 bcmreceive(Ether *edev)
401 ulong *pkt, len, idx;
404 for(; pkt = currentrecvret(ctlr); replenish(ctlr), consumerecvret(ctlr)) {
405 idx = pkt[7] & (RecvProdRingLen - 1);
406 bp = ctlr->recvs[idx];
408 print("bcm: nil block at %lux -- shouldn't happen\n", idx);
411 ctlr->recvs[idx] = 0;
412 len = pkt[2] & 0xFFFF;
413 bp->wp = bp->rp + len;
414 if((pkt[3] & PacketEnd) == 0) print("bcm: partial frame received -- shouldn't happen\n");
415 if(pkt[3] & FrameError) {
416 freeb(bp); /* dump erroneous packets */
418 etheriq(edev, bp, 1);
424 bcmtransclean(Ether *edev, int dolock)
430 ilock(&ctlr->txlock);
431 while(ctlr->sendcleani != (ctlr->status[4] >> 16)) {
432 freeb(ctlr->sends[ctlr->sendcleani]);
433 ctlr->sends[ctlr->sendcleani] = 0;
434 ctlr->sendcleani = (ctlr->sendcleani + 1) & (SendRingLen - 1);
437 iunlock(&ctlr->txlock);
441 bcmtransmit(Ether *edev)
449 ilock(&ctlr->txlock);
451 incr = (ctlr->sendri + 1) & (SendRingLen - 1);
452 if(incr == (ctlr->status[4] >> 16)) {
453 print("bcm: send queue full\n");
458 next = ctlr->sendr + ctlr->sendri * 4;
460 next[1] = PADDR(bp->rp);
461 next[2] = (BLEN(bp) << 16) | PacketEnd;
463 if(ctlr->sends[ctlr->sendri] != 0)
464 freeb(ctlr->sends[ctlr->sendri]);
465 ctlr->sends[ctlr->sendri] = bp;
467 csr32(ctlr, SendBDRingHostIndex) = ctlr->sendri = incr;
469 iunlock(&ctlr->txlock);
473 bcmerror(Ether *edev)
478 if(csr32(ctlr, FlowAttention)) {
479 if(csr32(ctlr, FlowAttention) & 0xF8FF8080UL) {
480 panic("bcm: fatal error %#.8ulx", csr32(ctlr, FlowAttention));
482 csr32(ctlr, FlowAttention) = 0;
484 csr32(ctlr, MACEventStatus) = 0; /* worth ignoring */
485 if(csr32(ctlr, ReadDMAStatus) || csr32(ctlr, WriteDMAStatus)) {
486 print("bcm: DMA error\n");
487 csr32(ctlr, ReadDMAStatus) = 0;
488 csr32(ctlr, WriteDMAStatus) = 0;
490 if(csr32(ctlr, RISCState)) {
491 if(csr32(ctlr, RISCState) & 0x78000403) {
492 panic("bcm: RISC halted %#.8ulx", csr32(ctlr, RISCState));
494 csr32(ctlr, RISCState) = 0;
499 bcminterrupt(Ureg*, void *arg)
507 ilock(&ctlr->imlock);
508 dummyread(csr32(ctlr, InterruptMailbox));
509 csr32(ctlr, InterruptMailbox) = 1;
510 status = ctlr->status[0];
511 tag = ctlr->status[1];
513 if(status & Error) bcmerror(edev);
514 if(status & LinkStateChange) checklink(edev);
515 // print("bcm: interrupt %8ulx %8ulx\n", ctlr->status[2], ctlr->status[4]);
517 bcmtransclean(edev, 1);
519 csr32(ctlr, InterruptMailbox) = tag << 24;
520 iunlock(&ctlr->imlock);
530 print("bcm: reset\n");
531 /* initialization procedure according to the datasheet */
532 csr32(ctlr, MiscHostCtl) |= MaskPCIInt | ClearIntA;
533 csr32(ctlr, SwArbitration) |= SwArbitSet1;
534 for(i = 0; i < 10000 && (csr32(ctlr, SwArbitration) & SwArbitWon1) == 0; i++)
537 iprint("bcm: arbiter failed to respond\n");
540 csr32(ctlr, MemArbiterMode) |= Enable;
541 csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister;
542 csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
543 csr32(ctlr, ModeControl) |= ByteWordSwap;
544 csr32(ctlr, MemoryWindow) = 0;
545 mem32(ctlr, 0xB50) = 0x4B657654; /* magic number bullshit */
546 csr32(ctlr, MiscConfiguration) |= GPHYPowerDownOverride | DisableGRCResetOnPCIE;
547 csr32(ctlr, MiscConfiguration) |= CoreClockBlocksReset;
549 ctlr->pdev->pcr |= 1<<1; /* pci memory access enable */
550 pcisetbme(ctlr->pdev);
551 csr32(ctlr, MiscHostCtl) |= MaskPCIInt;
552 csr32(ctlr, MemArbiterMode) |= Enable;
553 csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
554 csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister | TaggedStatus;
555 csr32(ctlr, ModeControl) |= ByteWordSwap;
556 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
558 for(i = 0; i < 100000 && mem32(ctlr, 0xB50) != 0xB49A89AB; i++)
561 iprint("bcm: chip failed to reset\n");
564 switch(ctlr->pdev->did){
568 csr32(ctlr, TLPControl) |= (1<<25) | (1<<29);
571 memset(ctlr->status, 0, 20);
572 csr32(ctlr, DMARWControl) = (csr32(ctlr, DMARWControl) & DMAWatermarkMask) | DMAWatermarkValue;
573 csr32(ctlr, ModeControl) |= HostSendBDs | HostStackUp | InterruptOnMAC;
574 csr32(ctlr, MiscConfiguration) = (csr32(ctlr, MiscConfiguration) & TimerMask) | TimerValue;
575 csr32(ctlr, MBUFLowWatermark) = 0x20;
576 csr32(ctlr, MBUFHighWatermark) = 0x60;
577 csr32(ctlr, LowWatermarkMaximum) = (csr32(ctlr, LowWatermarkMaximum) & LowWatermarkMaxMask) | LowWatermarkMaxValue;
578 csr32(ctlr, BufferManMode) |= Enable | Attn;
579 for(i = 0; i < 100 && (csr32(ctlr, BufferManMode) & Enable) == 0; i++)
582 iprint("bcm: buffer manager failed to start\n");
585 csr32(ctlr, FTQReset) = -1;
586 csr32(ctlr, FTQReset) = 0;
587 for(i = 0; i < 1000 && csr32(ctlr, FTQReset) != 0; i++)
590 iprint("bcm: ftq failed to reset\n");
593 csr32(ctlr, ReceiveBDHostAddr) = 0;
594 csr32(ctlr, ReceiveBDHostAddr + 4) = PADDR(ctlr->recvprod);
595 csr32(ctlr, ReceiveBDFlags) = RecvProdRingLen << 16;
596 csr32(ctlr, ReceiveBDNIC) = 0x6000;
597 csr32(ctlr, ReceiveBDRepl) = 25;
598 csr32(ctlr, SendBDRingHostIndex) = 0;
599 csr32(ctlr, SendBDRingHostIndex+4) = 0;
600 mem32(ctlr, SendRCB) = 0;
601 mem32(ctlr, SendRCB + 4) = PADDR(ctlr->sendr);
602 mem32(ctlr, SendRCB + 8) = SendRingLen << 16;
603 mem32(ctlr, SendRCB + 12) = 0x4000;
605 mem32(ctlr, RecvRetRCB + i * 0x10 + 8) = 2;
606 mem32(ctlr, RecvRetRCB) = 0;
607 mem32(ctlr, RecvRetRCB + 4) = PADDR(ctlr->recvret);
608 mem32(ctlr, RecvRetRCB + 8) = RecvRetRingLen << 16;
609 csr32(ctlr, RecvProdBDRingIndex) = 0;
610 csr32(ctlr, RecvProdBDRingIndex+4) = 0;
611 /* this delay is not in the datasheet, but necessary; Broadcom is fucking with us */
613 i = csr32(ctlr, 0x410);
614 j = edev->ea[0] = i >> 8;
615 j += edev->ea[1] = i;
616 i = csr32(ctlr, MACAddress + 4);
617 j += edev->ea[2] = i >> 24;
618 j += edev->ea[3] = i >> 16;
619 j += edev->ea[4] = i >> 8;
620 j += edev->ea[5] = i;
621 csr32(ctlr, EthernetRandomBackoff) = j & 0x3FF;
622 csr32(ctlr, ReceiveMTU) = Rbsz;
623 csr32(ctlr, TransmitMACLengths) = 0x2620;
624 csr32(ctlr, ReceiveListPlacement) = 1<<3; /* one list */
625 csr32(ctlr, ReceiveListPlacementMask) = 0xFFFFFF;
626 csr32(ctlr, ReceiveListPlacementConfiguration) |= ReceiveStats;
627 csr32(ctlr, SendInitiatorMask) = 0xFFFFFF;
628 csr32(ctlr, SendInitiatorConfiguration) |= SendStats;
629 csr32(ctlr, HostCoalescingMode) = 0;
630 for(i = 0; i < 200 && csr32(ctlr, HostCoalescingMode) != 0; i++)
633 iprint("bcm: host coalescing engine failed to stop\n");
636 csr32(ctlr, HostCoalescingRecvTicks) = 150;
637 csr32(ctlr, HostCoalescingSendTicks) = 150;
638 csr32(ctlr, RecvMaxCoalescedFrames) = 10;
639 csr32(ctlr, SendMaxCoalescedFrames) = 10;
640 csr32(ctlr, RecvMaxCoalescedFramesInt) = 0;
641 csr32(ctlr, SendMaxCoalescedFramesInt) = 0;
642 csr32(ctlr, StatusBlockHostAddr) = 0;
643 csr32(ctlr, StatusBlockHostAddr + 4) = PADDR(ctlr->status);
644 csr32(ctlr, HostCoalescingMode) |= Enable;
645 csr32(ctlr, ReceiveBDCompletionMode) |= Enable | Attn;
646 csr32(ctlr, ReceiveListPlacementMode) |= Enable;
647 csr32(ctlr, MACMode) |= MACEnable;
648 csr32(ctlr, MiscLocalControl) |= InterruptOnAttn | AutoSEEPROM;
649 csr32(ctlr, InterruptMailbox) = 0;
650 csr32(ctlr, WriteDMAMode) |= 0x200003fe; /* pulled out of my nose */
651 csr32(ctlr, ReadDMAMode) |= 0x3fe;
652 csr32(ctlr, ReceiveDataCompletionMode) |= Enable | Attn;
653 csr32(ctlr, SendDataCompletionMode) |= Enable;
654 csr32(ctlr, SendBDCompletionMode) |= Enable | Attn;
655 csr32(ctlr, ReceiveBDInitiatorMode) |= Enable | Attn;
656 csr32(ctlr, ReceiveDataBDInitiatorMode) |= Enable | (1<<4);
657 csr32(ctlr, SendDataInitiatorMode) |= Enable;
658 csr32(ctlr, SendBDInitiatorMode) |= Enable | Attn;
659 csr32(ctlr, SendBDSelectorMode) |= Enable | Attn;
661 while(replenish(ctlr) >= 0);
662 csr32(ctlr, TransmitMACMode) |= Enable;
663 csr32(ctlr, ReceiveMACMode) |= Enable;
664 csr32(ctlr, PowerControlStatus) &= ~3;
665 csr32(ctlr, MIStatus) |= 1<<0;
666 csr32(ctlr, MACEventEnable) = 0;
667 csr32(ctlr, MACEventStatus) |= (1<<12);
668 csr32(ctlr, MIMode) = 0xC0000;
670 miiw(ctlr, PhyControl, 1<<15);
671 for(i = 0; i < 1000 && miir(ctlr, PhyControl) & (1<<15); i++)
674 iprint("bcm: PHY failed to reset\n");
677 miiw(ctlr, PhyAuxControl, 2);
678 miir(ctlr, PhyIntStatus);
679 miir(ctlr, PhyIntStatus);
680 miiw(ctlr, PhyIntMask, ~(1<<1));
682 csr32(ctlr, MACEventEnable) |= 1<<12;
683 csr32(ctlr, MACHash) = -1;
684 csr32(ctlr, MACHash+4) = -1;
685 csr32(ctlr, MACHash+8) = -1;
686 csr32(ctlr, MACHash+12) = -1;
687 for(i = 0; i < 8; i++) csr32(ctlr, ReceiveRules + 8 * i) = 0;
688 csr32(ctlr, ReceiveRulesConfiguration) = 1 << 3;
689 csr32(ctlr, MSIMode) |= Enable;
690 csr32(ctlr, MiscHostCtl) &= ~(MaskPCIInt | ClearIntA);
700 while(pdev = pcimatch(pdev, 0, 0)) {
704 if(pdev->ccrb != 2 || pdev->ccru != 0)
706 if(pdev->vid != 0x14e4)
789 case BCM5906: /* ??? */
790 case BCM5906M: /* ??? */
791 case 0x1670: /* ??? */
797 ctlr = malloc(sizeof(Ctlr));
799 print("bcm: unable to alloc Ctlr\n");
802 ctlr->sends = malloc(sizeof(ctlr->sends[0]) * SendRingLen);
803 ctlr->recvs = malloc(sizeof(ctlr->recvs[0]) * RecvProdRingLen);
804 if(ctlr->sends == nil || ctlr->recvs == nil){
805 print("bcm: unable to alloc ctlr->sends and ctlr->recvs\n");
811 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
813 print("bcm: can't map %8.8luX\n", pdev->mem[0].bar);
820 ctlr->port = pdev->mem[0].bar & ~0x0F;
821 ctlr->status = xspanalloc(20, 16, 0);
822 ctlr->recvprod = xspanalloc(32 * RecvProdRingLen, 16, 0);
823 ctlr->recvret = xspanalloc(32 * RecvRetRingLen, 16, 0);
824 ctlr->sendr = xspanalloc(16 * SendRingLen, 16, 0);
826 bcmtail->link = ctlr;
834 bcmpromiscuous(void* arg, int on)
838 ctlr = ((Ether*)arg)->ctlr;
840 csr32(ctlr, ReceiveMACMode) |= 1<<8;
842 csr32(ctlr, ReceiveMACMode) &= ~(1<<8);
846 bcmmulticast(void*, uchar*, int)
859 for(ctlr = bcmhead; ctlr != nil; ctlr = ctlr->link) {
863 if(edev->port == 0 || edev->port == ctlr->port) {
873 edev->port = ctlr->port;
874 edev->irq = ctlr->pdev->intl;
875 edev->tbdf = ctlr->pdev->tbdf;
876 edev->interrupt = bcminterrupt;
877 edev->transmit = bcmtransmit;
878 edev->multicast = bcmmulticast;
879 edev->promiscuous = bcmpromiscuous;
883 if(bcminit(edev) < 0){
893 addethercard("bcm", bcmpnp);