4 * proper fatal error handling
11 #include "../port/lib.h"
16 #include "../port/error.h"
17 #include "../port/netif.h"
18 #include "../port/etherif.h"
20 #define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
22 typedef struct Ctlr Ctlr;
28 /* One Ring to find them, One Ring to bring them all and in the darkness bind them */
29 ulong *recvret, *recvprod, *sendr;
31 ulong recvreti, recvprodi, sendri, sendcleani;
32 Block **sends, **recvs;
37 RecvRetRingLen = 0x200,
38 RecvProdRingLen = 0x200,
47 PowerControlStatus = 0x4C,
54 EnablePCIStateRegister = 1<<4,
55 EnableClockControlRegister = 1<<5,
56 IndirectAccessEnable = 1<<7,
60 DMAWatermarkMask = ~(7<<19),
61 DMAWatermarkValue = 3<<19,
64 MemoryWindowData = 0x84,
69 InterruptMailbox = 0x204,
71 RecvProdBDRingIndex = 0x26c,
72 RecvBDRetRingIndex = 0x284,
73 SendBDRingHostIndex = 0x304,
76 MACPortMask = ~((1<<3)|(1<<2)),
79 MACEnable = (1<<23) | (1<<22) | (1<<21) | (1 << 15) | (1 << 14) | (1<<12) | (1<<11),
82 MACEventStatus = 0x404,
83 MACEventEnable = 0x408,
85 EthernetRandomBackoff = 0x438,
90 ReceiveMACMode = 0x468,
91 TransmitMACMode = 0x45C,
92 TransmitMACLengths = 0x464,
96 ReceiveRulesConfiguration = 0x500,
97 LowWatermarkMaximum = 0x504,
98 LowWatermarkMaxMask = ~0xFFFF,
99 LowWatermarkMaxValue = 2,
101 SendDataInitiatorMode = 0xC00,
102 SendInitiatorConfiguration = 0x0C08,
104 SendInitiatorMask = 0x0C0C,
106 SendDataCompletionMode = 0x1000,
107 SendBDSelectorMode = 0x1400,
108 SendBDInitiatorMode = 0x1800,
109 SendBDCompletionMode = 0x1C00,
111 ReceiveListPlacementMode = 0x2000,
112 ReceiveListPlacement = 0x2010,
113 ReceiveListPlacementConfiguration = 0x2014,
115 ReceiveListPlacementMask = 0x2018,
117 ReceiveDataBDInitiatorMode = 0x2400,
118 ReceiveBDHostAddr = 0x2450,
119 ReceiveBDFlags = 0x2458,
120 ReceiveBDNIC = 0x245C,
121 ReceiveDataCompletionMode = 0x2800,
122 ReceiveBDInitiatorMode = 0x2C00,
123 ReceiveBDRepl = 0x2C18,
125 ReceiveBDCompletionMode = 0x3000,
126 HostCoalescingMode = 0x3C00,
127 HostCoalescingRecvTicks = 0x3C08,
128 HostCoalescingSendTicks = 0x3C0C,
129 RecvMaxCoalescedFrames = 0x3C10,
130 SendMaxCoalescedFrames = 0x3C14,
131 RecvMaxCoalescedFramesInt = 0x3C20,
132 SendMaxCoalescedFramesInt = 0x3C24,
133 StatusBlockHostAddr = 0x3C38,
134 FlowAttention = 0x3C48,
136 MemArbiterMode = 0x4000,
138 BufferManMode = 0x4400,
140 MBUFLowWatermark = 0x4414,
141 MBUFHighWatermark = 0x4418,
143 ReadDMAMode = 0x4800,
144 ReadDMAStatus = 0x4804,
145 WriteDMAMode = 0x4C00,
146 WriteDMAStatus = 0x4C04,
152 ModeControl = 0x6800,
153 ByteWordSwap = (1<<4)|(1<<5)|(1<<2),//|(1<<1),
156 InterruptOnMAC = 1<<26,
158 MiscConfiguration = 0x6804,
159 CoreClockBlocksReset = 1<<0,
160 GPHYPowerDownOverride = 1<<26,
161 DisableGRCResetOnPCIE = 1<<29,
164 MiscLocalControl = 0x6808,
165 InterruptOnAttn = 1<<3,
168 SwArbitration = 0x7020,
175 PhyLinkStatus = 1<<2,
176 PhyAutoNegComplete = 1<<5,
177 PhyPartnerStatus = 0x05,
182 PhyGbitStatus = 0x0A,
185 PhyAuxControl = 0x18,
190 LinkStateChange = 1<<1,
280 #define csr32(c, r) ((c)->nic[(r)/4])
281 #define mem32(c, r) csr32(c, (r)+0x8000)
283 static Ctlr *bcmhead, *bcmtail;
292 miir(Ctlr *ctlr, int ra)
294 while(csr32(ctlr, MIComm) & (1<<29));
295 csr32(ctlr, MIComm) = (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
296 while(csr32(ctlr, MIComm) & (1<<29));
297 if(csr32(ctlr, MIComm) & (1<<28)) return -1;
298 return csr32(ctlr, MIComm) & 0xFFFF;
302 miiw(Ctlr *ctlr, int ra, int value)
304 while(csr32(ctlr, MIComm) & (1<<29));
305 csr32(ctlr, MIComm) = (value & 0xFFFF) | (ra << 16) | (1 << 21) | (1 << 27) | (1 << 29);
306 while(csr32(ctlr, MIComm) & (1<<29));
311 checklink(Ether *edev)
317 miir(ctlr, PhyStatus); /* dummy read necessary */
318 if(!(miir(ctlr, PhyStatus) & PhyLinkStatus)) {
322 print("bcm: no link\n");
326 while((miir(ctlr, PhyStatus) & PhyAutoNegComplete) == 0);
327 i = miir(ctlr, PhyGbitStatus);
328 if(i & (Phy1000FD | Phy1000HD)) {
330 ctlr->duplex = (i & Phy1000FD) != 0;
331 } else if(i = miir(ctlr, PhyPartnerStatus), i & (Phy100FD | Phy100HD)) {
333 ctlr->duplex = (i & Phy100FD) != 0;
334 } else if(i & (Phy10FD | Phy10HD)) {
336 ctlr->duplex = (i & Phy10FD) != 0;
341 print("bcm: link partner supports neither 10/100/1000 Mbps\n");
344 print("bcm: %d Mbps link, %s duplex\n", edev->mbps, ctlr->duplex ? "full" : "half");
346 if(ctlr->duplex) csr32(ctlr, MACMode) &= ~MACHalfDuplex;
347 else csr32(ctlr, MACMode) |= MACHalfDuplex;
348 if(edev->mbps >= 1000)
349 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
351 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortMII;
352 csr32(ctlr, MACEventStatus) |= (1<<4) | (1<<3); /* undocumented bits (sync and config changed) */
356 currentrecvret(Ctlr *ctlr)
358 if(ctlr->recvreti == (ctlr->status[4] & 0xFFFF)) return 0;
359 return ctlr->recvret + ctlr->recvreti * 8;
363 consumerecvret(Ctlr *ctlr)
365 csr32(ctlr, RecvBDRetRingIndex) = ctlr->recvreti = (ctlr->recvreti + 1) & (RecvRetRingLen - 1);
369 replenish(Ctlr *ctlr)
375 idx = ctlr->recvprodi;
376 incr = (idx + 1) & (RecvProdRingLen - 1);
377 if(incr == (ctlr->status[2] >> 16)) return -1;
378 if(ctlr->recvs[idx] != 0) return -1;
381 print("bcm: out of memory for receive buffers\n");
384 ctlr->recvs[idx] = bp;
385 next = ctlr->recvprod + idx * 8;
387 next[1] = PADDR(bp->rp);
391 csr32(ctlr, RecvProdBDRingIndex) = ctlr->recvprodi = incr;
396 bcmreceive(Ether *edev)
400 ulong *pkt, len, idx;
403 for(; pkt = currentrecvret(ctlr); replenish(ctlr), consumerecvret(ctlr)) {
404 idx = pkt[7] & (RecvProdRingLen - 1);
405 bp = ctlr->recvs[idx];
407 print("bcm: nil block at %lux -- shouldn't happen\n", idx);
410 ctlr->recvs[idx] = 0;
411 len = pkt[2] & 0xFFFF;
412 bp->wp = bp->rp + len;
413 if((pkt[3] & PacketEnd) == 0) print("bcm: partial frame received -- shouldn't happen\n");
414 if(pkt[3] & FrameError) {
415 freeb(bp); /* dump erroneous packets */
423 bcmtransclean(Ether *edev, int dolock)
429 ilock(&ctlr->txlock);
430 while(ctlr->sendcleani != (ctlr->status[4] >> 16)) {
431 freeb(ctlr->sends[ctlr->sendcleani]);
432 ctlr->sends[ctlr->sendcleani] = 0;
433 ctlr->sendcleani = (ctlr->sendcleani + 1) & (SendRingLen - 1);
436 iunlock(&ctlr->txlock);
440 bcmtransmit(Ether *edev)
448 ilock(&ctlr->txlock);
450 incr = (ctlr->sendri + 1) & (SendRingLen - 1);
451 if(incr == (ctlr->status[4] >> 16)) {
452 print("bcm: send queue full\n");
457 next = ctlr->sendr + ctlr->sendri * 4;
459 next[1] = PADDR(bp->rp);
460 next[2] = (BLEN(bp) << 16) | PacketEnd;
462 if(ctlr->sends[ctlr->sendri] != 0)
463 freeb(ctlr->sends[ctlr->sendri]);
464 ctlr->sends[ctlr->sendri] = bp;
466 csr32(ctlr, SendBDRingHostIndex) = ctlr->sendri = incr;
468 iunlock(&ctlr->txlock);
472 bcmerror(Ether *edev)
477 if(csr32(ctlr, FlowAttention)) {
478 if(csr32(ctlr, FlowAttention) & 0xF8FF8080UL) {
479 panic("bcm: fatal error %#.8ulx", csr32(ctlr, FlowAttention));
481 csr32(ctlr, FlowAttention) = 0;
483 csr32(ctlr, MACEventStatus) = 0; /* worth ignoring */
484 if(csr32(ctlr, ReadDMAStatus) || csr32(ctlr, WriteDMAStatus)) {
485 print("bcm: DMA error\n");
486 csr32(ctlr, ReadDMAStatus) = 0;
487 csr32(ctlr, WriteDMAStatus) = 0;
489 if(csr32(ctlr, RISCState)) {
490 if(csr32(ctlr, RISCState) & 0x78000403) {
491 panic("bcm: RISC halted %#.8ulx", csr32(ctlr, RISCState));
493 csr32(ctlr, RISCState) = 0;
498 bcminterrupt(Ureg*, void *arg)
506 ilock(&ctlr->imlock);
507 dummyread(csr32(ctlr, InterruptMailbox));
508 csr32(ctlr, InterruptMailbox) = 1;
509 status = ctlr->status[0];
510 tag = ctlr->status[1];
512 if(status & Error) bcmerror(edev);
513 if(status & LinkStateChange) checklink(edev);
514 // print("bcm: interrupt %8ulx %8ulx\n", ctlr->status[2], ctlr->status[4]);
516 bcmtransclean(edev, 1);
518 csr32(ctlr, InterruptMailbox) = tag << 24;
519 iunlock(&ctlr->imlock);
529 print("bcm: reset\n");
530 /* initialization procedure according to the datasheet */
531 csr32(ctlr, MiscHostCtl) |= MaskPCIInt | ClearIntA;
532 csr32(ctlr, SwArbitration) |= SwArbitSet1;
533 for(i = 0; i < 10000 && (csr32(ctlr, SwArbitration) & SwArbitWon1) == 0; i++)
536 iprint("bcm: arbiter failed to respond\n");
539 csr32(ctlr, MemArbiterMode) |= Enable;
540 csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister;
541 csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
542 csr32(ctlr, ModeControl) |= ByteWordSwap;
543 csr32(ctlr, MemoryWindow) = 0;
544 mem32(ctlr, 0xB50) = 0x4B657654; /* magic number bullshit */
545 csr32(ctlr, MiscConfiguration) |= GPHYPowerDownOverride | DisableGRCResetOnPCIE;
546 csr32(ctlr, MiscConfiguration) |= CoreClockBlocksReset;
548 ctlr->pdev->pcr |= 1<<1; /* pci memory access enable */
549 pcisetbme(ctlr->pdev);
550 csr32(ctlr, MiscHostCtl) |= MaskPCIInt;
551 csr32(ctlr, MemArbiterMode) |= Enable;
552 csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
553 csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister | TaggedStatus;
554 csr32(ctlr, ModeControl) |= ByteWordSwap;
555 csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
557 for(i = 0; i < 100000 && mem32(ctlr, 0xB50) != 0xB49A89AB; i++)
560 iprint("bcm: chip failed to reset\n");
563 switch(ctlr->pdev->did){
567 csr32(ctlr, TLPControl) |= (1<<25) | (1<<29);
570 memset(ctlr->status, 0, 20);
571 csr32(ctlr, DMARWControl) = (csr32(ctlr, DMARWControl) & DMAWatermarkMask) | DMAWatermarkValue;
572 csr32(ctlr, ModeControl) |= HostSendBDs | HostStackUp | InterruptOnMAC;
573 csr32(ctlr, MiscConfiguration) = (csr32(ctlr, MiscConfiguration) & TimerMask) | TimerValue;
574 csr32(ctlr, MBUFLowWatermark) = 0x20;
575 csr32(ctlr, MBUFHighWatermark) = 0x60;
576 csr32(ctlr, LowWatermarkMaximum) = (csr32(ctlr, LowWatermarkMaximum) & LowWatermarkMaxMask) | LowWatermarkMaxValue;
577 csr32(ctlr, BufferManMode) |= Enable | Attn;
578 for(i = 0; i < 100 && (csr32(ctlr, BufferManMode) & Enable) == 0; i++)
581 iprint("bcm: buffer manager failed to start\n");
584 csr32(ctlr, FTQReset) = -1;
585 csr32(ctlr, FTQReset) = 0;
586 for(i = 0; i < 1000 && csr32(ctlr, FTQReset) != 0; i++)
589 iprint("bcm: ftq failed to reset\n");
592 csr32(ctlr, ReceiveBDHostAddr) = 0;
593 csr32(ctlr, ReceiveBDHostAddr + 4) = PADDR(ctlr->recvprod);
594 csr32(ctlr, ReceiveBDFlags) = RecvProdRingLen << 16;
595 csr32(ctlr, ReceiveBDNIC) = 0x6000;
596 csr32(ctlr, ReceiveBDRepl) = 25;
597 csr32(ctlr, SendBDRingHostIndex) = 0;
598 csr32(ctlr, SendBDRingHostIndex+4) = 0;
599 mem32(ctlr, SendRCB) = 0;
600 mem32(ctlr, SendRCB + 4) = PADDR(ctlr->sendr);
601 mem32(ctlr, SendRCB + 8) = SendRingLen << 16;
602 mem32(ctlr, SendRCB + 12) = 0x4000;
604 mem32(ctlr, RecvRetRCB + i * 0x10 + 8) = 2;
605 mem32(ctlr, RecvRetRCB) = 0;
606 mem32(ctlr, RecvRetRCB + 4) = PADDR(ctlr->recvret);
607 mem32(ctlr, RecvRetRCB + 8) = RecvRetRingLen << 16;
608 csr32(ctlr, RecvProdBDRingIndex) = 0;
609 csr32(ctlr, RecvProdBDRingIndex+4) = 0;
610 /* this delay is not in the datasheet, but necessary; Broadcom is fucking with us */
612 i = csr32(ctlr, 0x410);
613 j = edev->ea[0] = i >> 8;
614 j += edev->ea[1] = i;
615 i = csr32(ctlr, MACAddress + 4);
616 j += edev->ea[2] = i >> 24;
617 j += edev->ea[3] = i >> 16;
618 j += edev->ea[4] = i >> 8;
619 j += edev->ea[5] = i;
620 csr32(ctlr, EthernetRandomBackoff) = j & 0x3FF;
621 csr32(ctlr, ReceiveMTU) = Rbsz;
622 csr32(ctlr, TransmitMACLengths) = 0x2620;
623 csr32(ctlr, ReceiveListPlacement) = 1<<3; /* one list */
624 csr32(ctlr, ReceiveListPlacementMask) = 0xFFFFFF;
625 csr32(ctlr, ReceiveListPlacementConfiguration) |= ReceiveStats;
626 csr32(ctlr, SendInitiatorMask) = 0xFFFFFF;
627 csr32(ctlr, SendInitiatorConfiguration) |= SendStats;
628 csr32(ctlr, HostCoalescingMode) = 0;
629 for(i = 0; i < 200 && csr32(ctlr, HostCoalescingMode) != 0; i++)
632 iprint("bcm: host coalescing engine failed to stop\n");
635 csr32(ctlr, HostCoalescingRecvTicks) = 150;
636 csr32(ctlr, HostCoalescingSendTicks) = 150;
637 csr32(ctlr, RecvMaxCoalescedFrames) = 10;
638 csr32(ctlr, SendMaxCoalescedFrames) = 10;
639 csr32(ctlr, RecvMaxCoalescedFramesInt) = 0;
640 csr32(ctlr, SendMaxCoalescedFramesInt) = 0;
641 csr32(ctlr, StatusBlockHostAddr) = 0;
642 csr32(ctlr, StatusBlockHostAddr + 4) = PADDR(ctlr->status);
643 csr32(ctlr, HostCoalescingMode) |= Enable;
644 csr32(ctlr, ReceiveBDCompletionMode) |= Enable | Attn;
645 csr32(ctlr, ReceiveListPlacementMode) |= Enable;
646 csr32(ctlr, MACMode) |= MACEnable;
647 csr32(ctlr, MiscLocalControl) |= InterruptOnAttn | AutoSEEPROM;
648 csr32(ctlr, InterruptMailbox) = 0;
649 csr32(ctlr, WriteDMAMode) |= 0x200003fe; /* pulled out of my nose */
650 csr32(ctlr, ReadDMAMode) |= 0x3fe;
651 csr32(ctlr, ReceiveDataCompletionMode) |= Enable | Attn;
652 csr32(ctlr, SendDataCompletionMode) |= Enable;
653 csr32(ctlr, SendBDCompletionMode) |= Enable | Attn;
654 csr32(ctlr, ReceiveBDInitiatorMode) |= Enable | Attn;
655 csr32(ctlr, ReceiveDataBDInitiatorMode) |= Enable | (1<<4);
656 csr32(ctlr, SendDataInitiatorMode) |= Enable;
657 csr32(ctlr, SendBDInitiatorMode) |= Enable | Attn;
658 csr32(ctlr, SendBDSelectorMode) |= Enable | Attn;
660 while(replenish(ctlr) >= 0);
661 csr32(ctlr, TransmitMACMode) |= Enable;
662 csr32(ctlr, ReceiveMACMode) |= Enable;
663 csr32(ctlr, PowerControlStatus) &= ~3;
664 csr32(ctlr, MIStatus) |= 1<<0;
665 csr32(ctlr, MACEventEnable) = 0;
666 csr32(ctlr, MACEventStatus) |= (1<<12);
667 csr32(ctlr, MIMode) = 0xC0000;
669 miiw(ctlr, PhyControl, 1<<15);
670 for(i = 0; i < 1000 && miir(ctlr, PhyControl) & (1<<15); i++)
673 iprint("bcm: PHY failed to reset\n");
676 miiw(ctlr, PhyAuxControl, 2);
677 miir(ctlr, PhyIntStatus);
678 miir(ctlr, PhyIntStatus);
679 miiw(ctlr, PhyIntMask, ~(1<<1));
681 csr32(ctlr, MACEventEnable) |= 1<<12;
682 csr32(ctlr, MACHash) = -1;
683 csr32(ctlr, MACHash+4) = -1;
684 csr32(ctlr, MACHash+8) = -1;
685 csr32(ctlr, MACHash+12) = -1;
686 for(i = 0; i < 8; i++) csr32(ctlr, ReceiveRules + 8 * i) = 0;
687 csr32(ctlr, ReceiveRulesConfiguration) = 1 << 3;
688 csr32(ctlr, MSIMode) |= Enable;
689 csr32(ctlr, MiscHostCtl) &= ~(MaskPCIInt | ClearIntA);
699 while(pdev = pcimatch(pdev, 0, 0)) {
703 if(pdev->ccrb != 2 || pdev->ccru != 0)
705 if(pdev->vid != 0x14e4)
788 case BCM5906: /* ??? */
789 case BCM5906M: /* ??? */
790 case 0x1670: /* ??? */
794 ctlr = malloc(sizeof(Ctlr));
796 print("bcm: unable to alloc Ctlr\n");
799 ctlr->sends = malloc(sizeof(ctlr->sends[0]) * SendRingLen);
800 ctlr->recvs = malloc(sizeof(ctlr->recvs[0]) * RecvProdRingLen);
801 if(ctlr->sends == nil || ctlr->recvs == nil){
802 print("bcm: unable to alloc ctlr->sends and ctlr->recvs\n");
808 mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size);
810 print("bcm: can't map %8.8luX\n", pdev->mem[0].bar);
817 ctlr->port = pdev->mem[0].bar & ~0x0F;
818 ctlr->status = xspanalloc(20, 16, 0);
819 ctlr->recvprod = xspanalloc(32 * RecvProdRingLen, 16, 0);
820 ctlr->recvret = xspanalloc(32 * RecvRetRingLen, 16, 0);
821 ctlr->sendr = xspanalloc(16 * SendRingLen, 16, 0);
823 bcmtail->link = ctlr;
831 bcmpromiscuous(void* arg, int on)
835 ctlr = ((Ether*)arg)->ctlr;
837 csr32(ctlr, ReceiveMACMode) |= 1<<8;
839 csr32(ctlr, ReceiveMACMode) &= ~(1<<8);
843 bcmmulticast(void*, uchar*, int)
856 for(ctlr = bcmhead; ctlr != nil; ctlr = ctlr->link) {
860 if(edev->port == 0 || edev->port == ctlr->port) {
869 pcienable(ctlr->pdev);
870 pcisetbme(ctlr->pdev);
873 edev->port = ctlr->port;
874 edev->irq = ctlr->pdev->intl;
875 edev->tbdf = ctlr->pdev->tbdf;
876 edev->transmit = bcmtransmit;
877 edev->multicast = bcmmulticast;
878 edev->promiscuous = bcmpromiscuous;
882 if(bcminit(edev) < 0){
887 intrenable(edev->irq, bcminterrupt, edev, edev->tbdf, edev->name);
895 addethercard("bcm", bcmpnp);