2 * National Semiconductor DP8390 and clone
3 * Network Interface Controller.
6 #include "../port/lib.h"
11 #include "../port/error.h"
12 #include "../port/netif.h"
13 #include "../port/etherif.h"
15 #include "ether8390.h"
17 enum { /* NIC core registers */
18 Cr = 0x00, /* command register, all pages */
21 Clda0 = 0x01, /* current local DMA address 0 */
22 Clda1 = 0x02, /* current local DMA address 1 */
23 Bnry = 0x03, /* boundary pointer (R/W) */
24 Tsr = 0x04, /* transmit status register */
25 Ncr = 0x05, /* number of collisions register */
26 Fifo = 0x06, /* FIFO */
27 Isr = 0x07, /* interrupt status register (R/W) */
28 Crda0 = 0x08, /* current remote DMA address 0 */
29 Crda1 = 0x09, /* current remote DMA address 1 */
30 Rsr = 0x0C, /* receive status register */
31 Ref0 = 0x0D, /* frame alignment errors */
32 Ref1 = 0x0E, /* CRC errors */
33 Ref2 = 0x0F, /* missed packet errors */
36 Pstart = 0x01, /* page start register */
37 Pstop = 0x02, /* page stop register */
38 Tpsr = 0x04, /* transmit page start address */
39 Tbcr0 = 0x05, /* transmit byte count register 0 */
40 Tbcr1 = 0x06, /* transmit byte count register 1 */
41 Rsar0 = 0x08, /* remote start address register 0 */
42 Rsar1 = 0x09, /* remote start address register 1 */
43 Rbcr0 = 0x0A, /* remote byte count register 0 */
44 Rbcr1 = 0x0B, /* remote byte count register 1 */
45 Rcr = 0x0C, /* receive configuration register */
46 Tcr = 0x0D, /* transmit configuration register */
47 Dcr = 0x0E, /* data configuration register */
48 Imr = 0x0F, /* interrupt mask */
50 /* Page 1, read/write */
51 Par0 = 0x01, /* physical address register 0 */
52 Curr = 0x07, /* current page register */
53 Mar0 = 0x08, /* multicast address register 0 */
57 Stp = 0x01, /* stop */
58 Sta = 0x02, /* start */
59 Txp = 0x04, /* transmit packet */
60 Rd0 = 0x08, /* remote DMA command */
63 RdREAD = Rd0, /* remote read */
64 RdWRITE = Rd1, /* remote write */
65 RdSEND = Rd1|Rd0, /* send packet */
66 RdABORT = Rd2, /* abort/complete remote DMA */
67 Ps0 = 0x40, /* page select */
75 Prx = 0x01, /* packet received */
76 Ptx = 0x02, /* packet transmitted */
77 Rxe = 0x04, /* receive error */
78 Txe = 0x08, /* transmit error */
79 Ovw = 0x10, /* overwrite warning */
80 Cnt = 0x20, /* counter overflow */
81 Rdc = 0x40, /* remote DMA complete */
82 Rst = 0x80, /* reset status */
86 Wts = 0x01, /* word transfer select */
87 Bos = 0x02, /* byte order select */
88 Las = 0x04, /* long address select */
89 Ls = 0x08, /* loopback select */
90 Arm = 0x10, /* auto-initialise remote */
91 Ft0 = 0x20, /* FIFO threshold select */
100 Crc = 0x01, /* inhibit CRC */
101 Lb0 = 0x02, /* encoded loopback control */
103 LpbkNORMAL = 0x00, /* normal operation */
104 LpbkNIC = Lb0, /* internal NIC module loopback */
105 LpbkENDEC = Lb1, /* internal ENDEC module loopback */
106 LpbkEXTERNAL = Lb1|Lb0, /* external loopback */
107 Atd = 0x08, /* auto transmit disable */
108 Ofst = 0x10, /* collision offset enable */
112 Ptxok = 0x01, /* packet transmitted */
113 Col = 0x04, /* transmit collided */
114 Abt = 0x08, /* tranmit aborted */
115 Crs = 0x10, /* carrier sense lost */
116 Fu = 0x20, /* FIFO underrun */
117 Cdh = 0x40, /* CD heartbeat */
118 Owc = 0x80, /* out of window collision */
122 Sep = 0x01, /* save errored packets */
123 Ar = 0x02, /* accept runt packets */
124 Ab = 0x04, /* accept broadcast */
125 Am = 0x08, /* accept multicast */
126 Pro = 0x10, /* promiscuous physical */
127 Mon = 0x20, /* monitor mode */
131 Prxok = 0x01, /* packet received intact */
132 Crce = 0x02, /* CRC error */
133 Fae = 0x04, /* frame alignment error */
134 Fo = 0x08, /* FIFO overrun */
135 Mpa = 0x10, /* missed packet */
136 Phy = 0x20, /* physical/multicast address */
137 Dis = 0x40, /* receiver disabled */
138 Dfr = 0x80, /* deferring */
141 typedef struct Hdr Hdr;
150 dp8390getea(Ether* ether, uchar* ea)
159 * Get the ethernet address from the chip.
160 * Take care to restore the command register
164 cr = regr(ctlr, Cr) & ~Txp;
165 regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr));
166 for(i = 0; i < Eaddrlen; i++)
167 ea[i] = regr(ctlr, Par0+i);
173 dp8390setea(Ether* ether)
182 * Set the ethernet address into the chip.
183 * Take care to restore the command register
184 * afterwards. Don't care about multicast
185 * addresses as multicast is never enabled
189 cr = regr(ctlr, Cr) & ~Txp;
190 regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr));
191 for(i = 0; i < Eaddrlen; i++)
192 regw(ctlr, Par0+i, ether->ea[i]);
198 _dp8390read(Dp8390* ctlr, void* to, ulong from, ulong len)
204 * Read some data at offset 'from' in the card's memory
205 * using the DP8390 remote DMA facility, and place it at
206 * 'to' in main memory, via the I/O data port.
208 cr = regr(ctlr, Cr) & ~Txp;
209 regw(ctlr, Cr, Page0|RdABORT|Sta);
210 regw(ctlr, Isr, Rdc);
213 * Set up the remote DMA address and count.
215 len = ROUNDUP(len, ctlr->width);
216 regw(ctlr, Rbcr0, len & 0xFF);
217 regw(ctlr, Rbcr1, (len>>8) & 0xFF);
218 regw(ctlr, Rsar0, from & 0xFF);
219 regw(ctlr, Rsar1, (from>>8) & 0xFF);
222 * Start the remote DMA read and suck the data
223 * out of the I/O port.
225 regw(ctlr, Cr, Page0|RdREAD|Sta);
226 rdread(ctlr, to, len);
229 * Wait for the remote DMA to complete. The timeout
230 * is necessary because this routine may be called on
231 * a non-existent chip during initialisation and, due
232 * to the miracles of the bus, it's possible to get this
233 * far and still be talking to a slot full of nothing.
235 for(timo = 10000; (regr(ctlr, Isr) & Rdc) == 0 && timo; timo--)
238 regw(ctlr, Isr, Rdc);
245 dp8390read(Dp8390* ctlr, void* to, ulong from, ulong len)
250 v = _dp8390read(ctlr, to, from, len);
257 dp8390write(Dp8390* ctlr, ulong to, void* from, ulong len)
265 * Write some data to offset 'to' in the card's memory
266 * using the DP8390 remote DMA facility, reading it at
267 * 'from' in main memory, via the I/O data port.
269 cr = regr(ctlr, Cr) & ~Txp;
270 regw(ctlr, Cr, Page0|RdABORT|Sta);
271 regw(ctlr, Isr, Rdc);
273 len = ROUNDUP(len, ctlr->width);
276 * Set up the remote DMA address and count.
277 * This is straight from the DP8390[12D] datasheet,
278 * hence the initial set up for read.
279 * Assumption here that the A7000 EtherV card will
280 * never need a dummyrr.
282 if(ctlr->dummyrr && (ctlr->width == 1 || ctlr->width == 2)){
288 regw(ctlr, Rbcr0, (len+1+width) & 0xFF);
289 regw(ctlr, Rbcr1, ((len+1+width)>>8) & 0xFF);
290 regw(ctlr, Rsar0, crda & 0xFF);
291 regw(ctlr, Rsar1, (crda>>8) & 0xFF);
292 regw(ctlr, Cr, Page0|RdREAD|Sta);
294 for(timo=0;; timo++){
296 print("ether8390: dummyrr timeout; assuming nodummyrr\n");
300 crda = regr(ctlr, Crda0);
301 crda |= regr(ctlr, Crda1)<<8;
304 * Start the remote DMA write and make sure
305 * the registers are correct.
307 regw(ctlr, Cr, Page0|RdWRITE|Sta);
309 crda = regr(ctlr, Crda0);
310 crda |= regr(ctlr, Crda1)<<8;
312 panic("crda write %lud to %lud", crda, to);
319 regw(ctlr, Rsar0, to & 0xFF);
320 regw(ctlr, Rsar1, (to>>8) & 0xFF);
321 regw(ctlr, Rbcr0, len & 0xFF);
322 regw(ctlr, Rbcr1, (len>>8) & 0xFF);
323 regw(ctlr, Cr, Page0|RdWRITE|Sta);
327 * Pump the data into the I/O port
328 * then wait for the remote DMA to finish.
330 rdwrite(ctlr, from, len);
331 for(timo = 10000; (regr(ctlr, Isr) & Rdc) == 0 && timo; timo--)
334 regw(ctlr, Isr, Rdc);
341 ringinit(Dp8390* ctlr)
343 regw(ctlr, Pstart, ctlr->pstart);
344 regw(ctlr, Pstop, ctlr->pstop);
345 regw(ctlr, Bnry, ctlr->pstop-1);
347 regw(ctlr, Cr, Page1|RdABORT|Stp);
348 regw(ctlr, Curr, ctlr->pstart);
349 regw(ctlr, Cr, Page0|RdABORT|Stp);
351 ctlr->nxtpkt = ctlr->pstart;
355 getcurr(Dp8390* ctlr)
359 cr = regr(ctlr, Cr) & ~Txp;
360 regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr));
361 curr = regr(ctlr, Curr);
368 receive(Ether* ether)
373 ulong count, data, len;
377 for(curr = getcurr(ctlr); ctlr->nxtpkt != curr; curr = getcurr(ctlr)){
378 data = ctlr->nxtpkt*Dp8390BufSz;
380 memmove(&hdr, (uchar*)KADDR(ether->mem) + data, sizeof(Hdr));
382 _dp8390read(ctlr, &hdr, data, sizeof(Hdr));
385 * Don't believe the upper byte count, work it
386 * out from the software next-page pointer and
387 * the current next-page pointer.
389 if(hdr.next > ctlr->nxtpkt)
390 len = hdr.next - ctlr->nxtpkt - 1;
392 len = (ctlr->pstop-ctlr->nxtpkt) + (hdr.next-ctlr->pstart) - 1;
393 if(hdr.len0 > (Dp8390BufSz-sizeof(Hdr)))
396 len = ((len<<8)|hdr.len0)-4;
399 * Chip is badly scrogged, reinitialise the ring.
401 if(hdr.next < ctlr->pstart || hdr.next >= ctlr->pstop
402 || len < 60 || len > sizeof(Etherpkt)){
403 print("dp8390: H%2.2ux+%2.2ux+%2.2ux+%2.2ux,%lud\n",
404 hdr.status, hdr.next, hdr.len0, hdr.len1, len);
405 regw(ctlr, Cr, Page0|RdABORT|Stp);
407 regw(ctlr, Cr, Page0|RdABORT|Sta);
413 * If it's a good packet read it in to the software buffer.
414 * If the packet wraps round the hardware ring, read it in
417 if((hdr.status & (Fo|Fae|Crce|Prxok)) == Prxok && (bp = iallocb(len))){
422 if((data+len) >= ctlr->pstop*Dp8390BufSz){
423 count = ctlr->pstop*Dp8390BufSz - data;
425 memmove(p, (uchar*)KADDR(ether->mem) + data, count);
427 _dp8390read(ctlr, p, data, count);
429 data = ctlr->pstart*Dp8390BufSz;
434 memmove(p, (uchar*)KADDR(ether->mem) + data, len);
436 _dp8390read(ctlr, p, data, len);
440 * Copy the packet to whoever wants it.
446 * Finished with this packet, update the
447 * hardware and software ring pointers.
449 ctlr->nxtpkt = hdr.next;
452 if(hdr.next < ctlr->pstart)
453 hdr.next = ctlr->pstop-1;
454 regw(ctlr, Bnry, hdr.next);
459 txstart(Ether* ether)
464 uchar minpkt[ETHERMINTU], *rp;
469 * This routine is called both from the top level and from interrupt
470 * level and expects to be called with ctlr already locked.
474 bp = qget(ether->oq);
479 * copy it to the card's memory by the appropriate means;
480 * start the transmission.
485 memmove((uchar*)KADDR(ether->mem) + ctlr->tstart*Dp8390BufSz, rp, len);
487 dp8390write(ctlr, ctlr->tstart*Dp8390BufSz, rp, len);
490 regw(ctlr, Tbcr0, len & 0xFF);
491 regw(ctlr, Tbcr1, (len>>8) & 0xFF);
492 regw(ctlr, Cr, Page0|RdABORT|Txp|Sta);
499 transmit(Ether* ether)
511 overflow(Ether *ether)
520 * The following procedure is taken from the DP8390[12D] datasheet,
521 * it seems pretty adamant that this is what has to be done.
523 txp = regr(ctlr, Cr) & Txp;
524 regw(ctlr, Cr, Page0|RdABORT|Stp);
526 regw(ctlr, Rbcr0, 0);
527 regw(ctlr, Rbcr1, 0);
530 if(txp && (regr(ctlr, Isr) & (Txe|Ptx)) == 0)
533 regw(ctlr, Tcr, LpbkNIC);
534 regw(ctlr, Cr, Page0|RdABORT|Sta);
536 regw(ctlr, Isr, Ovw);
537 regw(ctlr, Tcr, LpbkNORMAL);
540 regw(ctlr, Cr, Page0|RdABORT|Txp|Sta);
544 interrupt(Ureg*, void* arg)
554 * While there is something of interest,
555 * clear all the interrupts and process.
558 regw(ctlr, Imr, 0x00);
559 while(isr = (regr(ctlr, Isr) & (Cnt|Ovw|Txe|Rxe|Ptx|Prx))){
562 regw(ctlr, Isr, Ovw);
567 * Packets have been received.
568 * Take a spin round the ring.
572 regw(ctlr, Isr, Rxe|Prx);
576 * A packet completed transmission, successfully or
577 * not. Start transmission on the next buffered packet,
578 * and wake the output routine.
582 if((isr & Txe) && (r & (Cdh|Fu|Crs|Abt))){
583 print("dp8390: Tsr %#2.2ux", r);
587 regw(ctlr, Isr, Txe|Ptx);
596 ether->frames += regr(ctlr, Ref0);
597 ether->crcs += regr(ctlr, Ref1);
598 ether->buffs += regr(ctlr, Ref2);
599 regw(ctlr, Isr, Cnt);
602 regw(ctlr, Imr, Cnt|Ovw|Txe|Rxe|Ptx|Prx);
606 static uchar allmar[8] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
609 setfilter(Ether *ether, Dp8390 *ctlr)
620 } else if(ether->nmaddr){
625 cr = regr(ctlr, Cr) & ~Txp;
626 regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr));
627 for(i = 0; i < 8; i++)
628 regw(ctlr, Mar0+i, *(mar++));
635 promiscuous(void *arg, int )
644 setfilter(ether, ctlr);
649 setbit(Dp8390 *ctlr, int bit, int on)
656 if(++(ctlr->mref[bit]) == 1)
657 ctlr->mar[i] |= 1<<h;
659 if(--(ctlr->mref[bit]) <= 0){
661 ctlr->mar[i] &= ~(1<<h);
666 static uchar reverse[64];
669 multicast(void* arg, uchar *addr, int on)
679 for(i = 0; i < 64; i++)
680 reverse[i] = ((i&1)<<5) | ((i&2)<<3) | ((i&4)<<1)
681 | ((i&8)>>1) | ((i&16)>>3) | ((i&32)>>5);
687 h = ethercrc(addr, 6);
689 setbit(ctlr, reverse[h&0x3f], on);
690 setfilter(ether, ctlr);
703 * Enable the chip for transmit/receive.
704 * The init routine leaves the chip in monitor
705 * mode. Clear the missed-packet counter, it
706 * increments while in monitor mode.
707 * Sometimes there's an interrupt pending at this
708 * point but there's nothing in the Isr, so
709 * any pending interrupts are cleared and the
710 * mask of acceptable interrupts is enabled here.
718 regw(ctlr, Isr, 0xFF);
719 regw(ctlr, Imr, Cnt|Ovw|Txe|Rxe|Ptx|Prx);
721 r = regr(ctlr, Ref2);
722 regw(ctlr, Tcr, LpbkNORMAL);
728 disable(Dp8390* ctlr)
733 * Stop the chip. Set the Stp bit and wait for the chip
734 * to finish whatever was on its tiny mind before it sets
736 * The timeout is needed because there may not be a real
737 * chip there if this is called when probing for a device
740 regw(ctlr, Cr, Page0|RdABORT|Stp);
741 regw(ctlr, Rbcr0, 0);
742 regw(ctlr, Rbcr1, 0);
743 for(timo = 10000; (regr(ctlr, Isr) & Rst) == 0 && timo; timo--)
748 dp8390reset(Ether* ether)
755 * This is the initialisation procedure described
756 * as 'mandatory' in the datasheet, with references
757 * to the 3C503 technical reference manual.
761 regw(ctlr, Dcr, Ft4WORD|Ls|Wts);
763 regw(ctlr, Dcr, Ft4WORD|Ls);
765 regw(ctlr, Rbcr0, 0);
766 regw(ctlr, Rbcr1, 0);
768 regw(ctlr, Tcr, LpbkNIC);
769 regw(ctlr, Rcr, Mon);
772 * Init the ring hardware and software ring pointers.
773 * Can't initialise ethernet address as it may not be
777 regw(ctlr, Tpsr, ctlr->tstart);
780 * Clear any pending interrupts and mask then all off.
782 regw(ctlr, Isr, 0xFF);
786 * Leave the chip initialised,
787 * but in monitor mode.
789 regw(ctlr, Cr, Page0|RdABORT|Sta);
792 * Set up the software configuration.
794 ether->attach = attach;
795 ether->transmit = transmit;
798 ether->promiscuous = promiscuous;
799 ether->multicast = multicast;
802 intrenable(ether->irq, interrupt, ether, ether->tbdf, ether->name);