2 * Intel 8256[367], 8257[1-9], 8258[03], i350
3 * Gigabit Ethernet PCI-Express Controllers
4 * Coraid EtherDrive® hba
7 #include "../port/lib.h"
12 #include "../port/error.h"
13 #include "../port/netif.h"
18 * note: the 82575, 82576 and 82580 are operated using registers aliased
19 * to the 82563-style architecture. many features seen in the 82598
20 * are also seen in the 82575 part.
26 Ctrl = 0x0000, /* Device Control */
27 Status = 0x0008, /* Device Status */
28 Eec = 0x0010, /* EEPROM/Flash Control/Data */
29 Eerd = 0x0014, /* EEPROM Read */
30 Ctrlext = 0x0018, /* Extended Device Control */
31 Fla = 0x001c, /* Flash Access */
32 Mdic = 0x0020, /* MDI Control */
33 Fcal = 0x0028, /* Flow Control Address Low */
34 Fcah = 0x002C, /* Flow Control Address High */
35 Fct = 0x0030, /* Flow Control Type */
36 Kumctrlsta = 0x0034, /* Kumeran Control and Status Register */
37 Connsw = 0x0034, /* copper / fiber switch control; 82575/82576 */
38 Vet = 0x0038, /* VLAN EtherType */
39 Fcttv = 0x0170, /* Flow Control Transmit Timer Value */
40 Txcw = 0x0178, /* Transmit Configuration Word */
41 Rxcw = 0x0180, /* Receive Configuration Word */
42 Ledctl = 0x0E00, /* LED control */
43 Pba = 0x1000, /* Packet Buffer Allocation */
44 Pbs = 0x1008, /* Packet Buffer Size */
48 Icr = 0x00C0, /* Interrupt Cause Read */
49 Itr = 0x00c4, /* Interrupt Throttling Rate */
50 Ics = 0x00C8, /* Interrupt Cause Set */
51 Ims = 0x00D0, /* Interrupt Mask Set/Read */
52 Imc = 0x00D8, /* Interrupt mask Clear */
53 Iam = 0x00E0, /* Interrupt acknowledge Auto Mask */
54 Eitr = 0x1680, /* Extended itr; 82575/6 80 only */
58 Rctl = 0x0100, /* Control */
59 Ert = 0x2008, /* Early Receive Threshold (573[EVL], 82578 only) */
60 Fcrtl = 0x2160, /* Flow Control RX Threshold Low */
61 Fcrth = 0x2168, /* Flow Control Rx Threshold High */
62 Psrctl = 0x2170, /* Packet Split Receive Control */
63 Drxmxod = 0x2540, /* dma max outstanding bytes (82575) */
64 Rdbal = 0x2800, /* Rdesc Base Address Low Queue 0 */
65 Rdbah = 0x2804, /* Rdesc Base Address High Queue 0 */
66 Rdlen = 0x2808, /* Descriptor Length Queue 0 */
67 Srrctl = 0x280c, /* split and replication rx control (82575) */
68 Rdh = 0x2810, /* Descriptor Head Queue 0 */
69 Rdt = 0x2818, /* Descriptor Tail Queue 0 */
70 Rdtr = 0x2820, /* Descriptor Timer Ring */
71 Rxdctl = 0x2828, /* Descriptor Control */
72 Radv = 0x282C, /* Interrupt Absolute Delay Timer */
73 Rsrpd = 0x2c00, /* Small Packet Detect */
74 Raid = 0x2c08, /* ACK interrupt delay */
75 Cpuvec = 0x2c10, /* CPU Vector */
76 Rxcsum = 0x5000, /* Checksum Control */
77 Rmpl = 0x5004, /* rx maximum packet length (82575) */
78 Rfctl = 0x5008, /* Filter Control */
79 Mta = 0x5200, /* Multicast Table Array */
80 Ral = 0x5400, /* Receive Address Low */
81 Rah = 0x5404, /* Receive Address High */
82 Vfta = 0x5600, /* VLAN Filter Table Array */
83 Mrqc = 0x5818, /* Multiple Receive Queues Command */
87 Tctl = 0x0400, /* Transmit Control */
88 Tipg = 0x0410, /* Transmit IPG */
89 Tkabgtxd = 0x3004, /* glci afe band gap transmit ref data, or something */
90 Tdbal = 0x3800, /* Tdesc Base Address Low */
91 Tdbah = 0x3804, /* Tdesc Base Address High */
92 Tdlen = 0x3808, /* Descriptor Length */
93 Tdh = 0x3810, /* Descriptor Head */
94 Tdt = 0x3818, /* Descriptor Tail */
95 Tidv = 0x3820, /* Interrupt Delay Value */
96 Txdctl = 0x3828, /* Descriptor Control */
97 Tadv = 0x382C, /* Interrupt Absolute Delay Timer */
98 Tarc0 = 0x3840, /* Arbitration Counter Queue 0 */
102 Statistics = 0x4000, /* Start of Statistics Area */
103 Gorcl = 0x88/4, /* Good Octets Received Count */
104 Gotcl = 0x90/4, /* Good Octets Transmitted Count */
105 Torl = 0xC0/4, /* Total Octets Received */
106 Totl = 0xC8/4, /* Total Octets Transmitted */
107 Nstatistics = 0x124/4,
111 Lrst = 1<<3, /* link reset */
112 Slu = 1<<6, /* Set Link Up */
113 Devrst = 1<<26, /* Device Reset */
114 Rfce = 1<<27, /* Receive Flow Control Enable */
115 Tfce = 1<<28, /* Transmit Flow Control Enable */
116 Phyrst = 1<<31, /* Phy Reset */
120 Lu = 1<<1, /* Link Up */
121 Lanid = 3<<2, /* mask for Lan ID. */
122 Txoff = 1<<4, /* Transmission Paused */
123 Tbimode = 1<<5, /* TBI Mode Indication */
124 Phyra = 1<<10, /* PHY Reset Asserted */
125 GIOme = 1<<19, /* GIO Master Enable Status */
135 EEstart = 1<<0, /* Start Read */
136 EEdone = 1<<1, /* Read done */
140 Eerst = 1<<13, /* EEPROM Reset */
141 Linkmode = 3<<22, /* linkmode */
142 Internalphy = 0<<22, /* " internal phy (copper) */
143 Sgmii = 2<<22, /* " sgmii */
144 Serdes = 3<<22, /* " serdes */
149 Enrgirq = 1<<2, /* interrupt on power detect (enrgsrc) */
152 enum { /* EEPROM content offsets */
153 Ea = 0x00, /* Ethernet Address */
157 MDIdMASK = 0x0000FFFF, /* Data */
159 MDIrMASK = 0x001F0000, /* PHY Register Address */
161 MDIpMASK = 0x03E00000, /* PHY Address */
163 MDIwop = 0x04000000, /* Write Operation */
164 MDIrop = 0x08000000, /* Read Operation */
165 MDIready = 0x10000000, /* End of Transaction */
166 MDIie = 0x20000000, /* Interrupt Enable */
167 MDIe = 0x40000000, /* Error */
170 enum { /* phy interface */
171 Phyctl = 0, /* phy ctl register */
172 Physr = 1, /* phy status register */
173 Phyid1 = 2, /* phy id1 */
174 Phyid2 = 3, /* phy id2 */
175 Phyisr = 19, /* 82563 phy interrupt status register */
176 Phylhr = 19, /* 8257[12] link health register */
177 Physsr = 17, /* phy secondary status register */
178 Phyprst = 193<<8 | 17, /* 8256[34] phy port reset */
179 Phyier = 18, /* 82573 phy interrupt enable register */
180 Phypage = 22, /* 8256[34] page register */
181 Phystat = 26, /* 82580 phy status */
183 Rtlink = 1<<10, /* realtime link status */
184 Phyan = 1<<11, /* phy has autonegotiated */
187 Ran = 1<<9, /* restart auto negotiation */
188 Ean = 1<<12, /* enable auto negotiation */
191 Prst = 1<<0, /* reset the port */
193 /* 82573 Phyier bits */
194 Lscie = 1<<10, /* link status changed ie */
195 Ancie = 1<<11, /* auto negotiation complete ie */
196 Spdie = 1<<14, /* speed changed ie */
197 Panie = 1<<15, /* phy auto negotiation error ie */
199 /* Phylhr/Phyisr bits */
200 Anf = 1<<6, /* lhr: auto negotiation fault */
201 Ane = 1<<15, /* isr: auto negotiation error */
203 /* 82580 Phystat bits */
204 Ans = 1<<14 | 1<<15, /* 82580 autoneg. status */
205 Link = 1<<6, /* 82580 Link */
207 /* Rxcw builtin serdes */
220 enum { /* fiber (pcs) interface */
221 Pcsctl = 0x4208, /* pcs control */
222 Pcsstat = 0x420c, /* pcs status */
225 Pan = 1<<16, /* autoegotiate */
226 Prestart = 1<<17, /* restart an (self clearing) */
229 Linkok = 1<<0, /* link is okay */
230 Andone = 1<<16, /* an phase is done see below for success */
231 Anbad = 1<<19 | 1<<20, /* Anerror | Anremfault */
234 enum { /* Icr, Ics, Ims, Imc */
235 Txdw = 0x00000001, /* Transmit Descriptor Written Back */
236 Txqe = 0x00000002, /* Transmit Queue Empty */
237 Lsc = 0x00000004, /* Link Status Change */
238 Rxseq = 0x00000008, /* Receive Sequence Error */
239 Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */
240 Rxo = 0x00000040, /* Receiver Overrun */
241 Rxt0 = 0x00000080, /* Receiver Timer Interrupt; !82575/6/80 only */
242 Rxdw = 0x00000080, /* Rdesc write back; 82575/6/80 only */
243 Mdac = 0x00000200, /* MDIO Access Completed */
244 Rxcfgset = 0x00000400, /* Receiving /C/ ordered sets */
245 Ack = 0x00020000, /* Receive ACK frame */
246 Omed = 1<<20, /* media change; pcs interface */
250 TxcwFd = 0x00000020, /* Full Duplex */
251 TxcwHd = 0x00000040, /* Half Duplex */
252 TxcwPauseMASK = 0x00000180, /* Pause */
254 TxcwPs = 1<<TxcwPauseSHIFT, /* Pause Supported */
255 TxcwAs = 2<<TxcwPauseSHIFT, /* Asymmetric FC desired */
256 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
258 TxcwNpr = 0x00008000, /* Next Page Request */
259 TxcwConfig = 0x40000000, /* Transmit COnfig Control */
260 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
264 Rrst = 0x00000001, /* Receiver Software Reset */
265 Ren = 0x00000002, /* Receiver Enable */
266 Sbp = 0x00000004, /* Store Bad Packets */
267 Upe = 0x00000008, /* Unicast Promiscuous Enable */
268 Mpe = 0x00000010, /* Multicast Promiscuous Enable */
269 Lpe = 0x00000020, /* Long Packet Reception Enable */
270 RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */
271 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
272 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
273 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
274 MoMASK = 0x00003000, /* Multicast Offset */
275 Bam = 0x00008000, /* Broadcast Accept Mode */
276 BsizeMASK = 0x00030000, /* Receive Buffer Size */
277 Bsize16384 = 0x00010000, /* Bsex = 1 */
278 Bsize8192 = 0x00020000, /* Bsex = 1 */
279 Bsize2048 = 0x00000000,
280 Bsize1024 = 0x00010000,
281 Bsize512 = 0x00020000,
282 Bsize256 = 0x00030000,
283 BsizeFlex = 0x08000000, /* Flexable Bsize in 1kb increments */
284 Vfe = 0x00040000, /* VLAN Filter Enable */
285 Cfien = 0x00080000, /* Canonical Form Indicator Enable */
286 Cfi = 0x00100000, /* Canonical Form Indicator value */
287 Dpf = 0x00400000, /* Discard Pause Frames */
288 Pmcf = 0x00800000, /* Pass MAC Control Frames */
289 Bsex = 0x02000000, /* Buffer Size Extension */
290 Secrc = 0x04000000, /* Strip CRC from incoming packet */
298 Trst = 0x00000001, /* Transmitter Software Reset */
299 Ten = 0x00000002, /* Transmit Enable */
300 Psp = 0x00000008, /* Pad Short Packets */
301 Mulr = 0x10000000, /* Allow multiple concurrent requests */
302 CtMASK = 0x00000FF0, /* Collision Threshold */
304 ColdMASK = 0x003FF000, /* Collision Distance */
306 Swxoff = 0x00400000, /* Sofware XOFF Transmission */
307 Pbe = 0x00800000, /* Packet Burst Enable */
308 Rtlc = 0x01000000, /* Re-transmit on Late Collision */
309 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
312 enum { /* [RT]xdctl */
313 PthreshMASK = 0x0000003F, /* Prefetch Threshold */
315 HthreshMASK = 0x00003F00, /* Host Threshold */
317 WthreshMASK = 0x003F0000, /* Writeback Threshold */
319 Gran = 0x01000000, /* Granularity; not 82575 */
324 Ipofl = 0x0100, /* IP Checksum Off-load Enable */
325 Tuofl = 0x0200, /* TCP/UDP Checksum Off-load Enable */
328 typedef struct Rd { /* Receive Descriptor */
337 enum { /* Rd status */
338 Rdd = 0x01, /* Descriptor Done */
339 Reop = 0x02, /* End of Packet */
340 Ixsm = 0x04, /* Ignore Checksum Indication */
341 Vp = 0x08, /* Packet is 802.1Q (matched VET) */
342 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
343 Ipcs = 0x40, /* IP Checksum Calculated on Packet */
344 Pif = 0x80, /* Passed in-exact filter */
347 enum { /* Rd errors */
348 Ce = 0x01, /* CRC Error or Alignment Error */
349 Se = 0x02, /* Symbol Error */
350 Seq = 0x04, /* Sequence Error */
351 Cxe = 0x10, /* Carrier Extension Error */
352 Tcpe = 0x20, /* TCP/UDP Checksum Error */
353 Ipe = 0x40, /* IP Checksum Error */
354 Rxe = 0x80, /* RX Data Error */
357 typedef struct { /* Transmit Descriptor */
358 u32int addr[2]; /* Data */
363 enum { /* Tdesc control */
364 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
366 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
367 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
368 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
369 Teop = 0x01000000, /* End of Packet (DD) */
370 PtypeIP = 0x02000000, /* IP Packet Type (CD) */
371 Ifcs = 0x02000000, /* Insert FCS (DD) */
372 Tse = 0x04000000, /* TCP Segmentation Enable */
373 Rs = 0x08000000, /* Report Status */
374 Rps = 0x10000000, /* Report Status Sent */
375 Dext = 0x20000000, /* Descriptor Extension */
376 Vle = 0x40000000, /* VLAN Packet Enable */
377 Ide = 0x80000000, /* Interrupt Delay Enable */
380 enum { /* Tdesc status */
381 Tdd = 0x0001, /* Descriptor Done */
382 Ec = 0x0002, /* Excess Collisions */
383 Lc = 0x0004, /* Late Collision */
384 Tu = 0x0008, /* Transmit Underrun */
385 CssMASK = 0xFF00, /* Checksum Start Field */
397 /* 16 and 32-bit flash registers for ich flash parts */
398 Bfpr = 0x00/4, /* flash base 0:12; lim 16:28 */
399 Fsts = 0x04/2, /* flash status; Hsfsts */
400 Fctl = 0x06/2, /* flash control; Hsfctl */
401 Faddr = 0x08/4, /* flash address to r/w */
402 Fdata = 0x10/4, /* data @ address */
404 /* status register */
405 Fdone = 1<<0, /* flash cycle done */
406 Fcerr = 1<<1, /* cycle error; write 1 to clear */
407 Ael = 1<<2, /* direct access error log; 1 to clear */
408 Scip = 1<<5, /* spi cycle in progress */
409 Fvalid = 1<<14, /* flash descriptor valid */
411 /* control register */
412 Fgo = 1<<0, /* start cycle */
413 Flcycle = 1<<1, /* two bits: r=0; w=2 */
414 Fdbc = 1<<8, /* bytes to read; 5 bits */
418 Nrd = 256, /* power of two */
419 Ntd = 128, /* power of two */
420 Nrb = 512+512, /* private receive buffers per Ctlr */
421 Rbalign = BY2PG, /* rx buffer alignment */
425 * cavet emptor: 82577/78 have been entered speculatitively.
426 * awating datasheet from intel.
459 typedef struct Ctlrtype Ctlrtype;
467 static Ctlrtype cttab[Nctlrtype] = {
468 i82563, 9014, Fpba, "i82563",
469 i82566, 1514, Fload, "i82566",
470 i82567, 9234, Fload, "i82567",
471 i82567m, 1514, Fload, "i82567m",
472 i82571, 9234, Fpba, "i82571",
473 i82572, 9234, Fpba, "i82572",
474 i82573, 8192, Fert, "i82573", /* terrible perf above 8k */
475 i82574, 9018, 0, "i82574",
476 i82575, 9728, F75|Fflashea, "i82575",
477 i82576, 9728, F75, "i82576",
478 i82577, 4096, Fload|Fert, "i82577",
479 i82577m, 1514, Fload|Fert, "i82577",
480 i82578, 4096, Fload|Fert, "i82578",
481 i82578m, 1514, Fload|Fert, "i82578",
482 i82579, 9018, Fload|Fert|F79phy, "i82579",
483 i82580, 9728, F75|F79phy, "i82580",
484 i82583, 1514, 0, "i82583",
485 i350, 9728, F75|F79phy, "i350",
488 typedef void (*Freefn)(Block*);
490 typedef struct Ctlr Ctlr;
499 QLock alock; /* attach */
500 void *alloc; /* receive/transmit descriptors */
507 int im; /* interrupt mask */
513 u32int statistics[Nstatistics];
526 uchar ra[Eaddrlen]; /* receive address */
527 u32int mta[128]; /* multicast table array */
532 Rd *rdba; /* receive descriptor base address */
533 Block **rb; /* receive buffers */
534 uint rdh; /* receive descriptor head */
535 uint rdt; /* receive descriptor tail */
536 int rdtr; /* receive delay timer ring value */
537 int radv; /* receive interrupt absolute delay timer */
542 Td *tdba; /* transmit descriptor base address */
543 Block **tb; /* transmit buffers */
544 int tdh; /* transmit descriptor head */
545 int tdt; /* transmit descriptor tail */
550 u32int pba; /* packet buffer allocation */
553 #define csr32r(c, r) (*((c)->nic+((r)/4)))
554 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
556 static Ctlr *i82563ctlrhead;
557 static Ctlr *i82563ctlrtail;
559 static char *statistics[Nstatistics] = {
566 "Excessive Collisions",
567 "Multiple Collision",
575 "Carrier Extension Error",
576 "Receive Error Length",
582 "FC Received Unsupported",
583 "Packets Received (64 Bytes)",
584 "Packets Received (65-127 Bytes)",
585 "Packets Received (128-255 Bytes)",
586 "Packets Received (256-511 Bytes)",
587 "Packets Received (512-1023 Bytes)",
588 "Packets Received (1024-mtu Bytes)",
589 "Good Packets Received",
590 "Broadcast Packets Received",
591 "Multicast Packets Received",
592 "Good Packets Transmitted",
594 "Good Octets Received",
596 "Good Octets Transmitted",
600 "Receive No Buffers",
605 "Management Packets Rx",
606 "Management Packets Drop",
607 "Management Packets Tx",
608 "Total Octets Received",
610 "Total Octets Transmitted",
612 "Total Packets Received",
613 "Total Packets Transmitted",
614 "Packets Transmitted (64 Bytes)",
615 "Packets Transmitted (65-127 Bytes)",
616 "Packets Transmitted (128-255 Bytes)",
617 "Packets Transmitted (256-511 Bytes)",
618 "Packets Transmitted (512-1023 Bytes)",
619 "Packets Transmitted (1024-mtu Bytes)",
620 "Multicast Packets Transmitted",
621 "Broadcast Packets Transmitted",
622 "TCP Segmentation Context Transmitted",
623 "TCP Segmentation Context Fail",
624 "Interrupt Assertion",
625 "Interrupt Rx Pkt Timer",
626 "Interrupt Rx Abs Timer",
627 "Interrupt Tx Pkt Timer",
628 "Interrupt Tx Abs Timer",
629 "Interrupt Tx Queue Empty",
630 "Interrupt Tx Desc Low",
632 "Interrupt Rx Overrun",
638 return cttab[c->type].name;
642 i82563ifstat(Ether *edev, void *a, long n, ulong offset)
644 char *s, *p, *e, *stat;
649 p = s = smalloc(READSTR);
655 for(i = 0; i < Nstatistics; i++){
656 r = csr32r(ctlr, Statistics + i*4);
657 if((stat = statistics[i]) == nil)
665 ruvl += (uvlong)csr32r(ctlr, Statistics+(i+1)*4) << 32;
667 tuvl += ctlr->statistics[i];
668 tuvl += (uvlong)ctlr->statistics[i+1] << 32;
671 ctlr->statistics[i] = tuvl;
672 ctlr->statistics[i+1] = tuvl >> 32;
673 p = seprint(p, e, "%s: %llud %llud\n", stat, tuvl, ruvl);
678 ctlr->statistics[i] += r;
679 if(ctlr->statistics[i] == 0)
681 p = seprint(p, e, "%s: %ud %ud\n", stat,
682 ctlr->statistics[i], r);
687 p = seprint(p, e, "lintr: %ud %ud\n", ctlr->lintr, ctlr->lsleep);
688 p = seprint(p, e, "rintr: %ud %ud\n", ctlr->rintr, ctlr->rsleep);
689 p = seprint(p, e, "tintr: %ud %ud\n", ctlr->tintr, ctlr->txdw);
690 p = seprint(p, e, "ixcs: %ud %ud %ud\n", ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
691 p = seprint(p, e, "rdtr: %ud\n", ctlr->rdtr);
692 p = seprint(p, e, "radv: %ud\n", ctlr->radv);
693 p = seprint(p, e, "ctrl: %.8ux\n", csr32r(ctlr, Ctrl));
694 p = seprint(p, e, "ctrlext: %.8ux\n", csr32r(ctlr, Ctrlext));
695 p = seprint(p, e, "status: %.8ux\n", csr32r(ctlr, Status));
696 p = seprint(p, e, "txcw: %.8ux\n", csr32r(ctlr, Txcw));
697 p = seprint(p, e, "txdctl: %.8ux\n", csr32r(ctlr, Txdctl));
698 p = seprint(p, e, "pba: %.8ux\n", ctlr->pba);
700 p = seprint(p, e, "speeds: 10:%ud 100:%ud 1000:%ud ?:%ud\n",
701 ctlr->speeds[0], ctlr->speeds[1], ctlr->speeds[2], ctlr->speeds[3]);
702 p = seprint(p, e, "type: %s\n", cname(ctlr));
704 // p = seprint(p, e, "eeprom:");
705 // for(i = 0; i < 0x40; i++){
706 // if(i && ((i & 7) == 0))
707 // p = seprint(p, e, "\n ");
708 // p = seprint(p, e, " %4.4ux", ctlr->eeprom[i]);
710 // p = seprint(p, e, "\n");
713 n = readstr(offset, a, n, s);
715 qunlock(&ctlr->slock);
721 i82563promiscuous(void *arg, int on)
730 rctl = csr32r(ctlr, Rctl);
736 csr32w(ctlr, Rctl, rctl);
740 i82563multicast(void *arg, uchar *addr, int on)
750 if(ctlr->type == i82566)
752 bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
754 * multiple ether addresses can hash to the same filter bit,
755 * so it's never safe to clear a filter bit.
756 * if we want to clear filter bits, we need to keep track of
757 * all the multicast addresses in use, clear all the filter bits,
758 * then set the ones corresponding to in-use addresses.
761 ctlr->mta[x] |= 1<<bit;
763 // ctlr->mta[x] &= ~(1<<bit);
765 csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
769 i82563im(Ctlr *ctlr, int im)
771 ilock(&ctlr->imlock);
773 csr32w(ctlr, Ims, ctlr->im);
774 iunlock(&ctlr->imlock);
778 i82563txinit(Ctlr *ctlr)
784 if(cttab[ctlr->type].flag & F75)
785 csr32w(ctlr, Tctl, 0x0F<<CtSHIFT | Psp);
787 csr32w(ctlr, Tctl, 0x0F<<CtSHIFT | Psp | 66<<ColdSHIFT | Mulr);
788 csr32w(ctlr, Tipg, 6<<20 | 8<<10 | 8); /* yb sez: 0x702008 */
789 for(i = 0; i < ctlr->ntd; i++){
790 if((b = ctlr->tb[i]) != nil){
794 memset(&ctlr->tdba[i], 0, sizeof(Td));
796 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
797 csr32w(ctlr, Tdbah, 0);
798 csr32w(ctlr, Tdlen, ctlr->ntd * sizeof(Td));
799 ctlr->tdh = PREV(0, ctlr->ntd);
800 csr32w(ctlr, Tdh, 0);
802 csr32w(ctlr, Tdt, 0);
803 csr32w(ctlr, Tidv, 128);
804 csr32w(ctlr, Tadv, 64);
805 csr32w(ctlr, Tctl, csr32r(ctlr, Tctl) | Ten);
806 r = csr32r(ctlr, Txdctl) & ~WthreshMASK;
807 r |= 4<<WthreshSHIFT | 4<<PthreshSHIFT;
808 if(cttab[ctlr->type].flag & F75)
810 csr32w(ctlr, Txdctl, r);
814 i82563cleanup(Ctlr *c)
820 while(c->tdba[n = NEXT(tdh, c->ntd)].status & Tdd){
822 if((b = c->tb[tdh]) != nil){
826 iprint("82563 tx underrun!\n");
827 c->tdba[tdh].status = 0;
839 return (c->im & Txdw) == 0;
859 n = NEXT(tdt, ctlr->ntd);
860 if(n == i82563cleanup(ctlr)){
862 i82563im(ctlr, Txdw);
863 sleep(&ctlr->trendez, notrim, ctlr);
866 bp = qbread(edev->oq, 100000);
867 td = &ctlr->tdba[tdt];
868 td->addr[0] = PCIWADDR(bp->rp);
870 td->control = Ide|Rs|Ifcs|Teop|BLEN(bp);
874 csr32w(ctlr, Tdt, tdt);
879 i82563replenish(Ctlr *ctlr)
886 for(rdt = ctlr->rdt; NEXT(rdt, ctlr->nrd) != ctlr->rdh; rdt = NEXT(rdt, ctlr->nrd)){
887 rd = &ctlr->rdba[rdt];
888 if(ctlr->rb[rdt] != nil){
889 iprint("82563: tx overrun\n");
893 bp = allocb(ctlr->rbsz + Rbalign);
894 bp->rp = bp->wp = (uchar*)ROUND((uintptr)bp->base, Rbalign);
896 rd->addr[0] = PCIWADDR(bp->rp);
904 csr32w(ctlr, Rdt, rdt);
909 i82563rxinit(Ctlr *ctlr)
914 if(ctlr->rbsz <= 2048)
915 csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
917 i = ctlr->rbsz / 1024;
918 if(ctlr->rbsz % 1024)
920 if(cttab[ctlr->type].flag & F75){
921 csr32w(ctlr, Rctl, Lpe|Dpf|Bsize2048|Bam|RdtmsHALF|Secrc);
922 if(ctlr->type != i82575)
923 i |= (ctlr->nrd/2>>4)<<20; /* RdmsHalf */
924 csr32w(ctlr, Srrctl, i | Dropen);
925 csr32w(ctlr, Rmpl, ctlr->rbsz);
926 // csr32w(ctlr, Drxmxod, 0x7ff);
928 csr32w(ctlr, Rctl, Lpe|Dpf|BsizeFlex*i|Bam|RdtmsHALF|Secrc);
931 if(cttab[ctlr->type].flag & Fert)
932 csr32w(ctlr, Ert, 1024/8);
934 if(ctlr->type == i82566)
935 csr32w(ctlr, Pbs, 16);
937 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
938 csr32w(ctlr, Rdbah, 0);
939 csr32w(ctlr, Rdlen, ctlr->nrd * sizeof(Rd));
941 csr32w(ctlr, Rdh, 0);
943 csr32w(ctlr, Rdt, 0);
946 csr32w(ctlr, Rdtr, ctlr->rdtr);
947 csr32w(ctlr, Radv, ctlr->radv);
949 for(i = 0; i < ctlr->nrd; i++)
950 if((bp = ctlr->rb[i]) != nil){
954 if(cttab[ctlr->type].flag & F75)
955 csr32w(ctlr, Rxdctl, 1<<WthreshSHIFT | 8<<PthreshSHIFT | 1<<HthreshSHIFT | Enable);
957 csr32w(ctlr, Rxdctl, 2<<WthreshSHIFT | 2<<PthreshSHIFT);
960 * Enable checksum offload.
962 csr32w(ctlr, Rxcsum, Tuofl | Ipofl | ETHERHDRSIZE);
968 return ((Ctlr*)v)->rim != 0;
972 i82563rproc(void *arg)
984 csr32w(ctlr, Rctl, csr32r(ctlr, Rctl) | Ren);
985 if(cttab[ctlr->type].flag & F75){
986 csr32w(ctlr, Rxdctl, csr32r(ctlr, Rxdctl) | Enable);
987 im = Rxt0|Rxo|Rxdmt0|Rxseq|Ack;
989 im = Rxt0|Rxo|Rxdmt0|Rxseq|Ack;
996 i82563replenish(ctlr);
997 sleep(&ctlr->rrendez, i82563rim, ctlr);
1003 rd = &ctlr->rdba[rdh];
1004 if(!(rd->status & Rdd))
1008 * Accept eop packets with no errors.
1009 * With no errors and the Ixsm bit set,
1010 * the descriptor status Tpcs and Ipcs bits give
1011 * an indication of whether the checksums were
1012 * calculated and valid.
1015 if((rd->status & Reop) && rd->errors == 0){
1016 bp->wp += rd->length;
1017 if(!(rd->status & Ixsm)){
1019 if(rd->status & Ipcs){
1021 * IP checksum calculated
1022 * (and valid as errors == 0).
1027 if(rd->status & Tcpcs){
1029 * TCP/UDP checksum calculated
1030 * (and valid as errors == 0).
1033 bp->flag |= Btcpck|Budpck;
1035 bp->checksum = rd->checksum;
1038 etheriq(edev, bp, 1);
1041 ctlr->rb[rdh] = nil;
1043 ctlr->rdh = rdh = NEXT(rdh, ctlr->nrd);
1044 if(ctlr->nrd-ctlr->rdfree >= 32 || (rim & Rxdmt0))
1045 i82563replenish(ctlr);
1053 return ((Ctlr*)v)->lim != 0;
1056 static int speedtab[] = {
1061 phyread(Ctlr *c, int phyno, int reg)
1065 csr32w(c, Mdic, MDIrop | phyno<<MDIpSHIFT | reg<<MDIrSHIFT);
1067 for(i = 0; i < 64; i++){
1068 phy = csr32r(c, Mdic);
1069 if(phy & (MDIe|MDIready))
1073 if((phy & (MDIe|MDIready)) != MDIready){
1074 print("%s: phy %d wedged %.8ux\n", cttab[c->type].name, phyno, phy);
1077 return phy & 0xffff;
1081 phywrite0(Ctlr *c, int phyno, int reg, ushort val)
1085 csr32w(c, Mdic, MDIwop | phyno<<MDIpSHIFT | reg<<MDIrSHIFT | val);
1087 for(i = 0; i < 64; i++){
1088 phy = csr32r(c, Mdic);
1089 if(phy & (MDIe|MDIready))
1093 if((phy & (MDIe|MDIready)) != MDIready)
1099 setpage(Ctlr *c, uint phyno, uint p, uint r)
1103 if(c->type == i82563){
1104 if(r >= 16 && r <= 28 && r != 22)
1106 else if(r == 30 || r == 31)
1110 return phywrite0(c, phyno, pr, p);
1117 phywrite(Ctlr *c, uint phyno, uint reg, ushort v)
1119 if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0)
1120 panic("%s: bad phy reg %.4ux", cname(c), reg);
1121 return phywrite0(c, phyno, reg & 0xff, v);
1125 phyerrata(Ether *e, Ctlr *c, uint phyno)
1128 if(c->phyerrata == 0){
1130 phywrite(c, phyno, Phyprst, Prst); /* try a port reset */
1131 print("%s: phy port reset\n", cname(c));
1138 phyprobe(Ctlr *c, uint mask)
1142 for(phyno=0; mask != 0; phyno++, mask>>=1){
1145 if(phyread(c, phyno, Physr) == ~0)
1147 phy = (phyread(c, phyno, Phyid1) & 0x3FFF)<<6;
1148 phy |= phyread(c, phyno, Phyid2) >> 10;
1149 if(phy == 0xFFFFF || phy == 0)
1151 print("%s: phy%d oui %#ux\n", cname(c), phyno, phy);
1154 print("%s: no phy\n", cname(c));
1161 uint a, i, r, phy, phyno;
1168 phyno = phyprobe(c, 3<<1);
1170 print("%s: no phy, exiting\n", up->text);
1177 phy = phyread(c, phyno, Phystat);
1186 r = phyread(c, phyno, Phyctl);
1187 phywrite(c, phyno, Phyctl, r | Ran | Ean);
1190 e->link = i != 3 && (phy & Link) != 0;
1194 e->mbps = speedtab[i];
1198 sleep(&c->lrendez, i82563lim, c);
1205 uint a, i, phy, phyno;
1212 phyno = phyprobe(c, 3<<1);
1214 print("%s: no phy, exiting\n", up->text);
1218 if(c->type == i82573 && (phy = phyread(c, phyno, Phyier)) != ~0)
1219 phywrite(c, phyno, Phyier, phy | Lscie | Ancie | Spdie | Panie);
1224 phy = phyread(c, phyno, Physsr);
1239 a = phyread(c, phyno, Phyisr) & Ane;
1245 a = phyread(c, phyno, Phylhr) & Anf;
1250 phywrite(c, phyno, Phyctl, phyread(c, phyno, Phyctl) | Ran | Ean);
1252 e->link = (phy & Rtlink) != 0;
1256 e->mbps = speedtab[i];
1257 if(c->type == i82563)
1258 phyerrata(e, c, phyno);
1262 sleep(&c->lrendez, i82563lim, c);
1276 if(c->type == i82575 || c->type == i82576)
1277 csr32w(c, Connsw, Enrgirq);
1281 phy = csr32r(c, Pcsstat);
1282 e->link = phy & Linkok;
1286 else if(phy & Anbad)
1287 csr32w(c, Pcsctl, csr32r(c, Pcsctl) | Pan | Prestart);
1289 e->mbps = speedtab[i];
1291 i82563im(c, Lsc | Omed);
1293 sleep(&c->lrendez, i82563lim, c);
1298 serdeslproc(void *v)
1310 rx = csr32r(c, Rxcw);
1311 tx = csr32r(c, Txcw);
1313 e->link = (rx & 1<<31) != 0;
1314 // e->link = (csr32r(c, Status) & Lu) != 0;
1319 e->mbps = speedtab[i];
1323 sleep(&c->lrendez, i82563lim, c);
1328 i82563attach(Ether *edev)
1330 char name[KNAMELEN];
1334 qlock(&ctlr->alock);
1335 if(ctlr->alloc != nil){
1336 qunlock(&ctlr->alock);
1342 ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 255);
1343 ctlr->rb = malloc(ctlr->nrd * sizeof(Block*));
1344 ctlr->tb = malloc(ctlr->ntd * sizeof(Block*));
1345 if(ctlr->alloc == nil || ctlr->rb == nil || ctlr->tb == nil){
1352 qunlock(&ctlr->alock);
1355 ctlr->rdba = (Rd*)ROUNDUP((uintptr)ctlr->alloc, 256);
1356 ctlr->tdba = (Td*)(ctlr->rdba + ctlr->nrd);
1365 qunlock(&ctlr->alock);
1369 snprint(name, sizeof name, "#l%dl", edev->ctlrno);
1370 if(csr32r(ctlr, Status) & Tbimode)
1371 kproc(name, serdeslproc, edev); /* mac based serdes */
1372 else if((csr32r(ctlr, Ctrlext) & Linkmode) == Serdes)
1373 kproc(name, pcslproc, edev); /* phy based serdes */
1374 else if(cttab[ctlr->type].flag & F79phy)
1375 kproc(name, phyl79proc, edev);
1377 kproc(name, phylproc, edev);
1379 snprint(name, sizeof name, "#l%dr", edev->ctlrno);
1380 kproc(name, i82563rproc, edev);
1382 snprint(name, sizeof name, "#l%dt", edev->ctlrno);
1383 kproc(name, i82563tproc, edev);
1385 qunlock(&ctlr->alock);
1390 i82563interrupt(Ureg*, void *arg)
1399 ilock(&ctlr->imlock);
1400 csr32w(ctlr, Imc, ~0);
1403 while(icr = csr32r(ctlr, Icr) & ctlr->im){
1404 if(icr & (Lsc | Omed)){
1405 im &= ~(Lsc | Omed);
1406 ctlr->lim = icr & (Lsc | Omed);
1407 wakeup(&ctlr->lrendez);
1410 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack)){
1411 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
1412 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
1413 wakeup(&ctlr->rrendez);
1419 wakeup(&ctlr->trendez);
1424 csr32w(ctlr, Ims, im);
1425 iunlock(&ctlr->imlock);
1429 i82563detach(Ctlr *ctlr)
1433 /* balance rx/tx packet buffer; survives reset */
1434 if(ctlr->rbsz > 8192 && cttab[ctlr->type].flag & Fpba){
1435 ctlr->pba = csr32r(ctlr, Pba);
1436 r = ctlr->pba >> 16;
1437 r += ctlr->pba & 0xffff;
1439 csr32w(ctlr, Pba, r);
1440 }else if(ctlr->type == i82573 && ctlr->rbsz > 1514)
1441 csr32w(ctlr, Pba, 14);
1442 ctlr->pba = csr32r(ctlr, Pba);
1445 * Perform a device reset to get the chip back to the
1446 * power-on state, followed by an EEPROM reset to read
1447 * the defaults for some internal registers.
1449 csr32w(ctlr, Imc, ~0);
1450 csr32w(ctlr, Rctl, 0);
1451 csr32w(ctlr, Tctl, csr32r(ctlr, Tctl) & ~Ten);
1455 r = csr32r(ctlr, Ctrl);
1456 if(ctlr->type == i82566 || ctlr->type == i82579)
1459 * hack: 82579LM on lenovo X230 is stuck at 10mbps after
1460 * reseting the phy, but works fine if we dont reset.
1462 if(ctlr->pcidev->did == 0x1502)
1464 csr32w(ctlr, Ctrl, Devrst | r);
1466 for(timeo = 0;; timeo++){
1467 if((csr32r(ctlr, Ctrl) & (Devrst|Phyrst)) == 0)
1474 r = csr32r(ctlr, Ctrl);
1475 csr32w(ctlr, Ctrl, Slu|r);
1477 r = csr32r(ctlr, Ctrlext);
1478 csr32w(ctlr, Ctrlext, r|Eerst);
1480 for(timeo = 0; timeo < 1000; timeo++){
1481 if(!(csr32r(ctlr, Ctrlext) & Eerst))
1485 if(csr32r(ctlr, Ctrlext) & Eerst)
1488 csr32w(ctlr, Imc, ~0);
1490 for(timeo = 0; timeo < 1000; timeo++){
1491 if((csr32r(ctlr, Icr) & ~Rxcfg) == 0)
1495 if(csr32r(ctlr, Icr) & ~Rxcfg)
1502 i82563shutdown(Ether *edev)
1504 i82563detach(edev->ctlr);
1508 eeread(Ctlr *ctlr, int adr)
1512 csr32w(ctlr, Eerd, EEstart | adr << 2);
1514 while ((csr32r(ctlr, Eerd) & EEdone) == 0 && timeout--)
1517 print("%s: eeread timeout\n", cname(ctlr));
1520 return (csr32r(ctlr, Eerd) >> 16) & 0xffff;
1530 for (adr = 0; adr < 0x40; adr++) {
1531 data = eeread(ctlr, adr);
1532 if(data == -1) return -1;
1533 ctlr->eeprom[adr] = data;
1540 fcycle(Ctlr *, Flash *f)
1548 f->reg[Fsts] |= Fcerr | Ael;
1549 for(i = 0; i < 10; i++){
1559 fread(Ctlr *c, Flash *f, int ladr)
1565 if(fcycle(c, f) == -1)
1567 f->reg[Fsts] |= Fdone;
1568 f->reg32[Faddr] = ladr;
1570 /* setup flash control register */
1571 s = f->reg[Fctl] & ~0x3ff;
1572 f->reg[Fctl] = s | 1<<8 | Fgo; /* 2 byte read */
1574 while((f->reg[Fsts] & Fdone) == 0 && timeout--)
1577 print("%s: fread timeout\n", cname(c));
1580 if(f->reg[Fsts] & (Fcerr|Ael))
1582 return f->reg32[Fdata] & 0xffff;
1593 va = vmap(c->pcidev->mem[1].bar & ~0x0f, c->pcidev->mem[1].size);
1598 f.base = f.reg32[Bfpr] & 0x1fff;
1599 f.lim = f.reg32[Bfpr]>>16 & 0x1fff;
1600 if(csr32r(c, Eec) & Sec1val)
1601 f.base += f.lim+1 - f.base >> 1;
1604 for(adr = 0; adr < 0x40; adr++) {
1605 data = fread(c, &f, r + adr*2);
1608 c->eeprom[adr] = data;
1611 vunmap(va, c->pcidev->mem[1].size);
1616 defaultea(Ctlr *ctlr, uchar *ra)
1620 static uchar nilea[Eaddrlen];
1622 if(memcmp(ra, nilea, Eaddrlen) != 0)
1624 if(cttab[ctlr->type].flag & Fflashea){
1626 u = (uvlong)csr32r(ctlr, Rah)<<32u | (ulong)csr32r(ctlr, Ral);
1627 for(i = 0; i < Eaddrlen; i++)
1630 if(memcmp(ra, nilea, Eaddrlen) != 0)
1632 for(i = 0; i < Eaddrlen/2; i++){
1633 ra[2*i] = ctlr->eeprom[Ea+i];
1634 ra[2*i+1] = ctlr->eeprom[Ea+i] >> 8;
1636 r = (csr32r(ctlr, Status) & Lanid) >> 2;
1637 ra[5] += r; /* ea ctlr[n] = ea ctlr[0]+n */
1641 i82563reset(Ctlr *ctlr)
1646 if(i82563detach(ctlr))
1648 if(cttab[ctlr->type].flag & Fload)
1652 if(r != 0 && r != 0xbaba){
1653 print("%s: bad eeprom checksum - %#.4ux\n",
1659 defaultea(ctlr, ra);
1660 csr32w(ctlr, Ral, ra[3]<<24 | ra[2]<<16 | ra[1]<<8 | ra[0]);
1661 csr32w(ctlr, Rah, 1<<31 | ra[5]<<8 | ra[4]);
1662 for(i = 1; i < 16; i++){
1663 csr32w(ctlr, Ral+i*8, 0);
1664 csr32w(ctlr, Rah+i*8, 0);
1666 memset(ctlr->mta, 0, sizeof(ctlr->mta));
1667 for(i = 0; i < 128; i++)
1668 csr32w(ctlr, Mta + i*4, 0);
1669 csr32w(ctlr, Fcal, 0x00C28001);
1670 csr32w(ctlr, Fcah, 0x0100);
1671 if(ctlr->type != i82579)
1672 csr32w(ctlr, Fct, 0x8808);
1673 csr32w(ctlr, Fcttv, 0x0100);
1674 csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1675 csr32w(ctlr, Fcrth, ctlr->fcrth);
1676 if(cttab[ctlr->type].flag & F75)
1677 csr32w(ctlr, Eitr, 128<<2); /* 128 ¼ microsecond intervals */
1688 static Cmdtab i82563ctlmsg[] = {
1691 CMpause, "pause", 1,
1696 i82563ctl(Ether *edev, void *buf, long n)
1704 if((ctlr = edev->ctlr) == nil)
1707 cb = parsecmd(buf, n);
1713 ct = lookupcmd(cb, i82563ctlmsg, nelem(i82563ctlmsg));
1716 v = strtoul(cb->f[1], &p, 0);
1717 if(*p || v > 0xffff)
1720 csr32w(ctlr, Rdtr, v);
1723 v = strtoul(cb->f[1], &p, 0);
1724 if(*p || v > 0xffff)
1727 csr32w(ctlr, Radv, v);
1730 csr32w(ctlr, Ctrl, csr32r(ctlr, Ctrl) ^ (Rfce | Tfce));
1733 csr32w(ctlr, Ctrl, csr32r(ctlr, Ctrl) | Lrst | Phyrst);
1746 * Some names and did values are from
1747 * OpenBSD's em(4) Intel driver.
1750 case 0x1096: /* copper */
1751 case 0x10ba: /* copper “gilgal” */
1752 case 0x1098: /* serdes; not seen */
1753 case 0x10bb: /* serdes */
1755 case 0x1049: /* ich8; mm */
1756 case 0x104a: /* ich8; dm */
1757 case 0x104b: /* ich8; dc */
1758 case 0x104d: /* ich8; v “ninevah” */
1759 case 0x10bd: /* ich9; dm-2 */
1760 case 0x294c: /* ich9 */
1761 case 0x104c: /* ich8; untested */
1762 case 0x10c4: /* ich8; untested */
1763 case 0x10c5: /* ich8; untested */
1765 case 0x10de: /* lm ich10d */
1766 case 0x10df: /* lf ich10 */
1767 case 0x10e5: /* lm ich9 */
1768 case 0x10f5: /* lm ich9m; “boazman” */
1769 case 0x10ce: /* v ich10 */
1770 case 0x10c0: /* ich9 */
1771 case 0x10c2: /* ich9; untested */
1772 case 0x10c3: /* ich9; untested */
1773 case 0x1501: /* ich8; untested */
1775 case 0x10bf: /* lf ich9m */
1776 case 0x10cb: /* v ich9m */
1777 case 0x10cd: /* lf ich10 */
1778 case 0x10cc: /* lm ich10 */
1780 case 0x105e: /* eb copper */
1781 case 0x105f: /* eb fiber */
1782 case 0x1060: /* eb serdes */
1783 case 0x10a4: /* eb copper */
1784 case 0x10a5: /* eb fiber */
1785 case 0x10bc: /* eb copper */
1786 case 0x10d9: /* eb serdes */
1787 case 0x10da: /* eb serdes “ophir” */
1788 case 0x10a0: /* eb; untested */
1789 case 0x10a1: /* eb; untested */
1790 case 0x10d5: /* copper; untested */
1792 case 0x107d: /* ei copper */
1793 case 0x107e: /* ei fiber */
1794 case 0x107f: /* ei serdes */
1795 case 0x10b9: /* ei “rimon” */
1797 case 0x108b: /* e “vidalia” */
1798 case 0x108c: /* e (iamt) */
1799 case 0x109a: /* l “tekoa” */
1800 case 0x10b0: /* l; untested */
1801 case 0x10b2: /* v; untested */
1802 case 0x10b3: /* e; untested */
1803 case 0x10b4: /* l; untested */
1805 case 0x10d3: /* l or it; “hartwell” */
1806 case 0x10f6: /* la; untested */
1808 case 0x10a7: /* eb */
1809 case 0x10a9: /* eb fiber/serdes */
1810 case 0x10d6: /* untested */
1811 case 0x10e2: /* untested */
1813 case 0x10c9: /* copper */
1814 case 0x10e6: /* fiber */
1815 case 0x10e7: /* serdes; “kawela” */
1816 case 0x10e8: /* copper; untested */
1817 case 0x150a: /* untested */
1818 case 0x150d: /* serdes backplane */
1819 case 0x1518: /* serdes; untested */
1820 case 0x1526: /* untested */
1822 case 0x10ea: /* lc “calpella”; aka pch lan */
1824 case 0x10eb: /* lm “calpella” */
1826 case 0x10ef: /* dc “piketon” */
1828 case 0x1502: /* lm */
1829 case 0x1503: /* v “lewisville” */
1831 case 0x10f0: /* dm “king's creek” */
1833 case 0x150e: /* copper “barton hills” */
1834 case 0x150f: /* fiber */
1835 case 0x1510: /* serdes backplane */
1836 case 0x1511: /* sgmii sfp */
1837 case 0x1516: /* copper */
1839 case 0x1506: /* v */
1840 case 0x150c: /* untested */
1842 case 0x151f: /* “powerville” eeprom-less */
1843 case 0x1521: /* copper */
1844 case 0x1522: /* fiber */
1845 case 0x1523: /* serdes */
1846 case 0x1524: /* sgmii */
1847 case 0x1546: /* untested */
1858 i = pcicfgr32(p, PciSVID);
1859 if((i & 0xffff) == 0x1b52 && p->did == 1)
1870 for(p = nil; p = pcimatch(p, 0x8086, 0);){
1872 if((type = didtype(p->did)) == -1)
1874 ctlr = malloc(sizeof(Ctlr));
1876 print("%s: can't allocate memory\n", cttab[type].name);
1881 ctlr->rbsz = cttab[type].mtu;
1882 ctlr->port = p->mem[0].bar & ~0x0F;
1883 if(i82563ctlrhead != nil)
1884 i82563ctlrtail->next = ctlr;
1886 i82563ctlrhead = ctlr;
1887 i82563ctlrtail = ctlr;
1897 ctlr->nic = vmap(ctlr->port, p->mem[0].size);
1898 if(ctlr->nic == nil){
1899 print("%s: can't map 0x%lux\n", cname(ctlr), ctlr->port);
1902 if(i82563reset(ctlr)){
1903 vunmap(ctlr->nic, p->mem[0].size);
1906 pcisetbme(ctlr->pcidev);
1911 pnp(Ether *edev, int type)
1922 * Any adapter matches if no edev->port is supplied,
1923 * otherwise the ports must match.
1925 for(ctlr = i82563ctlrhead; ; ctlr = ctlr->next){
1930 if(type != -1 && ctlr->type != type)
1932 if(edev->port == 0 || edev->port == ctlr->port){
1934 memmove(ctlr->ra, edev->ea, Eaddrlen);
1935 if(setup(ctlr) == 0)
1941 edev->port = ctlr->port;
1942 edev->irq = ctlr->pcidev->intl;
1943 edev->tbdf = ctlr->pcidev->tbdf;
1945 edev->maxmtu = ctlr->rbsz;
1946 memmove(edev->ea, ctlr->ra, Eaddrlen);
1949 * Linkage to the generic ethernet driver.
1951 edev->attach = i82563attach;
1952 // edev->transmit = i82563transmit;
1953 edev->interrupt = i82563interrupt;
1954 edev->ifstat = i82563ifstat;
1955 edev->ctl = i82563ctl;
1958 edev->promiscuous = i82563promiscuous;
1959 edev->shutdown = i82563shutdown;
1960 edev->multicast = i82563multicast;
1974 return pnp(e, i82563);
1980 return pnp(e, i82566);
1986 return pnp(e, i82567m) & pnp(e, i82567);
1992 return pnp(e, i82571);
1998 return pnp(e, i82572);
2004 return pnp(e, i82573);
2010 return pnp(e, i82574);
2016 return pnp(e, i82575);
2022 return pnp(e, i82576);
2028 return pnp(e, i82577m) & pnp(e, i82577);
2034 return pnp(e, i82578m) & pnp(e, i82578);
2040 return pnp(e, i82579);
2046 return pnp(e, i82580);
2052 return pnp(e, i82583);
2058 return pnp(e, i350);
2062 ether82563link(void)
2065 * recognise lots of model numbers for debugging
2066 * also good for forcing onboard nic(s) as ether0
2067 * try to make that unnecessary by listing lom first.
2069 addethercard("i82563", i82563pnp);
2070 addethercard("i82566", i82566pnp);
2071 addethercard("i82574", i82574pnp);
2072 addethercard("i82576", i82576pnp);
2073 addethercard("i82567", i82567pnp);
2074 addethercard("i82573", i82573pnp);
2076 addethercard("i82571", i82571pnp);
2077 addethercard("i82572", i82572pnp);
2078 addethercard("i82575", i82575pnp);
2079 addethercard("i82577", i82577pnp);
2080 addethercard("i82578", i82578pnp);
2081 addethercard("i82579", i82579pnp);
2082 addethercard("i82580", i82580pnp);
2083 addethercard("i82583", i82583pnp);
2084 addethercard("i350", i350pnp);
2085 addethercard("igbepcie", anypnp);