2 * Intel 8256[367], 8257[1-9], 8258[03], i350
3 * Gigabit Ethernet PCI-Express Controllers
4 * Coraid EtherDrive® hba
7 #include "../port/lib.h"
12 #include "../port/error.h"
13 #include "../port/netif.h"
14 #include "../port/etherif.h"
17 * note: the 82575, 82576 and 82580 are operated using registers aliased
18 * to the 82563-style architecture. many features seen in the 82598
19 * are also seen in the 82575 part.
25 Ctrl = 0x0000, /* Device Control */
26 Status = 0x0008, /* Device Status */
27 Eec = 0x0010, /* EEPROM/Flash Control/Data */
28 Eerd = 0x0014, /* EEPROM Read */
29 Ctrlext = 0x0018, /* Extended Device Control */
30 Fla = 0x001c, /* Flash Access */
31 Mdic = 0x0020, /* MDI Control */
32 Fcal = 0x0028, /* Flow Control Address Low */
33 Fcah = 0x002C, /* Flow Control Address High */
34 Fct = 0x0030, /* Flow Control Type */
35 Kumctrlsta = 0x0034, /* Kumeran Control and Status Register */
36 Connsw = 0x0034, /* copper / fiber switch control; 82575/82576 */
37 Vet = 0x0038, /* VLAN EtherType */
38 Fcttv = 0x0170, /* Flow Control Transmit Timer Value */
39 Txcw = 0x0178, /* Transmit Configuration Word */
40 Rxcw = 0x0180, /* Receive Configuration Word */
41 Ledctl = 0x0E00, /* LED control */
42 Pba = 0x1000, /* Packet Buffer Allocation */
43 Pbs = 0x1008, /* Packet Buffer Size */
47 Icr = 0x00C0, /* Interrupt Cause Read */
48 Itr = 0x00c4, /* Interrupt Throttling Rate */
49 Ics = 0x00C8, /* Interrupt Cause Set */
50 Ims = 0x00D0, /* Interrupt Mask Set/Read */
51 Imc = 0x00D8, /* Interrupt mask Clear */
52 Iam = 0x00E0, /* Interrupt acknowledge Auto Mask */
53 Eitr = 0x1680, /* Extended itr; 82575/6 80 only */
57 Rctl = 0x0100, /* Control */
58 Ert = 0x2008, /* Early Receive Threshold (573[EVL], 82578 only) */
59 Fcrtl = 0x2160, /* Flow Control RX Threshold Low */
60 Fcrth = 0x2168, /* Flow Control Rx Threshold High */
61 Psrctl = 0x2170, /* Packet Split Receive Control */
62 Drxmxod = 0x2540, /* dma max outstanding bytes (82575) */
63 Rdbal = 0x2800, /* Rdesc Base Address Low Queue 0 */
64 Rdbah = 0x2804, /* Rdesc Base Address High Queue 0 */
65 Rdlen = 0x2808, /* Descriptor Length Queue 0 */
66 Srrctl = 0x280c, /* split and replication rx control (82575) */
67 Rdh = 0x2810, /* Descriptor Head Queue 0 */
68 Rdt = 0x2818, /* Descriptor Tail Queue 0 */
69 Rdtr = 0x2820, /* Descriptor Timer Ring */
70 Rxdctl = 0x2828, /* Descriptor Control */
71 Radv = 0x282C, /* Interrupt Absolute Delay Timer */
72 Rsrpd = 0x2c00, /* Small Packet Detect */
73 Raid = 0x2c08, /* ACK interrupt delay */
74 Cpuvec = 0x2c10, /* CPU Vector */
75 Rxcsum = 0x5000, /* Checksum Control */
76 Rmpl = 0x5004, /* rx maximum packet length (82575) */
77 Rfctl = 0x5008, /* Filter Control */
78 Mta = 0x5200, /* Multicast Table Array */
79 Ral = 0x5400, /* Receive Address Low */
80 Rah = 0x5404, /* Receive Address High */
81 Vfta = 0x5600, /* VLAN Filter Table Array */
82 Mrqc = 0x5818, /* Multiple Receive Queues Command */
86 Tctl = 0x0400, /* Transmit Control */
87 Tipg = 0x0410, /* Transmit IPG */
88 Tkabgtxd = 0x3004, /* glci afe band gap transmit ref data, or something */
89 Tdbal = 0x3800, /* Tdesc Base Address Low */
90 Tdbah = 0x3804, /* Tdesc Base Address High */
91 Tdlen = 0x3808, /* Descriptor Length */
92 Tdh = 0x3810, /* Descriptor Head */
93 Tdt = 0x3818, /* Descriptor Tail */
94 Tidv = 0x3820, /* Interrupt Delay Value */
95 Txdctl = 0x3828, /* Descriptor Control */
96 Tadv = 0x382C, /* Interrupt Absolute Delay Timer */
97 Tarc0 = 0x3840, /* Arbitration Counter Queue 0 */
101 Statistics = 0x4000, /* Start of Statistics Area */
102 Gorcl = 0x88/4, /* Good Octets Received Count */
103 Gotcl = 0x90/4, /* Good Octets Transmitted Count */
104 Torl = 0xC0/4, /* Total Octets Received */
105 Totl = 0xC8/4, /* Total Octets Transmitted */
106 Nstatistics = 0x124/4,
113 Lrst = 1<<3, /* link reset */
114 Slu = 1<<6, /* Set Link Up */
115 Devrst = 1<<26, /* Device Reset */
116 Rfce = 1<<27, /* Receive Flow Control Enable */
117 Tfce = 1<<28, /* Transmit Flow Control Enable */
118 Phyrst = 1<<31, /* Phy Reset */
122 Lu = 1<<1, /* Link Up */
123 Lanid = 3<<2, /* mask for Lan ID. */
124 Txoff = 1<<4, /* Transmission Paused */
125 Tbimode = 1<<5, /* TBI Mode Indication */
126 Phyra = 1<<10, /* PHY Reset Asserted */
127 GIOme = 1<<19, /* GIO Master Enable Status */
138 EEstart = 1<<0, /* Start Read */
139 EEdone = 1<<1, /* Read done */
143 Eerst = 1<<13, /* EEPROM Reset */
144 Linkmode = 3<<22, /* linkmode */
145 Internalphy = 0<<22, /* " internal phy (copper) */
146 Sgmii = 2<<22, /* " sgmii */
147 Serdes = 3<<22, /* " serdes */
152 Enrgirq = 1<<2, /* interrupt on power detect (enrgsrc) */
155 enum { /* EEPROM content offsets */
156 Ea = 0x00, /* Ethernet Address */
160 MDIdMASK = 0x0000FFFF, /* Data */
162 MDIrMASK = 0x001F0000, /* PHY Register Address */
164 MDIpMASK = 0x03E00000, /* PHY Address */
166 MDIwop = 0x04000000, /* Write Operation */
167 MDIrop = 0x08000000, /* Read Operation */
168 MDIready = 0x10000000, /* End of Transaction */
169 MDIie = 0x20000000, /* Interrupt Enable */
170 MDIe = 0x40000000, /* Error */
173 enum { /* phy interface */
174 Phyctl = 0, /* phy ctl register */
175 Physr = 1, /* phy status register */
176 Phyid1 = 2, /* phy id1 */
177 Phyid2 = 3, /* phy id2 */
178 Phyisr = 19, /* 82563 phy interrupt status register */
179 Phylhr = 19, /* 8257[12] link health register */
180 Physsr = 17, /* phy secondary status register */
181 Phyprst = 193<<8 | 17, /* 8256[34] phy port reset */
182 Phyier = 18, /* 82573 phy interrupt enable register */
183 Phypage = 22, /* 8256[34] page register */
184 Phystat = 26, /* 82580 phy status */
186 Rtlink = 1<<10, /* realtime link status */
187 Phyan = 1<<11, /* phy has autonegotiated */
190 Ran = 1<<9, /* restart auto negotiation */
191 Ean = 1<<12, /* enable auto negotiation */
194 Prst = 1<<0, /* reset the port */
196 /* 82573 Phyier bits */
197 Lscie = 1<<10, /* link status changed ie */
198 Ancie = 1<<11, /* auto negotiation complete ie */
199 Spdie = 1<<14, /* speed changed ie */
200 Panie = 1<<15, /* phy auto negotiation error ie */
202 /* Phylhr/Phyisr bits */
203 Anf = 1<<6, /* lhr: auto negotiation fault */
204 Ane = 1<<15, /* isr: auto negotiation error */
206 /* 82580 Phystat bits */
207 Ans = 1<<14 | 1<<15, /* 82580 autoneg. status */
208 Link = 1<<6, /* 82580 Link */
210 /* Rxcw builtin serdes */
223 enum { /* fiber (pcs) interface */
224 Pcsctl = 0x4208, /* pcs control */
225 Pcsstat = 0x420c, /* pcs status */
228 Pan = 1<<16, /* autoegotiate */
229 Prestart = 1<<17, /* restart an (self clearing) */
232 Linkok = 1<<0, /* link is okay */
233 Andone = 1<<16, /* an phase is done see below for success */
234 Anbad = 1<<19 | 1<<20, /* Anerror | Anremfault */
237 enum { /* Icr, Ics, Ims, Imc */
238 Txdw = 0x00000001, /* Transmit Descriptor Written Back */
239 Txqe = 0x00000002, /* Transmit Queue Empty */
240 Lsc = 0x00000004, /* Link Status Change */
241 Rxseq = 0x00000008, /* Receive Sequence Error */
242 Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */
243 Rxo = 0x00000040, /* Receiver Overrun */
244 Rxt0 = 0x00000080, /* Receiver Timer Interrupt; !82575/6/80 only */
245 Rxdw = 0x00000080, /* Rdesc write back; 82575/6/80 only */
246 Mdac = 0x00000200, /* MDIO Access Completed */
247 Rxcfgset = 0x00000400, /* Receiving /C/ ordered sets */
248 Ack = 0x00020000, /* Receive ACK frame */
249 Omed = 1<<20, /* media change; pcs interface */
253 TxcwFd = 0x00000020, /* Full Duplex */
254 TxcwHd = 0x00000040, /* Half Duplex */
255 TxcwPauseMASK = 0x00000180, /* Pause */
257 TxcwPs = 1<<TxcwPauseSHIFT, /* Pause Supported */
258 TxcwAs = 2<<TxcwPauseSHIFT, /* Asymmetric FC desired */
259 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
261 TxcwNpr = 0x00008000, /* Next Page Request */
262 TxcwConfig = 0x40000000, /* Transmit COnfig Control */
263 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
267 Rrst = 0x00000001, /* Receiver Software Reset */
268 Ren = 0x00000002, /* Receiver Enable */
269 Sbp = 0x00000004, /* Store Bad Packets */
270 Upe = 0x00000008, /* Unicast Promiscuous Enable */
271 Mpe = 0x00000010, /* Multicast Promiscuous Enable */
272 Lpe = 0x00000020, /* Long Packet Reception Enable */
273 RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */
274 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
275 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
276 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
277 MoMASK = 0x00003000, /* Multicast Offset */
278 Bam = 0x00008000, /* Broadcast Accept Mode */
279 BsizeMASK = 0x00030000, /* Receive Buffer Size */
280 Bsize16384 = 0x00010000, /* Bsex = 1 */
281 Bsize8192 = 0x00020000, /* Bsex = 1 */
282 Bsize2048 = 0x00000000,
283 Bsize1024 = 0x00010000,
284 Bsize512 = 0x00020000,
285 Bsize256 = 0x00030000,
286 BsizeFlex = 0x08000000, /* Flexable Bsize in 1kb increments */
287 Vfe = 0x00040000, /* VLAN Filter Enable */
288 Cfien = 0x00080000, /* Canonical Form Indicator Enable */
289 Cfi = 0x00100000, /* Canonical Form Indicator value */
290 Dpf = 0x00400000, /* Discard Pause Frames */
291 Pmcf = 0x00800000, /* Pass MAC Control Frames */
292 Bsex = 0x02000000, /* Buffer Size Extension */
293 Secrc = 0x04000000, /* Strip CRC from incoming packet */
301 Trst = 0x00000001, /* Transmitter Software Reset */
302 Ten = 0x00000002, /* Transmit Enable */
303 Psp = 0x00000008, /* Pad Short Packets */
304 Mulr = 0x10000000, /* Allow multiple concurrent requests */
305 CtMASK = 0x00000FF0, /* Collision Threshold */
307 ColdMASK = 0x003FF000, /* Collision Distance */
309 Swxoff = 0x00400000, /* Sofware XOFF Transmission */
310 Pbe = 0x00800000, /* Packet Burst Enable */
311 Rtlc = 0x01000000, /* Re-transmit on Late Collision */
312 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
315 enum { /* [RT]xdctl */
316 PthreshMASK = 0x0000003F, /* Prefetch Threshold */
318 HthreshMASK = 0x00003F00, /* Host Threshold */
320 WthreshMASK = 0x003F0000, /* Writeback Threshold */
322 Gran = 0x01000000, /* Granularity; not 82575 */
327 Ipofl = 0x0100, /* IP Checksum Off-load Enable */
328 Tuofl = 0x0200, /* TCP/UDP Checksum Off-load Enable */
331 typedef struct Rd { /* Receive Descriptor */
340 enum { /* Rd status */
341 Rdd = 0x01, /* Descriptor Done */
342 Reop = 0x02, /* End of Packet */
343 Ixsm = 0x04, /* Ignore Checksum Indication */
344 Vp = 0x08, /* Packet is 802.1Q (matched VET) */
345 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
346 Ipcs = 0x40, /* IP Checksum Calculated on Packet */
347 Pif = 0x80, /* Passed in-exact filter */
350 enum { /* Rd errors */
351 Ce = 0x01, /* CRC Error or Alignment Error */
352 Se = 0x02, /* Symbol Error */
353 Seq = 0x04, /* Sequence Error */
354 Cxe = 0x10, /* Carrier Extension Error */
355 Tcpe = 0x20, /* TCP/UDP Checksum Error */
356 Ipe = 0x40, /* IP Checksum Error */
357 Rxe = 0x80, /* RX Data Error */
360 typedef struct { /* Transmit Descriptor */
361 u32int addr[2]; /* Data */
366 enum { /* Tdesc control */
367 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
369 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
370 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
371 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
372 Teop = 0x01000000, /* End of Packet (DD) */
373 PtypeIP = 0x02000000, /* IP Packet Type (CD) */
374 Ifcs = 0x02000000, /* Insert FCS (DD) */
375 Tse = 0x04000000, /* TCP Segmentation Enable */
376 Rs = 0x08000000, /* Report Status */
377 Rps = 0x10000000, /* Report Status Sent */
378 Dext = 0x20000000, /* Descriptor Extension */
379 Vle = 0x40000000, /* VLAN Packet Enable */
380 Ide = 0x80000000, /* Interrupt Delay Enable */
383 enum { /* Tdesc status */
384 Tdd = 0x0001, /* Descriptor Done */
385 Ec = 0x0002, /* Excess Collisions */
386 Lc = 0x0004, /* Late Collision */
387 Tu = 0x0008, /* Transmit Underrun */
388 CssMASK = 0xFF00, /* Checksum Start Field */
400 /* 16 and 32-bit flash registers for ich flash parts */
401 Bfpr = 0x00/4, /* flash base 0:12; lim 16:28 */
402 Fsts = 0x04/2, /* flash status; Hsfsts */
403 Fctl = 0x06/2, /* flash control; Hsfctl */
404 Faddr = 0x08/4, /* flash address to r/w */
405 Fdata = 0x10/4, /* data @ address */
407 /* status register */
408 Fdone = 1<<0, /* flash cycle done */
409 Fcerr = 1<<1, /* cycle error; write 1 to clear */
410 Ael = 1<<2, /* direct access error log; 1 to clear */
411 Scip = 1<<5, /* spi cycle in progress */
412 Fvalid = 1<<14, /* flash descriptor valid */
414 /* control register */
415 Fgo = 1<<0, /* start cycle */
416 Flcycle = 1<<1, /* two bits: r=0; w=2 */
417 Fdbc = 1<<8, /* bytes to read; 5 bits */
421 Nrd = 256, /* power of two */
422 Ntd = 128, /* power of two */
423 Nrb = 512+512, /* private receive buffers per Ctlr */
424 Rbalign = BY2PG, /* rx buffer alignment */
428 * cavet emptor: 82577/78 have been entered speculatitively.
429 * awating datasheet from intel.
469 typedef struct Ctlrtype Ctlrtype;
476 static Ctlrtype cttab[Nctlrtype] = {
477 [i82563] "i82563", 9014, Fpba,
478 [i82566] "i82566", 1514, Fload,
479 [i82567] "i82567", 9234, Fload,
480 [i82567m] "i82567m", 1514, Fload,
481 [i82571] "i82571", 9234, Fpba,
482 [i82572] "i82572", 9234, Fpba,
483 [i82573] "i82573", 8192, Fert|Fbadcsum, /* terrible perf above 8k */
484 [i82574] "i82574", 9018, 0,
485 [i82575] "i82575", 9728, F75|Fflashea,
486 [i82576] "i82576", 9728, F75,
487 [i82577] "i82577", 4096, Fload|Fert,
488 [i82577m] "i82577", 1514, Fload|Fert,
489 [i82578] "i82578", 4096, Fload|Fert,
490 [i82578m] "i82578", 1514, Fload|Fert,
491 [i82579] "i82579", 9018, Fload|Fert|F79phy|Fnofct,
492 [i82580] "i82580", 9728, F75|F79phy,
493 [i82583] "i82583", 1514, 0,
494 [i210] "i210", 9728, F75|Fnofct|Fert,
495 [i217] "i217", 2048, Fload|Fert|F79phy|Fnofct|Fnofca|Fbadcsum,/* 9018, but unstable above 2k */
496 [i218] "i218", 9018, Fload|Fert|F79phy|Fnofct|Fnofca|Fbadcsum,
497 [i219] "i219", 9018, Fload|Fert|F79phy|Fnofct|Fnofca|Fbadcsum,
498 [i350] "i350", 9728, F75|F79phy|Fnofct,
501 typedef void (*Freefn)(Block*);
503 typedef struct Ctlr Ctlr;
512 QLock alock; /* attach */
513 void *alloc; /* receive/transmit descriptors */
520 int im; /* interrupt mask */
526 u32int statistics[Nstatistics];
539 uchar ra[Eaddrlen]; /* receive address */
540 u32int mta[128]; /* multicast table array */
545 Rd *rdba; /* receive descriptor base address */
546 Block **rb; /* receive buffers */
547 uint rdh; /* receive descriptor head */
548 uint rdt; /* receive descriptor tail */
549 int rdtr; /* receive delay timer ring value */
550 int radv; /* receive interrupt absolute delay timer */
555 Td *tdba; /* transmit descriptor base address */
556 Block **tb; /* transmit buffers */
557 int tdh; /* transmit descriptor head */
558 int tdt; /* transmit descriptor tail */
563 u32int pba; /* packet buffer allocation */
566 #define csr32r(c, r) (*((c)->nic+((r)/4)))
567 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
569 static Ctlr *i82563ctlrhead;
570 static Ctlr *i82563ctlrtail;
572 static char *statistics[Nstatistics] = {
579 "Excessive Collisions",
580 "Multiple Collision",
588 "Carrier Extension Error",
589 "Receive Error Length",
595 "FC Received Unsupported",
596 "Packets Received (64 Bytes)",
597 "Packets Received (65-127 Bytes)",
598 "Packets Received (128-255 Bytes)",
599 "Packets Received (256-511 Bytes)",
600 "Packets Received (512-1023 Bytes)",
601 "Packets Received (1024-mtu Bytes)",
602 "Good Packets Received",
603 "Broadcast Packets Received",
604 "Multicast Packets Received",
605 "Good Packets Transmitted",
607 "Good Octets Received",
609 "Good Octets Transmitted",
613 "Receive No Buffers",
618 "Management Packets Rx",
619 "Management Packets Drop",
620 "Management Packets Tx",
621 "Total Octets Received",
623 "Total Octets Transmitted",
625 "Total Packets Received",
626 "Total Packets Transmitted",
627 "Packets Transmitted (64 Bytes)",
628 "Packets Transmitted (65-127 Bytes)",
629 "Packets Transmitted (128-255 Bytes)",
630 "Packets Transmitted (256-511 Bytes)",
631 "Packets Transmitted (512-1023 Bytes)",
632 "Packets Transmitted (1024-mtu Bytes)",
633 "Multicast Packets Transmitted",
634 "Broadcast Packets Transmitted",
635 "TCP Segmentation Context Transmitted",
636 "TCP Segmentation Context Fail",
637 "Interrupt Assertion",
638 "Interrupt Rx Pkt Timer",
639 "Interrupt Rx Abs Timer",
640 "Interrupt Tx Pkt Timer",
641 "Interrupt Tx Abs Timer",
642 "Interrupt Tx Queue Empty",
643 "Interrupt Tx Desc Low",
645 "Interrupt Rx Overrun",
651 return cttab[c->type].name;
655 i82563ifstat(Ether *edev, void *a, long n, ulong offset)
657 char *s, *p, *e, *stat;
662 p = s = smalloc(READSTR);
668 for(i = 0; i < Nstatistics; i++){
669 r = csr32r(ctlr, Statistics + i*4);
670 if((stat = statistics[i]) == nil)
678 ruvl += (uvlong)csr32r(ctlr, Statistics+(i+1)*4) << 32;
680 tuvl += ctlr->statistics[i];
681 tuvl += (uvlong)ctlr->statistics[i+1] << 32;
684 ctlr->statistics[i] = tuvl;
685 ctlr->statistics[i+1] = tuvl >> 32;
686 p = seprint(p, e, "%s: %llud %llud\n", stat, tuvl, ruvl);
691 ctlr->statistics[i] += r;
692 if(ctlr->statistics[i] == 0)
694 p = seprint(p, e, "%s: %ud %ud\n", stat,
695 ctlr->statistics[i], r);
700 p = seprint(p, e, "lintr: %ud %ud\n", ctlr->lintr, ctlr->lsleep);
701 p = seprint(p, e, "rintr: %ud %ud\n", ctlr->rintr, ctlr->rsleep);
702 p = seprint(p, e, "tintr: %ud %ud\n", ctlr->tintr, ctlr->txdw);
703 p = seprint(p, e, "ixcs: %ud %ud %ud\n", ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
704 p = seprint(p, e, "rdtr: %ud\n", ctlr->rdtr);
705 p = seprint(p, e, "radv: %ud\n", ctlr->radv);
706 p = seprint(p, e, "ctrl: %.8ux\n", csr32r(ctlr, Ctrl));
707 p = seprint(p, e, "ctrlext: %.8ux\n", csr32r(ctlr, Ctrlext));
708 p = seprint(p, e, "status: %.8ux\n", csr32r(ctlr, Status));
709 p = seprint(p, e, "txcw: %.8ux\n", csr32r(ctlr, Txcw));
710 p = seprint(p, e, "txdctl: %.8ux\n", csr32r(ctlr, Txdctl));
711 p = seprint(p, e, "pba: %.8ux\n", ctlr->pba);
713 p = seprint(p, e, "speeds: 10:%ud 100:%ud 1000:%ud ?:%ud\n",
714 ctlr->speeds[0], ctlr->speeds[1], ctlr->speeds[2], ctlr->speeds[3]);
715 p = seprint(p, e, "type: %s\n", cname(ctlr));
717 p = seprint(p, e, "eeprom:");
718 for(i = 0; i < 0x40; i++){
719 if(i && ((i & 7) == 0))
720 p = seprint(p, e, "\n ");
721 p = seprint(p, e, " %4.4ux", ctlr->eeprom[i]);
723 p = seprint(p, e, "\n");
726 n = readstr(offset, a, n, s);
728 qunlock(&ctlr->slock);
734 i82563promiscuous(void *arg, int on)
743 rctl = csr32r(ctlr, Rctl);
749 csr32w(ctlr, Rctl, rctl);
753 i82563multicast(void *arg, uchar *addr, int on)
772 bit = (addr[5]<<2)|(addr[4]>>6);
776 bit = (addr[5]<<4)|(addr[4]>>4);
783 * multiple ether addresses can hash to the same filter bit,
784 * so it's never safe to clear a filter bit.
785 * if we want to clear filter bits, we need to keep track of
786 * all the multicast addresses in use, clear all the filter bits,
787 * then set the ones corresponding to in-use addresses.
790 ctlr->mta[x] |= 1<<bit;
792 csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
796 i82563im(Ctlr *ctlr, int im)
798 ilock(&ctlr->imlock);
800 csr32w(ctlr, Ims, ctlr->im);
801 iunlock(&ctlr->imlock);
805 i82563txinit(Ctlr *ctlr)
811 if(cttab[ctlr->type].flag & F75)
812 csr32w(ctlr, Tctl, 0x0F<<CtSHIFT | Psp);
814 csr32w(ctlr, Tctl, 0x0F<<CtSHIFT | Psp | 66<<ColdSHIFT | Mulr);
815 csr32w(ctlr, Tipg, 6<<20 | 8<<10 | 8); /* yb sez: 0x702008 */
816 for(i = 0; i < ctlr->ntd; i++){
817 if((b = ctlr->tb[i]) != nil){
821 memset(&ctlr->tdba[i], 0, sizeof(Td));
823 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
824 csr32w(ctlr, Tdbah, 0);
825 csr32w(ctlr, Tdlen, ctlr->ntd * sizeof(Td));
826 ctlr->tdh = PREV(0, ctlr->ntd);
827 csr32w(ctlr, Tdh, 0);
829 csr32w(ctlr, Tdt, 0);
830 csr32w(ctlr, Tidv, 128);
831 csr32w(ctlr, Tadv, 64);
832 csr32w(ctlr, Tctl, csr32r(ctlr, Tctl) | Ten);
833 r = csr32r(ctlr, Txdctl) & ~WthreshMASK;
834 r |= 4<<WthreshSHIFT | 4<<PthreshSHIFT;
835 if(cttab[ctlr->type].flag & F75)
837 csr32w(ctlr, Txdctl, r);
841 i82563cleanup(Ctlr *c)
847 while(c->tdba[n = NEXT(tdh, c->ntd)].status & Tdd){
849 if((b = c->tb[tdh]) != nil){
853 iprint("82563 tx underrun!\n");
854 c->tdba[tdh].status = 0;
866 return (c->im & Txdw) == 0;
886 n = NEXT(tdt, ctlr->ntd);
887 if(n == i82563cleanup(ctlr)){
889 i82563im(ctlr, Txdw);
890 sleep(&ctlr->trendez, notrim, ctlr);
893 bp = qbread(edev->oq, 100000);
894 td = &ctlr->tdba[tdt];
895 td->addr[0] = PCIWADDR(bp->rp);
897 td->control = Ide|Rs|Ifcs|Teop|BLEN(bp);
901 csr32w(ctlr, Tdt, tdt);
906 i82563replenish(Ctlr *ctlr)
913 for(rdt = ctlr->rdt; NEXT(rdt, ctlr->nrd) != ctlr->rdh; rdt = NEXT(rdt, ctlr->nrd)){
914 rd = &ctlr->rdba[rdt];
915 if(ctlr->rb[rdt] != nil){
916 iprint("82563: tx overrun\n");
920 bp = allocb(ctlr->rbsz + Rbalign);
921 bp->rp = bp->wp = (uchar*)ROUND((uintptr)bp->base, Rbalign);
923 rd->addr[0] = PCIWADDR(bp->rp);
931 csr32w(ctlr, Rdt, rdt);
936 i82563rxinit(Ctlr *ctlr)
941 if(ctlr->rbsz <= 2048)
942 csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
944 i = ctlr->rbsz / 1024;
945 if(cttab[ctlr->type].flag & F75){
946 csr32w(ctlr, Rctl, Lpe|Dpf|Bsize2048|Bam|RdtmsHALF|Secrc);
947 if(ctlr->type != i82575)
948 i |= (ctlr->nrd/2>>4)<<20; /* RdmsHalf */
949 csr32w(ctlr, Srrctl, i | Dropen);
950 csr32w(ctlr, Rmpl, ctlr->rbsz);
951 // csr32w(ctlr, Drxmxod, 0x7ff);
953 csr32w(ctlr, Rctl, Lpe|Dpf|BsizeFlex*i|Bam|RdtmsHALF|Secrc);
956 if(cttab[ctlr->type].flag & Fert)
957 csr32w(ctlr, Ert, 1024/8);
959 if(ctlr->type == i82566)
960 csr32w(ctlr, Pbs, 16);
962 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
963 csr32w(ctlr, Rdbah, 0);
964 csr32w(ctlr, Rdlen, ctlr->nrd * sizeof(Rd));
966 csr32w(ctlr, Rdh, 0);
968 csr32w(ctlr, Rdt, 0);
971 csr32w(ctlr, Rdtr, ctlr->rdtr);
972 csr32w(ctlr, Radv, ctlr->radv);
974 for(i = 0; i < ctlr->nrd; i++)
975 if((bp = ctlr->rb[i]) != nil){
979 if(cttab[ctlr->type].flag & F75)
980 csr32w(ctlr, Rxdctl, 1<<WthreshSHIFT | 8<<PthreshSHIFT | 1<<HthreshSHIFT | Enable);
982 csr32w(ctlr, Rxdctl, 2<<WthreshSHIFT | 2<<PthreshSHIFT);
985 * Enable checksum offload.
987 csr32w(ctlr, Rxcsum, Tuofl | Ipofl | ETHERHDRSIZE);
993 return ((Ctlr*)v)->rim != 0;
997 i82563rproc(void *arg)
1009 csr32w(ctlr, Rctl, csr32r(ctlr, Rctl) | Ren);
1010 if(cttab[ctlr->type].flag & F75){
1011 csr32w(ctlr, Rxdctl, csr32r(ctlr, Rxdctl) | Enable);
1012 im = Rxt0|Rxo|Rxdmt0|Rxseq|Ack;
1014 im = Rxt0|Rxo|Rxdmt0|Rxseq|Ack;
1021 i82563replenish(ctlr);
1022 sleep(&ctlr->rrendez, i82563rim, ctlr);
1028 rd = &ctlr->rdba[rdh];
1029 if(!(rd->status & Rdd))
1033 * Accept eop packets with no errors.
1034 * With no errors and the Ixsm bit set,
1035 * the descriptor status Tpcs and Ipcs bits give
1036 * an indication of whether the checksums were
1037 * calculated and valid.
1040 if((rd->status & Reop) && rd->errors == 0){
1041 bp->wp += rd->length;
1042 if(!(rd->status & Ixsm)){
1044 if(rd->status & Ipcs){
1046 * IP checksum calculated
1047 * (and valid as errors == 0).
1052 if(rd->status & Tcpcs){
1054 * TCP/UDP checksum calculated
1055 * (and valid as errors == 0).
1058 bp->flag |= Btcpck|Budpck;
1060 bp->checksum = rd->checksum;
1066 ctlr->rb[rdh] = nil;
1068 ctlr->rdh = rdh = NEXT(rdh, ctlr->nrd);
1069 if(ctlr->nrd-ctlr->rdfree >= 32 || (rim & Rxdmt0))
1070 i82563replenish(ctlr);
1078 return ((Ctlr*)v)->lim != 0;
1081 static int speedtab[] = {
1086 phyread(Ctlr *c, int phyno, int reg)
1090 csr32w(c, Mdic, MDIrop | phyno<<MDIpSHIFT | reg<<MDIrSHIFT);
1092 for(i = 0; i < 64; i++){
1093 phy = csr32r(c, Mdic);
1094 if(phy & (MDIe|MDIready))
1098 if((phy & (MDIe|MDIready)) != MDIready){
1099 print("%s: phy %d wedged %.8ux\n", cname(c), phyno, phy);
1102 return phy & 0xffff;
1106 phywrite0(Ctlr *c, int phyno, int reg, ushort val)
1110 csr32w(c, Mdic, MDIwop | phyno<<MDIpSHIFT | reg<<MDIrSHIFT | val);
1112 for(i = 0; i < 64; i++){
1113 phy = csr32r(c, Mdic);
1114 if(phy & (MDIe|MDIready))
1118 if((phy & (MDIe|MDIready)) != MDIready)
1124 setpage(Ctlr *c, uint phyno, uint p, uint r)
1128 if(c->type == i82563){
1129 if(r >= 16 && r <= 28 && r != 22)
1131 else if(r == 30 || r == 31)
1135 return phywrite0(c, phyno, pr, p);
1142 phywrite(Ctlr *c, uint phyno, uint reg, ushort v)
1144 if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0)
1145 panic("%s: bad phy reg %.4ux", cname(c), reg);
1146 return phywrite0(c, phyno, reg & 0xff, v);
1150 phyerrata(Ether *e, Ctlr *c, uint phyno)
1153 if(c->phyerrata == 0){
1155 phywrite(c, phyno, Phyprst, Prst); /* try a port reset */
1156 print("%s: phy port reset\n", cname(c));
1163 phyprobe(Ctlr *c, uint mask)
1167 for(phyno=0; mask != 0; phyno++, mask>>=1){
1170 if(phyread(c, phyno, Physr) == ~0)
1172 phy = (phyread(c, phyno, Phyid1) & 0x3FFF)<<6;
1173 phy |= phyread(c, phyno, Phyid2) >> 10;
1174 if(phy == 0xFFFFF || phy == 0)
1176 print("%s: phy%d oui %#ux\n", cname(c), phyno, phy);
1179 print("%s: no phy\n", cname(c));
1184 lsleep(Ctlr *c, uint m)
1189 sleep(&c->lrendez, i82563lim, c);
1195 uint i, r, phy, phyno;
1204 while((phyno = phyprobe(c, 3<<1)) == ~0)
1210 tsleep(&up->sleep, return0, 0, 150);
1211 phy = phyread(c, phyno, Phystat);
1215 r = phyread(c, phyno, Phyctl);
1218 phywrite(c, phyno, Phyctl, r | Ran | Ean);
1223 e->link = i != 3 && (phy & Link) != 0;
1227 e->mbps = speedtab[i];
1235 uint a, i, phy, phyno;
1244 while((phyno = phyprobe(c, 3<<1)) == ~0)
1247 if(c->type == i82573 && (phy = phyread(c, phyno, Phyier)) != ~0)
1248 phywrite(c, phyno, Phyier, phy | Lscie | Ancie | Spdie | Panie);
1251 phy = phyread(c, phyno, Physsr);
1266 a = phyread(c, phyno, Phyisr) & Ane;
1272 a = phyread(c, phyno, Phylhr) & Anf;
1277 phywrite(c, phyno, Phyctl, phyread(c, phyno, Phyctl) | Ran | Ean);
1279 e->link = (phy & Rtlink) != 0;
1283 e->mbps = speedtab[i];
1284 if(c->type == i82563)
1285 phyerrata(e, c, phyno);
1302 if(c->type == i82575 || c->type == i82576)
1303 csr32w(c, Connsw, Enrgirq);
1305 phy = csr32r(c, Pcsstat);
1306 e->link = phy & Linkok;
1310 else if(phy & Anbad)
1311 csr32w(c, Pcsctl, csr32r(c, Pcsctl) | Pan | Prestart);
1313 e->mbps = speedtab[i];
1314 lsleep(c, Lsc | Omed);
1319 serdeslproc(void *v)
1330 rx = csr32r(c, Rxcw);
1331 tx = csr32r(c, Txcw);
1333 e->link = (rx & 1<<31) != 0;
1334 // e->link = (csr32r(c, Status) & Lu) != 0;
1339 e->mbps = speedtab[i];
1345 i82563attach(Ether *edev)
1347 char name[KNAMELEN];
1351 qlock(&ctlr->alock);
1352 if(ctlr->alloc != nil){
1353 qunlock(&ctlr->alock);
1359 ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 255);
1360 ctlr->rb = malloc(ctlr->nrd * sizeof(Block*));
1361 ctlr->tb = malloc(ctlr->ntd * sizeof(Block*));
1362 if(ctlr->alloc == nil || ctlr->rb == nil || ctlr->tb == nil){
1369 qunlock(&ctlr->alock);
1372 ctlr->rdba = (Rd*)ROUNDUP((uintptr)ctlr->alloc, 256);
1373 ctlr->tdba = (Td*)(ctlr->rdba + ctlr->nrd);
1382 qunlock(&ctlr->alock);
1386 snprint(name, sizeof name, "#l%dl", edev->ctlrno);
1387 if(csr32r(ctlr, Status) & Tbimode)
1388 kproc(name, serdeslproc, edev); /* mac based serdes */
1389 else if((csr32r(ctlr, Ctrlext) & Linkmode) == Serdes)
1390 kproc(name, pcslproc, edev); /* phy based serdes */
1391 else if(cttab[ctlr->type].flag & F79phy)
1392 kproc(name, phyl79proc, edev);
1394 kproc(name, phylproc, edev);
1396 snprint(name, sizeof name, "#l%dr", edev->ctlrno);
1397 kproc(name, i82563rproc, edev);
1399 snprint(name, sizeof name, "#l%dt", edev->ctlrno);
1400 kproc(name, i82563tproc, edev);
1402 qunlock(&ctlr->alock);
1407 i82563interrupt(Ureg*, void *arg)
1416 ilock(&ctlr->imlock);
1417 csr32w(ctlr, Imc, ~0);
1420 while(icr = csr32r(ctlr, Icr) & ctlr->im){
1421 if(icr & (Lsc | Omed)){
1422 im &= ~(Lsc | Omed);
1423 ctlr->lim = icr & (Lsc | Omed);
1424 wakeup(&ctlr->lrendez);
1427 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack)){
1428 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
1429 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
1430 wakeup(&ctlr->rrendez);
1436 wakeup(&ctlr->trendez);
1441 csr32w(ctlr, Ims, im);
1442 iunlock(&ctlr->imlock);
1446 i82563detach(Ctlr *ctlr)
1450 /* balance rx/tx packet buffer; survives reset */
1451 if(ctlr->rbsz > 8192 && cttab[ctlr->type].flag & Fpba){
1452 ctlr->pba = csr32r(ctlr, Pba);
1453 r = ctlr->pba >> 16;
1454 r += ctlr->pba & 0xffff;
1456 csr32w(ctlr, Pba, r);
1457 }else if(ctlr->type == i82573 && ctlr->rbsz > 1514)
1458 csr32w(ctlr, Pba, 14);
1459 ctlr->pba = csr32r(ctlr, Pba);
1462 * Perform a device reset to get the chip back to the
1463 * power-on state, followed by an EEPROM reset to read
1464 * the defaults for some internal registers.
1466 csr32w(ctlr, Imc, ~0);
1467 csr32w(ctlr, Rctl, 0);
1468 csr32w(ctlr, Tctl, csr32r(ctlr, Tctl) & ~Ten);
1472 r = csr32r(ctlr, Ctrl);
1473 if(ctlr->type == i82566 || ctlr->type == i82579)
1476 * hack: 82579LM on lenovo X230 is stuck at 10mbps after
1477 * reseting the phy, but works fine if we dont reset.
1479 if(ctlr->pcidev->did == 0x1502)
1481 csr32w(ctlr, Ctrl, Devrst | r);
1483 for(timeo = 0;; timeo++){
1484 if((csr32r(ctlr, Ctrl) & (Devrst|Phyrst)) == 0)
1491 r = csr32r(ctlr, Ctrl);
1492 csr32w(ctlr, Ctrl, Slu|r);
1494 r = csr32r(ctlr, Ctrlext);
1495 csr32w(ctlr, Ctrlext, r|Eerst);
1497 for(timeo = 0; timeo < 1000; timeo++){
1498 if(!(csr32r(ctlr, Ctrlext) & Eerst))
1502 if(csr32r(ctlr, Ctrlext) & Eerst)
1505 csr32w(ctlr, Imc, ~0);
1507 for(timeo = 0; timeo < 1000; timeo++){
1508 if((csr32r(ctlr, Icr) & ~Rxcfg) == 0)
1512 if(csr32r(ctlr, Icr) & ~Rxcfg)
1519 i82563shutdown(Ether *edev)
1521 i82563detach(edev->ctlr);
1525 eeread(Ctlr *ctlr, int adr)
1529 csr32w(ctlr, Eerd, EEstart | adr << 2);
1531 while ((csr32r(ctlr, Eerd) & EEdone) == 0 && timeout--)
1534 print("%s: eeread timeout\n", cname(ctlr));
1537 return (csr32r(ctlr, Eerd) >> 16) & 0xffff;
1547 for (adr = 0; adr < 0x40; adr++) {
1548 data = eeread(ctlr, adr);
1549 if(data == -1) return -1;
1550 ctlr->eeprom[adr] = data;
1557 fread16(Ctlr *c, Flash *f, int ladr)
1566 f->reg[Fsts] |= Fcerr | Ael;
1567 for(timeout = 0; timeout < 10; timeout++){
1575 f->reg[Fsts] |= Fdone;
1576 f->reg32[Faddr] = ladr;
1578 /* setup flash control register */
1579 s = f->reg[Fctl] & ~0x3ff;
1580 f->reg[Fctl] = s | 1<<8 | Fgo; /* 2 byte read */
1582 while((f->reg[Fsts] & Fdone) == 0 && timeout--)
1585 print("%s: fread timeout\n", cname(c));
1588 if(f->reg[Fsts] & (Fcerr|Ael))
1590 return f->reg32[Fdata] & 0xffff;
1594 fread32(Ctlr *c, Flash *f, int ladr, u32int *data)
1600 s = f->reg32[Fsts/2];
1603 f->reg32[Fsts/2] |= Fcerr | Ael;
1604 for(timeout = 0; timeout < 10; timeout++){
1608 s = f->reg32[Fsts/2];
1612 f->reg32[Fsts/2] |= Fdone;
1613 f->reg32[Faddr] = ladr;
1615 /* setup flash control register */
1616 s = (f->reg32[Fctl/2] >> 16) & ~0x3ff;
1617 f->reg32[Fctl/2] = (s | 3<<8 | Fgo) << 16; /* 4 byte read */
1619 while((f->reg32[Fsts/2] & Fdone) == 0 && timeout--)
1622 print("%s: fread timeout\n", cname(c));
1625 if(f->reg32[Fsts/2] & (Fcerr|Ael))
1627 *data = f->reg32[Fdata];
1639 f.reg32 = &c->nic[0xe000/4];
1642 f.lim = (((csr32r(c, 0xC) >> 1) & 0x1F) + 1) << 12;
1644 if(fread32(c, &f, r + 0x24, &w) == -1 || (w & 0xC000) != 0x8000)
1647 for(adr = 0; adr < 0x20; adr++) {
1648 if(fread32(c, &f, r + adr*4, &w) == -1)
1650 c->eeprom[adr*2+0] = w;
1651 c->eeprom[adr*2+1] = w>>16;
1666 memset(c->eeprom, 0xFF, sizeof(c->eeprom));
1667 if(c->pcidev->mem[1].bar == 0)
1668 return fload32(c); /* i219 */
1670 va = vmap(c->pcidev->mem[1].bar & ~0x0f, c->pcidev->mem[1].size);
1675 f.base = f.reg32[Bfpr] & 0x1fff;
1676 f.lim = f.reg32[Bfpr]>>16 & 0x1fff;
1677 if(csr32r(c, Eec) & Sec1val)
1678 f.base += f.lim+1 - f.base >> 1;
1681 for(adr = 0; adr < 0x40; adr++) {
1682 data = fread16(c, &f, r + adr*2);
1685 c->eeprom[adr] = data;
1689 vunmap(va, c->pcidev->mem[1].size);
1699 memset(c->eeprom, 0xFF, sizeof(c->eeprom));
1700 for(i=0; i<64; i++){
1701 w = csr32r(c, Invmdata0 + i*4);
1703 case 0: // uninitialized structure
1705 case 1: // word auto load
1706 a = (w & 0xFE00) >> 9;
1707 if(a < nelem(c->eeprom))
1708 c->eeprom[a] = w >> 16;
1710 case 2: // csr auto load
1712 case 3: // phy auto load
1714 case 4: // rsa key sha256
1716 case 5: // invalidated structure
1719 print("invm: %.2x %.8ux\n", i, w);
1728 defaultea(Ctlr *ctlr, uchar *ra)
1732 static uchar nilea[Eaddrlen];
1734 if(memcmp(ra, nilea, Eaddrlen) != 0)
1736 if(cttab[ctlr->type].flag & Fflashea){
1738 u = (uvlong)csr32r(ctlr, Rah)<<32u | (ulong)csr32r(ctlr, Ral);
1739 for(i = 0; i < Eaddrlen; i++)
1742 if(memcmp(ra, nilea, Eaddrlen) != 0)
1744 for(i = 0; i < Eaddrlen/2; i++){
1745 ra[2*i] = ctlr->eeprom[Ea+i];
1746 ra[2*i+1] = ctlr->eeprom[Ea+i] >> 8;
1748 r = (csr32r(ctlr, Status) & Lanid) >> 2;
1749 ra[5] += r; /* ea ctlr[n] = ea ctlr[0]+n */
1753 i82563reset(Ctlr *ctlr)
1758 if(i82563detach(ctlr))
1760 flag = cttab[ctlr->type].flag;
1762 if(ctlr->type == i210 && (csr32r(ctlr, Eec) & Flupd) == 0)
1764 else if(flag & Fload)
1769 if(r != 0 && r != 0xbaba){
1770 print("%s: bad eeprom checksum - %#.4ux", cname(ctlr), r);
1772 print("; ignored\n");
1780 defaultea(ctlr, ra);
1781 csr32w(ctlr, Ral, ra[3]<<24 | ra[2]<<16 | ra[1]<<8 | ra[0]);
1782 csr32w(ctlr, Rah, 1<<31 | ra[5]<<8 | ra[4]);
1783 for(i = 1; i < 16; i++){
1784 csr32w(ctlr, Ral+i*8, 0);
1785 csr32w(ctlr, Rah+i*8, 0);
1787 memset(ctlr->mta, 0, sizeof(ctlr->mta));
1788 for(i = 0; i < 128; i++)
1789 csr32w(ctlr, Mta + i*4, 0);
1790 if((flag & Fnofca) == 0){
1791 csr32w(ctlr, Fcal, 0x00C28001);
1792 csr32w(ctlr, Fcah, 0x0100);
1794 if((flag & Fnofct) == 0)
1795 csr32w(ctlr, Fct, 0x8808);
1796 csr32w(ctlr, Fcttv, 0x0100);
1797 csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1798 csr32w(ctlr, Fcrth, ctlr->fcrth);
1800 csr32w(ctlr, Eitr, 128<<2); /* 128 ¼ microsecond intervals */
1811 static Cmdtab i82563ctlmsg[] = {
1814 CMpause, "pause", 1,
1819 i82563ctl(Ether *edev, void *buf, long n)
1827 if((ctlr = edev->ctlr) == nil)
1830 cb = parsecmd(buf, n);
1836 ct = lookupcmd(cb, i82563ctlmsg, nelem(i82563ctlmsg));
1839 v = strtoul(cb->f[1], &p, 0);
1840 if(*p || v > 0xffff)
1843 csr32w(ctlr, Rdtr, v);
1846 v = strtoul(cb->f[1], &p, 0);
1847 if(*p || v > 0xffff)
1850 csr32w(ctlr, Radv, v);
1853 csr32w(ctlr, Ctrl, csr32r(ctlr, Ctrl) ^ (Rfce | Tfce));
1856 csr32w(ctlr, Ctrl, csr32r(ctlr, Ctrl) | Lrst | Phyrst);
1869 * Some names and did values are from
1870 * OpenBSD's em(4) Intel driver.
1873 case 0x1096: /* copper */
1874 case 0x10ba: /* copper “gilgal” */
1875 case 0x1098: /* serdes; not seen */
1876 case 0x10bb: /* serdes */
1878 case 0x1049: /* ich8; mm */
1879 case 0x104a: /* ich8; dm */
1880 case 0x104b: /* ich8; dc */
1881 case 0x104d: /* ich8; v “ninevah” */
1882 case 0x10bd: /* ich9; dm-2 */
1883 case 0x294c: /* ich9 */
1884 case 0x104c: /* ich8; untested */
1885 case 0x10c4: /* ich8; untested */
1886 case 0x10c5: /* ich8; untested */
1888 case 0x10de: /* lm ich10d */
1889 case 0x10df: /* lf ich10 */
1890 case 0x10e5: /* lm ich9 */
1891 case 0x10f5: /* lm ich9m; “boazman” */
1892 case 0x10ce: /* v ich10 */
1893 case 0x10c0: /* ich9 */
1894 case 0x10c2: /* ich9; untested */
1895 case 0x10c3: /* ich9; untested */
1896 case 0x1501: /* ich8; untested */
1898 case 0x10bf: /* lf ich9m */
1899 case 0x10cb: /* v ich9m */
1900 case 0x10cd: /* lf ich10 */
1901 case 0x10cc: /* lm ich10 */
1903 case 0x105e: /* eb copper */
1904 case 0x105f: /* eb fiber */
1905 case 0x1060: /* eb serdes */
1906 case 0x10a4: /* eb copper */
1907 case 0x10a5: /* eb fiber */
1908 case 0x10bc: /* eb copper */
1909 case 0x10d9: /* eb serdes */
1910 case 0x10da: /* eb serdes “ophir” */
1911 case 0x10a0: /* eb; untested */
1912 case 0x10a1: /* eb; untested */
1913 case 0x10d5: /* copper; untested */
1915 case 0x107d: /* ei copper */
1916 case 0x107e: /* ei fiber */
1917 case 0x107f: /* ei serdes */
1918 case 0x10b9: /* ei “rimon” */
1920 case 0x108b: /* e “vidalia” */
1921 case 0x108c: /* e (iamt) */
1922 case 0x109a: /* l “tekoa” */
1923 case 0x10b0: /* l; untested */
1924 case 0x10b2: /* v; untested */
1925 case 0x10b3: /* e; untested */
1926 case 0x10b4: /* l; untested */
1928 case 0x10d3: /* l or it; “hartwell” */
1929 case 0x10f6: /* la; untested */
1931 case 0x10a7: /* eb */
1932 case 0x10a9: /* eb fiber/serdes */
1933 case 0x10d6: /* untested */
1934 case 0x10e2: /* untested */
1936 case 0x10c9: /* copper */
1937 case 0x10e6: /* fiber */
1938 case 0x10e7: /* serdes; “kawela” */
1939 case 0x10e8: /* copper; untested */
1940 case 0x150a: /* untested */
1941 case 0x150d: /* serdes backplane */
1942 case 0x1518: /* serdes; untested */
1943 case 0x1526: /* untested */
1945 case 0x10ea: /* lc “calpella”; aka pch lan */
1947 case 0x10eb: /* lm “calpella” */
1949 case 0x10ef: /* dc “piketon” */
1951 case 0x1502: /* lm */
1952 case 0x1503: /* v “lewisville” */
1954 case 0x10f0: /* dm “king's creek” */
1956 case 0x150e: /* copper “barton hills” */
1957 case 0x150f: /* fiber */
1958 case 0x1510: /* serdes backplane */
1959 case 0x1511: /* sgmii sfp */
1960 case 0x1516: /* copper */
1962 case 0x1506: /* v */
1963 case 0x150c: /* untested */
1965 case 0x1533: /* i210-t1 */
1966 case 0x1534: /* i210 */
1967 case 0x1536: /* i210-fiber */
1968 case 0x1537: /* i210-backplane */
1969 case 0x1538: /* i210 sgmii */
1970 case 0x1539: /* i211 copper */
1971 case 0x157b: /* i210 copper flashless */
1972 case 0x157c: /* i210 serdes flashless */
1974 case 0x153a: /* i217-lm */
1975 case 0x153b: /* i217-v */
1977 case 0x1559: /* i218-v */
1978 case 0x155a: /* i218-lm */
1979 case 0x15a0: /* i218-lm */
1980 case 0x15a1: /* i218-v */
1981 case 0x15a2: /* i218-lm */
1982 case 0x15a3: /* i218-v */
1984 case 0x156f: /* i219-lm */
1985 case 0x15b7: /* i219-lm */
1986 case 0x1570: /* i219-v */
1987 case 0x15b8: /* i219-v */
1988 case 0x15b9: /* i219-lm */
1989 case 0x15d6: /* i219-v */
1990 case 0x15d7: /* i219-lm */
1991 case 0x15d8: /* i219-v */
1992 case 0x15e3: /* i219-lm */
1994 case 0x151f: /* i350 “powerville” eeprom-less */
1995 case 0x1521: /* i350 copper */
1996 case 0x1522: /* i350 fiber */
1997 case 0x1523: /* i350 serdes */
1998 case 0x1524: /* i350 sgmii */
1999 case 0x1546: /* i350 DA4 (untested) */
2000 case 0x1f40: /* i354 backplane */
2001 case 0x1f41: /* i354 sgmii */
2002 case 0x1f42: /* i354 sgmii (c2000) */
2003 case 0x1f45: /* i354 backplane 2.5 */
2014 i = pcicfgr32(p, PciSVID);
2015 if((i & 0xffff) == 0x1b52 && p->did == 1)
2026 for(p = nil; p = pcimatch(p, 0x8086, 0);){
2028 if((type = didtype(p->did)) == -1)
2030 ctlr = malloc(sizeof(Ctlr));
2032 print("%s: can't allocate memory\n", cttab[type].name);
2037 ctlr->rbsz = ROUND(cttab[type].mtu, 1024);
2038 ctlr->port = p->mem[0].bar & ~0x0F;
2039 if(i82563ctlrhead != nil)
2040 i82563ctlrtail->next = ctlr;
2042 i82563ctlrhead = ctlr;
2043 i82563ctlrtail = ctlr;
2053 ctlr->nic = vmap(ctlr->port, p->mem[0].size);
2054 if(ctlr->nic == nil){
2055 print("%s: can't map 0x%lux\n", cname(ctlr), ctlr->port);
2059 if(i82563reset(ctlr)){
2061 vunmap(ctlr->nic, p->mem[0].size);
2069 pnp(Ether *edev, int type)
2080 * Any adapter matches if no edev->port is supplied,
2081 * otherwise the ports must match.
2083 for(ctlr = i82563ctlrhead; ; ctlr = ctlr->next){
2088 if(type != -1 && ctlr->type != type)
2090 if(edev->port == 0 || edev->port == ctlr->port){
2092 memmove(ctlr->ra, edev->ea, Eaddrlen);
2093 if(setup(ctlr) == 0)
2099 edev->port = ctlr->port;
2100 edev->irq = ctlr->pcidev->intl;
2101 edev->tbdf = ctlr->pcidev->tbdf;
2103 edev->maxmtu = cttab[ctlr->type].mtu;
2104 memmove(edev->ea, ctlr->ra, Eaddrlen);
2107 * Linkage to the generic ethernet driver.
2109 edev->attach = i82563attach;
2110 // edev->transmit = i82563transmit;
2111 edev->ifstat = i82563ifstat;
2112 edev->ctl = i82563ctl;
2115 edev->promiscuous = i82563promiscuous;
2116 edev->shutdown = i82563shutdown;
2117 edev->multicast = i82563multicast;
2119 intrenable(edev->irq, i82563interrupt, edev, edev->tbdf, edev->name);
2133 return pnp(e, i82563);
2139 return pnp(e, i82566);
2145 return pnp(e, i82567m) & pnp(e, i82567);
2151 return pnp(e, i82571);
2157 return pnp(e, i82572);
2163 return pnp(e, i82573);
2169 return pnp(e, i82574);
2175 return pnp(e, i82575);
2181 return pnp(e, i82576);
2187 return pnp(e, i82577m) & pnp(e, i82577);
2193 return pnp(e, i82578m) & pnp(e, i82578);
2199 return pnp(e, i82579);
2205 return pnp(e, i82580);
2211 return pnp(e, i82583);
2217 return pnp(e, i210);
2223 return pnp(e, i217);
2229 return pnp(e, i218);
2235 return pnp(e, i219);
2241 return pnp(e, i350);
2245 ether82563link(void)
2248 * recognise lots of model numbers for debugging
2249 * also good for forcing onboard nic(s) as ether0
2250 * try to make that unnecessary by listing lom first.
2252 addethercard("i82563", i82563pnp);
2253 addethercard("i82566", i82566pnp);
2254 addethercard("i82574", i82574pnp);
2255 addethercard("i82576", i82576pnp);
2256 addethercard("i82567", i82567pnp);
2257 addethercard("i82573", i82573pnp);
2259 addethercard("i82571", i82571pnp);
2260 addethercard("i82572", i82572pnp);
2261 addethercard("i82575", i82575pnp);
2262 addethercard("i82577", i82577pnp);
2263 addethercard("i82578", i82578pnp);
2264 addethercard("i82579", i82579pnp);
2265 addethercard("i82580", i82580pnp);
2266 addethercard("i82583", i82583pnp);
2267 addethercard("i210", i210pnp);
2268 addethercard("i217", i217pnp);
2269 addethercard("i218", i218pnp);
2270 addethercard("i219", i219pnp);
2271 addethercard("i350", i350pnp);
2272 addethercard("igbepcie", anypnp);