2 * Intel 82557 Fast Ethernet PCI Bus LAN Controller
3 * as found on the Intel EtherExpress PRO/100B. This chip is full
4 * of smarts, unfortunately they're not all in the right place.
6 * the PCI scanning code could be made common to other adapters;
7 * auto-negotiation, full-duplex;
8 * optionally use memory-mapped registers;
9 * detach for PCI reset problems (also towards loadable drivers).
12 #include "../port/lib.h"
17 #include "../port/error.h"
18 #include "../port/netif.h"
23 Nrfd = 64, /* receive frame area */
24 Ncb = 64, /* maximum control blocks queued */
26 NullPointer = 0xFFFFFFFF, /* 82557 NULL pointer */
30 Status = 0x00, /* byte or word (word includes Ack) */
31 Ack = 0x01, /* byte */
32 CommandR = 0x02, /* byte or word (word includes Interrupt) */
33 Interrupt = 0x03, /* byte */
34 General = 0x04, /* dword */
35 Port = 0x08, /* dword */
36 Fcr = 0x0C, /* Flash control register */
37 Ecr = 0x0E, /* EEPROM control register */
38 Mcr = 0x10, /* MDI control register */
39 Gstatus = 0x1D, /* General status register */
45 RUnoresources = 0x0008,
47 RUrbd = 0x0020, /* bit */
48 RUstatus = 0x003F, /* mask */
53 CUstatus = 0x00C0, /* mask */
55 StatSWI = 0x0400, /* SoftWare generated Interrupt */
56 StatMDI = 0x0800, /* MDI r/w done */
57 StatRNR = 0x1000, /* Receive unit Not Ready */
58 StatCNA = 0x2000, /* Command unit Not Active (Active->Idle) */
59 StatFR = 0x4000, /* Finished Receiving */
60 StatCX = 0x8000, /* Command eXecuted */
61 StatTNO = 0x8000, /* Transmit NOT OK */
64 enum { /* Command (byte) */
68 LoadDCA = 0x40, /* Load Dump Counters Address */
69 DumpSC = 0x50, /* Dump Statistical Counters */
70 LoadCUB = 0x60, /* Load CU Base */
71 ResetSA = 0x70, /* Dump and Reset Statistical Counters */
76 LoadHDS = 0x05, /* Load Header Data Size */
77 LoadRUB = 0x06, /* Load RU Base */
78 RBDresume = 0x07, /* Resume frame reception */
81 enum { /* Interrupt (byte) */
82 InterruptM = 0x01, /* interrupt Mask */
83 InterruptSI = 0x02, /* Software generated Interrupt */
87 EEsk = 0x01, /* serial clock */
88 EEcs = 0x02, /* chip select */
89 EEdi = 0x04, /* serial data in */
90 EEdo = 0x08, /* serial data out */
92 EEstart = 0x04, /* start bit */
93 EEread = 0x02, /* read opcode */
97 MDIread = 0x08000000, /* read opcode */
98 MDIwrite = 0x04000000, /* write opcode */
99 MDIready = 0x10000000, /* ready bit */
100 MDIie = 0x20000000, /* interrupt enable */
114 RfdCollision = 0x00000001,
115 RfdIA = 0x00000002, /* IA match */
116 RfdRxerr = 0x00000010, /* PHY character error */
117 RfdType = 0x00000020, /* Type frame */
118 RfdRunt = 0x00000080,
119 RfdOverrun = 0x00000100,
120 RfdBuffer = 0x00000200,
121 RfdAlignment = 0x00000400,
124 RfdOK = 0x00002000, /* frame received OK */
125 RfdC = 0x00008000, /* reception Complete */
126 RfdSF = 0x00080000, /* Simplified or Flexible (1) Rfd */
127 RfdH = 0x00100000, /* Header RFD */
129 RfdI = 0x20000000, /* Interrupt after completion */
130 RfdS = 0x40000000, /* Suspend after completion */
131 RfdEL = 0x80000000, /* End of List */
139 typedef struct Cb Cb;
145 uchar data[24]; /* CbIAS + CbConfigure */
162 enum { /* action command */
163 CbU = 0x1000, /* transmit underrun */
164 CbOK = 0x2000, /* DMA completed OK */
165 CbC = 0x8000, /* execution Complete */
168 CbIAS = 0x0001, /* Individual Address Setup */
169 CbConfigure = 0x0002,
170 CbMAS = 0x0003, /* Multicast Address Setup */
174 CbCommand = 0x0007, /* mask */
176 CbSF = 0x0008, /* Flexible-mode CbTransmit */
178 CbI = 0x2000, /* Interrupt after completion */
179 CbS = 0x4000, /* Suspend after completion */
180 CbEL = 0x8000, /* End of List */
183 enum { /* CbTransmit count */
187 typedef struct Ctlr Ctlr;
188 typedef struct Ctlr {
189 Lock slock; /* attach */
197 int eepromsz; /* address size in bits */
204 Lock rlock; /* registers */
205 int command; /* last command issued */
207 Block* rfdhead; /* receive side */
211 Lock cblock; /* transmit side */
214 uchar configdata[24];
224 Lock dlock; /* dump statistical counters */
228 static Ctlr* ctlrhead;
229 static Ctlr* ctlrtail;
231 static uchar configdata[24] = {
232 0x16, /* byte count */
233 0x08, /* Rx/Tx FIFO limit */
234 0x00, /* adaptive IFS */
236 0x00, /* Rx DMA maximum byte count */
237 // 0x80, /* Tx DMA maximum byte count */
238 0x00, /* Tx DMA maximum byte count */
239 0x32, /* !late SCB, CNA interrupts */
240 0x03, /* discard short Rx frames */
244 0x2E, /* normal operation, NSAI */
245 0x00, /* linear priority */
246 0x60, /* inter-frame spacing */
249 0xC8, /* 503, promiscuous mode off */
252 0xF3, /* transmit padding enable */
253 0x80, /* full duplex pin enable */
254 0x3F, /* no Multi IA */
255 0x05, /* no Multi Cast ALL */
258 #define csr8r(c, r) (inb((c)->port+(r)))
259 #define csr16r(c, r) (ins((c)->port+(r)))
260 #define csr32r(c, r) (inl((c)->port+(r)))
261 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
262 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
263 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
266 command(Ctlr* ctlr, int c, int v)
273 * Only back-to-back CUresume can be done
274 * without waiting for any previous command to complete.
275 * This should be the common case.
276 * Unfortunately there's a chip errata where back-to-back
277 * CUresumes can be lost, the fix is to always wait.
278 if(c == CUresume && ctlr->command == CUresume){
279 csr8w(ctlr, CommandR, c);
280 iunlock(&ctlr->rlock);
285 for(timeo = 0; timeo < 100; timeo++){
286 if(!csr8r(ctlr, CommandR))
292 iunlock(&ctlr->rlock);
293 iprint("i82557: command %#ux %#ux timeout\n", c, v);
305 csr32w(ctlr, General, v);
319 csr8w(ctlr, CommandR, c);
322 iunlock(&ctlr->rlock);
331 if(bp = iallocb(sizeof(Rfd))){
335 rfd->rbd = NullPointer;
337 rfd->size = sizeof(Etherpkt);
348 static void txstart(Ether*);
352 tsleep(&up->sleep, return0, 0, 4000);
355 * Hmmm. This doesn't seem right. Currently
356 * the device can't be disabled but it may be in
360 if(ctlr == nil || ctlr->state == 0){
361 print("%s: exiting\n", up->text);
362 pexit("disabled", 0);
365 ilock(&ctlr->cblock);
367 ctlr->action = CbMAS;
370 iunlock(&ctlr->cblock);
382 if(ctlr->state == 0){
384 csr8w(ctlr, Interrupt, 0);
385 iunlock(&ctlr->rlock);
386 command(ctlr, RUstart, PADDR(ctlr->rfdhead->rp));
390 * Start the watchdog timer for the receive lockup errata
391 * unless the EEPROM compatibility word indicates it may be
394 if((ctlr->eeprom[0x03] & 0x0003) != 0x0003){
395 snprint(name, KNAMELEN, "#l%dwatchdog", ether->ctlrno);
396 kproc(name, watchdog, ether);
399 unlock(&ctlr->slock);
403 ifstat(Ether* ether, void* a, long n, ulong offset)
414 * Start the command then
415 * wait for completion status,
419 command(ctlr, DumpSC, 0);
420 while(ctlr->dump[16] == 0)
423 ether->oerrs = ctlr->dump[1]+ctlr->dump[2]+ctlr->dump[3];
424 ether->crcs = ctlr->dump[10];
425 ether->frames = ctlr->dump[11];
426 ether->buffs = ctlr->dump[12]+ctlr->dump[15];
427 ether->overflows = ctlr->dump[13];
430 unlock(&ctlr->dlock);
434 memmove(dump, ctlr->dump, sizeof(dump));
435 unlock(&ctlr->dlock);
437 p = smalloc(READSTR);
438 len = snprint(p, READSTR, "transmit good frames: %lud\n", dump[0]);
439 len += snprint(p+len, READSTR-len, "transmit maximum collisions errors: %lud\n", dump[1]);
440 len += snprint(p+len, READSTR-len, "transmit late collisions errors: %lud\n", dump[2]);
441 len += snprint(p+len, READSTR-len, "transmit underrun errors: %lud\n", dump[3]);
442 len += snprint(p+len, READSTR-len, "transmit lost carrier sense: %lud\n", dump[4]);
443 len += snprint(p+len, READSTR-len, "transmit deferred: %lud\n", dump[5]);
444 len += snprint(p+len, READSTR-len, "transmit single collisions: %lud\n", dump[6]);
445 len += snprint(p+len, READSTR-len, "transmit multiple collisions: %lud\n", dump[7]);
446 len += snprint(p+len, READSTR-len, "transmit total collisions: %lud\n", dump[8]);
447 len += snprint(p+len, READSTR-len, "receive good frames: %lud\n", dump[9]);
448 len += snprint(p+len, READSTR-len, "receive CRC errors: %lud\n", dump[10]);
449 len += snprint(p+len, READSTR-len, "receive alignment errors: %lud\n", dump[11]);
450 len += snprint(p+len, READSTR-len, "receive resource errors: %lud\n", dump[12]);
451 len += snprint(p+len, READSTR-len, "receive overrun errors: %lud\n", dump[13]);
452 len += snprint(p+len, READSTR-len, "receive collision detect errors: %lud\n", dump[14]);
453 len += snprint(p+len, READSTR-len, "receive short frame errors: %lud\n", dump[15]);
454 len += snprint(p+len, READSTR-len, "nop: %d\n", ctlr->nop);
455 if(ctlr->cbqmax > ctlr->cbqmaxhw)
456 ctlr->cbqmaxhw = ctlr->cbqmax;
457 len += snprint(p+len, READSTR-len, "cbqmax: %d\n", ctlr->cbqmax);
459 len += snprint(p+len, READSTR-len, "threshold: %d\n", ctlr->threshold);
461 len += snprint(p+len, READSTR-len, "eeprom:");
462 for(i = 0; i < (1<<ctlr->eepromsz); i++){
463 if(i && ((i & 0x07) == 0))
464 len += snprint(p+len, READSTR-len, "\n ");
465 len += snprint(p+len, READSTR-len, " %4.4ux", ctlr->eeprom[i]);
468 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)){
469 phyaddr = ctlr->eeprom[6] & 0x00FF;
470 len += snprint(p+len, READSTR-len, "\nphy %2d:", phyaddr);
471 for(i = 0; i < 6; i++){
472 static int miir(Ctlr*, int, int);
474 len += snprint(p+len, READSTR-len, " %4.4ux",
475 miir(ctlr, phyaddr, i));
479 snprint(p+len, READSTR-len, "\n");
480 n = readstr(offset, a, n, p);
487 txstart(Ether* ether)
494 while(ctlr->cbq < (ctlr->ncb-1)){
495 cb = ctlr->cbhead->next;
496 if(ctlr->action == 0){
497 bp = qget(ether->oq);
501 cb->command = CbS|CbSF|CbTransmit;
502 cb->tbd = PADDR(&cb->tba);
504 cb->threshold = ctlr->threshold;
506 cb->tba = PADDR(bp->rp);
508 cb->tbasz = BLEN(bp);
510 else if(ctlr->action == CbConfigure){
511 cb->command = CbS|CbConfigure;
512 memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata));
515 else if(ctlr->action == CbIAS){
516 cb->command = CbS|CbIAS;
517 memmove(cb->data, ether->ea, Eaddrlen);
520 else if(ctlr->action == CbMAS){
521 cb->command = CbS|CbMAS;
522 memset(cb->data, 0, sizeof(cb->data));
526 print("#l%d: action %#ux\n", ether->ctlrno, ctlr->action);
533 ctlr->cbhead->command &= ~CbS;
539 * Workaround for some broken HUB chips
540 * when connected at 10Mb/s half-duplex.
543 command(ctlr, CUnop, 0);
546 command(ctlr, CUresume, 0);
548 if(ctlr->cbq > ctlr->cbqmax)
549 ctlr->cbqmax = ctlr->cbq;
553 configure(Ether* ether, int promiscuous)
558 ilock(&ctlr->cblock);
560 ctlr->configdata[6] |= 0x80; /* Save Bad Frames */
561 //ctlr->configdata[6] &= ~0x40; /* !Discard Overrun Rx Frames */
562 ctlr->configdata[7] &= ~0x01; /* !Discard Short Rx Frames */
563 ctlr->configdata[15] |= 0x01; /* Promiscuous mode */
564 ctlr->configdata[18] &= ~0x01; /* (!Padding enable?), !stripping enable */
565 ctlr->configdata[21] |= 0x08; /* Multi Cast ALL */
568 ctlr->configdata[6] &= ~0x80;
569 //ctlr->configdata[6] |= 0x40;
570 ctlr->configdata[7] |= 0x01;
571 ctlr->configdata[15] &= ~0x01;
572 ctlr->configdata[18] |= 0x01; /* 0x03? */
573 ctlr->configdata[21] &= ~0x08;
575 ctlr->action = CbConfigure;
577 iunlock(&ctlr->cblock);
581 promiscuous(void* arg, int on)
587 multicast(void* ether, uchar *addr, int add)
591 * TODO: if (add) add addr to list of mcast addrs in controller
592 * else remove addr from list of mcast addrs in controller
593 * enable multicast input (see CbMAS) instead of promiscuous mode.
600 transmit(Ether* ether)
605 ilock(&ctlr->cblock);
607 iunlock(&ctlr->cblock);
611 receive(Ether* ether)
616 Block *bp, *pbp, *xbp;
620 for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){
622 * If it's an OK receive frame
624 * 2) if it's small, try to allocate a block and copy
625 * the data, then adjust the necessary fields for reuse;
626 * 3) if it's big, try to allocate a new Rfd and if
628 * adjust the received buffer pointers for the
629 * actual data received;
630 * initialise the replacement buffer to point to
631 * the next in the ring;
632 * initialise bp to point to the replacement;
633 * 4) if there's a good packet, pass it on for disposal.
635 if(rfd->field & RfdOK){
637 count = rfd->count & 0x3FFF;
638 if((count < ETHERMAXTU/4) && (pbp = iallocb(count))){
639 memmove(pbp->rp, bp->rp+offsetof(Rfd, data[0]), count);
640 pbp->wp = pbp->rp + count;
645 else if(xbp = rfdalloc(rfd->link)){
646 bp->rp += offsetof(Rfd, data[0]);
647 bp->wp = bp->rp + count;
649 xbp->next = bp->next;
656 etheriq(ether, pbp, 1);
664 * The ring tail pointer follows the head with with one
665 * unused buffer in between to defeat hardware prefetch;
666 * once the tail pointer has been bumped on to the next
667 * and the new tail has the Suspend bit set, it can be
668 * removed from the old tail buffer.
669 * As a replacement for the current head buffer may have
670 * been allocated above, ensure that the new tail points
671 * to it (next and link).
673 rfd = (Rfd*)ctlr->rfdtail->rp;
674 ctlr->rfdtail = ctlr->rfdtail->next;
675 ctlr->rfdtail->next = bp;
676 ((Rfd*)ctlr->rfdtail->rp)->link = PADDR(bp->rp);
677 ((Rfd*)ctlr->rfdtail->rp)->field |= RfdS;
682 * Finally done with the current (possibly replaced)
683 * head, move on to the next and maintain the sentinel
684 * between tail and head.
686 ctlr->rfdhead = bp->next;
692 interrupt(Ureg*, void* arg)
704 status = csr16r(ctlr, Status);
705 csr8w(ctlr, Ack, (status>>8) & 0xFF);
706 iunlock(&ctlr->rlock);
708 if(!(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI)))
712 * If the watchdog timer for the receiver lockup errata is running,
713 * let it know the receiver is active.
715 if(status & (StatFR|StatRNR)){
716 ilock(&ctlr->cblock);
718 iunlock(&ctlr->cblock);
726 if(status & StatRNR){
727 command(ctlr, RUresume, 0);
731 if(status & StatCNA){
732 ilock(&ctlr->cblock);
736 if(!(cb->status & CbC))
742 if((cb->status & CbU) && ctlr->threshold < 0xE0)
751 iunlock(&ctlr->cblock);
756 if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))
757 panic("#l%d: status %#ux", ether->ctlrno, status);
770 * Create the Receive Frame Area (RFA) as a ring of allocated
772 * A sentinel buffer is maintained between the last buffer in
773 * the ring (marked with RfdS) and the head buffer to defeat the
774 * hardware prefetch of the next RFD and allow dynamic buffer
778 for(i = 0; i < Nrfd; i++){
780 if(ctlr->rfdhead == nil)
782 bp->next = ctlr->rfdhead;
784 link = PADDR(bp->rp);
786 ctlr->rfdtail->next = ctlr->rfdhead;
787 rfd = (Rfd*)ctlr->rfdtail->rp;
788 rfd->link = PADDR(ctlr->rfdhead->rp);
790 ctlr->rfdhead = ctlr->rfdhead->next;
793 * Create a ring of control blocks for the
796 ilock(&ctlr->cblock);
797 ctlr->cbr = malloc(ctlr->ncb*sizeof(Cb));
799 panic("i82557: can't allocate cbr");
800 for(i = 0; i < ctlr->ncb; i++){
801 ctlr->cbr[i].status = CbC|CbOK;
802 ctlr->cbr[i].command = CbS|CbNOP;
803 ctlr->cbr[i].link = PADDR(&ctlr->cbr[NEXT(i, ctlr->ncb)].status);
804 ctlr->cbr[i].next = &ctlr->cbr[NEXT(i, ctlr->ncb)];
806 ctlr->cbhead = ctlr->cbr;
807 ctlr->cbtail = ctlr->cbr;
810 memmove(ctlr->configdata, configdata, sizeof(configdata));
811 ctlr->threshold = 80;
814 iunlock(&ctlr->cblock);
818 miir(Ctlr* ctlr, int phyadd, int regadd)
822 lock(&ctlr->miilock);
823 csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16));
825 for(timo = 64; timo; timo--){
826 mcr = csr32r(ctlr, Mcr);
831 unlock(&ctlr->miilock);
840 miiw(Ctlr* ctlr, int phyadd, int regadd, int data)
844 lock(&ctlr->miilock);
845 csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF));
847 for(timo = 64; timo; timo--){
848 mcr = csr32r(ctlr, Mcr);
853 unlock(&ctlr->miilock);
862 hy93c46r(Ctlr* ctlr, int r)
864 int data, i, op, size;
867 * Hyundai HY93C46 or equivalent serial EEPROM.
868 * This sequence for reading a 16-bit register 'r'
869 * in the EEPROM is taken straight from Section
870 * 3.3.4.2 of the Intel 82557 User's Guide.
873 csr16w(ctlr, Ecr, EEcs);
875 for(i = 2; i >= 0; i--){
876 data = (((op>>i) & 0x01)<<2)|EEcs;
877 csr16w(ctlr, Ecr, data);
878 csr16w(ctlr, Ecr, data|EEsk);
880 csr16w(ctlr, Ecr, data);
885 * First time through must work out the EEPROM size.
887 if((size = ctlr->eepromsz) == 0)
890 for(size = size-1; size >= 0; size--){
891 data = (((r>>size) & 0x01)<<2)|EEcs;
892 csr16w(ctlr, Ecr, data);
893 csr16w(ctlr, Ecr, data|EEsk);
895 csr16w(ctlr, Ecr, data);
897 if(!(csr16r(ctlr, Ecr) & EEdo))
902 for(i = 15; i >= 0; i--){
903 csr16w(ctlr, Ecr, EEcs|EEsk);
905 if(csr16r(ctlr, Ecr) & EEdo)
907 csr16w(ctlr, Ecr, EEcs);
911 csr16w(ctlr, Ecr, 0);
913 if(ctlr->eepromsz == 0){
914 ctlr->eepromsz = 8-size;
915 ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
916 if(ctlr->eeprom == nil)
917 panic("i82557: can't allocate eeprom");
933 while(p = pcimatch(p, 0x8086, 0)){
937 case 0x1031: /* Intel 82562EM */
938 case 0x103B: /* Intel 82562EM */
939 case 0x103C: /* Intel 82562EM */
940 case 0x1050: /* Intel 82562EZ */
941 case 0x1039: /* Intel 82801BD PRO/100 VE */
942 case 0x103A: /* Intel 82562 PRO/100 VE */
943 case 0x103D: /* Intel 82562 PRO/100 VE */
944 case 0x1064: /* Intel 82562 PRO/100 VE */
945 case 0x2449: /* Intel 82562ET */
946 case 0x27DC: /* Intel 82801G PRO/100 VE */
949 case 0x1209: /* Intel 82559ER */
950 case 0x1229: /* Intel 8255[789] */
951 case 0x1030: /* Intel 82559 InBusiness 10/100 */
955 if(pcigetpms(p) > 0){
958 for(i = 0; i < 6; i++)
959 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
960 pcicfgw8(p, PciINTL, p->intl);
961 pcicfgw8(p, PciLTR, p->ltr);
962 pcicfgw8(p, PciCLS, p->cls);
963 pcicfgw16(p, PciPCR, p->pcr);
967 * bar[0] is the memory-mapped register address (4KB),
968 * bar[1] is the I/O port register address (32 bytes) and
969 * bar[2] is for the flash ROM (1MB).
971 port = p->mem[1].bar & ~0x01;
972 if(ioalloc(port, p->mem[1].size, 0, "i82557") < 0){
973 print("i82557: port %#ux in use\n", port);
977 ctlr = malloc(sizeof(Ctlr));
979 print("i82557: can't allocate memory\n");
988 ctlrtail->next = ctlr;
997 static char* mediatable[9] = {
999 "10BASE-2", /* BNC */
1000 "10BASE-5", /* AUI */
1014 for(i = 0; i < 32; i++){
1015 if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF)
1018 x = miir(ctlr, i, 3);
1020 //print("phy%d: oui %#ux reg1 %#ux\n", i, oui, miir(ctlr, i, 1));
1022 ctlr->eeprom[6] = i;
1024 ctlr->eeprom[6] |= 0x07<<8;
1025 else if(oui == 0x80017){
1027 ctlr->eeprom[6] |= 0x0A<<8;
1029 ctlr->eeprom[6] |= 0x04<<8;
1037 shutdown(Ether* ether)
1039 Ctlr *ctlr = ether->ctlr;
1041 print("ether82557 shutting down\n");
1042 csr32w(ctlr, Port, 0);
1044 csr8w(ctlr, Interrupt, InterruptM);
1051 int anar, anlpar, bmcr, bmsr, i, k, medium, phyaddr, x;
1060 * Any adapter matches if no ether->port is supplied,
1061 * otherwise the ports must match.
1063 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1066 if(ether->port == 0 || ether->port == ctlr->port){
1075 * Initialise the Ctlr structure.
1076 * Perform a software reset after which should ensure busmastering
1077 * is still enabled. The EtherExpress PRO/100B appears to leave
1078 * the PCI configuration alone (see the 'To do' list above) so punt
1080 * Load the RUB and CUB registers for linear addressing (0).
1083 ether->port = ctlr->port;
1084 ether->irq = ctlr->pcidev->intl;
1085 ether->tbdf = ctlr->pcidev->tbdf;
1087 ilock(&ctlr->rlock);
1088 csr32w(ctlr, Port, 0);
1090 csr8w(ctlr, Interrupt, InterruptM);
1091 iunlock(&ctlr->rlock);
1093 command(ctlr, LoadRUB, 0);
1094 command(ctlr, LoadCUB, 0);
1095 command(ctlr, LoadDCA, PADDR(ctlr->dump));
1098 * Initialise the receive frame, transmit ring and configuration areas.
1105 * Do a dummy read first to get the size
1106 * and allocate ctlr->eeprom.
1110 for(i = 0; i < (1<<ctlr->eepromsz); i++){
1111 x = hy93c46r(ctlr, i);
1112 ctlr->eeprom[i] = x;
1116 print("#l%d: EEPROM checksum - %#4.4ux\n", ether->ctlrno, sum);
1119 * Eeprom[6] indicates whether there is a PHY and whether
1120 * it's not 10Mb-only, in which case use the given PHY address
1121 * to set any PHY specific options and determine the speed.
1122 * Unfortunately, sometimes the EEPROM is blank except for
1123 * the ether address and checksum; in this case look at the
1124 * controller type and if it's am 82558 or 82559 it has an
1125 * embedded PHY so scan for that.
1126 * If no PHY, assume 82503 (serial) operation.
1128 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000))
1129 phyaddr = ctlr->eeprom[6] & 0x00FF;
1131 switch(ctlr->pcidev->rid){
1132 case 0x01: /* 82557 A-step */
1133 case 0x02: /* 82557 B-step */
1134 case 0x03: /* 82557 C-step */
1138 case 0x04: /* 82558 A-step */
1139 case 0x05: /* 82558 B-step */
1140 case 0x06: /* 82559 A-step */
1141 case 0x07: /* 82559 B-step */
1142 case 0x08: /* 82559 C-step */
1143 case 0x09: /* 82559ER A-step */
1144 phyaddr = scanphy(ctlr);
1149 * Resolve the highest common ability of the two
1150 * link partners. In descending order:
1151 * 0x0100 100BASE-TX Full Duplex
1154 * 0x0040 10BASE-T Full Duplex
1157 anar = miir(ctlr, phyaddr, 0x04);
1158 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1166 switch((ctlr->eeprom[6]>>8) & 0x001F){
1168 case 0x04: /* DP83840 */
1169 case 0x0A: /* DP83840A */
1171 * The DP83840[A] requires some tweaking for
1172 * reliable operation.
1173 * The manual says bit 10 should be unconditionally
1174 * set although it supposedly only affects full-duplex
1175 * operation (an & 0x0140).
1177 x = miir(ctlr, phyaddr, 0x17) & ~0x0520;
1179 for(i = 0; i < ether->nopt; i++){
1180 if(cistrcmp(ether->opt[i], "congestioncontrol"))
1185 miiw(ctlr, phyaddr, 0x17, x);
1188 * If the link partner can't autonegotiate, determine
1189 * the speed from elsewhere.
1192 miir(ctlr, phyaddr, 0x01);
1193 bmsr = miir(ctlr, phyaddr, 0x01);
1194 x = miir(ctlr, phyaddr, 0x19);
1195 if((bmsr & 0x0004) && !(x & 0x0040))
1200 case 0x07: /* Intel 82555 */
1202 * Auto-negotiation may fail if the other end is
1203 * a DP83840A and the cable is short.
1205 miir(ctlr, phyaddr, 0x01);
1206 bmsr = miir(ctlr, phyaddr, 0x01);
1207 if((miir(ctlr, phyaddr, 0) & 0x1000) && !(bmsr & 0x0020)){
1208 miiw(ctlr, phyaddr, 0x1A, 0x2010);
1209 x = miir(ctlr, phyaddr, 0);
1210 miiw(ctlr, phyaddr, 0, 0x0200|x);
1211 for(i = 0; i < 3000; i++){
1213 if(miir(ctlr, phyaddr, 0x01) & 0x0020)
1216 miiw(ctlr, phyaddr, 0x1A, 0x2000);
1218 anar = miir(ctlr, phyaddr, 0x04);
1219 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1231 * Force speed and duplex if no auto-negotiation.
1235 for(i = 0; i < ether->nopt; i++){
1236 for(k = 0; k < nelem(mediatable); k++){
1237 if(cistrcmp(mediatable[k], ether->opt[i]))
1247 case 0x00: /* 10BASE-T */
1248 case 0x01: /* 10BASE-2 */
1249 case 0x02: /* 10BASE-5 */
1250 bmcr &= ~(0x2000|0x0100);
1251 ctlr->configdata[19] &= ~0x40;
1254 case 0x03: /* 100BASE-TX */
1255 case 0x06: /* 100BASE-T4 */
1256 case 0x07: /* 100BASE-FX */
1257 ctlr->configdata[19] &= ~0x40;
1261 case 0x04: /* 10BASE-TFD */
1262 bmcr = (bmcr & ~0x2000)|0x0100;
1263 ctlr->configdata[19] |= 0x40;
1266 case 0x05: /* 100BASE-TXFD */
1267 case 0x08: /* 100BASE-FXFD */
1268 bmcr |= 0x2000|0x0100;
1269 ctlr->configdata[19] |= 0x40;
1274 miiw(ctlr, phyaddr, 0x00, bmcr);
1280 ctlr->configdata[8] = 1;
1281 ctlr->configdata[15] &= ~0x80;
1284 ctlr->configdata[8] = 0;
1285 ctlr->configdata[15] |= 0x80;
1289 * Workaround for some broken HUB chips when connected at 10Mb/s
1291 * This is a band-aid, but as there's no dynamic auto-negotiation
1292 * code at the moment, only deactivate the workaround code in txstart
1293 * if the link is 100Mb/s.
1295 if(ether->mbps != 10)
1299 * Load the chip configuration and start it off.
1302 ether->oq = qopen(256*1024, Qmsg, 0, 0);
1303 configure(ether, 0);
1304 command(ctlr, CUstart, PADDR(&ctlr->cbr->status));
1307 * Check if the adapter's station address is to be overridden.
1308 * If not, read it from the EEPROM and set in ether->ea prior to loading
1309 * the station address with the Individual Address Setup command.
1311 memset(ea, 0, Eaddrlen);
1312 if(memcmp(ea, ether->ea, Eaddrlen) == 0){
1313 for(i = 0; i < Eaddrlen/2; i++){
1314 x = ctlr->eeprom[i];
1316 ether->ea[2*i+1] = x>>8;
1320 ilock(&ctlr->cblock);
1321 ctlr->action = CbIAS;
1323 iunlock(&ctlr->cblock);
1326 * Linkage to the generic ethernet driver.
1328 ether->attach = attach;
1329 ether->transmit = transmit;
1330 ether->interrupt = interrupt;
1331 ether->ifstat = ifstat;
1332 ether->shutdown = shutdown;
1334 ether->promiscuous = promiscuous;
1335 ether->multicast = multicast;
1342 ether82557link(void)
1344 addethercard("i82557", reset);