sys/src/9/pc/ether82557.c

   1 /*
   2  * Intel 82557 Fast Ethernet PCI Bus LAN Controller
   3  * as found on the Intel EtherExpress PRO/100B. This chip is full
   4  * of smarts, unfortunately they're not all in the right place.
   5  * To do:
   6  *      the PCI scanning code could be made common to other adapters;
   7  *      auto-negotiation, full-duplex;
   8  *      optionally use memory-mapped registers;
   9  *      detach for PCI reset problems (also towards loadable drivers).
  10  */
  11 #include "u.h"
  12 #include "../port/lib.h"
  13 #include "mem.h"
  14 #include "dat.h"
  15 #include "fns.h"
  16 #include "io.h"
  17 #include "../port/error.h"
  18 #include "../port/netif.h"
  19
  20 #include "etherif.h"
  21
  22 enum {
  23         Nrfd            = 64,           /* receive frame area */
  24         Ncb             = 64,           /* maximum control blocks queued */
  25
  26         NullPointer     = 0xFFFFFFFF,   /* 82557 NULL pointer */
  27 };
  28
  29 enum {                                  /* CSR */
  30         Status          = 0x00,         /* byte or word (word includes Ack) */
  31         Ack             = 0x01,         /* byte */
  32         CommandR        = 0x02,         /* byte or word (word includes Interrupt) */
  33         Interrupt       = 0x03,         /* byte */
  34         General         = 0x04,         /* dword */
  35         Port            = 0x08,         /* dword */
  36         Fcr             = 0x0C,         /* Flash control register */
  37         Ecr             = 0x0E,         /* EEPROM control register */
  38         Mcr             = 0x10,         /* MDI control register */
  39         Gstatus         = 0x1D,         /* General status register */
  40 };
  41
  42 enum {                                  /* Status */
  43         RUidle          = 0x0000,
  44         RUsuspended     = 0x0004,
  45         RUnoresources   = 0x0008,
  46         RUready         = 0x0010,
  47         RUrbd           = 0x0020,       /* bit */
  48         RUstatus        = 0x003F,       /* mask */
  49
  50         CUidle          = 0x0000,
  51         CUsuspended     = 0x0040,
  52         CUactive        = 0x0080,
  53         CUstatus        = 0x00C0,       /* mask */
  54
  55         StatSWI         = 0x0400,       /* SoftWare generated Interrupt */
  56         StatMDI         = 0x0800,       /* MDI r/w done */
  57         StatRNR         = 0x1000,       /* Receive unit Not Ready */
  58         StatCNA         = 0x2000,       /* Command unit Not Active (Active->Idle) */
  59         StatFR          = 0x4000,       /* Finished Receiving */
  60         StatCX          = 0x8000,       /* Command eXecuted */
  61         StatTNO         = 0x8000,       /* Transmit NOT OK */
  62 };
  63
  64 enum {                                  /* Command (byte) */
  65         CUnop           = 0x00,
  66         CUstart         = 0x10,
  67         CUresume        = 0x20,
  68         LoadDCA         = 0x40,         /* Load Dump Counters Address */
  69         DumpSC          = 0x50,         /* Dump Statistical Counters */
  70         LoadCUB         = 0x60,         /* Load CU Base */
  71         ResetSA         = 0x70,         /* Dump and Reset Statistical Counters */
  72
  73         RUstart         = 0x01,
  74         RUresume        = 0x02,
  75         RUabort         = 0x04,
  76         LoadHDS         = 0x05,         /* Load Header Data Size */
  77         LoadRUB         = 0x06,         /* Load RU Base */
  78         RBDresume       = 0x07,         /* Resume frame reception */
  79 };
  80
  81 enum {                                  /* Interrupt (byte) */
  82         InterruptM      = 0x01,         /* interrupt Mask */
  83         InterruptSI     = 0x02,         /* Software generated Interrupt */
  84 };
  85
  86 enum {                                  /* Ecr */
  87         EEsk            = 0x01,         /* serial clock */
  88         EEcs            = 0x02,         /* chip select */
  89         EEdi            = 0x04,         /* serial data in */
  90         EEdo            = 0x08,         /* serial data out */
  91
  92         EEstart         = 0x04,         /* start bit */
  93         EEread          = 0x02,         /* read opcode */
  94 };
  95
  96 enum {                                  /* Mcr */
  97         MDIread         = 0x08000000,   /* read opcode */
  98         MDIwrite        = 0x04000000,   /* write opcode */
  99         MDIready        = 0x10000000,   /* ready bit */
 100         MDIie           = 0x20000000,   /* interrupt enable */
 101 };
 102
 103 typedef struct Rfd {
 104         int     field;
 105         ulong   link;
 106         ulong   rbd;
 107         ushort  count;
 108         ushort  size;
 109
 110         uchar   data[1700];
 111 } Rfd;
 112
 113 enum {                                  /* field */
 114         RfdCollision    = 0x00000001,
 115         RfdIA           = 0x00000002,   /* IA match */
 116         RfdRxerr        = 0x00000010,   /* PHY character error */
 117         RfdType         = 0x00000020,   /* Type frame */
 118         RfdRunt         = 0x00000080,
 119         RfdOverrun      = 0x00000100,
 120         RfdBuffer       = 0x00000200,
 121         RfdAlignment    = 0x00000400,
 122         RfdCRC          = 0x00000800,
 123
 124         RfdOK           = 0x00002000,   /* frame received OK */
 125         RfdC            = 0x00008000,   /* reception Complete */
 126         RfdSF           = 0x00080000,   /* Simplified or Flexible (1) Rfd */
 127         RfdH            = 0x00100000,   /* Header RFD */
 128
 129         RfdI            = 0x20000000,   /* Interrupt after completion */
 130         RfdS            = 0x40000000,   /* Suspend after completion */
 131         RfdEL           = 0x80000000,   /* End of List */
 132 };
 133
 134 enum {                                  /* count */
 135         RfdF            = 0x4000,
 136         RfdEOF          = 0x8000,
 137 };
 138
 139 typedef struct Cb Cb;
 140 typedef struct Cb {
 141         ushort  status;
 142         ushort  command;
 143         ulong   link;
 144         union {
 145                 uchar   data[24];       /* CbIAS + CbConfigure */
 146                 struct {
 147                         ulong   tbd;
 148                         ushort  count;
 149                         uchar   threshold;
 150                         uchar   number;
 151
 152                         ulong   tba;
 153                         ushort  tbasz;
 154                         ushort  pad;
 155                 };
 156         };
 157
 158         Block*  bp;
 159         Cb*     next;
 160 } Cb;
 161
 162 enum {                                  /* action command */
 163         CbU             = 0x1000,       /* transmit underrun */
 164         CbOK            = 0x2000,       /* DMA completed OK */
 165         CbC             = 0x8000,       /* execution Complete */
 166
 167         CbNOP           = 0x0000,
 168         CbIAS           = 0x0001,       /* Individual Address Setup */
 169         CbConfigure     = 0x0002,
 170         CbMAS           = 0x0003,       /* Multicast Address Setup */
 171         CbTransmit      = 0x0004,
 172         CbDump          = 0x0006,
 173         CbDiagnose      = 0x0007,
 174         CbCommand       = 0x0007,       /* mask */
 175
 176         CbSF            = 0x0008,       /* Flexible-mode CbTransmit */
 177
 178         CbI             = 0x2000,       /* Interrupt after completion */
 179         CbS             = 0x4000,       /* Suspend after completion */
 180         CbEL            = 0x8000,       /* End of List */
 181 };
 182
 183 enum {                                  /* CbTransmit count */
 184         CbEOF           = 0x8000,
 185 };
 186
 187 typedef struct Ctlr Ctlr;
 188 typedef struct Ctlr {
 189         Lock    slock;                  /* attach */
 190         int     state;
 191
 192         int     port;
 193         Pcidev* pcidev;
 194         Ctlr*   next;
 195         int     active;
 196
 197         int     eepromsz;               /* address size in bits */
 198         ushort* eeprom;
 199
 200         Lock    miilock;
 201
 202         int     tick;
 203
 204         Lock    rlock;                  /* registers */
 205         int     command;                /* last command issued */
 206
 207         Block*  rfdhead;                /* receive side */
 208         Block*  rfdtail;
 209         int     nrfd;
 210
 211         Lock    cblock;                 /* transmit side */
 212         int     action;
 213         int     nop;
 214         uchar   configdata[24];
 215         int     threshold;
 216         int     ncb;
 217         Cb*     cbr;
 218         Cb*     cbhead;
 219         Cb*     cbtail;
 220         int     cbq;
 221         int     cbqmax;
 222         int     cbqmaxhw;
 223
 224         Lock    dlock;                  /* dump statistical counters */
 225         ulong   dump[17];
 226 } Ctlr;
 227
 228 static Ctlr* ctlrhead;
 229 static Ctlr* ctlrtail;
 230
 231 static uchar configdata[24] = {
 232         0x16,                           /* byte count */
 233         0x08,                           /* Rx/Tx FIFO limit */
 234         0x00,                           /* adaptive IFS */
 235         0x00,
 236         0x00,                           /* Rx DMA maximum byte count */
 237 //      0x80,                           /* Tx DMA maximum byte count */
 238         0x00,                           /* Tx DMA maximum byte count */
 239         0x32,                           /* !late SCB, CNA interrupts */
 240         0x03,                           /* discard short Rx frames */
 241         0x00,                           /* 503/MII */
 242
 243         0x00,
 244         0x2E,                           /* normal operation, NSAI */
 245         0x00,                           /* linear priority */
 246         0x60,                           /* inter-frame spacing */
 247         0x00,
 248         0xF2,
 249         0xC8,                           /* 503, promiscuous mode off */
 250         0x00,
 251         0x40,
 252         0xF3,                           /* transmit padding enable */
 253         0x80,                           /* full duplex pin enable */
 254         0x3F,                           /* no Multi IA */
 255         0x05,                           /* no Multi Cast ALL */
 256 };
 257
 258 #define csr8r(c, r)     (inb((c)->port+(r)))
 259 #define csr16r(c, r)    (ins((c)->port+(r)))
 260 #define csr32r(c, r)    (inl((c)->port+(r)))
 261 #define csr8w(c, r, b)  (outb((c)->port+(r), (int)(b)))
 262 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
 263 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
 264
 265 static void
 266 command(Ctlr* ctlr, int c, int v)
 267 {
 268         int timeo;
 269
 270         ilock(&ctlr->rlock);
 271
 272         /*
 273          * Only back-to-back CUresume can be done
 274          * without waiting for any previous command to complete.
 275          * This should be the common case.
 276          * Unfortunately there's a chip errata where back-to-back
 277          * CUresumes can be lost, the fix is to always wait.
 278         if(c == CUresume && ctlr->command == CUresume){
 279                 csr8w(ctlr, CommandR, c);
 280                 iunlock(&ctlr->rlock);
 281                 return;
 282         }
 283          */
 284
 285         for(timeo = 0; timeo < 100; timeo++){
 286                 if(!csr8r(ctlr, CommandR))
 287                         break;
 288                 microdelay(1);
 289         }
 290         if(timeo >= 100){
 291                 ctlr->command = -1;
 292                 iunlock(&ctlr->rlock);
 293                 iprint("i82557: command %#ux %#ux timeout\n", c, v);
 294                 return;
 295         }
 296
 297         switch(c){
 298
 299         case CUstart:
 300         case LoadDCA:
 301         case LoadCUB:
 302         case RUstart:
 303         case LoadHDS:
 304         case LoadRUB:
 305                 csr32w(ctlr, General, v);
 306                 break;
 307
 308         /*
 309         case CUnop:
 310         case CUresume:
 311         case DumpSC:
 312         case ResetSA:
 313         case RUresume:
 314         case RUabort:
 315          */
 316         default:
 317                 break;
 318         }
 319         csr8w(ctlr, CommandR, c);
 320         ctlr->command = c;
 321
 322         iunlock(&ctlr->rlock);
 323 }
 324
 325 static Block*
 326 rfdalloc(ulong link)
 327 {
 328         Block *bp;
 329         Rfd *rfd;
 330
 331         if(bp = iallocb(sizeof(Rfd))){
 332                 rfd = (Rfd*)bp->rp;
 333                 rfd->field = 0;
 334                 rfd->link = link;
 335                 rfd->rbd = NullPointer;
 336                 rfd->count = 0;
 337                 rfd->size = sizeof(Etherpkt);
 338         }
 339
 340         return bp;
 341 }
 342
 343 static void
 344 watchdog(void* arg)
 345 {
 346         Ether *ether;
 347         Ctlr *ctlr;
 348         static void txstart(Ether*);
 349
 350         ether = arg;
 351         for(;;){
 352                 tsleep(&up->sleep, return0, 0, 4000);
 353
 354                 /*
 355                  * Hmmm. This doesn't seem right. Currently
 356                  * the device can't be disabled but it may be in
 357                  * the future.
 358                  */
 359                 ctlr = ether->ctlr;
 360                 if(ctlr == nil || ctlr->state == 0){
 361                         print("%s: exiting\n", up->text);
 362                         pexit("disabled", 0);
 363                 }
 364
 365                 ilock(&ctlr->cblock);
 366                 if(ctlr->tick++){
 367                         ctlr->action = CbMAS;
 368                         txstart(ether);
 369                 }
 370                 iunlock(&ctlr->cblock);
 371         }
 372 }
 373
 374 static void
 375 attach(Ether* ether)
 376 {
 377         Ctlr *ctlr;
 378         char name[KNAMELEN];
 379
 380         ctlr = ether->ctlr;
 381         lock(&ctlr->slock);
 382         if(ctlr->state == 0){
 383                 ilock(&ctlr->rlock);
 384                 csr8w(ctlr, Interrupt, 0);
 385                 iunlock(&ctlr->rlock);
 386                 command(ctlr, RUstart, PADDR(ctlr->rfdhead->rp));
 387                 ctlr->state = 1;
 388
 389                 /*
 390                  * Start the watchdog timer for the receive lockup errata
 391                  * unless the EEPROM compatibility word indicates it may be
 392                  * omitted.
 393                  */
 394                 if((ctlr->eeprom[0x03] & 0x0003) != 0x0003){
 395                         snprint(name, KNAMELEN, "#l%dwatchdog", ether->ctlrno);
 396                         kproc(name, watchdog, ether);
 397                 }
 398         }
 399         unlock(&ctlr->slock);
 400 }
 401
 402 static long
 403 ifstat(Ether* ether, void* a, long n, ulong offset)
 404 {
 405         char *p;
 406         int i, len, phyaddr;
 407         Ctlr *ctlr;
 408         ulong dump[17];
 409
 410         ctlr = ether->ctlr;
 411         lock(&ctlr->dlock);
 412         if(waserror()){
 413                 unlock(&ctlr->dlock);
 414                 nexterror();
 415         }
 416
 417         /*
 418          * Start the command then
 419          * wait for completion status,
 420          * should be 0xA005.
 421          */
 422         ctlr->dump[16] = 0;
 423         command(ctlr, DumpSC, 0);
 424         for(i = 0; i < 1000 && ctlr->dump[16] == 0; i++)
 425                 microdelay(100);
 426         if(i == 1000)
 427                 error("command timeout");
 428
 429         memmove(dump, ctlr->dump, sizeof(dump));
 430
 431         ether->oerrs = dump[1]+dump[2]+dump[3];
 432         ether->crcs = dump[10];
 433         ether->frames = dump[11];
 434         ether->buffs = dump[12]+dump[15];
 435         ether->overflows = dump[13];
 436
 437         poperror();
 438         unlock(&ctlr->dlock);
 439
 440         if(n == 0)
 441                 return 0;
 442
 443         p = smalloc(READSTR);
 444         len = snprint(p, READSTR, "transmit good frames: %lud\n", dump[0]);
 445         len += snprint(p+len, READSTR-len, "transmit maximum collisions errors: %lud\n", dump[1]);
 446         len += snprint(p+len, READSTR-len, "transmit late collisions errors: %lud\n", dump[2]);
 447         len += snprint(p+len, READSTR-len, "transmit underrun errors: %lud\n", dump[3]);
 448         len += snprint(p+len, READSTR-len, "transmit lost carrier sense: %lud\n", dump[4]);
 449         len += snprint(p+len, READSTR-len, "transmit deferred: %lud\n", dump[5]);
 450         len += snprint(p+len, READSTR-len, "transmit single collisions: %lud\n", dump[6]);
 451         len += snprint(p+len, READSTR-len, "transmit multiple collisions: %lud\n", dump[7]);
 452         len += snprint(p+len, READSTR-len, "transmit total collisions: %lud\n", dump[8]);
 453         len += snprint(p+len, READSTR-len, "receive good frames: %lud\n", dump[9]);
 454         len += snprint(p+len, READSTR-len, "receive CRC errors: %lud\n", dump[10]);
 455         len += snprint(p+len, READSTR-len, "receive alignment errors: %lud\n", dump[11]);
 456         len += snprint(p+len, READSTR-len, "receive resource errors: %lud\n", dump[12]);
 457         len += snprint(p+len, READSTR-len, "receive overrun errors: %lud\n", dump[13]);
 458         len += snprint(p+len, READSTR-len, "receive collision detect errors: %lud\n", dump[14]);
 459         len += snprint(p+len, READSTR-len, "receive short frame errors: %lud\n", dump[15]);
 460         len += snprint(p+len, READSTR-len, "nop: %d\n", ctlr->nop);
 461         if(ctlr->cbqmax > ctlr->cbqmaxhw)
 462                 ctlr->cbqmaxhw = ctlr->cbqmax;
 463         len += snprint(p+len, READSTR-len, "cbqmax: %d\n", ctlr->cbqmax);
 464         ctlr->cbqmax = 0;
 465         len += snprint(p+len, READSTR-len, "threshold: %d\n", ctlr->threshold);
 466
 467         len += snprint(p+len, READSTR-len, "eeprom:");
 468         for(i = 0; i < (1<<ctlr->eepromsz); i++){
 469                 if(i && ((i & 0x07) == 0))
 470                         len += snprint(p+len, READSTR-len, "\n       ");
 471                 len += snprint(p+len, READSTR-len, " %4.4ux", ctlr->eeprom[i]);
 472         }
 473
 474         if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)){
 475                 phyaddr = ctlr->eeprom[6] & 0x00FF;
 476                 len += snprint(p+len, READSTR-len, "\nphy %2d:", phyaddr);
 477                 for(i = 0; i < 6; i++){
 478                         static int miir(Ctlr*, int, int);
 479
 480                         len += snprint(p+len, READSTR-len, " %4.4ux",
 481                                 miir(ctlr, phyaddr, i));
 482                 }
 483         }
 484
 485         snprint(p+len, READSTR-len, "\n");
 486         n = readstr(offset, a, n, p);
 487         free(p);
 488
 489         return n;
 490 }
 491
 492 static void
 493 txstart(Ether* ether)
 494 {
 495         Ctlr *ctlr;
 496         Block *bp;
 497         Cb *cb;
 498
 499         ctlr = ether->ctlr;
 500         while(ctlr->cbq < (ctlr->ncb-1)){
 501                 cb = ctlr->cbhead->next;
 502                 if(ctlr->action == 0){
 503                         bp = qget(ether->oq);
 504                         if(bp == nil)
 505                                 break;
 506
 507                         cb->command = CbS|CbSF|CbTransmit;
 508                         cb->tbd = PADDR(&cb->tba);
 509                         cb->count = 0;
 510                         cb->threshold = ctlr->threshold;
 511                         cb->number = 1;
 512                         cb->tba = PADDR(bp->rp);
 513                         cb->bp = bp;
 514                         cb->tbasz = BLEN(bp);
 515                 }
 516                 else if(ctlr->action == CbConfigure){
 517                         cb->command = CbS|CbConfigure;
 518                         memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata));
 519                         ctlr->action = 0;
 520                 }
 521                 else if(ctlr->action == CbIAS){
 522                         cb->command = CbS|CbIAS;
 523                         memmove(cb->data, ether->ea, Eaddrlen);
 524                         ctlr->action = 0;
 525                 }
 526                 else if(ctlr->action == CbMAS){
 527                         cb->command = CbS|CbMAS;
 528                         memset(cb->data, 0, sizeof(cb->data));
 529                         ctlr->action = 0;
 530                 }
 531                 else{
 532                         print("#l%d: action %#ux\n", ether->ctlrno, ctlr->action);
 533                         ctlr->action = 0;
 534                         break;
 535                 }
 536                 cb->status = 0;
 537
 538                 coherence();
 539                 ctlr->cbhead->command &= ~CbS;
 540                 ctlr->cbhead = cb;
 541                 ctlr->cbq++;
 542         }
 543
 544         /*
 545          * Workaround for some broken HUB chips
 546          * when connected at 10Mb/s half-duplex.
 547          */
 548         if(ctlr->nop){
 549                 command(ctlr, CUnop, 0);
 550                 microdelay(1);
 551         }
 552         command(ctlr, CUresume, 0);
 553
 554         if(ctlr->cbq > ctlr->cbqmax)
 555                 ctlr->cbqmax = ctlr->cbq;
 556 }
 557
 558 static void
 559 configure(Ether* ether, int promiscuous)
 560 {
 561         Ctlr *ctlr;
 562
 563         ctlr = ether->ctlr;
 564         ilock(&ctlr->cblock);
 565         if(promiscuous){
 566                 ctlr->configdata[6] |= 0x80;            /* Save Bad Frames */
 567                 //ctlr->configdata[6] &= ~0x40;         /* !Discard Overrun Rx Frames */
 568                 ctlr->configdata[7] &= ~0x01;           /* !Discard Short Rx Frames */
 569                 ctlr->configdata[15] |= 0x01;           /* Promiscuous mode */
 570                 ctlr->configdata[18] &= ~0x01;          /* (!Padding enable?), !stripping enable */
 571                 ctlr->configdata[21] |= 0x08;           /* Multi Cast ALL */
 572         }
 573         else{
 574                 ctlr->configdata[6] &= ~0x80;
 575                 //ctlr->configdata[6] |= 0x40;
 576                 ctlr->configdata[7] |= 0x01;
 577                 ctlr->configdata[15] &= ~0x01;
 578                 ctlr->configdata[18] |= 0x01;           /* 0x03? */
 579                 ctlr->configdata[21] &= ~0x08;
 580         }
 581         ctlr->action = CbConfigure;
 582         txstart(ether);
 583         iunlock(&ctlr->cblock);
 584 }
 585
 586 static void
 587 promiscuous(void* arg, int on)
 588 {
 589         configure(arg, on);
 590 }
 591
 592 static void
 593 multicast(void* ether, uchar *addr, int add)
 594 {
 595         USED(addr);
 596         /*
 597          * TODO: if (add) add addr to list of mcast addrs in controller
 598          *      else remove addr from list of mcast addrs in controller
 599          * enable multicast input (see CbMAS) instead of promiscuous mode.
 600          */
 601         if (add)
 602                 configure(ether, 1);
 603 }
 604
 605 static void
 606 transmit(Ether* ether)
 607 {
 608         Ctlr *ctlr;
 609
 610         ctlr = ether->ctlr;
 611         ilock(&ctlr->cblock);
 612         txstart(ether);
 613         iunlock(&ctlr->cblock);
 614 }
 615
 616 static void
 617 receive(Ether* ether)
 618 {
 619         Rfd *rfd;
 620         Ctlr *ctlr;
 621         int count;
 622         Block *bp, *pbp, *xbp;
 623
 624         ctlr = ether->ctlr;
 625         bp = ctlr->rfdhead;
 626         for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){
 627                 /*
 628                  * If it's an OK receive frame
 629                  * 1) save the count
 630                  * 2) if it's small, try to allocate a block and copy
 631                  *    the data, then adjust the necessary fields for reuse;
 632                  * 3) if it's big, try to allocate a new Rfd and if
 633                  *    successful
 634                  *      adjust the received buffer pointers for the
 635                  *        actual data received;
 636                  *      initialise the replacement buffer to point to
 637                  *        the next in the ring;
 638                  *      initialise bp to point to the replacement;
 639                  * 4) if there's a good packet, pass it on for disposal.
 640                  */
 641                 if(rfd->field & RfdOK){
 642                         pbp = nil;
 643                         count = rfd->count & 0x3FFF;
 644                         if((count < ETHERMAXTU/4) && (pbp = iallocb(count))){
 645                                 memmove(pbp->rp, bp->rp+offsetof(Rfd, data[0]), count);
 646                                 pbp->wp = pbp->rp + count;
 647
 648                                 rfd->count = 0;
 649                                 rfd->field = 0;
 650                         }
 651                         else if(xbp = rfdalloc(rfd->link)){
 652                                 bp->rp += offsetof(Rfd, data[0]);
 653                                 bp->wp = bp->rp + count;
 654
 655                                 xbp->next = bp->next;
 656                                 bp->next = 0;
 657
 658                                 pbp = bp;
 659                                 bp = xbp;
 660                         }
 661                         if(pbp != nil)
 662                                 etheriq(ether, pbp, 1);
 663                 }
 664                 else{
 665                         rfd->count = 0;
 666                         rfd->field = 0;
 667                 }
 668
 669                 /*
 670                  * The ring tail pointer follows the head with with one
 671                  * unused buffer in between to defeat hardware prefetch;
 672                  * once the tail pointer has been bumped on to the next
 673                  * and the new tail has the Suspend bit set, it can be
 674                  * removed from the old tail buffer.
 675                  * As a replacement for the current head buffer may have
 676                  * been allocated above, ensure that the new tail points
 677                  * to it (next and link).
 678                  */
 679                 rfd = (Rfd*)ctlr->rfdtail->rp;
 680                 ctlr->rfdtail = ctlr->rfdtail->next;
 681                 ctlr->rfdtail->next = bp;
 682                 ((Rfd*)ctlr->rfdtail->rp)->link = PADDR(bp->rp);
 683                 ((Rfd*)ctlr->rfdtail->rp)->field |= RfdS;
 684                 coherence();
 685                 rfd->field &= ~RfdS;
 686
 687                 /*
 688                  * Finally done with the current (possibly replaced)
 689                  * head, move on to the next and maintain the sentinel
 690                  * between tail and head.
 691                  */
 692                 ctlr->rfdhead = bp->next;
 693                 bp = ctlr->rfdhead;
 694         }
 695 }
 696
 697 static void
 698 interrupt(Ureg*, void* arg)
 699 {
 700         Cb* cb;
 701         Ctlr *ctlr;
 702         Ether *ether;
 703         int status;
 704
 705         ether = arg;
 706         ctlr = ether->ctlr;
 707
 708         for(;;){
 709                 ilock(&ctlr->rlock);
 710                 status = csr16r(ctlr, Status);
 711                 csr8w(ctlr, Ack, (status>>8) & 0xFF);
 712                 iunlock(&ctlr->rlock);
 713
 714                 if(!(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI)))
 715                         break;
 716
 717                 /*
 718                  * If the watchdog timer for the receiver lockup errata is running,
 719                  * let it know the receiver is active.
 720                  */
 721                 if(status & (StatFR|StatRNR)){
 722                         ilock(&ctlr->cblock);
 723                         ctlr->tick = 0;
 724                         iunlock(&ctlr->cblock);
 725                 }
 726
 727                 if(status & StatFR){
 728                         receive(ether);
 729                         status &= ~StatFR;
 730                 }
 731
 732                 if(status & StatRNR){
 733                         command(ctlr, RUresume, 0);
 734                         status &= ~StatRNR;
 735                 }
 736
 737                 if(status & StatCNA){
 738                         ilock(&ctlr->cblock);
 739
 740                         cb = ctlr->cbtail;
 741                         while(ctlr->cbq){
 742                                 if(!(cb->status & CbC))
 743                                         break;
 744                                 if(cb->bp){
 745                                         freeb(cb->bp);
 746                                         cb->bp = nil;
 747                                 }
 748                                 if((cb->status & CbU) && ctlr->threshold < 0xE0)
 749                                         ctlr->threshold++;
 750
 751                                 ctlr->cbq--;
 752                                 cb = cb->next;
 753                         }
 754                         ctlr->cbtail = cb;
 755
 756                         txstart(ether);
 757                         iunlock(&ctlr->cblock);
 758
 759                         status &= ~StatCNA;
 760                 }
 761
 762                 if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))
 763                         panic("#l%d: status %#ux", ether->ctlrno, status);
 764         }
 765 }
 766
 767 static void
 768 ctlrinit(Ctlr* ctlr)
 769 {
 770         int i;
 771         Block *bp;
 772         Rfd *rfd;
 773         ulong link;
 774
 775         /*
 776          * Create the Receive Frame Area (RFA) as a ring of allocated
 777          * buffers.
 778          * A sentinel buffer is maintained between the last buffer in
 779          * the ring (marked with RfdS) and the head buffer to defeat the
 780          * hardware prefetch of the next RFD and allow dynamic buffer
 781          * allocation.
 782          */
 783         link = NullPointer;
 784         for(i = 0; i < Nrfd; i++){
 785                 bp = rfdalloc(link);
 786                 if(ctlr->rfdhead == nil)
 787                         ctlr->rfdtail = bp;
 788                 bp->next = ctlr->rfdhead;
 789                 ctlr->rfdhead = bp;
 790                 link = PADDR(bp->rp);
 791         }
 792         ctlr->rfdtail->next = ctlr->rfdhead;
 793         rfd = (Rfd*)ctlr->rfdtail->rp;
 794         rfd->link = PADDR(ctlr->rfdhead->rp);
 795         rfd->field |= RfdS;
 796         ctlr->rfdhead = ctlr->rfdhead->next;
 797
 798         /*
 799          * Create a ring of control blocks for the
 800          * transmit side.
 801          */
 802         ilock(&ctlr->cblock);
 803         ctlr->cbr = malloc(ctlr->ncb*sizeof(Cb));
 804         if(ctlr->cbr == nil)
 805                 panic("i82557: can't allocate cbr");
 806         for(i = 0; i < ctlr->ncb; i++){
 807                 ctlr->cbr[i].status = CbC|CbOK;
 808                 ctlr->cbr[i].command = CbS|CbNOP;
 809                 ctlr->cbr[i].link = PADDR(&ctlr->cbr[NEXT(i, ctlr->ncb)].status);
 810                 ctlr->cbr[i].next = &ctlr->cbr[NEXT(i, ctlr->ncb)];
 811         }
 812         ctlr->cbhead = ctlr->cbr;
 813         ctlr->cbtail = ctlr->cbr;
 814         ctlr->cbq = 0;
 815
 816         memmove(ctlr->configdata, configdata, sizeof(configdata));
 817         ctlr->threshold = 80;
 818         ctlr->tick = 0;
 819
 820         iunlock(&ctlr->cblock);
 821 }
 822
 823 static int
 824 miir(Ctlr* ctlr, int phyadd, int regadd)
 825 {
 826         int mcr, timo;
 827
 828         lock(&ctlr->miilock);
 829         csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16));
 830         mcr = 0;
 831         for(timo = 64; timo; timo--){
 832                 mcr = csr32r(ctlr, Mcr);
 833                 if(mcr & MDIready)
 834                         break;
 835                 microdelay(1);
 836         }
 837         unlock(&ctlr->miilock);
 838
 839         if(mcr & MDIready)
 840                 return mcr & 0xFFFF;
 841
 842         return -1;
 843 }
 844
 845 static int
 846 miiw(Ctlr* ctlr, int phyadd, int regadd, int data)
 847 {
 848         int mcr, timo;
 849
 850         lock(&ctlr->miilock);
 851         csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF));
 852         mcr = 0;
 853         for(timo = 64; timo; timo--){
 854                 mcr = csr32r(ctlr, Mcr);
 855                 if(mcr & MDIready)
 856                         break;
 857                 microdelay(1);
 858         }
 859         unlock(&ctlr->miilock);
 860
 861         if(mcr & MDIready)
 862                 return 0;
 863
 864         return -1;
 865 }
 866
 867 static int
 868 hy93c46r(Ctlr* ctlr, int r)
 869 {
 870         int data, i, op, size;
 871
 872         /*
 873          * Hyundai HY93C46 or equivalent serial EEPROM.
 874          * This sequence for reading a 16-bit register 'r'
 875          * in the EEPROM is taken straight from Section
 876          * 3.3.4.2 of the Intel 82557 User's Guide.
 877          */
 878 reread:
 879         csr16w(ctlr, Ecr, EEcs);
 880         op = EEstart|EEread;
 881         for(i = 2; i >= 0; i--){
 882                 data = (((op>>i) & 0x01)<<2)|EEcs;
 883                 csr16w(ctlr, Ecr, data);
 884                 csr16w(ctlr, Ecr, data|EEsk);
 885                 microdelay(1);
 886                 csr16w(ctlr, Ecr, data);
 887                 microdelay(1);
 888         }
 889
 890         /*
 891          * First time through must work out the EEPROM size.
 892          */
 893         if((size = ctlr->eepromsz) == 0)
 894                 size = 8;
 895
 896         for(size = size-1; size >= 0; size--){
 897                 data = (((r>>size) & 0x01)<<2)|EEcs;
 898                 csr16w(ctlr, Ecr, data);
 899                 csr16w(ctlr, Ecr, data|EEsk);
 900                 delay(1);
 901                 csr16w(ctlr, Ecr, data);
 902                 microdelay(1);
 903                 if(!(csr16r(ctlr, Ecr) & EEdo))
 904                         break;
 905         }
 906
 907         data = 0;
 908         for(i = 15; i >= 0; i--){
 909                 csr16w(ctlr, Ecr, EEcs|EEsk);
 910                 microdelay(1);
 911                 if(csr16r(ctlr, Ecr) & EEdo)
 912                         data |= (1<<i);
 913                 csr16w(ctlr, Ecr, EEcs);
 914                 microdelay(1);
 915         }
 916
 917         csr16w(ctlr, Ecr, 0);
 918
 919         if(ctlr->eepromsz == 0){
 920                 ctlr->eepromsz = 8-size;
 921                 ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
 922                 if(ctlr->eeprom == nil)
 923                         panic("i82557: can't allocate eeprom");
 924                 goto reread;
 925         }
 926
 927         return data;
 928 }
 929
 930 static void
 931 i82557pci(void)
 932 {
 933         Pcidev *p;
 934         Ctlr *ctlr;
 935         int i, nop, port;
 936
 937         p = nil;
 938         nop = 0;
 939         while(p = pcimatch(p, 0x8086, 0)){
 940                 switch(p->did){
 941                 default:
 942                         continue;
 943                 case 0x1031:            /* Intel 82562EM */
 944                 case 0x103B:            /* Intel 82562EM */
 945                 case 0x103C:            /* Intel 82562EM */
 946                 case 0x1050:            /* Intel 82562EZ */
 947                 case 0x1039:            /* Intel 82801BD PRO/100 VE */
 948                 case 0x103A:            /* Intel 82562 PRO/100 VE */
 949                 case 0x103D:            /* Intel 82562 PRO/100 VE */
 950                 case 0x1064:            /* Intel 82562 PRO/100 VE */
 951                 case 0x2449:            /* Intel 82562ET */
 952                 case 0x27DC:            /* Intel 82801G PRO/100 VE */
 953                         nop = 1;
 954                         /*FALLTHROUGH*/
 955                 case 0x1209:            /* Intel 82559ER */
 956                 case 0x1229:            /* Intel 8255[789] */
 957                 case 0x1030:            /* Intel 82559 InBusiness 10/100  */
 958                         break;
 959                 }
 960
 961                 if(pcigetpms(p) > 0){
 962                         pcisetpms(p, 0);
 963
 964                         for(i = 0; i < 6; i++)
 965                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
 966                         pcicfgw8(p, PciINTL, p->intl);
 967                         pcicfgw8(p, PciLTR, p->ltr);
 968                         pcicfgw8(p, PciCLS, p->cls);
 969                         pcicfgw16(p, PciPCR, p->pcr);
 970                 }
 971
 972                 /*
 973                  * bar[0] is the memory-mapped register address (4KB),
 974                  * bar[1] is the I/O port register address (32 bytes) and
 975                  * bar[2] is for the flash ROM (1MB).
 976                  */
 977                 port = p->mem[1].bar & ~0x01;
 978                 if(ioalloc(port, p->mem[1].size, 0, "i82557") < 0){
 979                         print("i82557: port %#ux in use\n", port);
 980                         continue;
 981                 }
 982
 983                 ctlr = malloc(sizeof(Ctlr));
 984                 if(ctlr == nil){
 985                         print("i82557: can't allocate memory\n");
 986                         iofree(port);
 987                         continue;
 988                 }
 989                 ctlr->port = port;
 990                 ctlr->pcidev = p;
 991                 ctlr->nop = nop;
 992
 993                 if(ctlrhead != nil)
 994                         ctlrtail->next = ctlr;
 995                 else
 996                         ctlrhead = ctlr;
 997                 ctlrtail = ctlr;
 998
 999                 pcisetbme(p);
1000         }
1001 }
1002
1003 static char* mediatable[9] = {
1004         "10BASE-T",                             /* TP */
1005         "10BASE-2",                             /* BNC */
1006         "10BASE-5",                             /* AUI */
1007         "100BASE-TX",
1008         "10BASE-TFD",
1009         "100BASE-TXFD",
1010         "100BASE-T4",
1011         "100BASE-FX",
1012         "100BASE-FXFD",
1013 };
1014
1015 static int
1016 scanphy(Ctlr* ctlr)
1017 {
1018         int i, oui, x;
1019
1020         for(i = 0; i < 32; i++){
1021                 if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF)
1022                         continue;
1023                 oui <<= 6;
1024                 x = miir(ctlr, i, 3);
1025                 oui |= x>>10;
1026                 //print("phy%d: oui %#ux reg1 %#ux\n", i, oui, miir(ctlr, i, 1));
1027
1028                 ctlr->eeprom[6] = i;
1029                 if(oui == 0xAA00)
1030                         ctlr->eeprom[6] |= 0x07<<8;
1031                 else if(oui == 0x80017){
1032                         if(x & 0x01)
1033                                 ctlr->eeprom[6] |= 0x0A<<8;
1034                         else
1035                                 ctlr->eeprom[6] |= 0x04<<8;
1036                 }
1037                 return i;
1038         }
1039         return -1;
1040 }
1041
1042 static void
1043 shutdown(Ether* ether)
1044 {
1045         Ctlr *ctlr = ether->ctlr;
1046
1047 print("ether82557 shutting down\n");
1048         csr32w(ctlr, Port, 0);
1049         delay(1);
1050         csr8w(ctlr, Interrupt, InterruptM);
1051 }
1052
1053
1054 static int
1055 reset(Ether* ether)
1056 {
1057         int anar, anlpar, bmcr, bmsr, i, k, medium, phyaddr, x;
1058         unsigned short sum;
1059         uchar ea[Eaddrlen];
1060         Ctlr *ctlr;
1061
1062         if(ctlrhead == nil)
1063                 i82557pci();
1064
1065         /*
1066          * Any adapter matches if no ether->port is supplied,
1067          * otherwise the ports must match.
1068          */
1069         for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1070                 if(ctlr->active)
1071                         continue;
1072                 if(ether->port == 0 || ether->port == ctlr->port){
1073                         ctlr->active = 1;
1074                         break;
1075                 }
1076         }
1077         if(ctlr == nil)
1078                 return -1;
1079
1080         /*
1081          * Initialise the Ctlr structure.
1082          * Perform a software reset after which should ensure busmastering
1083          * is still enabled. The EtherExpress PRO/100B appears to leave
1084          * the PCI configuration alone (see the 'To do' list above) so punt
1085          * for now.
1086          * Load the RUB and CUB registers for linear addressing (0).
1087          */
1088         ether->ctlr = ctlr;
1089         ether->port = ctlr->port;
1090         ether->irq = ctlr->pcidev->intl;
1091         ether->tbdf = ctlr->pcidev->tbdf;
1092
1093         ilock(&ctlr->rlock);
1094         csr32w(ctlr, Port, 0);
1095         delay(1);
1096         csr8w(ctlr, Interrupt, InterruptM);
1097         iunlock(&ctlr->rlock);
1098
1099         command(ctlr, LoadRUB, 0);
1100         command(ctlr, LoadCUB, 0);
1101         command(ctlr, LoadDCA, PADDR(ctlr->dump));
1102
1103         /*
1104          * Initialise the receive frame, transmit ring and configuration areas.
1105          */
1106         ctlr->ncb = Ncb;
1107         ctlrinit(ctlr);
1108
1109         /*
1110          * Read the EEPROM.
1111          * Do a dummy read first to get the size
1112          * and allocate ctlr->eeprom.
1113          */
1114         hy93c46r(ctlr, 0);
1115         sum = 0;
1116         for(i = 0; i < (1<<ctlr->eepromsz); i++){
1117                 x = hy93c46r(ctlr, i);
1118                 ctlr->eeprom[i] = x;
1119                 sum += x;
1120         }
1121         if(sum != 0xBABA)
1122                 print("#l%d: EEPROM checksum - %#4.4ux\n", ether->ctlrno, sum);
1123
1124         /*
1125          * Eeprom[6] indicates whether there is a PHY and whether
1126          * it's not 10Mb-only, in which case use the given PHY address
1127          * to set any PHY specific options and determine the speed.
1128          * Unfortunately, sometimes the EEPROM is blank except for
1129          * the ether address and checksum; in this case look at the
1130          * controller type and if it's am 82558 or 82559 it has an
1131          * embedded PHY so scan for that.
1132          * If no PHY, assume 82503 (serial) operation.
1133          */
1134         if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000))
1135                 phyaddr = ctlr->eeprom[6] & 0x00FF;
1136         else
1137         switch(ctlr->pcidev->rid){
1138         case 0x01:                      /* 82557 A-step */
1139         case 0x02:                      /* 82557 B-step */
1140         case 0x03:                      /* 82557 C-step */
1141         default:
1142                 phyaddr = -1;
1143                 break;
1144         case 0x04:                      /* 82558 A-step */
1145         case 0x05:                      /* 82558 B-step */
1146         case 0x06:                      /* 82559 A-step */
1147         case 0x07:                      /* 82559 B-step */
1148         case 0x08:                      /* 82559 C-step */
1149         case 0x09:                      /* 82559ER A-step */
1150                 phyaddr = scanphy(ctlr);
1151                 break;
1152         }
1153         if(phyaddr >= 0){
1154                 /*
1155                  * Resolve the highest common ability of the two
1156                  * link partners. In descending order:
1157                  *      0x0100          100BASE-TX Full Duplex
1158                  *      0x0200          100BASE-T4
1159                  *      0x0080          100BASE-TX
1160                  *      0x0040          10BASE-T Full Duplex
1161                  *      0x0020          10BASE-T
1162                  */
1163                 anar = miir(ctlr, phyaddr, 0x04);
1164                 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1165                 anar &= anlpar;
1166                 bmcr = 0;
1167                 if(anar & 0x380)
1168                         bmcr = 0x2000;
1169                 if(anar & 0x0140)
1170                         bmcr |= 0x0100;
1171
1172                 switch((ctlr->eeprom[6]>>8) & 0x001F){
1173
1174                 case 0x04:                              /* DP83840 */
1175                 case 0x0A:                              /* DP83840A */
1176                         /*
1177                          * The DP83840[A] requires some tweaking for
1178                          * reliable operation.
1179                          * The manual says bit 10 should be unconditionally
1180                          * set although it supposedly only affects full-duplex
1181                          * operation (an & 0x0140).
1182                          */
1183                         x = miir(ctlr, phyaddr, 0x17) & ~0x0520;
1184                         x |= 0x0420;
1185                         for(i = 0; i < ether->nopt; i++){
1186                                 if(cistrcmp(ether->opt[i], "congestioncontrol"))
1187                                         continue;
1188                                 x |= 0x0100;
1189                                 break;
1190                         }
1191                         miiw(ctlr, phyaddr, 0x17, x);
1192
1193                         /*
1194                          * If the link partner can't autonegotiate, determine
1195                          * the speed from elsewhere.
1196                          */
1197                         if(anlpar == 0){
1198                                 miir(ctlr, phyaddr, 0x01);
1199                                 bmsr = miir(ctlr, phyaddr, 0x01);
1200                                 x = miir(ctlr, phyaddr, 0x19);
1201                                 if((bmsr & 0x0004) && !(x & 0x0040))
1202                                         bmcr = 0x2000;
1203                         }
1204                         break;
1205
1206                 case 0x07:                              /* Intel 82555 */
1207                         /*
1208                          * Auto-negotiation may fail if the other end is
1209                          * a DP83840A and the cable is short.
1210                          */
1211                         miir(ctlr, phyaddr, 0x01);
1212                         bmsr = miir(ctlr, phyaddr, 0x01);
1213                         if((miir(ctlr, phyaddr, 0) & 0x1000) && !(bmsr & 0x0020)){
1214                                 miiw(ctlr, phyaddr, 0x1A, 0x2010);
1215                                 x = miir(ctlr, phyaddr, 0);
1216                                 miiw(ctlr, phyaddr, 0, 0x0200|x);
1217                                 for(i = 0; i < 3000; i++){
1218                                         delay(1);
1219                                         if(miir(ctlr, phyaddr, 0x01) & 0x0020)
1220                                                 break;
1221                                 }
1222                                 miiw(ctlr, phyaddr, 0x1A, 0x2000);
1223
1224                                 anar = miir(ctlr, phyaddr, 0x04);
1225                                 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1226                                 anar &= anlpar;
1227                                 bmcr = 0;
1228                                 if(anar & 0x380)
1229                                         bmcr = 0x2000;
1230                                 if(anar & 0x0140)
1231                                         bmcr |= 0x0100;
1232                         }
1233                         break;
1234                 }
1235
1236                 /*
1237                  * Force speed and duplex if no auto-negotiation.
1238                  */
1239                 if(anlpar == 0){
1240                         medium = -1;
1241                         for(i = 0; i < ether->nopt; i++){
1242                                 for(k = 0; k < nelem(mediatable); k++){
1243                                         if(cistrcmp(mediatable[k], ether->opt[i]))
1244                                                 continue;
1245                                         medium = k;
1246                                         break;
1247                                 }
1248
1249                                 switch(medium){
1250                                 default:
1251                                         break;
1252
1253                                 case 0x00:                      /* 10BASE-T */
1254                                 case 0x01:                      /* 10BASE-2 */
1255                                 case 0x02:                      /* 10BASE-5 */
1256                                         bmcr &= ~(0x2000|0x0100);
1257                                         ctlr->configdata[19] &= ~0x40;
1258                                         break;
1259
1260                                 case 0x03:                      /* 100BASE-TX */
1261                                 case 0x06:                      /* 100BASE-T4 */
1262                                 case 0x07:                      /* 100BASE-FX */
1263                                         ctlr->configdata[19] &= ~0x40;
1264                                         bmcr |= 0x2000;
1265                                         break;
1266
1267                                 case 0x04:                      /* 10BASE-TFD */
1268                                         bmcr = (bmcr & ~0x2000)|0x0100;
1269                                         ctlr->configdata[19] |= 0x40;
1270                                         break;
1271
1272                                 case 0x05:                      /* 100BASE-TXFD */
1273                                 case 0x08:                      /* 100BASE-FXFD */
1274                                         bmcr |= 0x2000|0x0100;
1275                                         ctlr->configdata[19] |= 0x40;
1276                                         break;
1277                                 }
1278                         }
1279                         if(medium != -1)
1280                                 miiw(ctlr, phyaddr, 0x00, bmcr);
1281                 }
1282
1283                 if(bmcr & 0x2000)
1284                         ether->mbps = 100;
1285
1286                 ctlr->configdata[8] = 1;
1287                 ctlr->configdata[15] &= ~0x80;
1288         }
1289         else{
1290                 ctlr->configdata[8] = 0;
1291                 ctlr->configdata[15] |= 0x80;
1292         }
1293
1294         /*
1295          * Workaround for some broken HUB chips when connected at 10Mb/s
1296          * half-duplex.
1297          * This is a band-aid, but as there's no dynamic auto-negotiation
1298          * code at the moment, only deactivate the workaround code in txstart
1299          * if the link is 100Mb/s.
1300          */
1301         if(ether->mbps != 10)
1302                 ctlr->nop = 0;
1303
1304         /*
1305          * Load the chip configuration and start it off.
1306          */
1307         if(ether->oq == 0)
1308                 ether->oq = qopen(256*1024, Qmsg, 0, 0);
1309         configure(ether, 0);
1310         command(ctlr, CUstart, PADDR(&ctlr->cbr->status));
1311
1312         /*
1313          * Check if the adapter's station address is to be overridden.
1314          * If not, read it from the EEPROM and set in ether->ea prior to loading
1315          * the station address with the Individual Address Setup command.
1316          */
1317         memset(ea, 0, Eaddrlen);
1318         if(memcmp(ea, ether->ea, Eaddrlen) == 0){
1319                 for(i = 0; i < Eaddrlen/2; i++){
1320                         x = ctlr->eeprom[i];
1321                         ether->ea[2*i] = x;
1322                         ether->ea[2*i+1] = x>>8;
1323                 }
1324         }
1325
1326         ilock(&ctlr->cblock);
1327         ctlr->action = CbIAS;
1328         txstart(ether);
1329         iunlock(&ctlr->cblock);
1330
1331         /*
1332          * Linkage to the generic ethernet driver.
1333          */
1334         ether->attach = attach;
1335         ether->transmit = transmit;
1336         ether->interrupt = interrupt;
1337         ether->ifstat = ifstat;
1338         ether->shutdown = shutdown;
1339
1340         ether->promiscuous = promiscuous;
1341         ether->multicast = multicast;
1342         ether->arg = ether;
1343
1344         return 0;
1345 }
1346
1347 void
1348 ether82557link(void)
1349 {
1350         addethercard("i82557",  reset);
1351 }