sys/src/9/pc/ether82557.c

   1 /*
   2  * Intel 82557 Fast Ethernet PCI Bus LAN Controller
   3  * as found on the Intel EtherExpress PRO/100B. This chip is full
   4  * of smarts, unfortunately they're not all in the right place.
   5  * To do:
   6  *      the PCI scanning code could be made common to other adapters;
   7  *      auto-negotiation, full-duplex;
   8  *      optionally use memory-mapped registers;
   9  *      detach for PCI reset problems (also towards loadable drivers).
  10  */
  11 #include "u.h"
  12 #include "../port/lib.h"
  13 #include "mem.h"
  14 #include "dat.h"
  15 #include "fns.h"
  16 #include "io.h"
  17 #include "../port/error.h"
  18 #include "../port/netif.h"
  19
  20 #include "etherif.h"
  21
  22 enum {
  23         Nrfd            = 64,           /* receive frame area */
  24         Ncb             = 64,           /* maximum control blocks queued */
  25
  26         NullPointer     = 0xFFFFFFFF,   /* 82557 NULL pointer */
  27 };
  28
  29 enum {                                  /* CSR */
  30         Status          = 0x00,         /* byte or word (word includes Ack) */
  31         Ack             = 0x01,         /* byte */
  32         CommandR        = 0x02,         /* byte or word (word includes Interrupt) */
  33         Interrupt       = 0x03,         /* byte */
  34         General         = 0x04,         /* dword */
  35         Port            = 0x08,         /* dword */
  36         Fcr             = 0x0C,         /* Flash control register */
  37         Ecr             = 0x0E,         /* EEPROM control register */
  38         Mcr             = 0x10,         /* MDI control register */
  39         Gstatus         = 0x1D,         /* General status register */
  40 };
  41
  42 enum {                                  /* Status */
  43         RUidle          = 0x0000,
  44         RUsuspended     = 0x0004,
  45         RUnoresources   = 0x0008,
  46         RUready         = 0x0010,
  47         RUrbd           = 0x0020,       /* bit */
  48         RUstatus        = 0x003F,       /* mask */
  49
  50         CUidle          = 0x0000,
  51         CUsuspended     = 0x0040,
  52         CUactive        = 0x0080,
  53         CUstatus        = 0x00C0,       /* mask */
  54
  55         StatSWI         = 0x0400,       /* SoftWare generated Interrupt */
  56         StatMDI         = 0x0800,       /* MDI r/w done */
  57         StatRNR         = 0x1000,       /* Receive unit Not Ready */
  58         StatCNA         = 0x2000,       /* Command unit Not Active (Active->Idle) */
  59         StatFR          = 0x4000,       /* Finished Receiving */
  60         StatCX          = 0x8000,       /* Command eXecuted */
  61         StatTNO         = 0x8000,       /* Transmit NOT OK */
  62 };
  63
  64 enum {                                  /* Command (byte) */
  65         CUnop           = 0x00,
  66         CUstart         = 0x10,
  67         CUresume        = 0x20,
  68         LoadDCA         = 0x40,         /* Load Dump Counters Address */
  69         DumpSC          = 0x50,         /* Dump Statistical Counters */
  70         LoadCUB         = 0x60,         /* Load CU Base */
  71         ResetSA         = 0x70,         /* Dump and Reset Statistical Counters */
  72
  73         RUstart         = 0x01,
  74         RUresume        = 0x02,
  75         RUabort         = 0x04,
  76         LoadHDS         = 0x05,         /* Load Header Data Size */
  77         LoadRUB         = 0x06,         /* Load RU Base */
  78         RBDresume       = 0x07,         /* Resume frame reception */
  79 };
  80
  81 enum {                                  /* Interrupt (byte) */
  82         InterruptM      = 0x01,         /* interrupt Mask */
  83         InterruptSI     = 0x02,         /* Software generated Interrupt */
  84 };
  85
  86 enum {                                  /* Ecr */
  87         EEsk            = 0x01,         /* serial clock */
  88         EEcs            = 0x02,         /* chip select */
  89         EEdi            = 0x04,         /* serial data in */
  90         EEdo            = 0x08,         /* serial data out */
  91
  92         EEstart         = 0x04,         /* start bit */
  93         EEread          = 0x02,         /* read opcode */
  94 };
  95
  96 enum {                                  /* Mcr */
  97         MDIread         = 0x08000000,   /* read opcode */
  98         MDIwrite        = 0x04000000,   /* write opcode */
  99         MDIready        = 0x10000000,   /* ready bit */
 100         MDIie           = 0x20000000,   /* interrupt enable */
 101 };
 102
 103 typedef struct Rfd {
 104         int     field;
 105         ulong   link;
 106         ulong   rbd;
 107         ushort  count;
 108         ushort  size;
 109
 110         uchar   data[1700];
 111 } Rfd;
 112
 113 enum {                                  /* field */
 114         RfdCollision    = 0x00000001,
 115         RfdIA           = 0x00000002,   /* IA match */
 116         RfdRxerr        = 0x00000010,   /* PHY character error */
 117         RfdType         = 0x00000020,   /* Type frame */
 118         RfdRunt         = 0x00000080,
 119         RfdOverrun      = 0x00000100,
 120         RfdBuffer       = 0x00000200,
 121         RfdAlignment    = 0x00000400,
 122         RfdCRC          = 0x00000800,
 123
 124         RfdOK           = 0x00002000,   /* frame received OK */
 125         RfdC            = 0x00008000,   /* reception Complete */
 126         RfdSF           = 0x00080000,   /* Simplified or Flexible (1) Rfd */
 127         RfdH            = 0x00100000,   /* Header RFD */
 128
 129         RfdI            = 0x20000000,   /* Interrupt after completion */
 130         RfdS            = 0x40000000,   /* Suspend after completion */
 131         RfdEL           = 0x80000000,   /* End of List */
 132 };
 133
 134 enum {                                  /* count */
 135         RfdF            = 0x4000,
 136         RfdEOF          = 0x8000,
 137 };
 138
 139 typedef struct Cb Cb;
 140 typedef struct Cb {
 141         ushort  status;
 142         ushort  command;
 143         ulong   link;
 144         union {
 145                 uchar   data[24];       /* CbIAS + CbConfigure */
 146                 struct {
 147                         ulong   tbd;
 148                         ushort  count;
 149                         uchar   threshold;
 150                         uchar   number;
 151
 152                         ulong   tba;
 153                         ushort  tbasz;
 154                         ushort  pad;
 155                 };
 156         };
 157
 158         Block*  bp;
 159         Cb*     next;
 160 } Cb;
 161
 162 enum {                                  /* action command */
 163         CbU             = 0x1000,       /* transmit underrun */
 164         CbOK            = 0x2000,       /* DMA completed OK */
 165         CbC             = 0x8000,       /* execution Complete */
 166
 167         CbNOP           = 0x0000,
 168         CbIAS           = 0x0001,       /* Individual Address Setup */
 169         CbConfigure     = 0x0002,
 170         CbMAS           = 0x0003,       /* Multicast Address Setup */
 171         CbTransmit      = 0x0004,
 172         CbDump          = 0x0006,
 173         CbDiagnose      = 0x0007,
 174         CbCommand       = 0x0007,       /* mask */
 175
 176         CbSF            = 0x0008,       /* Flexible-mode CbTransmit */
 177
 178         CbI             = 0x2000,       /* Interrupt after completion */
 179         CbS             = 0x4000,       /* Suspend after completion */
 180         CbEL            = 0x8000,       /* End of List */
 181 };
 182
 183 enum {                                  /* CbTransmit count */
 184         CbEOF           = 0x8000,
 185 };
 186
 187 typedef struct Ctlr Ctlr;
 188 typedef struct Ctlr {
 189         Lock    slock;                  /* attach */
 190         int     state;
 191
 192         int     port;
 193         Pcidev* pcidev;
 194         Ctlr*   next;
 195         int     active;
 196
 197         int     eepromsz;               /* address size in bits */
 198         ushort* eeprom;
 199
 200         Lock    miilock;
 201
 202         int     tick;
 203
 204         Lock    rlock;                  /* registers */
 205         int     command;                /* last command issued */
 206
 207         Block*  rfdhead;                /* receive side */
 208         Block*  rfdtail;
 209         int     nrfd;
 210
 211         Lock    cblock;                 /* transmit side */
 212         int     action;
 213         int     nop;
 214         uchar   configdata[24];
 215         int     threshold;
 216         int     ncb;
 217         Cb*     cbr;
 218         Cb*     cbhead;
 219         Cb*     cbtail;
 220         int     cbq;
 221         int     cbqmax;
 222         int     cbqmaxhw;
 223
 224         Lock    dlock;                  /* dump statistical counters */
 225         ulong   dump[17];
 226 } Ctlr;
 227
 228 static Ctlr* ctlrhead;
 229 static Ctlr* ctlrtail;
 230
 231 static uchar configdata[24] = {
 232         0x16,                           /* byte count */
 233         0x08,                           /* Rx/Tx FIFO limit */
 234         0x00,                           /* adaptive IFS */
 235         0x00,
 236         0x00,                           /* Rx DMA maximum byte count */
 237 //      0x80,                           /* Tx DMA maximum byte count */
 238         0x00,                           /* Tx DMA maximum byte count */
 239         0x32,                           /* !late SCB, CNA interrupts */
 240         0x03,                           /* discard short Rx frames */
 241         0x00,                           /* 503/MII */
 242
 243         0x00,
 244         0x2E,                           /* normal operation, NSAI */
 245         0x00,                           /* linear priority */
 246         0x60,                           /* inter-frame spacing */
 247         0x00,
 248         0xF2,
 249         0xC8,                           /* 503, promiscuous mode off */
 250         0x00,
 251         0x40,
 252         0xF3,                           /* transmit padding enable */
 253         0x80,                           /* full duplex pin enable */
 254         0x3F,                           /* no Multi IA */
 255         0x05,                           /* no Multi Cast ALL */
 256 };
 257
 258 #define csr8r(c, r)     (inb((c)->port+(r)))
 259 #define csr16r(c, r)    (ins((c)->port+(r)))
 260 #define csr32r(c, r)    (inl((c)->port+(r)))
 261 #define csr8w(c, r, b)  (outb((c)->port+(r), (int)(b)))
 262 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
 263 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
 264
 265 static void
 266 command(Ctlr* ctlr, int c, int v)
 267 {
 268         int timeo;
 269
 270         ilock(&ctlr->rlock);
 271
 272         /*
 273          * Only back-to-back CUresume can be done
 274          * without waiting for any previous command to complete.
 275          * This should be the common case.
 276          * Unfortunately there's a chip errata where back-to-back
 277          * CUresumes can be lost, the fix is to always wait.
 278         if(c == CUresume && ctlr->command == CUresume){
 279                 csr8w(ctlr, CommandR, c);
 280                 iunlock(&ctlr->rlock);
 281                 return;
 282         }
 283          */
 284
 285         for(timeo = 0; timeo < 100; timeo++){
 286                 if(!csr8r(ctlr, CommandR))
 287                         break;
 288                 microdelay(1);
 289         }
 290         if(timeo >= 100){
 291                 ctlr->command = -1;
 292                 iunlock(&ctlr->rlock);
 293                 iprint("i82557: command %#ux %#ux timeout\n", c, v);
 294                 return;
 295         }
 296
 297         switch(c){
 298
 299         case CUstart:
 300         case LoadDCA:
 301         case LoadCUB:
 302         case RUstart:
 303         case LoadHDS:
 304         case LoadRUB:
 305                 csr32w(ctlr, General, v);
 306                 break;
 307
 308         /*
 309         case CUnop:
 310         case CUresume:
 311         case DumpSC:
 312         case ResetSA:
 313         case RUresume:
 314         case RUabort:
 315          */
 316         default:
 317                 break;
 318         }
 319         csr8w(ctlr, CommandR, c);
 320         ctlr->command = c;
 321
 322         iunlock(&ctlr->rlock);
 323 }
 324
 325 static Block*
 326 rfdalloc(ulong link)
 327 {
 328         Block *bp;
 329         Rfd *rfd;
 330
 331         if(bp = iallocb(sizeof(Rfd))){
 332                 rfd = (Rfd*)bp->rp;
 333                 rfd->field = 0;
 334                 rfd->link = link;
 335                 rfd->rbd = NullPointer;
 336                 rfd->count = 0;
 337                 rfd->size = sizeof(Etherpkt);
 338         }
 339
 340         return bp;
 341 }
 342
 343 static void
 344 watchdog(void* arg)
 345 {
 346         Ether *ether;
 347         Ctlr *ctlr;
 348         static void txstart(Ether*);
 349
 350         ether = arg;
 351         while(waserror())
 352                 ;
 353         for(;;){
 354                 tsleep(&up->sleep, return0, 0, 4000);
 355
 356                 /*
 357                  * Hmmm. This doesn't seem right. Currently
 358                  * the device can't be disabled but it may be in
 359                  * the future.
 360                  */
 361                 ctlr = ether->ctlr;
 362                 if(ctlr == nil || ctlr->state == 0)
 363                         break;
 364
 365                 ilock(&ctlr->cblock);
 366                 if(ctlr->tick++){
 367                         ctlr->action = CbMAS;
 368                         txstart(ether);
 369                 }
 370                 iunlock(&ctlr->cblock);
 371         }
 372         print("%s: exiting\n", up->text);
 373         pexit("disabled", 1);
 374 }
 375
 376 static void
 377 attach(Ether* ether)
 378 {
 379         Ctlr *ctlr;
 380         char name[KNAMELEN];
 381
 382         ctlr = ether->ctlr;
 383         lock(&ctlr->slock);
 384         if(ctlr->state == 0){
 385                 ilock(&ctlr->rlock);
 386                 csr8w(ctlr, Interrupt, 0);
 387                 iunlock(&ctlr->rlock);
 388                 command(ctlr, RUstart, PADDR(ctlr->rfdhead->rp));
 389                 ctlr->state = 1;
 390
 391                 /*
 392                  * Start the watchdog timer for the receive lockup errata
 393                  * unless the EEPROM compatibility word indicates it may be
 394                  * omitted.
 395                  */
 396                 if((ctlr->eeprom[0x03] & 0x0003) != 0x0003){
 397                         snprint(name, KNAMELEN, "#l%dwatchdog", ether->ctlrno);
 398                         kproc(name, watchdog, ether);
 399                 }
 400         }
 401         unlock(&ctlr->slock);
 402 }
 403
 404 static long
 405 ifstat(Ether* ether, void* a, long n, ulong offset)
 406 {
 407         char *p;
 408         int i, len, phyaddr;
 409         Ctlr *ctlr;
 410         ulong dump[17];
 411
 412         ctlr = ether->ctlr;
 413         lock(&ctlr->dlock);
 414         if(waserror()){
 415                 unlock(&ctlr->dlock);
 416                 nexterror();
 417         }
 418
 419         /*
 420          * Start the command then
 421          * wait for completion status,
 422          * should be 0xA005.
 423          */
 424         ctlr->dump[16] = 0;
 425         command(ctlr, DumpSC, 0);
 426         for(i = 0; i < 1000 && ctlr->dump[16] == 0; i++)
 427                 microdelay(100);
 428         if(i == 1000)
 429                 error("command timeout");
 430
 431         memmove(dump, ctlr->dump, sizeof(dump));
 432
 433         ether->oerrs = dump[1]+dump[2]+dump[3];
 434         ether->crcs = dump[10];
 435         ether->frames = dump[11];
 436         ether->buffs = dump[12]+dump[15];
 437         ether->overflows = dump[13];
 438
 439         poperror();
 440         unlock(&ctlr->dlock);
 441
 442         if(n == 0)
 443                 return 0;
 444
 445         p = smalloc(READSTR);
 446         len = snprint(p, READSTR, "transmit good frames: %lud\n", dump[0]);
 447         len += snprint(p+len, READSTR-len, "transmit maximum collisions errors: %lud\n", dump[1]);
 448         len += snprint(p+len, READSTR-len, "transmit late collisions errors: %lud\n", dump[2]);
 449         len += snprint(p+len, READSTR-len, "transmit underrun errors: %lud\n", dump[3]);
 450         len += snprint(p+len, READSTR-len, "transmit lost carrier sense: %lud\n", dump[4]);
 451         len += snprint(p+len, READSTR-len, "transmit deferred: %lud\n", dump[5]);
 452         len += snprint(p+len, READSTR-len, "transmit single collisions: %lud\n", dump[6]);
 453         len += snprint(p+len, READSTR-len, "transmit multiple collisions: %lud\n", dump[7]);
 454         len += snprint(p+len, READSTR-len, "transmit total collisions: %lud\n", dump[8]);
 455         len += snprint(p+len, READSTR-len, "receive good frames: %lud\n", dump[9]);
 456         len += snprint(p+len, READSTR-len, "receive CRC errors: %lud\n", dump[10]);
 457         len += snprint(p+len, READSTR-len, "receive alignment errors: %lud\n", dump[11]);
 458         len += snprint(p+len, READSTR-len, "receive resource errors: %lud\n", dump[12]);
 459         len += snprint(p+len, READSTR-len, "receive overrun errors: %lud\n", dump[13]);
 460         len += snprint(p+len, READSTR-len, "receive collision detect errors: %lud\n", dump[14]);
 461         len += snprint(p+len, READSTR-len, "receive short frame errors: %lud\n", dump[15]);
 462         len += snprint(p+len, READSTR-len, "nop: %d\n", ctlr->nop);
 463         if(ctlr->cbqmax > ctlr->cbqmaxhw)
 464                 ctlr->cbqmaxhw = ctlr->cbqmax;
 465         len += snprint(p+len, READSTR-len, "cbqmax: %d\n", ctlr->cbqmax);
 466         ctlr->cbqmax = 0;
 467         len += snprint(p+len, READSTR-len, "threshold: %d\n", ctlr->threshold);
 468
 469         len += snprint(p+len, READSTR-len, "eeprom:");
 470         for(i = 0; i < (1<<ctlr->eepromsz); i++){
 471                 if(i && ((i & 0x07) == 0))
 472                         len += snprint(p+len, READSTR-len, "\n       ");
 473                 len += snprint(p+len, READSTR-len, " %4.4ux", ctlr->eeprom[i]);
 474         }
 475
 476         if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)){
 477                 phyaddr = ctlr->eeprom[6] & 0x00FF;
 478                 len += snprint(p+len, READSTR-len, "\nphy %2d:", phyaddr);
 479                 for(i = 0; i < 6; i++){
 480                         static int miir(Ctlr*, int, int);
 481
 482                         len += snprint(p+len, READSTR-len, " %4.4ux",
 483                                 miir(ctlr, phyaddr, i));
 484                 }
 485         }
 486
 487         snprint(p+len, READSTR-len, "\n");
 488         n = readstr(offset, a, n, p);
 489         free(p);
 490
 491         return n;
 492 }
 493
 494 static void
 495 txstart(Ether* ether)
 496 {
 497         Ctlr *ctlr;
 498         Block *bp;
 499         Cb *cb;
 500
 501         ctlr = ether->ctlr;
 502         while(ctlr->cbq < (ctlr->ncb-1)){
 503                 cb = ctlr->cbhead->next;
 504                 if(ctlr->action == 0){
 505                         bp = qget(ether->oq);
 506                         if(bp == nil)
 507                                 break;
 508
 509                         cb->command = CbS|CbSF|CbTransmit;
 510                         cb->tbd = PADDR(&cb->tba);
 511                         cb->count = 0;
 512                         cb->threshold = ctlr->threshold;
 513                         cb->number = 1;
 514                         cb->tba = PADDR(bp->rp);
 515                         cb->bp = bp;
 516                         cb->tbasz = BLEN(bp);
 517                 }
 518                 else if(ctlr->action == CbConfigure){
 519                         cb->command = CbS|CbConfigure;
 520                         memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata));
 521                         ctlr->action = 0;
 522                 }
 523                 else if(ctlr->action == CbIAS){
 524                         cb->command = CbS|CbIAS;
 525                         memmove(cb->data, ether->ea, Eaddrlen);
 526                         ctlr->action = 0;
 527                 }
 528                 else if(ctlr->action == CbMAS){
 529                         cb->command = CbS|CbMAS;
 530                         memset(cb->data, 0, sizeof(cb->data));
 531                         ctlr->action = 0;
 532                 }
 533                 else{
 534                         print("#l%d: action %#ux\n", ether->ctlrno, ctlr->action);
 535                         ctlr->action = 0;
 536                         break;
 537                 }
 538                 cb->status = 0;
 539
 540                 coherence();
 541                 ctlr->cbhead->command &= ~CbS;
 542                 ctlr->cbhead = cb;
 543                 ctlr->cbq++;
 544         }
 545
 546         /*
 547          * Workaround for some broken HUB chips
 548          * when connected at 10Mb/s half-duplex.
 549          */
 550         if(ctlr->nop){
 551                 command(ctlr, CUnop, 0);
 552                 microdelay(1);
 553         }
 554         command(ctlr, CUresume, 0);
 555
 556         if(ctlr->cbq > ctlr->cbqmax)
 557                 ctlr->cbqmax = ctlr->cbq;
 558 }
 559
 560 static void
 561 configure(Ether* ether, int promiscuous)
 562 {
 563         Ctlr *ctlr;
 564
 565         ctlr = ether->ctlr;
 566         ilock(&ctlr->cblock);
 567         if(promiscuous){
 568                 ctlr->configdata[6] |= 0x80;            /* Save Bad Frames */
 569                 //ctlr->configdata[6] &= ~0x40;         /* !Discard Overrun Rx Frames */
 570                 ctlr->configdata[7] &= ~0x01;           /* !Discard Short Rx Frames */
 571                 ctlr->configdata[15] |= 0x01;           /* Promiscuous mode */
 572                 ctlr->configdata[18] &= ~0x01;          /* (!Padding enable?), !stripping enable */
 573                 ctlr->configdata[21] |= 0x08;           /* Multi Cast ALL */
 574         }
 575         else{
 576                 ctlr->configdata[6] &= ~0x80;
 577                 //ctlr->configdata[6] |= 0x40;
 578                 ctlr->configdata[7] |= 0x01;
 579                 ctlr->configdata[15] &= ~0x01;
 580                 ctlr->configdata[18] |= 0x01;           /* 0x03? */
 581                 ctlr->configdata[21] &= ~0x08;
 582         }
 583         ctlr->action = CbConfigure;
 584         txstart(ether);
 585         iunlock(&ctlr->cblock);
 586 }
 587
 588 static void
 589 promiscuous(void* arg, int on)
 590 {
 591         configure(arg, on);
 592 }
 593
 594 static void
 595 multicast(void* ether, uchar *addr, int add)
 596 {
 597         USED(addr);
 598         /*
 599          * TODO: if (add) add addr to list of mcast addrs in controller
 600          *      else remove addr from list of mcast addrs in controller
 601          * enable multicast input (see CbMAS) instead of promiscuous mode.
 602          */
 603         if (add)
 604                 configure(ether, 1);
 605 }
 606
 607 static void
 608 transmit(Ether* ether)
 609 {
 610         Ctlr *ctlr;
 611
 612         ctlr = ether->ctlr;
 613         ilock(&ctlr->cblock);
 614         txstart(ether);
 615         iunlock(&ctlr->cblock);
 616 }
 617
 618 static void
 619 receive(Ether* ether)
 620 {
 621         Rfd *rfd;
 622         Ctlr *ctlr;
 623         int count;
 624         Block *bp, *pbp, *xbp;
 625
 626         ctlr = ether->ctlr;
 627         bp = ctlr->rfdhead;
 628         for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){
 629                 /*
 630                  * If it's an OK receive frame
 631                  * 1) save the count
 632                  * 2) if it's small, try to allocate a block and copy
 633                  *    the data, then adjust the necessary fields for reuse;
 634                  * 3) if it's big, try to allocate a new Rfd and if
 635                  *    successful
 636                  *      adjust the received buffer pointers for the
 637                  *        actual data received;
 638                  *      initialise the replacement buffer to point to
 639                  *        the next in the ring;
 640                  *      initialise bp to point to the replacement;
 641                  * 4) if there's a good packet, pass it on for disposal.
 642                  */
 643                 if(rfd->field & RfdOK){
 644                         pbp = nil;
 645                         count = rfd->count & 0x3FFF;
 646                         if((count < ETHERMAXTU/4) && (pbp = iallocb(count))){
 647                                 memmove(pbp->rp, bp->rp+offsetof(Rfd, data[0]), count);
 648                                 pbp->wp = pbp->rp + count;
 649
 650                                 rfd->count = 0;
 651                                 rfd->field = 0;
 652                         }
 653                         else if(xbp = rfdalloc(rfd->link)){
 654                                 bp->rp += offsetof(Rfd, data[0]);
 655                                 bp->wp = bp->rp + count;
 656
 657                                 xbp->next = bp->next;
 658                                 bp->next = 0;
 659
 660                                 pbp = bp;
 661                                 bp = xbp;
 662                         }
 663                         if(pbp != nil)
 664                                 etheriq(ether, pbp, 1);
 665                 }
 666                 else{
 667                         rfd->count = 0;
 668                         rfd->field = 0;
 669                 }
 670
 671                 /*
 672                  * The ring tail pointer follows the head with with one
 673                  * unused buffer in between to defeat hardware prefetch;
 674                  * once the tail pointer has been bumped on to the next
 675                  * and the new tail has the Suspend bit set, it can be
 676                  * removed from the old tail buffer.
 677                  * As a replacement for the current head buffer may have
 678                  * been allocated above, ensure that the new tail points
 679                  * to it (next and link).
 680                  */
 681                 rfd = (Rfd*)ctlr->rfdtail->rp;
 682                 ctlr->rfdtail = ctlr->rfdtail->next;
 683                 ctlr->rfdtail->next = bp;
 684                 ((Rfd*)ctlr->rfdtail->rp)->link = PADDR(bp->rp);
 685                 ((Rfd*)ctlr->rfdtail->rp)->field |= RfdS;
 686                 coherence();
 687                 rfd->field &= ~RfdS;
 688
 689                 /*
 690                  * Finally done with the current (possibly replaced)
 691                  * head, move on to the next and maintain the sentinel
 692                  * between tail and head.
 693                  */
 694                 ctlr->rfdhead = bp->next;
 695                 bp = ctlr->rfdhead;
 696         }
 697 }
 698
 699 static void
 700 interrupt(Ureg*, void* arg)
 701 {
 702         Cb* cb;
 703         Ctlr *ctlr;
 704         Ether *ether;
 705         int status;
 706
 707         ether = arg;
 708         ctlr = ether->ctlr;
 709
 710         for(;;){
 711                 ilock(&ctlr->rlock);
 712                 status = csr16r(ctlr, Status);
 713                 csr8w(ctlr, Ack, (status>>8) & 0xFF);
 714                 iunlock(&ctlr->rlock);
 715
 716                 if(!(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI)))
 717                         break;
 718
 719                 /*
 720                  * If the watchdog timer for the receiver lockup errata is running,
 721                  * let it know the receiver is active.
 722                  */
 723                 if(status & (StatFR|StatRNR)){
 724                         ilock(&ctlr->cblock);
 725                         ctlr->tick = 0;
 726                         iunlock(&ctlr->cblock);
 727                 }
 728
 729                 if(status & StatFR){
 730                         receive(ether);
 731                         status &= ~StatFR;
 732                 }
 733
 734                 if(status & StatRNR){
 735                         command(ctlr, RUresume, 0);
 736                         status &= ~StatRNR;
 737                 }
 738
 739                 if(status & StatCNA){
 740                         ilock(&ctlr->cblock);
 741
 742                         cb = ctlr->cbtail;
 743                         while(ctlr->cbq){
 744                                 if(!(cb->status & CbC))
 745                                         break;
 746                                 if(cb->bp){
 747                                         freeb(cb->bp);
 748                                         cb->bp = nil;
 749                                 }
 750                                 if((cb->status & CbU) && ctlr->threshold < 0xE0)
 751                                         ctlr->threshold++;
 752
 753                                 ctlr->cbq--;
 754                                 cb = cb->next;
 755                         }
 756                         ctlr->cbtail = cb;
 757
 758                         txstart(ether);
 759                         iunlock(&ctlr->cblock);
 760
 761                         status &= ~StatCNA;
 762                 }
 763
 764                 if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))
 765                         panic("#l%d: status %#ux", ether->ctlrno, status);
 766         }
 767 }
 768
 769 static void
 770 ctlrinit(Ctlr* ctlr)
 771 {
 772         int i;
 773         Block *bp;
 774         Rfd *rfd;
 775         ulong link;
 776
 777         /*
 778          * Create the Receive Frame Area (RFA) as a ring of allocated
 779          * buffers.
 780          * A sentinel buffer is maintained between the last buffer in
 781          * the ring (marked with RfdS) and the head buffer to defeat the
 782          * hardware prefetch of the next RFD and allow dynamic buffer
 783          * allocation.
 784          */
 785         link = NullPointer;
 786         for(i = 0; i < Nrfd; i++){
 787                 bp = rfdalloc(link);
 788                 if(bp == nil)
 789                         panic("i82557: can't allocate rfd buffer");
 790                 if(ctlr->rfdhead == nil)
 791                         ctlr->rfdtail = bp;
 792                 bp->next = ctlr->rfdhead;
 793                 ctlr->rfdhead = bp;
 794                 link = PADDR(bp->rp);
 795         }
 796         ctlr->rfdtail->next = ctlr->rfdhead;
 797         rfd = (Rfd*)ctlr->rfdtail->rp;
 798         rfd->link = PADDR(ctlr->rfdhead->rp);
 799         rfd->field |= RfdS;
 800         ctlr->rfdhead = ctlr->rfdhead->next;
 801
 802         /*
 803          * Create a ring of control blocks for the
 804          * transmit side.
 805          */
 806         ilock(&ctlr->cblock);
 807         ctlr->cbr = malloc(ctlr->ncb*sizeof(Cb));
 808         if(ctlr->cbr == nil)
 809                 panic("i82557: can't allocate cbr");
 810         for(i = 0; i < ctlr->ncb; i++){
 811                 ctlr->cbr[i].status = CbC|CbOK;
 812                 ctlr->cbr[i].command = CbS|CbNOP;
 813                 ctlr->cbr[i].link = PADDR(&ctlr->cbr[NEXT(i, ctlr->ncb)].status);
 814                 ctlr->cbr[i].next = &ctlr->cbr[NEXT(i, ctlr->ncb)];
 815         }
 816         ctlr->cbhead = ctlr->cbr;
 817         ctlr->cbtail = ctlr->cbr;
 818         ctlr->cbq = 0;
 819
 820         memmove(ctlr->configdata, configdata, sizeof(configdata));
 821         ctlr->threshold = 80;
 822         ctlr->tick = 0;
 823
 824         iunlock(&ctlr->cblock);
 825 }
 826
 827 static int
 828 miir(Ctlr* ctlr, int phyadd, int regadd)
 829 {
 830         int mcr, timo;
 831
 832         lock(&ctlr->miilock);
 833         csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16));
 834         mcr = 0;
 835         for(timo = 64; timo; timo--){
 836                 mcr = csr32r(ctlr, Mcr);
 837                 if(mcr & MDIready)
 838                         break;
 839                 microdelay(1);
 840         }
 841         unlock(&ctlr->miilock);
 842
 843         if(mcr & MDIready)
 844                 return mcr & 0xFFFF;
 845
 846         return -1;
 847 }
 848
 849 static int
 850 miiw(Ctlr* ctlr, int phyadd, int regadd, int data)
 851 {
 852         int mcr, timo;
 853
 854         lock(&ctlr->miilock);
 855         csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF));
 856         mcr = 0;
 857         for(timo = 64; timo; timo--){
 858                 mcr = csr32r(ctlr, Mcr);
 859                 if(mcr & MDIready)
 860                         break;
 861                 microdelay(1);
 862         }
 863         unlock(&ctlr->miilock);
 864
 865         if(mcr & MDIready)
 866                 return 0;
 867
 868         return -1;
 869 }
 870
 871 static int
 872 hy93c46r(Ctlr* ctlr, int r)
 873 {
 874         int data, i, op, size;
 875
 876         /*
 877          * Hyundai HY93C46 or equivalent serial EEPROM.
 878          * This sequence for reading a 16-bit register 'r'
 879          * in the EEPROM is taken straight from Section
 880          * 3.3.4.2 of the Intel 82557 User's Guide.
 881          */
 882 reread:
 883         csr16w(ctlr, Ecr, EEcs);
 884         op = EEstart|EEread;
 885         for(i = 2; i >= 0; i--){
 886                 data = (((op>>i) & 0x01)<<2)|EEcs;
 887                 csr16w(ctlr, Ecr, data);
 888                 csr16w(ctlr, Ecr, data|EEsk);
 889                 microdelay(1);
 890                 csr16w(ctlr, Ecr, data);
 891                 microdelay(1);
 892         }
 893
 894         /*
 895          * First time through must work out the EEPROM size.
 896          */
 897         if((size = ctlr->eepromsz) == 0)
 898                 size = 8;
 899
 900         for(size = size-1; size >= 0; size--){
 901                 data = (((r>>size) & 0x01)<<2)|EEcs;
 902                 csr16w(ctlr, Ecr, data);
 903                 csr16w(ctlr, Ecr, data|EEsk);
 904                 delay(1);
 905                 csr16w(ctlr, Ecr, data);
 906                 microdelay(1);
 907                 if(!(csr16r(ctlr, Ecr) & EEdo))
 908                         break;
 909         }
 910
 911         data = 0;
 912         for(i = 15; i >= 0; i--){
 913                 csr16w(ctlr, Ecr, EEcs|EEsk);
 914                 microdelay(1);
 915                 if(csr16r(ctlr, Ecr) & EEdo)
 916                         data |= (1<<i);
 917                 csr16w(ctlr, Ecr, EEcs);
 918                 microdelay(1);
 919         }
 920
 921         csr16w(ctlr, Ecr, 0);
 922
 923         if(ctlr->eepromsz == 0){
 924                 ctlr->eepromsz = 8-size;
 925                 ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
 926                 if(ctlr->eeprom == nil)
 927                         panic("i82557: can't allocate eeprom");
 928                 goto reread;
 929         }
 930
 931         return data;
 932 }
 933
 934 static void
 935 i82557pci(void)
 936 {
 937         Pcidev *p;
 938         Ctlr *ctlr;
 939         int i, nop, port;
 940
 941         p = nil;
 942         nop = 0;
 943         while(p = pcimatch(p, 0x8086, 0)){
 944                 switch(p->did){
 945                 default:
 946                         continue;
 947                 case 0x1031:            /* Intel 82562EM */
 948                 case 0x103B:            /* Intel 82562EM */
 949                 case 0x103C:            /* Intel 82562EM */
 950                 case 0x1050:            /* Intel 82562EZ */
 951                 case 0x1039:            /* Intel 82801BD PRO/100 VE */
 952                 case 0x103A:            /* Intel 82562 PRO/100 VE */
 953                 case 0x103D:            /* Intel 82562 PRO/100 VE */
 954                 case 0x1064:            /* Intel 82562 PRO/100 VE */
 955                 case 0x2449:            /* Intel 82562ET */
 956                 case 0x27DC:            /* Intel 82801G PRO/100 VE */
 957                         nop = 1;
 958                         /*FALLTHROUGH*/
 959                 case 0x1209:            /* Intel 82559ER */
 960                 case 0x1229:            /* Intel 8255[789] */
 961                 case 0x1030:            /* Intel 82559 InBusiness 10/100  */
 962                         break;
 963                 }
 964
 965                 if(pcigetpms(p) > 0){
 966                         pcisetpms(p, 0);
 967
 968                         for(i = 0; i < 6; i++)
 969                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
 970                         pcicfgw8(p, PciINTL, p->intl);
 971                         pcicfgw8(p, PciLTR, p->ltr);
 972                         pcicfgw8(p, PciCLS, p->cls);
 973                         pcicfgw16(p, PciPCR, p->pcr);
 974                 }
 975
 976                 /*
 977                  * bar[0] is the memory-mapped register address (4KB),
 978                  * bar[1] is the I/O port register address (32 bytes) and
 979                  * bar[2] is for the flash ROM (1MB).
 980                  */
 981                 port = p->mem[1].bar & ~0x01;
 982                 if(ioalloc(port, p->mem[1].size, 0, "i82557") < 0){
 983                         print("i82557: port %#ux in use\n", port);
 984                         continue;
 985                 }
 986
 987                 ctlr = malloc(sizeof(Ctlr));
 988                 if(ctlr == nil){
 989                         print("i82557: can't allocate memory\n");
 990                         iofree(port);
 991                         continue;
 992                 }
 993                 ctlr->port = port;
 994                 ctlr->pcidev = p;
 995                 ctlr->nop = nop;
 996
 997                 if(ctlrhead != nil)
 998                         ctlrtail->next = ctlr;
 999                 else
1000                         ctlrhead = ctlr;
1001                 ctlrtail = ctlr;
1002
1003                 pcisetbme(p);
1004         }
1005 }
1006
1007 static char* mediatable[9] = {
1008         "10BASE-T",                             /* TP */
1009         "10BASE-2",                             /* BNC */
1010         "10BASE-5",                             /* AUI */
1011         "100BASE-TX",
1012         "10BASE-TFD",
1013         "100BASE-TXFD",
1014         "100BASE-T4",
1015         "100BASE-FX",
1016         "100BASE-FXFD",
1017 };
1018
1019 static int
1020 scanphy(Ctlr* ctlr)
1021 {
1022         int i, oui, x;
1023
1024         for(i = 0; i < 32; i++){
1025                 if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF)
1026                         continue;
1027                 oui <<= 6;
1028                 x = miir(ctlr, i, 3);
1029                 oui |= x>>10;
1030                 //print("phy%d: oui %#ux reg1 %#ux\n", i, oui, miir(ctlr, i, 1));
1031
1032                 ctlr->eeprom[6] = i;
1033                 if(oui == 0xAA00)
1034                         ctlr->eeprom[6] |= 0x07<<8;
1035                 else if(oui == 0x80017){
1036                         if(x & 0x01)
1037                                 ctlr->eeprom[6] |= 0x0A<<8;
1038                         else
1039                                 ctlr->eeprom[6] |= 0x04<<8;
1040                 }
1041                 return i;
1042         }
1043         return -1;
1044 }
1045
1046 static void
1047 shutdown(Ether* ether)
1048 {
1049         Ctlr *ctlr = ether->ctlr;
1050
1051 print("ether82557 shutting down\n");
1052         csr32w(ctlr, Port, 0);
1053         delay(1);
1054         csr8w(ctlr, Interrupt, InterruptM);
1055 }
1056
1057
1058 static int
1059 reset(Ether* ether)
1060 {
1061         int anar, anlpar, bmcr, bmsr, i, k, medium, phyaddr, x;
1062         unsigned short sum;
1063         uchar ea[Eaddrlen];
1064         Ctlr *ctlr;
1065
1066         if(ctlrhead == nil)
1067                 i82557pci();
1068
1069         /*
1070          * Any adapter matches if no ether->port is supplied,
1071          * otherwise the ports must match.
1072          */
1073         for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1074                 if(ctlr->active)
1075                         continue;
1076                 if(ether->port == 0 || ether->port == ctlr->port){
1077                         ctlr->active = 1;
1078                         break;
1079                 }
1080         }
1081         if(ctlr == nil)
1082                 return -1;
1083
1084         /*
1085          * Initialise the Ctlr structure.
1086          * Perform a software reset after which should ensure busmastering
1087          * is still enabled. The EtherExpress PRO/100B appears to leave
1088          * the PCI configuration alone (see the 'To do' list above) so punt
1089          * for now.
1090          * Load the RUB and CUB registers for linear addressing (0).
1091          */
1092         ether->ctlr = ctlr;
1093         ether->port = ctlr->port;
1094         ether->irq = ctlr->pcidev->intl;
1095         ether->tbdf = ctlr->pcidev->tbdf;
1096
1097         ilock(&ctlr->rlock);
1098         csr32w(ctlr, Port, 0);
1099         delay(1);
1100         csr8w(ctlr, Interrupt, InterruptM);
1101         iunlock(&ctlr->rlock);
1102
1103         command(ctlr, LoadRUB, 0);
1104         command(ctlr, LoadCUB, 0);
1105         command(ctlr, LoadDCA, PADDR(ctlr->dump));
1106
1107         /*
1108          * Initialise the receive frame, transmit ring and configuration areas.
1109          */
1110         ctlr->ncb = Ncb;
1111         ctlrinit(ctlr);
1112
1113         /*
1114          * Read the EEPROM.
1115          * Do a dummy read first to get the size
1116          * and allocate ctlr->eeprom.
1117          */
1118         hy93c46r(ctlr, 0);
1119         sum = 0;
1120         for(i = 0; i < (1<<ctlr->eepromsz); i++){
1121                 x = hy93c46r(ctlr, i);
1122                 ctlr->eeprom[i] = x;
1123                 sum += x;
1124         }
1125         if(sum != 0xBABA)
1126                 print("#l%d: EEPROM checksum - %#4.4ux\n", ether->ctlrno, sum);
1127
1128         /*
1129          * Eeprom[6] indicates whether there is a PHY and whether
1130          * it's not 10Mb-only, in which case use the given PHY address
1131          * to set any PHY specific options and determine the speed.
1132          * Unfortunately, sometimes the EEPROM is blank except for
1133          * the ether address and checksum; in this case look at the
1134          * controller type and if it's am 82558 or 82559 it has an
1135          * embedded PHY so scan for that.
1136          * If no PHY, assume 82503 (serial) operation.
1137          */
1138         if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000))
1139                 phyaddr = ctlr->eeprom[6] & 0x00FF;
1140         else
1141         switch(ctlr->pcidev->rid){
1142         case 0x01:                      /* 82557 A-step */
1143         case 0x02:                      /* 82557 B-step */
1144         case 0x03:                      /* 82557 C-step */
1145         default:
1146                 phyaddr = -1;
1147                 break;
1148         case 0x04:                      /* 82558 A-step */
1149         case 0x05:                      /* 82558 B-step */
1150         case 0x06:                      /* 82559 A-step */
1151         case 0x07:                      /* 82559 B-step */
1152         case 0x08:                      /* 82559 C-step */
1153         case 0x09:                      /* 82559ER A-step */
1154                 phyaddr = scanphy(ctlr);
1155                 break;
1156         }
1157         if(phyaddr >= 0){
1158                 /*
1159                  * Resolve the highest common ability of the two
1160                  * link partners. In descending order:
1161                  *      0x0100          100BASE-TX Full Duplex
1162                  *      0x0200          100BASE-T4
1163                  *      0x0080          100BASE-TX
1164                  *      0x0040          10BASE-T Full Duplex
1165                  *      0x0020          10BASE-T
1166                  */
1167                 anar = miir(ctlr, phyaddr, 0x04);
1168                 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1169                 anar &= anlpar;
1170                 bmcr = 0;
1171                 if(anar & 0x380)
1172                         bmcr = 0x2000;
1173                 if(anar & 0x0140)
1174                         bmcr |= 0x0100;
1175
1176                 switch((ctlr->eeprom[6]>>8) & 0x001F){
1177
1178                 case 0x04:                              /* DP83840 */
1179                 case 0x0A:                              /* DP83840A */
1180                         /*
1181                          * The DP83840[A] requires some tweaking for
1182                          * reliable operation.
1183                          * The manual says bit 10 should be unconditionally
1184                          * set although it supposedly only affects full-duplex
1185                          * operation (an & 0x0140).
1186                          */
1187                         x = miir(ctlr, phyaddr, 0x17) & ~0x0520;
1188                         x |= 0x0420;
1189                         for(i = 0; i < ether->nopt; i++){
1190                                 if(cistrcmp(ether->opt[i], "congestioncontrol"))
1191                                         continue;
1192                                 x |= 0x0100;
1193                                 break;
1194                         }
1195                         miiw(ctlr, phyaddr, 0x17, x);
1196
1197                         /*
1198                          * If the link partner can't autonegotiate, determine
1199                          * the speed from elsewhere.
1200                          */
1201                         if(anlpar == 0){
1202                                 miir(ctlr, phyaddr, 0x01);
1203                                 bmsr = miir(ctlr, phyaddr, 0x01);
1204                                 x = miir(ctlr, phyaddr, 0x19);
1205                                 if((bmsr & 0x0004) && !(x & 0x0040))
1206                                         bmcr = 0x2000;
1207                         }
1208                         break;
1209
1210                 case 0x07:                              /* Intel 82555 */
1211                         /*
1212                          * Auto-negotiation may fail if the other end is
1213                          * a DP83840A and the cable is short.
1214                          */
1215                         miir(ctlr, phyaddr, 0x01);
1216                         bmsr = miir(ctlr, phyaddr, 0x01);
1217                         if((miir(ctlr, phyaddr, 0) & 0x1000) && (bmsr & 0x0020))
1218                                 break;
1219                         miiw(ctlr, phyaddr, 0x1A, 0x2010);
1220                         x = miir(ctlr, phyaddr, 0);
1221                         miiw(ctlr, phyaddr, 0, 0x1200|x);
1222                         for(i = 0; i < 3000; i++){
1223                                 delay(1);
1224                                 if(miir(ctlr, phyaddr, 0x01) & 0x0020)
1225                                         break;
1226                         }
1227                         miiw(ctlr, phyaddr, 0x1A, 0x2000);
1228
1229                         anar = miir(ctlr, phyaddr, 0x04);
1230                         anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
1231                         anar &= anlpar;
1232                         bmcr = 0;
1233                         if(anar & 0x380)
1234                                 bmcr = 0x2000;
1235                         if(anar & 0x0140)
1236                                 bmcr |= 0x0100;
1237                         break;
1238                 }
1239
1240                 /*
1241                  * Force speed and duplex if no auto-negotiation.
1242                  */
1243                 if(anlpar == 0){
1244                         medium = -1;
1245                         for(i = 0; i < ether->nopt; i++){
1246                                 for(k = 0; k < nelem(mediatable); k++){
1247                                         if(cistrcmp(mediatable[k], ether->opt[i]))
1248                                                 continue;
1249                                         medium = k;
1250                                         break;
1251                                 }
1252
1253                                 switch(medium){
1254                                 default:
1255                                         break;
1256
1257                                 case 0x00:                      /* 10BASE-T */
1258                                 case 0x01:                      /* 10BASE-2 */
1259                                 case 0x02:                      /* 10BASE-5 */
1260                                         bmcr &= ~(0x2000|0x0100);
1261                                         ctlr->configdata[19] &= ~0x40;
1262                                         break;
1263
1264                                 case 0x03:                      /* 100BASE-TX */
1265                                 case 0x06:                      /* 100BASE-T4 */
1266                                 case 0x07:                      /* 100BASE-FX */
1267                                         ctlr->configdata[19] &= ~0x40;
1268                                         bmcr |= 0x2000;
1269                                         break;
1270
1271                                 case 0x04:                      /* 10BASE-TFD */
1272                                         bmcr = (bmcr & ~0x2000)|0x0100;
1273                                         ctlr->configdata[19] |= 0x40;
1274                                         break;
1275
1276                                 case 0x05:                      /* 100BASE-TXFD */
1277                                 case 0x08:                      /* 100BASE-FXFD */
1278                                         bmcr |= 0x2000|0x0100;
1279                                         ctlr->configdata[19] |= 0x40;
1280                                         break;
1281                                 }
1282                         }
1283                         if(medium != -1)
1284                                 miiw(ctlr, phyaddr, 0x00, bmcr);
1285                 }
1286
1287                 if(bmcr & 0x2000)
1288                         ether->mbps = 100;
1289
1290                 ctlr->configdata[8] = 1;
1291                 ctlr->configdata[15] &= ~0x80;
1292         }
1293         else{
1294                 ctlr->configdata[8] = 0;
1295                 ctlr->configdata[15] |= 0x80;
1296         }
1297
1298         /*
1299          * Workaround for some broken HUB chips when connected at 10Mb/s
1300          * half-duplex.
1301          * This is a band-aid, but as there's no dynamic auto-negotiation
1302          * code at the moment, only deactivate the workaround code in txstart
1303          * if the link is 100Mb/s.
1304          */
1305         if(ether->mbps != 10)
1306                 ctlr->nop = 0;
1307
1308         /*
1309          * Load the chip configuration and start it off.
1310          */
1311         if(ether->oq == 0)
1312                 ether->oq = qopen(256*1024, Qmsg, 0, 0);
1313         configure(ether, 0);
1314         command(ctlr, CUstart, PADDR(&ctlr->cbr->status));
1315
1316         /*
1317          * Check if the adapter's station address is to be overridden.
1318          * If not, read it from the EEPROM and set in ether->ea prior to loading
1319          * the station address with the Individual Address Setup command.
1320          */
1321         memset(ea, 0, Eaddrlen);
1322         if(memcmp(ea, ether->ea, Eaddrlen) == 0){
1323                 for(i = 0; i < Eaddrlen/2; i++){
1324                         x = ctlr->eeprom[i];
1325                         ether->ea[2*i] = x;
1326                         ether->ea[2*i+1] = x>>8;
1327                 }
1328         }
1329
1330         ilock(&ctlr->cblock);
1331         ctlr->action = CbIAS;
1332         txstart(ether);
1333         iunlock(&ctlr->cblock);
1334
1335         /*
1336          * Linkage to the generic ethernet driver.
1337          */
1338         ether->attach = attach;
1339         ether->transmit = transmit;
1340         ether->interrupt = interrupt;
1341         ether->ifstat = ifstat;
1342         ether->shutdown = shutdown;
1343
1344         ether->promiscuous = promiscuous;
1345         ether->multicast = multicast;
1346         ether->arg = ether;
1347
1348         return 0;
1349 }
1350
1351 void
1352 ether82557link(void)
1353 {
1354         addethercard("i82557",  reset);
1355 }