sys/src/9/pc/ether82543gc.c

   1 /*
   2  * Intel RS-82543GC Gigabit Ethernet Controller
   3  * as found on the Intel PRO/1000[FT] Server Adapter.
   4  * The older non-[FT] cards use the 82542 (LSI L2A1157) chip; no attempt
   5  * is made to handle the older chip although it should be possible.
   6  * The datasheet is not very clear about running on a big-endian system
   7  * and this driver assumes little-endian throughout.
   8  * To do:
   9  *      GMII/MII
  10  *      receive tuning
  11  *      transmit tuning
  12  */
  13 #include "u.h"
  14 #include "../port/lib.h"
  15 #include "mem.h"
  16 #include "dat.h"
  17 #include "fns.h"
  18 #include "io.h"
  19 #include "../port/pci.h"
  20 #include "../port/error.h"
  21 #include "../port/netif.h"
  22 #include "../port/etherif.h"
  23
  24 enum {
  25         Ctrl            = 0x00000000,   /* Device Control */
  26         Status          = 0x00000008,   /* Device Status */
  27         Eecd            = 0x00000010,   /* EEPROM/Flash Control/Data */
  28         Ctrlext         = 0x00000018,   /* Extended Device Control */
  29         Mdic            = 0x00000020,   /* MDI Control */
  30         Fcal            = 0x00000028,   /* Flow Control Address Low */
  31         Fcah            = 0x0000002C,   /* Flow Control Address High */
  32         Fct             = 0x00000030,   /* Flow Control Type */
  33         Icr             = 0x000000C0,   /* Interrupt Cause Read */
  34         Ics             = 0x000000C8,   /* Interrupt Cause Set */
  35         Ims             = 0x000000D0,   /* Interrupt Mask Set/Read */
  36         Imc             = 0x000000D8,   /* Interrupt mask Clear */
  37         Rctl            = 0x00000100,   /* Receive Control */
  38         Fcttv           = 0x00000170,   /* Flow Control Transmit Timer Value */
  39         Txcw            = 0x00000178,   /* Transmit configuration word reg. */
  40         Rxcw            = 0x00000180,   /* Receive configuration word reg. */
  41         Tctl            = 0x00000400,   /* Transmit Control */
  42         Tipg            = 0x00000410,   /* Transmit IPG */
  43         Tbt             = 0x00000448,   /* Transmit Burst Timer */
  44         Ait             = 0x00000458,   /* Adaptive IFS Throttle */
  45         Fcrtl           = 0x00002160,   /* Flow Control RX Threshold Low */
  46         Fcrth           = 0x00002168,   /* Flow Control Rx Threshold High */
  47         Rdfh            = 0x00002410,   /* Receive data fifo head */
  48         Rdft            = 0x00002418,   /* Receive data fifo tail */
  49         Rdfhs           = 0x00002420,   /* Receive data fifo head saved */
  50         Rdfts           = 0x00002428,   /* Receive data fifo tail saved */
  51         Rdfpc           = 0x00002430,   /* Receive data fifo packet count */
  52         Rdbal           = 0x00002800,   /* Rdesc Base Address Low */
  53         Rdbah           = 0x00002804,   /* Rdesc Base Address High */
  54         Rdlen           = 0x00002808,   /* Receive Descriptor Length */
  55         Rdh             = 0x00002810,   /* Receive Descriptor Head */
  56         Rdt             = 0x00002818,   /* Receive Descriptor Tail */
  57         Rdtr            = 0x00002820,   /* Receive Descriptor Timer Ring */
  58         Rxdctl          = 0x00002828,   /* Receive Descriptor Control */
  59         Txdmac          = 0x00003000,   /* Transfer DMA Control */
  60         Ett             = 0x00003008,   /* Early Transmit Control */
  61         Tdfh            = 0x00003410,   /* Transmit data fifo head */
  62         Tdft            = 0x00003418,   /* Transmit data fifo tail */
  63         Tdfhs           = 0x00003420,   /* Transmit data Fifo Head saved */
  64         Tdfts           = 0x00003428,   /* Transmit data fifo tail saved */
  65         Tdfpc           = 0x00003430,   /* Trasnmit data Fifo packet count */
  66         Tdbal           = 0x00003800,   /* Tdesc Base Address Low */
  67         Tdbah           = 0x00003804,   /* Tdesc Base Address High */
  68         Tdlen           = 0x00003808,   /* Transmit Descriptor Length */
  69         Tdh             = 0x00003810,   /* Transmit Descriptor Head */
  70         Tdt             = 0x00003818,   /* Transmit Descriptor Tail */
  71         Tidv            = 0x00003820,   /* Transmit Interrupt Delay Value */
  72         Txdctl          = 0x00003828,   /* Transmit Descriptor Control */
  73
  74         Statistics      = 0x00004000,   /* Start of Statistics Area */
  75         Gorcl           = 0x88/4,       /* Good Octets Received Count */
  76         Gotcl           = 0x90/4,       /* Good Octets Transmitted Count */
  77         Torl            = 0xC0/4,       /* Total Octets Received */
  78         Totl            = 0xC8/4,       /* Total Octets Transmitted */
  79         Nstatistics     = 64,
  80
  81         Rxcsum          = 0x00005000,   /* Receive Checksum Control */
  82         Mta             = 0x00005200,   /* Multicast Table Array */
  83         Ral             = 0x00005400,   /* Receive Address Low */
  84         Rah             = 0x00005404,   /* Receive Address High */
  85 };
  86
  87 enum {                                  /* Ctrl */
  88         Bem             = 0x00000002,   /* Big Endian Mode */
  89         Prior           = 0x00000004,   /* Priority on the PCI bus */
  90         Lrst            = 0x00000008,   /* Link Reset */
  91         Asde            = 0x00000020,   /* Auto-Speed Detection Enable */
  92         Slu             = 0x00000040,   /* Set Link Up */
  93         Ilos            = 0x00000080,   /* Invert Loss of Signal (LOS) */
  94         Frcspd          = 0x00000800,   /* Force Speed */
  95         Frcdplx         = 0x00001000,   /* Force Duplex */
  96         Swdpinslo       = 0x003C0000,   /* Software Defined Pins - lo nibble */
  97         Swdpin0         = 0x00040000,
  98         Swdpin1         = 0x00080000,
  99         Swdpin2         = 0x00100000,
 100         Swdpin3         = 0x00200000,
 101         Swdpiolo        = 0x03C00000,   /* Software Defined I/O Pins */
 102         Swdpio0         = 0x00400000,
 103         Swdpio1         = 0x00800000,
 104         Swdpio2         = 0x01000000,
 105         Swdpio3         = 0x02000000,
 106         Devrst          = 0x04000000,   /* Device Reset */
 107         Rfce            = 0x08000000,   /* Receive Flow Control Enable */
 108         Tfce            = 0x10000000,   /* Transmit Flow Control Enable */
 109         Vme             = 0x40000000,   /* VLAN Mode Enable */
 110 };
 111
 112 enum {                                  /* Status */
 113         Lu              = 0x00000002,   /* Link Up */
 114         Tckok           = 0x00000004,   /* Transmit clock is running */
 115         Rbcok           = 0x00000008,   /* Receive clock is running */
 116         Txoff           = 0x00000010,   /* Transmission Paused */
 117         Tbimode         = 0x00000020,   /* TBI Mode Indication */
 118         SpeedMASK       = 0x000000C0,
 119         Speed10         = 0x00000000,   /* 10Mb/s */
 120         Speed100        = 0x00000040,   /* 100Mb/s */
 121         Speed1000       = 0x00000080,   /* 1000Mb/s */
 122         Mtxckok         = 0x00000400,   /* MTX clock is running */
 123         Pci66           = 0x00000800,   /* PCI Bus speed indication */
 124         Bus64           = 0x00001000,   /* PCI Bus width indication */
 125 };
 126
 127 enum {                                  /* Ctrl and Status */
 128         Fd              = 0x00000001,   /* Full-Duplex */
 129         AsdvMASK        = 0x00000300,
 130         Asdv10          = 0x00000000,   /* 10Mb/s */
 131         Asdv100         = 0x00000100,   /* 100Mb/s */
 132         Asdv1000        = 0x00000200,   /* 1000Mb/s */
 133 };
 134
 135 enum {                                  /* Eecd */
 136         Sk              = 0x00000001,   /* Clock input to the EEPROM */
 137         Cs              = 0x00000002,   /* Chip Select */
 138         Di              = 0x00000004,   /* Data Input to the EEPROM */
 139         Do              = 0x00000008,   /* Data Output from the EEPROM */
 140 };
 141
 142 enum {                                  /* Ctrlext */
 143         Gpien           = 0x0000000F,   /* General Purpose Interrupt Enables */
 144         Swdpinshi       = 0x000000F0,   /* Software Defined Pins - hi nibble */
 145         Swdpiohi        = 0x00000F00,   /* Software Defined Pins - I or O */
 146         Asdchk          = 0x00001000,   /* ASD Check */
 147         Eerst           = 0x00002000,   /* EEPROM Reset */
 148         Ips             = 0x00004000,   /* Invert Power State */
 149         Spdbyps         = 0x00008000,   /* Speed Select Bypass */
 150 };
 151
 152 enum {                                  /* EEPROM content offsets */
 153         Ea              = 0x00,         /* Ethernet Address */
 154         Cf              = 0x03,         /* Compatibility Field */
 155         Pba             = 0x08,         /* Printed Board Assembly number */
 156         Icw1            = 0x0A,         /* Initialization Control Word 1 */
 157         Sid             = 0x0B,         /* Subsystem ID */
 158         Svid            = 0x0C,         /* Subsystem Vendor ID */
 159         Did             = 0x0D,         /* Device ID */
 160         Vid             = 0x0E,         /* Vendor ID */
 161         Icw2            = 0x0F,         /* Initialization Control Word 2 */
 162 };
 163
 164 enum {                                  /* Mdic */
 165         MDIdMASK        = 0x0000FFFF,   /* Data */
 166         MDIdSHIFT       = 0,
 167         MDIrMASK        = 0x001F0000,   /* PHY Register Address */
 168         MDIrSHIFT       = 16,
 169         MDIpMASK        = 0x03E00000,   /* PHY Address */
 170         MDIpSHIFT       = 21,
 171         MDIwop          = 0x04000000,   /* Write Operation */
 172         MDIrop          = 0x08000000,   /* Read Operation */
 173         MDIready        = 0x10000000,   /* End of Transaction */
 174         MDIie           = 0x20000000,   /* Interrupt Enable */
 175         MDIe            = 0x40000000,   /* Error */
 176 };
 177
 178 enum {                                  /* Icr, Ics, Ims, Imc */
 179         Txdw            = 0x00000001,   /* Transmit Descriptor Written Back */
 180         Txqe            = 0x00000002,   /* Transmit Queue Empty */
 181         Lsc             = 0x00000004,   /* Link Status Change */
 182         Rxseq           = 0x00000008,   /* Receive Sequence Error */
 183         Rxdmt0          = 0x00000010,   /* Rdesc Minimum Threshold Reached */
 184         Rxo             = 0x00000040,   /* Receiver Overrun */
 185         Rxt0            = 0x00000080,   /* Receiver Timer Interrupt */
 186         Mdac            = 0x00000200,   /* MDIO Access Completed */
 187         Rxcfg           = 0x00000400,   /* Receiving /C/ ordered sets */
 188         Gpi0            = 0x00000800,   /* General Purpose Interrupts */
 189         Gpi1            = 0x00001000,
 190         Gpi2            = 0x00002000,
 191         Gpi3            = 0x00004000,
 192 };
 193
 194 enum {                                  /* Txcw */
 195         Ane             = 0x80000000,   /* Autonegotiate enable */
 196         Np              = 0x00008000,   /* Next Page */
 197         As              = 0x00000100,   /* Asymmetric Flow control desired */
 198         Ps              = 0x00000080,   /* Pause supported */
 199         Hd              = 0x00000040,   /* Half duplex supported */
 200         TxcwFd          = 0x00000020,   /* Full Duplex supported */
 201 };
 202
 203 enum {                                  /* Rxcw */
 204         Rxword          = 0x0000FFFF,   /* Data from auto-negotiation process */
 205         Rxnocarrier     = 0x04000000,   /* Carrier Sense indication */
 206         Rxinvalid       = 0x08000000,   /* Invalid Symbol during configuration */
 207         Rxchange        = 0x10000000,   /* Change to the Rxword indication */
 208         Rxconfig        = 0x20000000,   /* /C/ order set reception indication */
 209         Rxsync          = 0x40000000,   /* Lost bit synchronization indication */
 210         Anc             = 0x80000000,   /* Auto Negotiation Complete */
 211 };
 212
 213 enum {                                  /* Rctl */
 214         Rrst            = 0x00000001,   /* Receiver Software Reset */
 215         Ren             = 0x00000002,   /* Receiver Enable */
 216         Sbp             = 0x00000004,   /* Store Bad Packets */
 217         Upe             = 0x00000008,   /* Unicast Promiscuous Enable */
 218         Mpe             = 0x00000010,   /* Multicast Promiscuous Enable */
 219         Lpe             = 0x00000020,   /* Long Packet Reception Enable */
 220         LbmMASK         = 0x000000C0,   /* Loopback Mode */
 221         LbmOFF          = 0x00000000,   /* No Loopback */
 222         LbmTBI          = 0x00000040,   /* TBI Loopback */
 223         LbmMII          = 0x00000080,   /* GMII/MII Loopback */
 224         LbmXCVR         = 0x000000C0,   /* Transceiver Loopback */
 225         RdtmsMASK       = 0x00000300,   /* Rdesc Minimum Threshold Size */
 226         RdtmsHALF       = 0x00000000,   /* Threshold is 1/2 Rdlen */
 227         RdtmsQUARTER    = 0x00000100,   /* Threshold is 1/4 Rdlen */
 228         RdtmsEIGHTH     = 0x00000200,   /* Threshold is 1/8 Rdlen */
 229         MoMASK          = 0x00003000,   /* Multicast Offset */
 230         Bam             = 0x00008000,   /* Broadcast Accept Mode */
 231         BsizeMASK       = 0x00030000,   /* Receive Buffer Size */
 232         Bsize2048       = 0x00000000,   /* Bsex = 0 */
 233         Bsize1024       = 0x00010000,   /* Bsex = 0 */
 234         Bsize512        = 0x00020000,   /* Bsex = 0 */
 235         Bsize256        = 0x00030000,   /* Bsex = 0 */
 236         Bsize16384      = 0x00010000,   /* Bsex = 1 */
 237         Vfe             = 0x00040000,   /* VLAN Filter Enable */
 238         Cfien           = 0x00080000,   /* Canonical Form Indicator Enable */
 239         Cfi             = 0x00100000,   /* Canonical Form Indicator value */
 240         Dpf             = 0x00400000,   /* Discard Pause Frames */
 241         Pmcf            = 0x00800000,   /* Pass MAC Control Frames */
 242         Bsex            = 0x02000000,   /* Buffer Size Extension */
 243         Secrc           = 0x04000000,   /* Strip CRC from incoming packet */
 244 };
 245
 246 enum {                                  /* Tctl */
 247         Trst            = 0x00000001,   /* Transmitter Software Reset */
 248         Ten             = 0x00000002,   /* Transmit Enable */
 249         Psp             = 0x00000008,   /* Pad Short Packets */
 250         CtMASK          = 0x00000FF0,   /* Collision Threshold */
 251         CtSHIFT         = 4,
 252         ColdMASK        = 0x003FF000,   /* Collision Distance */
 253         ColdSHIFT       = 12,
 254         Swxoff          = 0x00400000,   /* Sofware XOFF Transmission */
 255         Pbe             = 0x00800000,   /* Packet Burst Enable */
 256         Rtlc            = 0x01000000,   /* Re-transmit on Late Collision */
 257         Nrtu            = 0x02000000,   /* No Re-transmit on Underrrun */
 258 };
 259
 260 enum {                                  /* [RT]xdctl */
 261         PthreshMASK     = 0x0000003F,   /* Prefetch Threshold */
 262         PthreshSHIFT    = 0,
 263         HthreshMASK     = 0x00003F00,   /* Host Threshold */
 264         HthreshSHIFT    = 8,
 265         WthreshMASK     = 0x003F0000,   /* Writeback Threshold */
 266         WthreshSHIFT    = 16,
 267         Gran            = 0x00000000,   /* Granularity */
 268         RxGran          = 0x01000000,   /* Granularity */
 269 };
 270
 271 enum {                                  /* Rxcsum */
 272         PcssMASK        = 0x000000FF,   /* Packet Checksum Start */
 273         PcssSHIFT       = 0,
 274         Ipofl           = 0x00000100,   /* IP Checksum Off-load Enable */
 275         Tuofl           = 0x00000200,   /* TCP/UDP Checksum Off-load Enable */
 276 };
 277
 278 enum {                                  /* Receive Delay Timer Ring */
 279         Fpd             = 0x80000000,   /* Flush partial Descriptor Block */
 280 };
 281
 282 typedef struct Rdesc {                  /* Receive Descriptor */
 283         uint    addr[2];
 284         ushort  length;
 285         ushort  checksum;
 286         uchar   status;
 287         uchar   errors;
 288         ushort  special;
 289 } Rdesc;
 290
 291 enum {                                  /* Rdesc status */
 292         Rdd             = 0x01,         /* Descriptor Done */
 293         Reop            = 0x02,         /* End of Packet */
 294         Ixsm            = 0x04,         /* Ignore Checksum Indication */
 295         Vp              = 0x08,         /* Packet is 802.1Q (matched VET) */
 296         Tcpcs           = 0x20,         /* TCP Checksum Calculated on Packet */
 297         Ipcs            = 0x40,         /* IP Checksum Calculated on Packet */
 298         Pif             = 0x80,         /* Passed in-exact filter */
 299 };
 300
 301 enum {                                  /* Rdesc errors */
 302         Ce              = 0x01,         /* CRC Error or Alignment Error */
 303         Se              = 0x02,         /* Symbol Error */
 304         Seq             = 0x04,         /* Sequence Error */
 305         Cxe             = 0x10,         /* Carrier Extension Error */
 306         Tcpe            = 0x20,         /* TCP/UDP Checksum Error */
 307         Ipe             = 0x40,         /* IP Checksum Error */
 308         Rxe             = 0x80,         /* RX Data Error */
 309 };
 310
 311 typedef struct Tdesc {                  /* Legacy+Normal Transmit Descriptor */
 312         uint    addr[2];
 313         uint    control;                /* varies with descriptor type */
 314         uint    status;                 /* varies with descriptor type */
 315 } Tdesc;
 316
 317 enum {                                  /* Tdesc control */
 318         CsoMASK         = 0x00000F00,   /* Checksum Offset */
 319         CsoSHIFT        = 16,
 320         Teop            = 0x01000000,   /* End of Packet */
 321         Ifcs            = 0x02000000,   /* Insert FCS */
 322         Ic              = 0x04000000,   /* Insert Checksum (Dext == 0) */
 323         Tse             = 0x04000000,   /* TCP Segmentaion Enable (Dext == 1) */
 324         Rs              = 0x08000000,   /* Report Status */
 325         Rps             = 0x10000000,   /* Report Status Sent */
 326         Dext            = 0x20000000,   /* Extension (!legacy) */
 327         Vle             = 0x40000000,   /* VLAN Packet Enable */
 328         Ide             = 0x80000000,   /* Interrupt Delay Enable */
 329 };
 330
 331 enum {                                  /* Tdesc status */
 332         Tdd             = 0x00000001,   /* Descriptor Done */
 333         Ec              = 0x00000002,   /* Excess Collisions */
 334         Lc              = 0x00000004,   /* Late Collision */
 335         Tu              = 0x00000008,   /* Transmit Underrun */
 336         CssMASK         = 0x0000FF00,   /* Checksum Start Field */
 337         CssSHIFT        = 8,
 338 };
 339
 340 enum {
 341         Nrdesc          = 256,          /* multiple of 8 */
 342         Ntdesc          = 256,          /* multiple of 8 */
 343         Nblocks         = 4098,         /* total number of blocks to use */
 344
 345         SBLOCKSIZE      = 2048,
 346         JBLOCKSIZE      = 16384,
 347
 348         NORMAL          = 1,
 349         JUMBO           = 2,
 350 };
 351
 352 typedef struct Ctlr Ctlr;
 353 typedef struct Ctlr {
 354         uvlong  port;
 355         Pcidev* pcidev;
 356         Ctlr*   next;
 357         int     active;
 358         int     started;
 359         int     id;
 360         ushort  eeprom[0x40];
 361
 362         int*    nic;
 363         int     im;                     /* interrupt mask */
 364
 365         Lock    slock;
 366         uint    statistics[Nstatistics];
 367
 368         Lock    rdlock;
 369         Rdesc*  rdba;                   /* receive descriptor base address */
 370         Block*  rb[Nrdesc];             /* receive buffers */
 371         int     rdh;                    /* receive descriptor head */
 372         int     rdt;                    /* receive descriptor tail */
 373         Block** freehead;               /* points to long or short head */
 374
 375         Lock    tdlock;
 376         Tdesc*  tdba;                   /* transmit descriptor base address */
 377         Block*  tb[Ntdesc];             /* transmit buffers */
 378         int     tdh;                    /* transmit descriptor head */
 379         int     tdt;                    /* transmit descriptor tail */
 380         int     txstalled;              /* count of times unable to send */
 381
 382         int     txcw;
 383         int     fcrtl;
 384         int     fcrth;
 385
 386         ulong   multimask[128];         /* bit mask for multicast addresses */
 387 } Ctlr;
 388
 389 static Ctlr* gc82543ctlrhead;
 390 static Ctlr* gc82543ctlrtail;
 391
 392 static Lock freelistlock;
 393 static Block* freeShortHead;
 394 static Block* freeJumboHead;
 395
 396 #define csr32r(c, r)    (*((c)->nic+((r)/4)))
 397 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
 398
 399 static void gc82543watchdog(void* arg);
 400
 401 static void
 402 gc82543attach(Ether* edev)
 403 {
 404         int ctl;
 405         Ctlr *ctlr;
 406         char name[KNAMELEN];
 407
 408         /*
 409          * To do here:
 410          *      one-time stuff;
 411          *              adjust queue length depending on speed;
 412          *              flow control.
 413          *      more needed here...
 414          */
 415         ctlr = edev->ctlr;
 416         lock(&ctlr->slock);
 417         if(ctlr->started){
 418                 unlock(&ctlr->slock);
 419                 return;
 420         }
 421
 422         ctl = csr32r(ctlr, Rctl)|Ren;
 423         csr32w(ctlr, Rctl, ctl);
 424         ctl = csr32r(ctlr, Tctl)|Ten;
 425         csr32w(ctlr, Tctl, ctl);
 426
 427         csr32w(ctlr, Ims, ctlr->im);
 428
 429         ctlr->started = 1;
 430         unlock(&ctlr->slock);
 431
 432         snprint(name, KNAMELEN, "#l%d82543", edev->ctlrno);
 433         kproc(name, gc82543watchdog, edev);
 434 }
 435
 436 static char* statistics[Nstatistics] = {
 437         "CRC Error",
 438         "Alignment Error",
 439         "Symbol Error",
 440         "RX Error",
 441         "Missed Packets",
 442         "Single Collision",
 443         "Excessive Collisions",
 444         "Multiple Collision",
 445         "Late Collisions",
 446         nil,
 447         "Collision",
 448         "Transmit Underrun",
 449         "Defer",
 450         "Transmit - No CRS",
 451         "Sequence Error",
 452         "Carrier Extension Error",
 453         "Receive Error Length",
 454         nil,
 455         "XON Received",
 456         "XON Transmitted",
 457         "XOFF Received",
 458         "XOFF Transmitted",
 459         "FC Received Unsupported",
 460         "Packets Received (64 Bytes)",
 461         "Packets Received (65-127 Bytes)",
 462         "Packets Received (128-255 Bytes)",
 463         "Packets Received (256-511 Bytes)",
 464         "Packets Received (512-1023 Bytes)",
 465         "Packets Received (1024-1522 Bytes)",
 466         "Good Packets Received",
 467         "Broadcast Packets Received",
 468         "Multicast Packets Received",
 469         "Good Packets Transmitted",
 470         nil,
 471         "Good Octets Received",
 472         nil,
 473         "Good Octets Transmitted",
 474         nil,
 475         nil,
 476         nil,
 477         "Receive No Buffers",
 478         "Receive Undersize",
 479         "Receive Fragment",
 480         "Receive Oversize",
 481         "Receive Jabber",
 482         nil,
 483         nil,
 484         nil,
 485         "Total Octets Received",
 486         nil,
 487         "Total Octets Transmitted",
 488         nil,
 489         "Total Packets Received",
 490         "Total Packets Transmitted",
 491         "Packets Transmitted (64 Bytes)",
 492         "Packets Transmitted (65-127 Bytes)",
 493         "Packets Transmitted (128-255 Bytes)",
 494         "Packets Transmitted (256-511 Bytes)",
 495         "Packets Transmitted (512-1023 Bytes)",
 496         "Packets Transmitted (1024-1522 Bytes)",
 497         "Multicast Packets Transmitted",
 498         "Broadcast Packets Transmitted",
 499         "TCP Segmentation Context Transmitted",
 500         "TCP Segmentation Context Fail",
 501 };
 502
 503 static long
 504 gc82543ifstat(Ether* edev, void* a, long n, ulong offset)
 505 {
 506         Ctlr *ctlr;
 507         char *p, *s;
 508         int i, l, r;
 509         uvlong tuvl, ruvl;
 510
 511         p = smalloc(READSTR);
 512
 513         ctlr = edev->ctlr;
 514         lock(&ctlr->slock);
 515         l = 0;
 516         for(i = 0; i < Nstatistics; i++){
 517                 r = csr32r(ctlr, Statistics+i*4);
 518                 if((s = statistics[i]) == nil)
 519                         continue;
 520                 switch(i){
 521                 case Gorcl:
 522                 case Gotcl:
 523                 case Torl:
 524                 case Totl:
 525                         ruvl = r;
 526                         ruvl += ((uvlong)csr32r(ctlr, Statistics+(i+1)*4))<<32;
 527                         tuvl = ruvl;
 528                         tuvl += ctlr->statistics[i];
 529                         tuvl += ((uvlong)ctlr->statistics[i+1])<<32;
 530                         if(tuvl == 0)
 531                                 continue;
 532                         ctlr->statistics[i] = tuvl;
 533                         ctlr->statistics[i+1] = tuvl>>32;
 534                         l += snprint(p+l, READSTR-l, "%s: %llud %llud\n",
 535                                 s, tuvl, ruvl);
 536                         i++;
 537                         break;
 538
 539                 default:
 540                         ctlr->statistics[i] += r;
 541                         if(ctlr->statistics[i] == 0)
 542                                 continue;
 543                         l += snprint(p+l, READSTR-l, "%s: %ud %ud\n",
 544                                 s, ctlr->statistics[i], r);
 545                         break;
 546                 }
 547         }
 548
 549         l += snprint(p+l, READSTR-l, "eeprom:");
 550         for(i = 0; i < 0x40; i++){
 551                 if(i && ((i & 0x07) == 0))
 552                         l += snprint(p+l, READSTR-l, "\n       ");
 553                 l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
 554         }
 555
 556         snprint(p+l, READSTR-l, "\ntxstalled %d\n", ctlr->txstalled);
 557         n = readstr(offset, a, n, p);
 558         free(p);
 559         unlock(&ctlr->slock);
 560
 561         return n;
 562 }
 563
 564 static void
 565 gc82543promiscuous(void* arg, int on)
 566 {
 567         int rctl;
 568         Ctlr *ctlr;
 569         Ether *edev;
 570
 571         edev = arg;
 572         ctlr = edev->ctlr;
 573
 574         rctl = csr32r(ctlr, Rctl);
 575         rctl &= ~MoMASK;                /* make sure we're using bits 47:36 */
 576         if(on)
 577                 rctl |= Upe|Mpe;
 578         else
 579                 rctl &= ~(Upe|Mpe);
 580         csr32w(ctlr, Rctl, rctl);
 581 }
 582
 583 static void
 584 gc82543multicast(void* arg, uchar* addr, int on)
 585 {
 586         int bit, x;
 587         Ctlr *ctlr;
 588         Ether *edev;
 589
 590         edev = arg;
 591         ctlr = edev->ctlr;
 592         x = addr[5]>>1;
 593         bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
 594         if(on)
 595                 ctlr->multimask[x] |= 1<<bit;
 596         else
 597                 ctlr->multimask[x] &= ~(1<<bit);
 598
 599         csr32w(ctlr, Mta+x*4, ctlr->multimask[x]);
 600 }
 601
 602 static long
 603 gc82543ctl(Ether* edev, void* buf, long n)
 604 {
 605         Cmdbuf *cb;
 606         Ctlr *ctlr;
 607         int ctrl, i, r;
 608
 609         ctlr = edev->ctlr;
 610         if(ctlr == nil)
 611                 error(Enonexist);
 612
 613         lock(&ctlr->slock);
 614         r = 0;
 615         cb = parsecmd(buf, n);
 616         if(cb->nf < 2)
 617                 r = -1;
 618         else if(cistrcmp(cb->f[0], "auto") == 0){
 619                 ctrl = csr32r(ctlr, Ctrl);
 620                 if(cistrcmp(cb->f[1], "off") == 0){
 621                         csr32w(ctlr, Txcw, ctlr->txcw & ~Ane);
 622                         ctrl |= (Slu|Fd);
 623                         if(ctlr->txcw & As)
 624                                 ctrl |= Rfce;
 625                         if(ctlr->txcw & Ps)
 626                                 ctrl |= Tfce;
 627                         csr32w(ctlr, Ctrl, ctrl);
 628                 }
 629                 else if(cistrcmp(cb->f[1], "on") == 0){
 630                         csr32w(ctlr, Txcw, ctlr->txcw);
 631                         ctrl &= ~(Slu|Fd);
 632                         csr32w(ctlr, Ctrl, ctrl);
 633                 }
 634                 else
 635                         r = -1;
 636         }
 637         else if(cistrcmp(cb->f[0], "clear") == 0){
 638                 if(cistrcmp(cb->f[1], "stats") == 0){
 639                         for(i = 0; i < Nstatistics; i++)
 640                                 ctlr->statistics[i] = 0;
 641                 }
 642                 else
 643                         r = -1;
 644         }
 645         else
 646                 r = -1;
 647         unlock(&ctlr->slock);
 648
 649         free(cb);
 650         return (r == 0) ? n : r;
 651 }
 652
 653 static void
 654 gc82543txinit(Ctlr* ctlr)
 655 {
 656         int i;
 657         int tdsize;
 658         Block *bp, **bpp;
 659
 660         tdsize = ROUND(Ntdesc*sizeof(Tdesc), 4096);
 661
 662         if(ctlr->tdba == nil)
 663                 ctlr->tdba = xspanalloc(tdsize, 32, 0);
 664
 665         for(i = 0; i < Ntdesc; i++){
 666                 bpp = &ctlr->tb[i];
 667                 bp = *bpp;
 668                 if(bp != nil){
 669                         *bpp = nil;
 670                         freeb(bp);
 671                 }
 672                 memset(&ctlr->tdba[i], 0, sizeof(Tdesc));
 673         }
 674
 675         csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
 676         csr32w(ctlr, Tdbah, 0);
 677         csr32w(ctlr, Tdlen, Ntdesc*sizeof(Tdesc));
 678
 679         /*
 680          * set the ring head and tail pointers.
 681          */
 682         ctlr->tdh = 0;
 683         csr32w(ctlr, Tdh, ctlr->tdh);
 684         ctlr->tdt = 0;
 685         csr32w(ctlr, Tdt, ctlr->tdt);
 686
 687         csr32w(ctlr, Tipg, (6<<20)|(8<<10)|6);
 688         csr32w(ctlr, Tidv, 128);
 689         csr32w(ctlr, Ait, 0);
 690         csr32w(ctlr, Txdmac, 0);
 691         csr32w(ctlr, Txdctl, Gran|(4<<WthreshSHIFT)|(1<<HthreshSHIFT)|16);
 692         csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(6<<ColdSHIFT));
 693
 694         ctlr->im |= Txdw;
 695 }
 696
 697 static void
 698 gc82543transmit(Ether* edev)
 699 {
 700         Block *bp, **bpp;
 701         Ctlr *ctlr;
 702         Tdesc *tdesc;
 703         int tdh, tdt, s;
 704
 705         ctlr = edev->ctlr;
 706
 707         ilock(&ctlr->tdlock);
 708         tdh = ctlr->tdh;
 709         for(;;){
 710                 /*
 711                  * Free any completed packets
 712                  */
 713                 tdesc = &ctlr->tdba[tdh];
 714                 if(!(tdesc->status & Tdd))
 715                         break;
 716                 memset(tdesc, 0, sizeof(Tdesc));
 717                 bpp = &ctlr->tb[tdh];
 718                 bp = *bpp;
 719                 if(bp != nil){
 720                         *bpp = nil;
 721                         freeb(bp);
 722                 }
 723                 tdh = NEXT(tdh, Ntdesc);
 724         }
 725         ctlr->tdh = tdh;
 726         s = csr32r(ctlr, Status);
 727
 728         /*
 729          * Try to fill the ring back up
 730          * but only if link is up and transmission isn't paused.
 731          */
 732         if((s & (Txoff|Lu)) == Lu){
 733                 tdt = ctlr->tdt;
 734                 while(NEXT(tdt, Ntdesc) != tdh){
 735                         if((bp = qget(edev->oq)) == nil)
 736                                 break;
 737
 738                         tdesc = &ctlr->tdba[tdt];
 739                         tdesc->addr[0] = PCIWADDR(bp->rp);
 740                         tdesc->control = Ide|Rs|Ifcs|Teop|BLEN(bp);
 741                         ctlr->tb[tdt] = bp;
 742                         tdt = NEXT(tdt, Ntdesc);
 743                 }
 744
 745                 if(tdt != ctlr->tdt){
 746                         ctlr->tdt = tdt;
 747                         csr32w(ctlr, Tdt, tdt);
 748                 }
 749         }
 750         else
 751                 ctlr->txstalled++;
 752
 753         iunlock(&ctlr->tdlock);
 754 }
 755
 756 static Block *
 757 gc82543allocb(Ctlr* ctlr)
 758 {
 759         Block *bp;
 760
 761         ilock(&freelistlock);
 762         if((bp = *(ctlr->freehead)) != nil){
 763                 *(ctlr->freehead) = bp->next;
 764                 bp->next = nil;
 765         }
 766         iunlock(&freelistlock);
 767         return bp;
 768 }
 769
 770 static void
 771 gc82543replenish(Ctlr* ctlr)
 772 {
 773         int rdt;
 774         Block *bp;
 775         Rdesc *rdesc;
 776
 777         ilock(&ctlr->rdlock);
 778         rdt = ctlr->rdt;
 779         while(NEXT(rdt, Nrdesc) != ctlr->rdh){
 780                 rdesc = &ctlr->rdba[rdt];
 781                 if(ctlr->rb[rdt] == nil){
 782                         bp = gc82543allocb(ctlr);
 783                         if(bp == nil){
 784                                 iprint("no available buffers\n");
 785                                 break;
 786                         }
 787                         ctlr->rb[rdt] = bp;
 788                         rdesc->addr[0] = PCIWADDR(bp->rp);
 789                         rdesc->addr[1] = 0;
 790                 }
 791                 coherence();
 792                 rdesc->status = 0;
 793                 rdt = NEXT(rdt, Nrdesc);
 794         }
 795         ctlr->rdt = rdt;
 796         csr32w(ctlr, Rdt, rdt);
 797         iunlock(&ctlr->rdlock);
 798 }
 799
 800 static void
 801 gc82543rxinit(Ctlr* ctlr)
 802 {
 803         int rdsize, i;
 804
 805         csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
 806
 807         /*
 808          * Allocate the descriptor ring and load its
 809          * address and length into the NIC.
 810          */
 811         rdsize = ROUND(Nrdesc*sizeof(Rdesc), 4096);
 812         if(ctlr->rdba == nil)
 813                 ctlr->rdba = xspanalloc(rdsize, 32, 0);
 814         memset(ctlr->rdba, 0, rdsize);
 815
 816         ctlr->rdh = 0;
 817         ctlr->rdt = 0;
 818
 819         csr32w(ctlr, Rdtr, Fpd|64);
 820         csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
 821         csr32w(ctlr, Rdbah, 0);
 822         csr32w(ctlr, Rdlen, Nrdesc*sizeof(Rdesc));
 823         csr32w(ctlr, Rdh, 0);
 824         csr32w(ctlr, Rdt, 0);
 825         for(i = 0; i < Nrdesc; i++){
 826                 if(ctlr->rb[i] != nil){
 827                         freeb(ctlr->rb[i]);
 828                         ctlr->rb[i] = nil;
 829                 }
 830         }
 831         gc82543replenish(ctlr);
 832
 833         csr32w(ctlr, Rxdctl, RxGran|(8<<WthreshSHIFT)|(4<<HthreshSHIFT)|1);
 834         ctlr->im |= Rxt0|Rxo|Rxdmt0|Rxseq;
 835 }
 836
 837 static void
 838 gc82543recv(Ether* edev, int icr)
 839 {
 840         Block *bp;
 841         Ctlr *ctlr;
 842         Rdesc *rdesc;
 843         int rdh;
 844
 845         ctlr = edev->ctlr;
 846
 847         rdh = ctlr->rdh;
 848         for(;;){
 849                 rdesc = &ctlr->rdba[rdh];
 850
 851                 if(!(rdesc->status & Rdd))
 852                         break;
 853
 854                 if((rdesc->status & Reop) && rdesc->errors == 0){
 855                         bp = ctlr->rb[rdh];
 856                         ctlr->rb[rdh] = nil;
 857                         bp->wp += rdesc->length;
 858                         bp->next = nil;
 859                         etheriq(edev, bp);
 860                 }
 861
 862                 if(ctlr->rb[rdh] != nil){
 863                         /* either non eop packet, or error */
 864                         freeb(ctlr->rb[rdh]);
 865                         ctlr->rb[rdh] = nil;
 866                 }
 867                 memset(rdesc, 0, sizeof(Rdesc));
 868                 coherence();
 869                 rdh = NEXT(rdh, Nrdesc);
 870         }
 871         ctlr->rdh = rdh;
 872
 873         if(icr & Rxdmt0)
 874                 gc82543replenish(ctlr);
 875 }
 876
 877 static void
 878 freegc82543short(Block *bp)
 879 {
 880         ilock(&freelistlock);
 881         /* reset read/write pointer to proper positions */
 882         bp->rp = bp->lim - ROUND(SBLOCKSIZE, BLOCKALIGN);
 883         bp->wp = bp->rp;
 884         bp->next = freeShortHead;
 885         freeShortHead = bp;
 886         iunlock(&freelistlock);
 887 }
 888
 889 static void
 890 freegc82532jumbo(Block *bp)
 891 {
 892         ilock(&freelistlock);
 893         /* reset read/write pointer to proper positions */
 894         bp->rp = bp->lim - ROUND(JBLOCKSIZE, BLOCKALIGN);
 895         bp->wp = bp->rp;
 896         bp->next = freeJumboHead;
 897         freeJumboHead = bp;
 898         iunlock(&freelistlock);
 899 }
 900
 901 static void
 902 linkintr(Ctlr* ctlr)
 903 {
 904         int ctrl;
 905
 906         ctrl = csr32r(ctlr, Ctrl);
 907
 908         if((ctrl & Swdpin1) ||
 909           ((csr32r(ctlr, Rxcw) & Rxconfig) && !(csr32r(ctlr, Txcw) & Ane))){
 910                 csr32w(ctlr, Txcw, ctlr->txcw);
 911                 ctrl &= ~(Slu|Fd|Frcdplx);
 912                 csr32w(ctlr, Ctrl, ctrl);
 913         }
 914 }
 915
 916 static void
 917 gc82543interrupt(Ureg*, void* arg)
 918 {
 919         Ctlr *ctlr;
 920         Ether *edev;
 921         int icr;
 922
 923         edev = arg;
 924         ctlr = edev->ctlr;
 925
 926         while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){
 927                 /*
 928                  * Link status changed.
 929                  */
 930                 if(icr & (Lsc|Rxseq))
 931                         linkintr(ctlr);
 932
 933                 /*
 934                  * Process recv buffers.
 935                  */
 936                 gc82543recv(edev, icr);
 937
 938                 /*
 939                  * Refill transmit ring and free packets.
 940                  */
 941                 gc82543transmit(edev);
 942         }
 943 }
 944
 945 static int
 946 gc82543init(Ether* edev)
 947 {
 948         int csr, i;
 949         Block *bp;
 950         Ctlr *ctlr;
 951
 952         ctlr = edev->ctlr;
 953
 954         /*
 955          * Allocate private buffer pool to use for receiving packets.
 956          */
 957         ilock(&freelistlock);
 958         if (ctlr->freehead == nil){
 959                 for(i = 0; i < Nblocks; i++){
 960                         bp = iallocb(SBLOCKSIZE);
 961                         if(bp != nil){
 962                                 bp->next = freeShortHead;
 963                                 bp->free = freegc82543short;
 964                                 freeShortHead = bp;
 965                         }
 966                         else{
 967                                 print("82543gc: no memory\n");
 968                                 break;
 969                         }
 970                 }
 971                 ctlr->freehead = &freeShortHead;
 972         }
 973         iunlock(&freelistlock);
 974
 975         /*
 976          * Set up the receive addresses.
 977          * There are 16 addresses. The first should be the MAC address.
 978          * The others are cleared and not marked valid (MS bit of Rah).
 979          */
 980         csr = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
 981         csr32w(ctlr, Ral, csr);
 982         csr = 0x80000000|(edev->ea[5]<<8)|edev->ea[4];
 983         csr32w(ctlr, Rah, csr);
 984         for(i = 1; i < 16; i++){
 985                 csr32w(ctlr, Ral+i*8, 0);
 986                 csr32w(ctlr, Rah+i*8, 0);
 987         }
 988
 989         /*
 990          * Clear the Multicast Table Array.
 991          * It's a 4096 bit vector accessed as 128 32-bit registers.
 992          */
 993         for(i = 0; i < 128; i++)
 994                 csr32w(ctlr, Mta+i*4, 0);
 995
 996         gc82543txinit(ctlr);
 997         gc82543rxinit(ctlr);
 998
 999         return 0;
1000 }
1001
1002 static int
1003 at93c46io(Ctlr* ctlr, char* op, int data)
1004 {
1005         char *lp, *p;
1006         int i, loop, eecd, r;
1007
1008         eecd = csr32r(ctlr, Eecd);
1009
1010         r = 0;
1011         loop = -1;
1012         lp = nil;
1013         for(p = op; *p != '\0'; p++){
1014                 switch(*p){
1015                 default:
1016                         return -1;
1017                 case ' ':
1018                         continue;
1019                 case ':':                       /* start of loop */
1020                         if(lp != nil){
1021                                 if(p != (lp+1) || loop != 7)
1022                                         return -1;
1023                                 lp = p;
1024                                 loop = 15;
1025                                 continue;
1026                         }
1027                         lp = p;
1028                         loop = 7;
1029                         continue;
1030                 case ';':                       /* end of loop */
1031                         if(lp == nil)
1032                                 return -1;
1033                         loop--;
1034                         if(loop >= 0)
1035                                 p = lp;
1036                         else
1037                                 lp = nil;
1038                         continue;
1039                 case 'C':                       /* assert clock */
1040                         eecd |= Sk;
1041                         break;
1042                 case 'c':                       /* deassert clock */
1043                         eecd &= ~Sk;
1044                         break;
1045                 case 'D':                       /* next bit in 'data' byte */
1046                         if(loop < 0)
1047                                 return -1;
1048                         if(data & (1<<loop))
1049                                 eecd |= Di;
1050                         else
1051                                 eecd &= ~Di;
1052                         break;
1053                 case 'O':                       /* collect data output */
1054                         i = (csr32r(ctlr, Eecd) & Do) != 0;
1055                         if(loop >= 0)
1056                                 r |= (i<<loop);
1057                         else
1058                                 r = i;
1059                         continue;
1060                 case 'I':                       /* assert data input */
1061                         eecd |= Di;
1062                         break;
1063                 case 'i':                       /* deassert data input */
1064                         eecd &= ~Di;
1065                         break;
1066                 case 'S':                       /* enable chip select */
1067                         eecd |= Cs;
1068                         break;
1069                 case 's':                       /* disable chip select */
1070                         eecd &= ~Cs;
1071                         break;
1072                 }
1073                 csr32w(ctlr, Eecd, eecd);
1074                 microdelay(1);
1075         }
1076         if(loop >= 0)
1077                 return -1;
1078         return r;
1079 }
1080
1081 static int
1082 at93c46r(Ctlr* ctlr)
1083 {
1084         ushort sum;
1085         int addr, data;
1086
1087         sum = 0;
1088         for(addr = 0; addr < 0x40; addr++){
1089                 /*
1090                  * Read a word at address 'addr' from the Atmel AT93C46
1091                  * 3-Wire Serial EEPROM or compatible. The EEPROM access is
1092                  * controlled by 4 bits in Eecd. See the AT93C46 datasheet
1093                  * for protocol details.
1094                  */
1095                 if(at93c46io(ctlr, "S ICc :DCc;", (0x02<<6)|addr) != 0)
1096                         break;
1097                 data = at93c46io(ctlr, "::COc;", 0);
1098                 at93c46io(ctlr, "sic", 0);
1099                 ctlr->eeprom[addr] = data;
1100                 sum += data;
1101         }
1102
1103         return sum;
1104 }
1105
1106 static void
1107 gc82543detach(Ctlr* ctlr)
1108 {
1109         /*
1110          * Perform a device reset to get the chip back to the
1111          * power-on state, followed by an EEPROM reset to read
1112          * the defaults for some internal registers.
1113          */
1114         csr32w(ctlr, Imc, ~0);
1115         csr32w(ctlr, Rctl, 0);
1116         csr32w(ctlr, Tctl, 0);
1117
1118         delay(10);
1119
1120         csr32w(ctlr, Ctrl, Devrst);
1121         while(csr32r(ctlr, Ctrl) & Devrst)
1122                 ;
1123
1124         csr32w(ctlr, Ctrlext, Eerst);
1125         while(csr32r(ctlr, Ctrlext) & Eerst)
1126                 ;
1127
1128         csr32w(ctlr, Imc, ~0);
1129         while(csr32r(ctlr, Icr))
1130                 ;
1131 }
1132
1133 static void
1134 gc82543checklink(Ctlr* ctlr)
1135 {
1136         int ctrl, status, rxcw;
1137
1138         ctrl = csr32r(ctlr, Ctrl);
1139         status = csr32r(ctlr, Status);
1140         rxcw = csr32r(ctlr, Rxcw);
1141
1142         if(!(status & Lu)){
1143                 if(!(ctrl & (Swdpin1|Slu)) && !(rxcw & Rxconfig)){
1144                         csr32w(ctlr, Txcw, ctlr->txcw & ~Ane);
1145                         ctrl |= (Slu|Fd);
1146                         if(ctlr->txcw & As)
1147                                 ctrl |= Rfce;
1148                         if(ctlr->txcw & Ps)
1149                                 ctrl |= Tfce;
1150                         csr32w(ctlr, Ctrl, ctrl);
1151                 }
1152         }
1153         else if((ctrl & Slu) && (rxcw & Rxconfig)){
1154                 csr32w(ctlr, Txcw, ctlr->txcw);
1155                 ctrl &= ~(Slu|Fd);
1156                 csr32w(ctlr, Ctrl, ctrl);
1157         }
1158 }
1159
1160 static void
1161 gc82543shutdown(Ether* ether)
1162 {
1163         gc82543detach(ether->ctlr);
1164 }
1165
1166 static int
1167 gc82543reset(Ctlr* ctlr)
1168 {
1169         int ctl;
1170         int te;
1171
1172         /*
1173          * Read the EEPROM, validate the checksum
1174          * then get the device back to a power-on state.
1175          */
1176         if(at93c46r(ctlr) != 0xBABA)
1177                 return -1;
1178
1179         gc82543detach(ctlr);
1180
1181         te = ctlr->eeprom[Icw2];
1182         if((te & 0x3000) == 0){
1183                 ctlr->fcrtl = 0x00002000;
1184                 ctlr->fcrth = 0x00004000;
1185                 ctlr->txcw = Ane|TxcwFd;
1186         }
1187         else if((te & 0x3000) == 0x2000){
1188                 ctlr->fcrtl = 0;
1189                 ctlr->fcrth = 0;
1190                 ctlr->txcw = Ane|TxcwFd|As;
1191         }
1192         else{
1193                 ctlr->fcrtl = 0x00002000;
1194                 ctlr->fcrth = 0x00004000;
1195                 ctlr->txcw = Ane|TxcwFd|As|Ps;
1196         }
1197
1198         csr32w(ctlr, Txcw, ctlr->txcw);
1199
1200         csr32w(ctlr, Ctrlext, (te & 0x00f0)<<4);
1201
1202         csr32w(ctlr, Tctl, csr32r(ctlr, Tctl)|(64<<ColdSHIFT));
1203
1204         te = ctlr->eeprom[Icw1];
1205         ctl = ((te & 0x01E0)<<17)|(te & 0x0010)<<3;
1206         csr32w(ctlr, Ctrl, ctl);
1207
1208         delay(10);
1209
1210         /*
1211          * Flow control - values from the datasheet.
1212          */
1213         csr32w(ctlr, Fcal, 0x00C28001);
1214         csr32w(ctlr, Fcah, 0x00000100);
1215         csr32w(ctlr, Fct, 0x00008808);
1216         csr32w(ctlr, Fcttv, 0x00000100);
1217
1218         csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1219         csr32w(ctlr, Fcrth, ctlr->fcrth);
1220
1221         ctlr->im = Lsc;
1222         gc82543checklink(ctlr);
1223
1224         return 0;
1225 }
1226
1227 static void
1228 gc82543watchdog(void* arg)
1229 {
1230         Ether *edev;
1231         Ctlr *ctlr;
1232
1233         edev = arg;
1234         while(waserror())
1235                 ;
1236         for(;;){
1237                 tsleep(&up->sleep, return0, 0, 1000);
1238                 ctlr = edev->ctlr;
1239                 if(ctlr == nil)
1240                         break;
1241
1242                 gc82543checklink(ctlr);
1243                 gc82543replenish(ctlr);
1244         }
1245         print("%s: exiting\n", up->text);
1246         pexit("disabled", 1);
1247 }
1248
1249 static void
1250 gc82543pci(void)
1251 {
1252         int cls;
1253         void *mem;
1254         Pcidev *p;
1255         Ctlr *ctlr;
1256         uvlong io;
1257
1258         p = nil;
1259         while(p = pcimatch(p, 0, 0)){
1260                 if(p->ccrb != 0x02 || p->ccru != 0)
1261                         continue;
1262                 if(p->mem[0].bar & 1)
1263                         continue;
1264
1265                 switch((p->did<<16)|p->vid){
1266                 case (0x1000<<16)|0x8086:       /* LSI L2A1157 (82542) */
1267                 case (0x1004<<16)|0x8086:       /* Intel PRO/1000 T */
1268                 case (0x1008<<16)|0x8086:       /* Intel PRO/1000 XT */
1269                 default:
1270                         continue;
1271                 case (0x1001<<16)|0x8086:       /* Intel PRO/1000 F */
1272                         break;
1273                 }
1274
1275                 ctlr = malloc(sizeof(Ctlr));
1276                 if(ctlr == nil){
1277                         print("82543gc: can't allocate memory\n");
1278                         continue;
1279                 }
1280                 mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
1281                 if(mem == 0){
1282                         print("82543gc: can't map %8.8luX\n", p->mem[0].bar);
1283                         free(ctlr);
1284                         continue;
1285                 }
1286                 switch(p->cls){
1287                 case 0x08:
1288                 case 0x10:
1289                         break;
1290                 default:
1291                         print("82543gc: p->cls %#ux, setting to 0x10\n", p->cls);
1292                         p->cls = 0x10;
1293                         pcicfgw8(p, PciCLS, p->cls);
1294                 }
1295                 ctlr->port = p->mem[0].bar & ~0x0F;
1296                 ctlr->pcidev = p;
1297                 ctlr->id = (p->did<<16)|p->vid;
1298                 ctlr->nic = mem;
1299
1300                 if(gc82543ctlrhead != nil)
1301                         gc82543ctlrtail->next = ctlr;
1302                 else
1303                         gc82543ctlrhead = ctlr;
1304                 gc82543ctlrtail = ctlr;
1305         }
1306 }
1307
1308 static int
1309 gc82543pnp(Ether* edev)
1310 {
1311         int i;
1312         Ctlr *ctlr;
1313         uchar ea[Eaddrlen];
1314
1315         if(gc82543ctlrhead == nil)
1316                 gc82543pci();
1317
1318         /*
1319          * Any adapter matches if no edev->port is supplied,
1320          * otherwise the ports must match.
1321          */
1322         for(ctlr = gc82543ctlrhead; ctlr != nil; ctlr = ctlr->next){
1323                 if(ctlr->active)
1324                         continue;
1325                 if(edev->port == 0 || edev->port == ctlr->port){
1326                         ctlr->active = 1;
1327                         break;
1328                 }
1329         }
1330         if(ctlr == nil)
1331                 return -1;
1332
1333         pcienable(ctlr->pcidev);
1334         gc82543reset(ctlr);
1335
1336         edev->ctlr = ctlr;
1337         edev->port = ctlr->port;
1338         edev->irq = ctlr->pcidev->intl;
1339         edev->tbdf = ctlr->pcidev->tbdf;
1340         edev->mbps = 1000;
1341
1342         /*
1343          * Check if the adapter's station address is to be overridden.
1344          * If not, read it from the EEPROM and set in ether->ea prior to
1345          * loading the station address in the hardware.
1346          */
1347         memset(ea, 0, Eaddrlen);
1348         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1349                 for(i = Ea; i < Eaddrlen/2; i++){
1350                         edev->ea[2*i] = ctlr->eeprom[i];
1351                         edev->ea[2*i+1] = ctlr->eeprom[i]>>8;
1352                 }
1353         }
1354         gc82543init(edev);
1355         pcisetbme(ctlr->pcidev);
1356
1357         /*
1358          * Linkage to the generic ethernet driver.
1359          */
1360         edev->attach = gc82543attach;
1361         edev->transmit = gc82543transmit;
1362         edev->interrupt = gc82543interrupt;
1363         edev->ifstat = gc82543ifstat;
1364         edev->shutdown = gc82543shutdown;
1365         edev->ctl = gc82543ctl;
1366         edev->arg = edev;
1367         edev->promiscuous = gc82543promiscuous;
1368         edev->multicast = gc82543multicast;
1369
1370         return 0;
1371 }
1372
1373 void
1374 ether82543gclink(void)
1375 {
1376         addethercard("82543GC", gc82543pnp);
1377 }